1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include "sys/bge_impl2.h" 30 31 #define PIO_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->io_regs+(offset))) 32 33 /* 34 * Future features ... ? 35 */ 36 #define BGE_CFG_IO8 0 /* 8/16-bit cfg space BIS/BIC */ 37 #define BGE_IND_IO32 0 /* indirect access code */ 38 #define BGE_SEE_IO32 1 /* SEEPROM access code */ 39 #define BGE_FLASH_IO32 1 /* FLASH access code */ 40 41 /* 42 * BGE MSI tunable: 43 * 44 * By default MSI is enabled on all supported platforms but it is disabled 45 * for some Broadcom chips due to known MSI hardware issues. Currently MSI 46 * is enabled only for 5714C A2 and 5715C A2 broadcom chips. 47 */ 48 #if defined(__sparc) 49 boolean_t bge_enable_msi = B_TRUE; 50 #else 51 boolean_t bge_enable_msi = B_FALSE; 52 #endif 53 54 /* 55 * Property names 56 */ 57 static char knownids_propname[] = "bge-known-subsystems"; 58 59 /* 60 * Patchable globals: 61 * 62 * bge_autorecover 63 * Enables/disables automatic recovery after fault detection 64 * 65 * bge_mlcr_default 66 * Value to program into the MLCR; controls the chip's GPIO pins 67 * 68 * bge_dma_{rd,wr}prio 69 * Relative priorities of DMA reads & DMA writes respectively. 70 * These may each be patched to any value 0-3. Equal values 71 * will give "fair" (round-robin) arbitration for PCI access. 72 * Unequal values will give one or the other function priority. 73 * 74 * bge_dma_rwctrl 75 * Value to put in the Read/Write DMA control register. See 76 * the Broadcom PRM for things you can fiddle with in this 77 * register ... 78 * 79 * bge_{tx,rx}_{count,ticks}_{norm,intr} 80 * Send/receive interrupt coalescing parameters. Counts are 81 * #s of descriptors, ticks are in microseconds. *norm* values 82 * apply between status updates/interrupts; the *intr* values 83 * refer to the 'during-interrupt' versions - see the PRM. 84 * 85 * NOTE: these values have been determined by measurement. They 86 * differ significantly from the values recommended in the PRM. 87 */ 88 static uint32_t bge_autorecover = 1; 89 static uint32_t bge_mlcr_default = MLCR_DEFAULT; 90 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714; 91 92 static uint32_t bge_dma_rdprio = 1; 93 static uint32_t bge_dma_wrprio = 0; 94 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT; 95 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721; 96 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714; 97 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715; 98 99 uint32_t bge_rx_ticks_norm = 128; 100 uint32_t bge_tx_ticks_norm = 2048; /* 8 for FJ2+ !?!? */ 101 uint32_t bge_rx_count_norm = 8; 102 uint32_t bge_tx_count_norm = 128; 103 104 static uint32_t bge_rx_ticks_intr = 128; 105 static uint32_t bge_tx_ticks_intr = 0; /* 8 for FJ2+ !?!? */ 106 static uint32_t bge_rx_count_intr = 2; 107 static uint32_t bge_tx_count_intr = 0; 108 109 /* 110 * Memory pool configuration parameters. 111 * 112 * These are generally specific to each member of the chip family, since 113 * each one may have a different memory size/configuration. 114 * 115 * Setting the mbuf pool length for a specific type of chip to 0 inhibits 116 * the driver from programming the various registers; instead they are left 117 * at their hardware defaults. This is the preferred option for later chips 118 * (5705+), whereas the older chips *required* these registers to be set, 119 * since the h/w default was 0 ;-( 120 */ 121 static uint32_t bge_mbuf_pool_base = MBUF_POOL_BASE_DEFAULT; 122 static uint32_t bge_mbuf_pool_base_5704 = MBUF_POOL_BASE_5704; 123 static uint32_t bge_mbuf_pool_base_5705 = MBUF_POOL_BASE_5705; 124 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721; 125 static uint32_t bge_mbuf_pool_len = MBUF_POOL_LENGTH_DEFAULT; 126 static uint32_t bge_mbuf_pool_len_5704 = MBUF_POOL_LENGTH_5704; 127 static uint32_t bge_mbuf_pool_len_5705 = 0; /* use h/w default */ 128 static uint32_t bge_mbuf_pool_len_5721 = 0; 129 130 /* 131 * Various high and low water marks, thresholds, etc ... 132 * 133 * Note: these are taken from revision 7 of the PRM, and some are different 134 * from both the values in earlier PRMs *and* those determined experimentally 135 * and used in earlier versions of this driver ... 136 */ 137 static uint32_t bge_mbuf_hi_water = MBUF_HIWAT_DEFAULT; 138 static uint32_t bge_mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_DEFAULT; 139 static uint32_t bge_mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_DEFAULT; 140 141 static uint32_t bge_dmad_lo_water = DMAD_POOL_LOWAT_DEFAULT; 142 static uint32_t bge_dmad_hi_water = DMAD_POOL_HIWAT_DEFAULT; 143 static uint32_t bge_lowat_recv_frames = LOWAT_MAX_RECV_FRAMES_DEFAULT; 144 145 static uint32_t bge_replenish_std = STD_RCV_BD_REPLENISH_DEFAULT; 146 static uint32_t bge_replenish_mini = MINI_RCV_BD_REPLENISH_DEFAULT; 147 static uint32_t bge_replenish_jumbo = JUMBO_RCV_BD_REPLENISH_DEFAULT; 148 149 static uint32_t bge_watchdog_count = 1 << 16; 150 static uint16_t bge_dma_miss_limit = 20; 151 152 static uint32_t bge_stop_start_on_sync = 0; 153 154 boolean_t bge_jumbo_enable = B_TRUE; 155 static uint32_t bge_default_jumbo_size = BGE_JUMBO_BUFF_SIZE; 156 157 /* 158 * ========== Low-level chip & ring buffer manipulation ========== 159 */ 160 161 #define BGE_DBG BGE_DBG_REGS /* debug flag for this code */ 162 163 164 /* 165 * Config space read-modify-write routines 166 */ 167 168 #if BGE_CFG_IO8 169 170 /* 171 * 8- and 16-bit set/clr operations are not used; all the config registers 172 * that we need to do bit-twiddling on are 32 bits wide. I'll leave the 173 * code here, though, in case we ever find that we do want it after all ... 174 */ 175 176 static void bge_cfg_set8(bge_t *bgep, bge_regno_t regno, uint8_t bits); 177 #pragma inline(bge_cfg_set8) 178 179 static void 180 bge_cfg_set8(bge_t *bgep, bge_regno_t regno, uint8_t bits) 181 { 182 uint8_t regval; 183 184 BGE_TRACE(("bge_cfg_set8($%p, 0x%lx, 0x%x)", 185 (void *)bgep, regno, bits)); 186 187 regval = pci_config_get8(bgep->cfg_handle, regno); 188 189 BGE_DEBUG(("bge_cfg_set8($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 190 (void *)bgep, regno, bits, regval, regval | bits)); 191 192 regval |= bits; 193 pci_config_put8(bgep->cfg_handle, regno, regval); 194 } 195 196 static void bge_cfg_clr8(bge_t *bgep, bge_regno_t regno, uint8_t bits); 197 #pragma inline(bge_cfg_clr8) 198 199 static void 200 bge_cfg_clr8(bge_t *bgep, bge_regno_t regno, uint8_t bits) 201 { 202 uint8_t regval; 203 204 BGE_TRACE(("bge_cfg_clr8($%p, 0x%lx, 0x%x)", 205 (void *)bgep, regno, bits)); 206 207 regval = pci_config_get8(bgep->cfg_handle, regno); 208 209 BGE_DEBUG(("bge_cfg_clr8($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 210 (void *)bgep, regno, bits, regval, regval & ~bits)); 211 212 regval &= ~bits; 213 pci_config_put8(bgep->cfg_handle, regno, regval); 214 } 215 216 static void bge_cfg_set16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 217 #pragma inline(bge_cfg_set16) 218 219 static void 220 bge_cfg_set16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 221 { 222 uint16_t regval; 223 224 BGE_TRACE(("bge_cfg_set16($%p, 0x%lx, 0x%x)", 225 (void *)bgep, regno, bits)); 226 227 regval = pci_config_get16(bgep->cfg_handle, regno); 228 229 BGE_DEBUG(("bge_cfg_set16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 230 (void *)bgep, regno, bits, regval, regval | bits)); 231 232 regval |= bits; 233 pci_config_put16(bgep->cfg_handle, regno, regval); 234 } 235 236 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 237 #pragma inline(bge_cfg_clr16) 238 239 static void 240 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 241 { 242 uint16_t regval; 243 244 BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)", 245 (void *)bgep, regno, bits)); 246 247 regval = pci_config_get16(bgep->cfg_handle, regno); 248 249 BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 250 (void *)bgep, regno, bits, regval, regval & ~bits)); 251 252 regval &= ~bits; 253 pci_config_put16(bgep->cfg_handle, regno, regval); 254 } 255 256 #endif /* BGE_CFG_IO8 */ 257 258 static void bge_cfg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 259 #pragma inline(bge_cfg_set32) 260 261 static void 262 bge_cfg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 263 { 264 uint32_t regval; 265 266 BGE_TRACE(("bge_cfg_set32($%p, 0x%lx, 0x%x)", 267 (void *)bgep, regno, bits)); 268 269 regval = pci_config_get32(bgep->cfg_handle, regno); 270 271 BGE_DEBUG(("bge_cfg_set32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 272 (void *)bgep, regno, bits, regval, regval | bits)); 273 274 regval |= bits; 275 pci_config_put32(bgep->cfg_handle, regno, regval); 276 } 277 278 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 279 #pragma inline(bge_cfg_clr32) 280 281 static void 282 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 283 { 284 uint32_t regval; 285 286 BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)", 287 (void *)bgep, regno, bits)); 288 289 regval = pci_config_get32(bgep->cfg_handle, regno); 290 291 BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 292 (void *)bgep, regno, bits, regval, regval & ~bits)); 293 294 regval &= ~bits; 295 pci_config_put32(bgep->cfg_handle, regno, regval); 296 } 297 298 #if BGE_IND_IO32 299 300 /* 301 * Indirect access to registers & RISC scratchpads, using config space 302 * accesses only. 303 * 304 * This isn't currently used, but someday we might want to use it for 305 * restoring the Subsystem Device/Vendor registers (which aren't directly 306 * writable in Config Space), or for downloading firmware into the RISCs 307 * 308 * In any case there are endian issues to be resolved before this code is 309 * enabled; the bizarre way that bytes get twisted by this chip AND by 310 * the PCI bridge in SPARC systems mean that we shouldn't enable it until 311 * it's been thoroughly tested for all access sizes on all supported 312 * architectures (SPARC *and* x86!). 313 */ 314 static uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno); 315 #pragma inline(bge_ind_get32) 316 317 static uint32_t 318 bge_ind_get32(bge_t *bgep, bge_regno_t regno) 319 { 320 uint32_t val; 321 322 BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno)); 323 324 ASSERT(mutex_owned(bgep->genlock)); 325 326 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 327 val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR); 328 329 BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x", 330 (void *)bgep, regno, val)); 331 332 return (val); 333 } 334 335 static void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val); 336 #pragma inline(bge_ind_put32) 337 338 static void 339 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val) 340 { 341 BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)", 342 (void *)bgep, regno, val)); 343 344 ASSERT(mutex_owned(bgep->genlock)); 345 346 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 347 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val); 348 } 349 350 #endif /* BGE_IND_IO32 */ 351 352 #if BGE_DEBUGGING 353 354 static void bge_pci_check(bge_t *bgep); 355 #pragma no_inline(bge_pci_check) 356 357 static void 358 bge_pci_check(bge_t *bgep) 359 { 360 uint16_t pcistatus; 361 362 pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT); 363 if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0) 364 BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x", 365 (void *)bgep, pcistatus)); 366 } 367 368 #endif /* BGE_DEBUGGING */ 369 370 /* 371 * Perform first-stage chip (re-)initialisation, using only config-space 372 * accesses: 373 * 374 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 375 * returning the data in the structure pointed to by <idp>. 376 * + Configure the target-mode endianness (swap) options. 377 * + Disable interrupts and enable Memory Space accesses. 378 * + Enable or disable Bus Mastering according to the <enable_dma> flag. 379 * 380 * This sequence is adapted from Broadcom document 570X-PG102-R, 381 * page 102, steps 1-3, 6-8 and 11-13. The omitted parts of the sequence 382 * are 4 and 5 (Reset Core and wait) which are handled elsewhere. 383 * 384 * This function MUST be called before any non-config-space accesses 385 * are made; on this first call <enable_dma> is B_FALSE, and it 386 * effectively performs steps 3-1(!) of the initialisation sequence 387 * (the rest are not required but should be harmless). 388 * 389 * It MUST also be called also after a chip reset, as this disables 390 * Memory Space cycles! In this case, <enable_dma> is B_TRUE, and 391 * it is effectively performing steps 6-8. 392 */ 393 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma); 394 #pragma no_inline(bge_chip_cfg_init) 395 396 void 397 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma) 398 { 399 ddi_acc_handle_t handle; 400 uint16_t command; 401 uint32_t mhcr; 402 uint16_t value16; 403 int i; 404 405 BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)", 406 (void *)bgep, (void *)cidp, enable_dma)); 407 408 /* 409 * Step 3: save PCI cache line size and subsystem vendor ID 410 * 411 * Read all the config-space registers that characterise the 412 * chip, specifically vendor/device/revision/subsystem vendor 413 * and subsystem device id. We expect (but don't check) that 414 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704) 415 * 416 * Also save all bus-transation related registers (cache-line 417 * size, bus-grant/latency parameters, etc). Some of these are 418 * cleared by reset, so we'll have to restore them later. This 419 * comes from the Broadcom document 570X-PG102-R ... 420 * 421 * Note: Broadcom document 570X-PG102-R seems to be in error 422 * here w.r.t. the offsets of the Subsystem Vendor ID and 423 * Subsystem (Device) ID registers, which are the opposite way 424 * round according to the PCI standard. For good measure, we 425 * save/restore both anyway. 426 */ 427 handle = bgep->cfg_handle; 428 429 mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR); 430 cidp->asic_rev = mhcr & MHCR_CHIP_REV_MASK; 431 cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE); 432 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 433 434 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 435 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 436 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 437 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 438 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 439 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 440 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 441 442 BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s", 443 cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X", 444 cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow", 445 cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide", 446 cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low")); 447 BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 448 cidp->vendor, cidp->device, cidp->revision)); 449 BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x", 450 cidp->subven, cidp->subdev, cidp->asic_rev)); 451 BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x", 452 cidp->clsize, cidp->latency, cidp->command)); 453 454 /* 455 * Step 2 (also step 6): disable and clear interrupts. 456 * Steps 11-13: configure PIO endianness options, and enable 457 * indirect register access. We'll also select any other 458 * options controlled by the MHCR (eg tagged status, mask 459 * interrupt mode) at this stage ... 460 * 461 * Note: internally, the chip is 64-bit and BIG-endian, but 462 * since it talks to the host over a (LITTLE-endian) PCI bus, 463 * it normally swaps bytes around at the PCI interface. 464 * However, the PCI host bridge on SPARC systems normally 465 * swaps the byte lanes around too, since SPARCs are also 466 * BIG-endian. So it turns out that on SPARC, the right 467 * option is to tell the chip to swap (and the host bridge 468 * will swap back again), whereas on x86 we ask the chip 469 * NOT to swap, so the natural little-endianness of the 470 * PCI bus is assumed. Then the only thing that doesn't 471 * automatically work right is access to an 8-byte register 472 * by a little-endian host; but we don't want to set the 473 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte 474 * accesses don't go where expected ;-( So we live with 475 * that, and perform word-swaps in software in the few cases 476 * where a chip register is defined as an 8-byte value -- 477 * see the code below for details ... 478 * 479 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't 480 * very clear in the register description in the PRM, but 481 * Broadcom document 570X-PG104-R page 248 explains a little 482 * more (under "Broadcom Mask Mode"). The bit changes the way 483 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE 484 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same 485 * way as the 5700 did, which isn't very convenient. Setting 486 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT 487 * bit do just what its name says -- MASK the PCI #INTA output 488 * (i.e. deassert the signal at the pin) leaving all internal 489 * state unchanged. This is much more convenient for our 490 * interrupt handler, so we set MASK_INTERRUPT_MODE here. 491 * 492 * Note: the inconvenient semantics of the interrupt mailbox 493 * (nonzero disables and acknowledges/clears the interrupt, 494 * zero enables AND CLEARS it) would make race conditions 495 * likely in the interrupt handler: 496 * 497 * (1) acknowledge & disable interrupts 498 * (2) while (more to do) 499 * process packets 500 * (3) enable interrupts -- also clears pending 501 * 502 * If the chip received more packets and internally generated 503 * an interrupt between the check at (2) and the mbox write 504 * at (3), this interrupt would be lost :-( 505 * 506 * The best way to avoid this is to use TAGGED STATUS mode, 507 * where the chip includes a unique tag in each status block 508 * update, and the host, when re-enabling interrupts, passes 509 * the last tag it saw back to the chip; then the chip can 510 * see whether the host is truly up to date, and regenerate 511 * its interrupt if not. 512 */ 513 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 514 MHCR_ENABLE_TAGGED_STATUS_MODE | 515 MHCR_MASK_INTERRUPT_MODE | 516 MHCR_CLEAR_INTERRUPT_INTA; 517 518 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 519 mhcr |= MHCR_MASK_PCI_INT_OUTPUT; 520 521 #ifdef _BIG_ENDIAN 522 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 523 #endif /* _BIG_ENDIAN */ 524 525 pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr); 526 527 #ifdef BGE_IPMI_ASF 528 bgep->asf_wordswapped = B_FALSE; 529 #endif 530 /* 531 * Step 1 (also step 7): Enable PCI Memory Space accesses 532 * Disable Memory Write/Invalidate 533 * Enable or disable Bus Mastering 534 * 535 * Note that all other bits are taken from the original value saved 536 * the first time through here, rather than from the current register 537 * value, 'cos that will have been cleared by a soft RESET since. 538 * In this way we preserve the OBP/nexus-parent's preferred settings 539 * of the parity-error and system-error enable bits across multiple 540 * chip RESETs. 541 * 542 * Step 8: Disable PCI-X Relaxed Ordering -- doesn't apply 543 */ 544 command = bgep->chipid.command | PCI_COMM_MAE; 545 command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL); 546 if (enable_dma) 547 command |= PCI_COMM_ME; 548 /* 549 * on BCM5714 revision A0, false parity error gets generated 550 * due to a logic bug. Provide a workaround by disabling parrity 551 * error. 552 */ 553 if (((cidp->device == DEVICE_ID_5714C) || 554 (cidp->device == DEVICE_ID_5714S)) && 555 (cidp->revision == REVISION_ID_5714_A0)) { 556 command &= ~PCI_COMM_PARITY_DETECT; 557 } 558 pci_config_put16(handle, PCI_CONF_COMM, command); 559 560 /* 561 * On some PCI-E device, there were instances when 562 * the device was still link training. 563 */ 564 if (bgep->chipid.pci_type == BGE_PCI_E) { 565 i = 0; 566 value16 = pci_config_get16(handle, PCI_CONF_COMM); 567 while ((value16 != command) && (i < 100)) { 568 drv_usecwait(200); 569 value16 = pci_config_get16(handle, PCI_CONF_COMM); 570 ++i; 571 } 572 } 573 574 /* 575 * Clear any remaining error status bits 576 */ 577 pci_config_put16(handle, PCI_CONF_STAT, ~0); 578 579 /* 580 * Make sure these indirect-access registers are sane 581 * rather than random after power-up or reset 582 * 583 * For BCM5714C A3 silicon to avoid resource deadlocking 584 */ 585 if ((cidp->device == DEVICE_ID_5714C) && 586 (cidp->revision == REVISION_ID_5714_A3)) { 587 pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0x4900); 588 pci_config_put32(handle, PCI_CONF_BGE_RIADR, 1); 589 } else { 590 pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0); 591 pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0); 592 } 593 } 594 595 #ifdef __amd64 596 /* 597 * Distinguish CPU types 598 * 599 * These use to distinguish AMD64 or Intel EM64T of CPU running mode. 600 * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine 601 * for PCI-Express based network interface card. This is the work-around 602 * for those nics. 603 */ 604 static boolean_t bge_get_em64t_type(void); 605 #pragma inline(bge_get_em64t_type) 606 607 static boolean_t 608 bge_get_em64t_type(void) 609 { 610 611 return (x86_vendor == X86_VENDOR_Intel); 612 } 613 #endif 614 615 /* 616 * Operating register get/set access routines 617 */ 618 619 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno); 620 #pragma inline(bge_reg_get32) 621 622 uint32_t 623 bge_reg_get32(bge_t *bgep, bge_regno_t regno) 624 { 625 BGE_TRACE(("bge_reg_get32($%p, 0x%lx)", 626 (void *)bgep, regno)); 627 628 return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno))); 629 } 630 631 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data); 632 #pragma inline(bge_reg_put32) 633 634 void 635 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data) 636 { 637 BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)", 638 (void *)bgep, regno, data)); 639 640 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data); 641 BGE_PCICHK(bgep); 642 } 643 644 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 645 #pragma inline(bge_reg_set32) 646 647 void 648 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 649 { 650 uint32_t regval; 651 652 BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)", 653 (void *)bgep, regno, bits)); 654 655 regval = bge_reg_get32(bgep, regno); 656 regval |= bits; 657 bge_reg_put32(bgep, regno, regval); 658 } 659 660 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 661 #pragma inline(bge_reg_clr32) 662 663 void 664 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 665 { 666 uint32_t regval; 667 668 BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)", 669 (void *)bgep, regno, bits)); 670 671 regval = bge_reg_get32(bgep, regno); 672 regval &= ~bits; 673 bge_reg_put32(bgep, regno, regval); 674 } 675 676 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno); 677 #pragma inline(bge_reg_get64) 678 679 static uint64_t 680 bge_reg_get64(bge_t *bgep, bge_regno_t regno) 681 { 682 uint64_t regval; 683 684 #ifdef __amd64 685 if (bge_get_em64t_type()) { 686 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 687 regval <<= 32; 688 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 689 } else { 690 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 691 } 692 #else 693 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 694 #endif 695 696 #ifdef _LITTLE_ENDIAN 697 regval = (regval >> 32) | (regval << 32); 698 #endif /* _LITTLE_ENDIAN */ 699 700 BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx", 701 (void *)bgep, regno, regval)); 702 703 return (regval); 704 } 705 706 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data); 707 #pragma inline(bge_reg_put64) 708 709 static void 710 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data) 711 { 712 BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)", 713 (void *)bgep, regno, data)); 714 715 #ifdef _LITTLE_ENDIAN 716 data = ((data >> 32) | (data << 32)); 717 #endif /* _LITTLE_ENDIAN */ 718 719 #ifdef __amd64 720 if (bge_get_em64t_type()) { 721 ddi_put32(bgep->io_handle, 722 PIO_ADDR(bgep, regno), (uint32_t)data); 723 BGE_PCICHK(bgep); 724 ddi_put32(bgep->io_handle, 725 PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32)); 726 727 } else { 728 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 729 } 730 #else 731 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 732 #endif 733 734 BGE_PCICHK(bgep); 735 } 736 737 /* 738 * The DDI doesn't provide get/put functions for 128 bit data 739 * so we put RCBs out as two 64-bit chunks instead. 740 */ 741 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 742 #pragma inline(bge_reg_putrcb) 743 744 static void 745 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 746 { 747 uint64_t *p; 748 749 BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 750 (void *)bgep, addr, rcbp->host_ring_addr, 751 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 752 753 ASSERT((addr % sizeof (*rcbp)) == 0); 754 755 p = (void *)rcbp; 756 bge_reg_put64(bgep, addr, *p++); 757 bge_reg_put64(bgep, addr+8, *p); 758 } 759 760 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data); 761 #pragma inline(bge_mbx_put) 762 763 void 764 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data) 765 { 766 BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)", 767 (void *)bgep, regno, data)); 768 769 /* 770 * Mailbox registers are nominally 64 bits on the 5701, but 771 * the MSW isn't used. On the 5703, they're only 32 bits 772 * anyway. So here we just write the lower(!) 32 bits - 773 * remembering that the chip is big-endian, even though the 774 * PCI bus is little-endian ... 775 */ 776 #ifdef _BIG_ENDIAN 777 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data); 778 #else 779 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data); 780 #endif /* _BIG_ENDIAN */ 781 BGE_PCICHK(bgep); 782 } 783 784 #if BGE_DEBUGGING 785 786 void bge_led_mark(bge_t *bgep); 787 #pragma no_inline(bge_led_mark) 788 789 void 790 bge_led_mark(bge_t *bgep) 791 { 792 uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK | 793 LED_CONTROL_1000MBPS_LED | 794 LED_CONTROL_100MBPS_LED | 795 LED_CONTROL_10MBPS_LED; 796 797 /* 798 * Blink all three LINK LEDs on simultaneously, then all off, 799 * then restore to automatic hardware control. This is used 800 * in laboratory testing to trigger a logic analyser or scope. 801 */ 802 bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 803 led_ctrl ^= LED_CONTROL_OVERRIDE_LINK; 804 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 805 led_ctrl = LED_CONTROL_OVERRIDE_LINK; 806 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 807 } 808 809 #endif /* BGE_DEBUGGING */ 810 811 /* 812 * NIC on-chip memory access routines 813 * 814 * Only 32K of NIC memory is visible at a time, controlled by the 815 * Memory Window Base Address Register (in PCI config space). Once 816 * this is set, the 32K region of NIC-local memory that it refers 817 * to can be directly addressed in the upper 32K of the 64K of PCI 818 * memory space used for the device. 819 */ 820 821 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base); 822 #pragma inline(bge_nic_setwin) 823 824 static void 825 bge_nic_setwin(bge_t *bgep, bge_regno_t base) 826 { 827 BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)", 828 (void *)bgep, base)); 829 830 ASSERT((base & MWBAR_GRANULE_MASK) == 0); 831 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base); 832 } 833 834 835 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr); 836 #pragma inline(bge_nic_get32) 837 838 static uint32_t 839 bge_nic_get32(bge_t *bgep, bge_regno_t addr) 840 { 841 uint32_t data; 842 843 #ifdef BGE_IPMI_ASF 844 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 845 /* workaround for word swap error */ 846 if (addr & 4) 847 addr = addr - 4; 848 else 849 addr = addr + 4; 850 } 851 #endif 852 853 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 854 addr &= MWBAR_GRANULE_MASK; 855 addr += NIC_MEM_WINDOW_OFFSET; 856 857 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 858 859 BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x", 860 (void *)bgep, addr, data)); 861 862 return (data); 863 } 864 865 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data); 866 #pragma inline(bge_nic_put32) 867 868 void 869 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data) 870 { 871 BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)", 872 (void *)bgep, addr, data)); 873 874 #ifdef BGE_IPMI_ASF 875 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 876 /* workaround for word swap error */ 877 if (addr & 4) 878 addr = addr - 4; 879 else 880 addr = addr + 4; 881 } 882 #endif 883 884 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 885 addr &= MWBAR_GRANULE_MASK; 886 addr += NIC_MEM_WINDOW_OFFSET; 887 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data); 888 BGE_PCICHK(bgep); 889 } 890 891 892 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr); 893 #pragma inline(bge_nic_get64) 894 895 static uint64_t 896 bge_nic_get64(bge_t *bgep, bge_regno_t addr) 897 { 898 uint64_t data; 899 900 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 901 addr &= MWBAR_GRANULE_MASK; 902 addr += NIC_MEM_WINDOW_OFFSET; 903 904 #ifdef __amd64 905 if (bge_get_em64t_type()) { 906 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 907 data <<= 32; 908 data |= ddi_get32(bgep->io_handle, 909 PIO_ADDR(bgep, addr + 4)); 910 } else { 911 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 912 } 913 #else 914 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 915 #endif 916 917 BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx", 918 (void *)bgep, addr, data)); 919 920 return (data); 921 } 922 923 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data); 924 #pragma inline(bge_nic_put64) 925 926 static void 927 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data) 928 { 929 BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)", 930 (void *)bgep, addr, data)); 931 932 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 933 addr &= MWBAR_GRANULE_MASK; 934 addr += NIC_MEM_WINDOW_OFFSET; 935 936 #ifdef __amd64 937 if (bge_get_em64t_type()) { 938 ddi_put32(bgep->io_handle, 939 PIO_ADDR(bgep, addr), (uint32_t)data); 940 BGE_PCICHK(bgep); 941 ddi_put32(bgep->io_handle, 942 PIO_ADDR(bgep, addr + 4), (uint32_t)(data >> 32)); 943 } else { 944 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 945 } 946 #else 947 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 948 #endif 949 950 BGE_PCICHK(bgep); 951 } 952 953 /* 954 * The DDI doesn't provide get/put functions for 128 bit data 955 * so we put RCBs out as two 64-bit chunks instead. 956 */ 957 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 958 #pragma inline(bge_nic_putrcb) 959 960 static void 961 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 962 { 963 uint64_t *p; 964 965 BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 966 (void *)bgep, addr, rcbp->host_ring_addr, 967 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 968 969 ASSERT((addr % sizeof (*rcbp)) == 0); 970 971 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 972 addr &= MWBAR_GRANULE_MASK; 973 addr += NIC_MEM_WINDOW_OFFSET; 974 975 p = (void *)rcbp; 976 #ifdef __amd64 977 if (bge_get_em64t_type()) { 978 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 979 (uint32_t)(*p)); 980 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 981 (uint32_t)(*p >> 32)); 982 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 983 (uint32_t)(*(p + 1))); 984 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 985 (uint32_t)(*p >> 32)); 986 987 } else { 988 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 989 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p); 990 } 991 #else 992 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 993 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 994 #endif 995 996 BGE_PCICHK(bgep); 997 } 998 999 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes); 1000 #pragma inline(bge_nic_zero) 1001 1002 static void 1003 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes) 1004 { 1005 BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)", 1006 (void *)bgep, addr, nbytes)); 1007 1008 ASSERT((addr & ~MWBAR_GRANULE_MASK) == 1009 ((addr+nbytes) & ~MWBAR_GRANULE_MASK)); 1010 1011 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 1012 addr &= MWBAR_GRANULE_MASK; 1013 addr += NIC_MEM_WINDOW_OFFSET; 1014 1015 (void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr), 1016 nbytes, 1, DDI_DATA_SZ08_ACC); 1017 BGE_PCICHK(bgep); 1018 } 1019 1020 /* 1021 * MII (PHY) register get/set access routines 1022 * 1023 * These use the chip's MII auto-access method, controlled by the 1024 * MII Communication register at 0x044c, so the CPU doesn't have 1025 * to fiddle with the individual bits. 1026 */ 1027 1028 #undef BGE_DBG 1029 #define BGE_DBG BGE_DBG_MII /* debug flag for this code */ 1030 1031 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno, 1032 uint16_t data, uint32_t cmd); 1033 #pragma no_inline(bge_mii_access) 1034 1035 static uint16_t 1036 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd) 1037 { 1038 uint32_t timeout; 1039 uint32_t regval1; 1040 uint32_t regval2; 1041 1042 BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)", 1043 (void *)bgep, regno, data, cmd)); 1044 1045 ASSERT(mutex_owned(bgep->genlock)); 1046 1047 /* 1048 * Assemble the command ... 1049 */ 1050 cmd |= data << MI_COMMS_DATA_SHIFT; 1051 cmd |= regno << MI_COMMS_REGISTER_SHIFT; 1052 cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT; 1053 cmd |= MI_COMMS_START; 1054 1055 /* 1056 * Wait for any command already in progress ... 1057 * 1058 * Note: this *shouldn't* ever find that there is a command 1059 * in progress, because we already hold the <genlock> mutex. 1060 * Nonetheless, we have sometimes seen the MI_COMMS_START 1061 * bit set here -- it seems that the chip can initiate MII 1062 * accesses internally, even with polling OFF. 1063 */ 1064 regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1065 for (timeout = 1000; ; ) { 1066 if ((regval2 & MI_COMMS_START) == 0) { 1067 bge_reg_put32(bgep, MI_COMMS_REG, cmd); 1068 break; 1069 } 1070 if (--timeout == 0) 1071 break; 1072 drv_usecwait(10); 1073 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1074 } 1075 1076 if (timeout != 1000) 1077 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1078 "MI_COMMS_START set for %d us; 0x%x->0x%x", 1079 cmd, 10*(1000-timeout), regval1, regval2)); 1080 1081 ASSERT(timeout != 0); 1082 if (timeout == 0) 1083 return ((uint16_t)~0u); 1084 1085 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1086 for (timeout = 1000; ; ) { 1087 if ((regval1 & MI_COMMS_START) == 0) 1088 break; 1089 if (--timeout == 0) 1090 break; 1091 drv_usecwait(10); 1092 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1093 } 1094 1095 /* 1096 * Drop out early if the READ FAILED bit is set -- this chip 1097 * could be a 5703/4S, with a SerDes instead of a PHY! 1098 */ 1099 if (regval2 & MI_COMMS_READ_FAILED) 1100 return ((uint16_t)~0u); 1101 1102 ASSERT(timeout != 0); 1103 if (timeout == 0) 1104 return ((uint16_t)~0u); 1105 1106 /* 1107 * The PRM says to wait 5us after seeing the START bit clear 1108 * and then re-read the register to get the final value of the 1109 * data field, in order to avoid a race condition where the 1110 * START bit is clear but the data field isn't yet valid. 1111 * 1112 * Note: we don't actually seem to be encounter this race; 1113 * except when the START bit is seen set again (see below), 1114 * the data field doesn't change during this 5us interval. 1115 */ 1116 drv_usecwait(5); 1117 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1118 1119 /* 1120 * Unfortunately, when following the PRMs instructions above, 1121 * we have occasionally seen the START bit set again(!) in the 1122 * value read after the 5us delay. This seems to be due to the 1123 * chip autonomously starting another MII access internally. 1124 * In such cases, the command/data/etc fields relate to the 1125 * internal command, rather than the one that we thought had 1126 * just finished. So in this case, we fall back to returning 1127 * the data from the original read that showed START clear. 1128 */ 1129 if (regval2 & MI_COMMS_START) { 1130 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1131 "MI_COMMS_START set after transaction; 0x%x->0x%x", 1132 cmd, regval1, regval2)); 1133 regval2 = regval1; 1134 } 1135 1136 ASSERT((regval2 & MI_COMMS_START) == 0); 1137 if (regval2 & MI_COMMS_START) 1138 return ((uint16_t)~0u); 1139 1140 ASSERT((regval2 & MI_COMMS_READ_FAILED) == 0); 1141 if (regval2 & MI_COMMS_READ_FAILED) 1142 return ((uint16_t)~0u); 1143 1144 return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT); 1145 } 1146 1147 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno); 1148 #pragma no_inline(bge_mii_get16) 1149 1150 uint16_t 1151 bge_mii_get16(bge_t *bgep, bge_regno_t regno) 1152 { 1153 BGE_TRACE(("bge_mii_get16($%p, 0x%lx)", 1154 (void *)bgep, regno)); 1155 1156 ASSERT(mutex_owned(bgep->genlock)); 1157 1158 return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ)); 1159 } 1160 1161 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data); 1162 #pragma no_inline(bge_mii_put16) 1163 1164 void 1165 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data) 1166 { 1167 BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)", 1168 (void *)bgep, regno, data)); 1169 1170 ASSERT(mutex_owned(bgep->genlock)); 1171 1172 (void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE); 1173 } 1174 1175 #undef BGE_DBG 1176 #define BGE_DBG BGE_DBG_SEEPROM /* debug flag for this code */ 1177 1178 #if BGE_SEE_IO32 || BGE_FLASH_IO32 1179 1180 /* 1181 * Basic SEEPROM get/set access routine 1182 * 1183 * This uses the chip's SEEPROM auto-access method, controlled by the 1184 * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU 1185 * doesn't have to fiddle with the individual bits. 1186 * 1187 * The caller should hold <genlock> and *also* have already acquired 1188 * the right to access the SEEPROM, via bge_nvmem_acquire() above. 1189 * 1190 * Return value: 1191 * 0 on success, 1192 * ENODATA on access timeout (maybe retryable: device may just be busy) 1193 * EPROTO on other h/w or s/w errors. 1194 * 1195 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output 1196 * from a (successful) SEEPROM_ACCESS_READ. 1197 */ 1198 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1199 uint32_t *dp); 1200 #pragma no_inline(bge_seeprom_access) 1201 1202 static int 1203 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1204 { 1205 uint32_t tries; 1206 uint32_t regval; 1207 1208 ASSERT(mutex_owned(bgep->genlock)); 1209 1210 /* 1211 * On the newer chips that support both SEEPROM & Flash, we need 1212 * to specifically enable SEEPROM access (Flash is the default). 1213 * On older chips, we don't; SEEPROM is the only NVtype supported, 1214 * and the NVM control registers don't exist ... 1215 */ 1216 switch (bgep->chipid.nvtype) { 1217 case BGE_NVTYPE_NONE: 1218 case BGE_NVTYPE_UNKNOWN: 1219 _NOTE(NOTREACHED) 1220 case BGE_NVTYPE_SEEPROM: 1221 break; 1222 1223 case BGE_NVTYPE_LEGACY_SEEPROM: 1224 case BGE_NVTYPE_UNBUFFERED_FLASH: 1225 case BGE_NVTYPE_BUFFERED_FLASH: 1226 default: 1227 bge_reg_set32(bgep, NVM_CONFIG1_REG, 1228 NVM_CFG1_LEGACY_SEEPROM_MODE); 1229 break; 1230 } 1231 1232 /* 1233 * Check there's no command in progress. 1234 * 1235 * Note: this *shouldn't* ever find that there is a command 1236 * in progress, because we already hold the <genlock> mutex. 1237 * Also, to ensure we don't have a conflict with the chip's 1238 * internal firmware or a process accessing the same (shared) 1239 * SEEPROM through the other port of a 5704, we've already 1240 * been through the "software arbitration" protocol. 1241 * So this is just a final consistency check: we shouldn't 1242 * see EITHER the START bit (command started but not complete) 1243 * OR the COMPLETE bit (command completed but not cleared). 1244 */ 1245 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1246 if (regval & SEEPROM_ACCESS_START) 1247 return (EPROTO); 1248 if (regval & SEEPROM_ACCESS_COMPLETE) 1249 return (EPROTO); 1250 1251 /* 1252 * Assemble the command ... 1253 */ 1254 cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK; 1255 addr >>= SEEPROM_ACCESS_ADDRESS_SIZE; 1256 addr <<= SEEPROM_ACCESS_DEVID_SHIFT; 1257 cmd |= addr & SEEPROM_ACCESS_DEVID_MASK; 1258 cmd |= SEEPROM_ACCESS_START; 1259 cmd |= SEEPROM_ACCESS_COMPLETE; 1260 cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK; 1261 1262 bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp); 1263 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd); 1264 1265 /* 1266 * By observation, a successful access takes ~20us on a 5703/4, 1267 * but apparently much longer (up to 1000us) on the obsolescent 1268 * BCM5700/BCM5701. We want to be sure we don't get any false 1269 * timeouts here; but OTOH, we don't want a bogus access to lock 1270 * out interrupts for longer than necessary. So we'll allow up 1271 * to 1000us ... 1272 */ 1273 for (tries = 0; tries < 1000; ++tries) { 1274 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1275 if (regval & SEEPROM_ACCESS_COMPLETE) 1276 break; 1277 drv_usecwait(1); 1278 } 1279 1280 ASSERT((regval & SEEPROM_ACCESS_START) == 0); 1281 if (regval & SEEPROM_ACCESS_COMPLETE) { 1282 /* 1283 * All OK; read the SEEPROM data register, then write back 1284 * the value read from the address register in order to 1285 * clear the <complete> bit and leave the SEEPROM access 1286 * state machine idle, ready for the next access ... 1287 */ 1288 BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries)); 1289 *dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG); 1290 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval); 1291 return (0); 1292 } 1293 1294 /* 1295 * Hmm ... what happened here? 1296 * 1297 * Most likely, the user addressed an non-existent SEEPROM. Or 1298 * maybe the SEEPROM was busy internally (e.g. processing a write) 1299 * and didn't respond to being addressed. Either way, it's left 1300 * the SEEPROM access state machine wedged. So we'll reset it 1301 * before we leave, so it's ready for next time ... 1302 */ 1303 BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries)); 1304 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 1305 return (ENODATA); 1306 } 1307 1308 /* 1309 * Basic Flash get/set access routine 1310 * 1311 * These use the chip's Flash auto-access method, controlled by the 1312 * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to 1313 * fiddle with the individual bits. 1314 * 1315 * The caller should hold <genlock> and *also* have already acquired 1316 * the right to access the Flash, via bge_nvmem_acquire() above. 1317 * 1318 * Return value: 1319 * 0 on success, 1320 * ENODATA on access timeout (maybe retryable: device may just be busy) 1321 * ENODEV if the NVmem device is missing or otherwise unusable 1322 * 1323 * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output 1324 * from a (successful) NVM_FLASH_CMD_RD. 1325 */ 1326 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1327 uint32_t *dp); 1328 #pragma no_inline(bge_flash_access) 1329 1330 static int 1331 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1332 { 1333 uint32_t tries; 1334 uint32_t regval; 1335 1336 ASSERT(mutex_owned(bgep->genlock)); 1337 1338 /* 1339 * On the newer chips that support both SEEPROM & Flash, we need 1340 * to specifically disable SEEPROM access while accessing Flash. 1341 * The older chips don't support Flash, and the NVM registers don't 1342 * exist, so we shouldn't be here at all! 1343 */ 1344 switch (bgep->chipid.nvtype) { 1345 case BGE_NVTYPE_NONE: 1346 case BGE_NVTYPE_UNKNOWN: 1347 _NOTE(NOTREACHED) 1348 case BGE_NVTYPE_SEEPROM: 1349 return (ENODEV); 1350 1351 case BGE_NVTYPE_LEGACY_SEEPROM: 1352 case BGE_NVTYPE_UNBUFFERED_FLASH: 1353 case BGE_NVTYPE_BUFFERED_FLASH: 1354 default: 1355 bge_reg_clr32(bgep, NVM_CONFIG1_REG, 1356 NVM_CFG1_LEGACY_SEEPROM_MODE); 1357 break; 1358 } 1359 1360 /* 1361 * Assemble the command ... 1362 */ 1363 addr &= NVM_FLASH_ADDR_MASK; 1364 cmd |= NVM_FLASH_CMD_DOIT; 1365 cmd |= NVM_FLASH_CMD_FIRST; 1366 cmd |= NVM_FLASH_CMD_LAST; 1367 cmd |= NVM_FLASH_CMD_DONE; 1368 1369 bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp); 1370 bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr); 1371 bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd); 1372 1373 /* 1374 * Allow up to 1000ms ... 1375 */ 1376 for (tries = 0; tries < 1000; ++tries) { 1377 regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG); 1378 if (regval & NVM_FLASH_CMD_DONE) 1379 break; 1380 drv_usecwait(1); 1381 } 1382 1383 if (regval & NVM_FLASH_CMD_DONE) { 1384 /* 1385 * All OK; read the data from the Flash read register 1386 */ 1387 BGE_DEBUG(("bge_flash_access: complete after %d us", tries)); 1388 *dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG); 1389 return (0); 1390 } 1391 1392 /* 1393 * Hmm ... what happened here? 1394 * 1395 * Most likely, the user addressed an non-existent Flash. Or 1396 * maybe the Flash was busy internally (e.g. processing a write) 1397 * and didn't respond to being addressed. Either way, there's 1398 * nothing we can here ... 1399 */ 1400 BGE_DEBUG(("bge_flash_access: timed out after %d us", tries)); 1401 return (ENODATA); 1402 } 1403 1404 /* 1405 * The next two functions regulate access to the NVram (if fitted). 1406 * 1407 * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash 1408 * (SPI) interface, but they can be accessed through either port. These 1409 * are managed by different instance of this driver and have no software 1410 * state in common. 1411 * 1412 * In addition (and even on a single core chip) the chip's internal 1413 * firmware can access the SEEPROM/Flash, most notably after a RESET 1414 * when it may download code to run internally. 1415 * 1416 * So we need to arbitrate between these various software agents. For 1417 * this purpose, the chip provides the Software Arbitration Register, 1418 * which implements hardware(!) arbitration. 1419 * 1420 * This functionality didn't exist on older (5700/5701) chips, so there's 1421 * nothing we can do by way of arbitration on those; also, if there's no 1422 * SEEPROM/Flash fitted (or we couldn't determine what type), there's also 1423 * nothing to do. 1424 * 1425 * The internal firmware appears to use Request 0, which is the highest 1426 * priority. So we'd like to use Request 2, leaving one higher and one 1427 * lower for any future developments ... but apparently this doesn't 1428 * always work. So for now, the code uses Request 1 ;-( 1429 */ 1430 1431 #define NVM_READ_REQ NVM_READ_REQ1 1432 #define NVM_RESET_REQ NVM_RESET_REQ1 1433 #define NVM_SET_REQ NVM_SET_REQ1 1434 1435 static void bge_nvmem_relinquish(bge_t *bgep); 1436 #pragma no_inline(bge_nvmem_relinquish) 1437 1438 static void 1439 bge_nvmem_relinquish(bge_t *bgep) 1440 { 1441 uint32_t regval; 1442 1443 ASSERT(mutex_owned(bgep->genlock)); 1444 1445 switch (bgep->chipid.nvtype) { 1446 case BGE_NVTYPE_NONE: 1447 case BGE_NVTYPE_UNKNOWN: 1448 _NOTE(NOTREACHED) 1449 return; 1450 1451 case BGE_NVTYPE_SEEPROM: 1452 /* 1453 * No arbitration performed, no release needed 1454 */ 1455 return; 1456 1457 case BGE_NVTYPE_LEGACY_SEEPROM: 1458 case BGE_NVTYPE_UNBUFFERED_FLASH: 1459 case BGE_NVTYPE_BUFFERED_FLASH: 1460 default: 1461 break; 1462 } 1463 1464 /* 1465 * Our own request should be present (whether or not granted) ... 1466 */ 1467 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1468 ASSERT((regval & NVM_READ_REQ) != 0); 1469 1470 /* 1471 * ... this will make it go away. 1472 */ 1473 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ); 1474 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1475 ASSERT((regval & NVM_READ_REQ) == 0); 1476 } 1477 1478 /* 1479 * Arbitrate for access to the NVmem, if necessary 1480 * 1481 * Return value: 1482 * 0 on success 1483 * EAGAIN if the device is in use (retryable) 1484 * ENODEV if the NVmem device is missing or otherwise unusable 1485 */ 1486 static int bge_nvmem_acquire(bge_t *bgep); 1487 #pragma no_inline(bge_nvmem_acquire) 1488 1489 static int 1490 bge_nvmem_acquire(bge_t *bgep) 1491 { 1492 uint32_t regval; 1493 uint32_t tries; 1494 1495 ASSERT(mutex_owned(bgep->genlock)); 1496 1497 switch (bgep->chipid.nvtype) { 1498 case BGE_NVTYPE_NONE: 1499 case BGE_NVTYPE_UNKNOWN: 1500 /* 1501 * Access denied: no (recognisable) device fitted 1502 */ 1503 return (ENODEV); 1504 1505 case BGE_NVTYPE_SEEPROM: 1506 /* 1507 * Access granted: no arbitration needed (or possible) 1508 */ 1509 return (0); 1510 1511 case BGE_NVTYPE_LEGACY_SEEPROM: 1512 case BGE_NVTYPE_UNBUFFERED_FLASH: 1513 case BGE_NVTYPE_BUFFERED_FLASH: 1514 default: 1515 /* 1516 * Access conditional: conduct arbitration protocol 1517 */ 1518 break; 1519 } 1520 1521 /* 1522 * We're holding the per-port mutex <genlock>, so no-one other 1523 * threads can be attempting to access the NVmem through *this* 1524 * port. But it could be in use by the *other* port (of a 5704), 1525 * or by the chip's internal firmware, so we have to go through 1526 * the full (hardware) arbitration protocol ... 1527 * 1528 * Note that *because* we're holding <genlock>, the interrupt handler 1529 * won't be able to progress. So we're only willing to spin for a 1530 * fairly short time. Specifically: 1531 * 1532 * We *must* wait long enough for the hardware to resolve all 1533 * requests and determine the winner. Fortunately, this is 1534 * "almost instantaneous", even as observed by GHz CPUs. 1535 * 1536 * A successful access by another Solaris thread (via either 1537 * port) typically takes ~20us. So waiting a bit longer than 1538 * that will give a good chance of success, if the other user 1539 * *is* another thread on the other port. 1540 * 1541 * However, the internal firmware can hold on to the NVmem 1542 * for *much* longer: at least 10 milliseconds just after a 1543 * RESET, and maybe even longer if the NVmem actually contains 1544 * code to download and run on the internal CPUs. 1545 * 1546 * So, we'll allow 50us; if that's not enough then it's up to the 1547 * caller to retry later (hence the choice of return code EAGAIN). 1548 */ 1549 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1550 ASSERT((regval & NVM_READ_REQ) == 0); 1551 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ); 1552 1553 for (tries = 0; tries < 50; ++tries) { 1554 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1555 ASSERT((regval & NVM_READ_REQ) != 0); 1556 if (regval & NVM_WON_REQ1) 1557 break; 1558 drv_usecwait(1); 1559 } 1560 1561 if (regval & NVM_WON_REQ1) { 1562 BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries)); 1563 return (0); 1564 } 1565 1566 /* 1567 * Somebody else must be accessing the NVmem, so abandon our 1568 * attempt take control of it. The caller can try again later ... 1569 */ 1570 BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries)); 1571 bge_nvmem_relinquish(bgep); 1572 return (EAGAIN); 1573 } 1574 1575 /* 1576 * This code assumes that the GPIO1 bit has been wired up to the NVmem 1577 * write protect line in such a way that the NVmem is protected when 1578 * GPIO1 is an input, or is an output but driven high. Thus, to make the 1579 * NVmem writable we have to change GPIO1 to an output AND drive it low. 1580 * 1581 * Note: there's only one set of GPIO pins on a 5704, even though they 1582 * can be accessed through either port. So the chip has to resolve what 1583 * happens if the two ports program a single pin differently ... the rule 1584 * it uses is that if the ports disagree about the *direction* of a pin, 1585 * "output" wins over "input", but if they disagree about its *value* as 1586 * an output, then the pin is TRISTATED instead! In such a case, no-one 1587 * wins, and the external signal does whatever the external circuitry 1588 * defines as the default -- which we've assumed is the PROTECTED state. 1589 * So, we always change GPIO1 back to being an *input* whenever we're not 1590 * specifically using it to unprotect the NVmem. This allows either port 1591 * to update the NVmem, although obviously only one at a a time! 1592 * 1593 * The caller should hold <genlock> and *also* have already acquired the 1594 * right to access the NVmem, via bge_nvmem_acquire() above. 1595 */ 1596 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect); 1597 #pragma inline(bge_nvmem_protect) 1598 1599 static void 1600 bge_nvmem_protect(bge_t *bgep, boolean_t protect) 1601 { 1602 uint32_t regval; 1603 1604 ASSERT(mutex_owned(bgep->genlock)); 1605 1606 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 1607 if (protect) { 1608 regval |= MLCR_MISC_PINS_OUTPUT_1; 1609 regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1610 } else { 1611 regval &= ~MLCR_MISC_PINS_OUTPUT_1; 1612 regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1613 } 1614 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval); 1615 } 1616 1617 /* 1618 * Now put it all together ... 1619 * 1620 * Try to acquire control of the NVmem; if successful, then: 1621 * unprotect it (if we want to write to it) 1622 * perform the requested access 1623 * reprotect it (after a write) 1624 * relinquish control 1625 * 1626 * Return value: 1627 * 0 on success, 1628 * EAGAIN if the device is in use (retryable) 1629 * ENODATA on access timeout (maybe retryable: device may just be busy) 1630 * ENODEV if the NVmem device is missing or otherwise unusable 1631 * EPROTO on other h/w or s/w errors. 1632 */ 1633 static int 1634 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1635 { 1636 int err; 1637 1638 if ((err = bge_nvmem_acquire(bgep)) == 0) { 1639 switch (cmd) { 1640 case BGE_SEE_READ: 1641 err = bge_seeprom_access(bgep, 1642 SEEPROM_ACCESS_READ, addr, dp); 1643 break; 1644 1645 case BGE_SEE_WRITE: 1646 bge_nvmem_protect(bgep, B_FALSE); 1647 err = bge_seeprom_access(bgep, 1648 SEEPROM_ACCESS_WRITE, addr, dp); 1649 bge_nvmem_protect(bgep, B_TRUE); 1650 break; 1651 1652 case BGE_FLASH_READ: 1653 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1654 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1655 bge_reg_set32(bgep, NVM_ACCESS_REG, 1656 NVM_ACCESS_ENABLE); 1657 } 1658 err = bge_flash_access(bgep, 1659 NVM_FLASH_CMD_RD, addr, dp); 1660 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1661 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1662 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1663 NVM_ACCESS_ENABLE); 1664 } 1665 break; 1666 1667 case BGE_FLASH_WRITE: 1668 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1669 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1670 bge_reg_set32(bgep, NVM_ACCESS_REG, 1671 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1672 } 1673 bge_nvmem_protect(bgep, B_FALSE); 1674 err = bge_flash_access(bgep, 1675 NVM_FLASH_CMD_WR, addr, dp); 1676 bge_nvmem_protect(bgep, B_TRUE); 1677 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1678 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1679 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1680 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1681 } 1682 1683 break; 1684 1685 default: 1686 _NOTE(NOTREACHED) 1687 break; 1688 } 1689 bge_nvmem_relinquish(bgep); 1690 } 1691 1692 BGE_DEBUG(("bge_nvmem_rw32: err %d", err)); 1693 return (err); 1694 } 1695 1696 /* 1697 * Attempt to get a MAC address from the SEEPROM or Flash, if any 1698 */ 1699 static uint64_t bge_get_nvmac(bge_t *bgep); 1700 #pragma no_inline(bge_get_nvmac) 1701 1702 static uint64_t 1703 bge_get_nvmac(bge_t *bgep) 1704 { 1705 uint32_t mac_high; 1706 uint32_t mac_low; 1707 uint32_t addr; 1708 uint32_t cmd; 1709 uint64_t mac; 1710 1711 BGE_TRACE(("bge_get_nvmac($%p)", 1712 (void *)bgep)); 1713 1714 switch (bgep->chipid.nvtype) { 1715 case BGE_NVTYPE_NONE: 1716 case BGE_NVTYPE_UNKNOWN: 1717 default: 1718 return (0ULL); 1719 1720 case BGE_NVTYPE_SEEPROM: 1721 case BGE_NVTYPE_LEGACY_SEEPROM: 1722 cmd = BGE_SEE_READ; 1723 break; 1724 1725 case BGE_NVTYPE_UNBUFFERED_FLASH: 1726 case BGE_NVTYPE_BUFFERED_FLASH: 1727 cmd = BGE_FLASH_READ; 1728 break; 1729 } 1730 1731 addr = NVMEM_DATA_MAC_ADDRESS; 1732 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high)) 1733 return (0ULL); 1734 addr += 4; 1735 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low)) 1736 return (0ULL); 1737 1738 /* 1739 * The Broadcom chip is natively BIG-endian, so that's how the 1740 * MAC address is represented in NVmem. We may need to swap it 1741 * around on a little-endian host ... 1742 */ 1743 #ifdef _BIG_ENDIAN 1744 mac = mac_high; 1745 mac = mac << 32; 1746 mac |= mac_low; 1747 #else 1748 mac = BGE_BSWAP_32(mac_high); 1749 mac = mac << 32; 1750 mac |= BGE_BSWAP_32(mac_low); 1751 #endif /* _BIG_ENDIAN */ 1752 1753 return (mac); 1754 } 1755 1756 #else /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1757 1758 /* 1759 * Dummy version for when we're not supporting NVmem access 1760 */ 1761 static uint64_t bge_get_nvmac(bge_t *bgep); 1762 #pragma inline(bge_get_nvmac) 1763 1764 static uint64_t 1765 bge_get_nvmac(bge_t *bgep) 1766 { 1767 _NOTE(ARGUNUSED(bgep)) 1768 return (0ULL); 1769 } 1770 1771 #endif /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1772 1773 /* 1774 * Determine the type of NVmem that is (or may be) attached to this chip, 1775 */ 1776 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep); 1777 #pragma no_inline(bge_nvmem_id) 1778 1779 static enum bge_nvmem_type 1780 bge_nvmem_id(bge_t *bgep) 1781 { 1782 enum bge_nvmem_type nvtype; 1783 uint32_t config1; 1784 1785 BGE_TRACE(("bge_nvmem_id($%p)", 1786 (void *)bgep)); 1787 1788 switch (bgep->chipid.device) { 1789 default: 1790 /* 1791 * We shouldn't get here; it means we don't recognise 1792 * the chip, which means we don't know how to determine 1793 * what sort of NVmem (if any) it has. So we'll say 1794 * NONE, to disable the NVmem access code ... 1795 */ 1796 nvtype = BGE_NVTYPE_NONE; 1797 break; 1798 1799 case DEVICE_ID_5700: 1800 case DEVICE_ID_5700x: 1801 case DEVICE_ID_5701: 1802 /* 1803 * These devices support *only* SEEPROMs 1804 */ 1805 nvtype = BGE_NVTYPE_SEEPROM; 1806 break; 1807 1808 case DEVICE_ID_5702: 1809 case DEVICE_ID_5702fe: 1810 case DEVICE_ID_5703C: 1811 case DEVICE_ID_5703S: 1812 case DEVICE_ID_5704C: 1813 case DEVICE_ID_5704S: 1814 case DEVICE_ID_5704: 1815 case DEVICE_ID_5705M: 1816 case DEVICE_ID_5705C: 1817 case DEVICE_ID_5706: 1818 case DEVICE_ID_5782: 1819 case DEVICE_ID_5788: 1820 case DEVICE_ID_5751: 1821 case DEVICE_ID_5751M: 1822 case DEVICE_ID_5721: 1823 case DEVICE_ID_5714C: 1824 case DEVICE_ID_5714S: 1825 case DEVICE_ID_5715C: 1826 config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG); 1827 if (config1 & NVM_CFG1_FLASH_MODE) 1828 if (config1 & NVM_CFG1_BUFFERED_MODE) 1829 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1830 else 1831 nvtype = BGE_NVTYPE_UNBUFFERED_FLASH; 1832 else 1833 nvtype = BGE_NVTYPE_LEGACY_SEEPROM; 1834 break; 1835 } 1836 1837 return (nvtype); 1838 } 1839 1840 #undef BGE_DBG 1841 #define BGE_DBG BGE_DBG_CHIP /* debug flag for this code */ 1842 1843 static void 1844 bge_init_recv_rule(bge_t *bgep) 1845 { 1846 bge_recv_rule_t *rulep; 1847 uint32_t i; 1848 1849 /* 1850 * receive rule: direct all TCP traffic to ring RULE_MATCH_TO_RING 1851 * 1. to direct UDP traffic, set: 1852 * rulep->control = RULE_PROTO_CONTROL; 1853 * rulep->mask_value = RULE_UDP_MASK_VALUE; 1854 * 2. to direct ICMP traffic, set: 1855 * rulep->control = RULE_PROTO_CONTROL; 1856 * rulep->mask_value = RULE_ICMP_MASK_VALUE; 1857 * 3. to direct traffic by source ip, set: 1858 * rulep->control = RULE_SIP_CONTROL; 1859 * rulep->mask_value = RULE_SIP_MASK_VALUE; 1860 */ 1861 rulep = bgep->recv_rules; 1862 rulep->control = RULE_PROTO_CONTROL; 1863 rulep->mask_value = RULE_TCP_MASK_VALUE; 1864 1865 /* 1866 * set receive rule registers 1867 */ 1868 rulep = bgep->recv_rules; 1869 for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) { 1870 bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value); 1871 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control); 1872 } 1873 } 1874 1875 /* 1876 * Using the values captured by bge_chip_cfg_init(), and additional probes 1877 * as required, characterise the chip fully: determine the label by which 1878 * to refer to this chip, the correct settings for various registers, and 1879 * of course whether the device and/or subsystem are supported! 1880 */ 1881 void bge_chip_id_init(bge_t *bgep); 1882 #pragma no_inline(bge_chip_id_init) 1883 1884 void 1885 bge_chip_id_init(bge_t *bgep) 1886 { 1887 char buf[MAXPATHLEN]; /* any risk of stack overflow? */ 1888 boolean_t sys_ok; 1889 boolean_t dev_ok; 1890 chip_id_t *cidp; 1891 uint32_t subid; 1892 char *devname; 1893 char *sysname; 1894 int *ids; 1895 int err; 1896 uint_t i; 1897 1898 ASSERT(bgep->bge_chip_state == BGE_CHIP_INITIAL); 1899 1900 sys_ok = dev_ok = B_FALSE; 1901 cidp = &bgep->chipid; 1902 1903 /* 1904 * Check the PCI device ID to determine the generic chip type and 1905 * select parameters that depend on this. 1906 * 1907 * Note: because the SPARC platforms in general don't fit the 1908 * SEEPROM 'behind' the chip, the PCI revision ID register reads 1909 * as zero - which is why we use <asic_rev> rather than <revision> 1910 * below ... 1911 * 1912 * Note: in general we can't distinguish between the Copper/SerDes 1913 * versions by ID alone, as some Copper devices (e.g. some but not 1914 * all 5703Cs) have the same ID as the SerDes equivalents. So we 1915 * treat them the same here, and the MII code works out the media 1916 * type later on ... 1917 */ 1918 cidp->mbuf_base = bge_mbuf_pool_base; 1919 cidp->mbuf_length = bge_mbuf_pool_len; 1920 cidp->recv_slots = BGE_RECV_SLOTS_USED; 1921 cidp->bge_dma_rwctrl = bge_dma_rwctrl; 1922 cidp->pci_type = BGE_PCI_X; 1923 cidp->statistic_type = BGE_STAT_BLK; 1924 1925 if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX) 1926 cidp->rx_rings = BGE_RECV_RINGS_DEFAULT; 1927 if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX) 1928 cidp->tx_rings = BGE_SEND_RINGS_DEFAULT; 1929 1930 cidp->msi_enabled = B_FALSE; 1931 1932 switch (cidp->device) { 1933 case DEVICE_ID_5700: 1934 case DEVICE_ID_5700x: 1935 cidp->chip_label = 5700; 1936 cidp->flags |= CHIP_FLAG_NO_CSUM; 1937 break; 1938 1939 case DEVICE_ID_5701: 1940 cidp->chip_label = 5701; 1941 dev_ok = B_TRUE; 1942 cidp->flags |= CHIP_FLAG_NO_CSUM; 1943 break; 1944 1945 case DEVICE_ID_5702: 1946 case DEVICE_ID_5702fe: 1947 cidp->chip_label = 5702; 1948 dev_ok = B_TRUE; 1949 cidp->flags |= CHIP_FLAG_NO_CSUM; /* for now */ 1950 break; 1951 1952 case DEVICE_ID_5703C: 1953 case DEVICE_ID_5703S: 1954 case DEVICE_ID_5703: 1955 /* 1956 * Revision A0 of the 5703/5793 had various errata 1957 * that we can't or don't work around, so it's not 1958 * supported, but all later versions are 1959 */ 1960 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703; 1961 if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0) 1962 dev_ok = B_TRUE; 1963 break; 1964 1965 case DEVICE_ID_5704C: 1966 case DEVICE_ID_5704S: 1967 case DEVICE_ID_5704: 1968 /* 1969 * Revision A0 of the 5704/5794 had various errata 1970 * but we have workarounds, so it *is* supported. 1971 */ 1972 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704; 1973 cidp->mbuf_base = bge_mbuf_pool_base_5704; 1974 cidp->mbuf_length = bge_mbuf_pool_len_5704; 1975 dev_ok = B_TRUE; 1976 break; 1977 1978 case DEVICE_ID_5705C: 1979 case DEVICE_ID_5705M: 1980 case DEVICE_ID_5705MA3: 1981 case DEVICE_ID_5705F: 1982 cidp->chip_label = 5705; 1983 cidp->mbuf_base = bge_mbuf_pool_base_5705; 1984 cidp->mbuf_length = bge_mbuf_pool_len_5705; 1985 cidp->recv_slots = BGE_RECV_SLOTS_5705; 1986 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 1987 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 1988 cidp->flags |= CHIP_FLAG_NO_JUMBO; 1989 cidp->statistic_type = BGE_STAT_REG; 1990 dev_ok = B_TRUE; 1991 break; 1992 1993 case DEVICE_ID_5706: 1994 cidp->chip_label = 5706; 1995 cidp->flags |= CHIP_FLAG_NO_JUMBO; 1996 cidp->flags |= CHIP_FLAG_NO_CSUM; /* for now */ 1997 break; 1998 1999 case DEVICE_ID_5782: 2000 /* 2001 * Apart from the label, we treat this as a 5705(?) 2002 */ 2003 cidp->chip_label = 5782; 2004 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2005 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2006 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2007 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2008 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2009 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2010 cidp->statistic_type = BGE_STAT_REG; 2011 dev_ok = B_TRUE; 2012 break; 2013 2014 case DEVICE_ID_5788: 2015 /* 2016 * Apart from the label, we treat this as a 5705(?) 2017 */ 2018 cidp->chip_label = 5788; 2019 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2020 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2021 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2022 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2023 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2024 cidp->statistic_type = BGE_STAT_REG; 2025 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2026 dev_ok = B_TRUE; 2027 break; 2028 2029 case DEVICE_ID_5714C: 2030 if (cidp->revision >= REVISION_ID_5714_A2) 2031 cidp->msi_enabled = bge_enable_msi; 2032 /* FALLTHRU */ 2033 case DEVICE_ID_5714S: 2034 cidp->chip_label = 5714; 2035 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2036 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2037 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2038 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714; 2039 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2040 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2041 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2042 cidp->pci_type = BGE_PCI_E; 2043 cidp->statistic_type = BGE_STAT_REG; 2044 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2045 dev_ok = B_TRUE; 2046 break; 2047 2048 case DEVICE_ID_5715C: 2049 cidp->chip_label = 5715; 2050 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2051 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2052 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2053 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715; 2054 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2055 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2056 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2057 cidp->pci_type = BGE_PCI_E; 2058 cidp->statistic_type = BGE_STAT_REG; 2059 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2060 dev_ok = B_TRUE; 2061 break; 2062 2063 case DEVICE_ID_5721: 2064 cidp->chip_label = 5721; 2065 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2066 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2067 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2068 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2069 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2070 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2071 cidp->pci_type = BGE_PCI_E; 2072 cidp->statistic_type = BGE_STAT_REG; 2073 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2074 dev_ok = B_TRUE; 2075 break; 2076 2077 case DEVICE_ID_5751: 2078 case DEVICE_ID_5751M: 2079 cidp->chip_label = 5751; 2080 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2081 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2082 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2083 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2084 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2085 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2086 cidp->pci_type = BGE_PCI_E; 2087 cidp->statistic_type = BGE_STAT_REG; 2088 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2089 dev_ok = B_TRUE; 2090 break; 2091 2092 } 2093 2094 /* 2095 * Setup the default jumbo parameter. 2096 */ 2097 cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma; 2098 cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac; 2099 cidp->mbuf_hi_water = bge_mbuf_hi_water; 2100 cidp->ethmax_size = ETHERMAX; 2101 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT; 2102 2103 /* 2104 * If jumbo is enabled and this kind of chipset supports jumbo feature, 2105 * setup below jumbo specific parameters. 2106 */ 2107 if (bge_jumbo_enable && 2108 !(cidp->flags & CHIP_FLAG_NO_JUMBO) && 2109 (cidp->default_mtu > BGE_DEFAULT_MTU) && 2110 (cidp->default_mtu <= BGE_MAXIMUM_MTU)) { 2111 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_JUMBO; 2112 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_JUMBO; 2113 cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO; 2114 cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE; 2115 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO; 2116 cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED; 2117 cidp->ethmax_size = cidp->default_mtu + 2118 sizeof (struct ether_header); 2119 } 2120 2121 /* 2122 * Identify the NV memory type: SEEPROM or Flash? 2123 */ 2124 cidp->nvtype = bge_nvmem_id(bgep); 2125 2126 /* 2127 * Now, we want to check whether this device is part of a 2128 * supported subsystem (e.g., on the motherboard of a Sun 2129 * branded platform). 2130 * 2131 * Rule 1: If the Subsystem Vendor ID is "Sun", then it's OK ;-) 2132 */ 2133 if (cidp->subven == VENDOR_ID_SUN) 2134 sys_ok = B_TRUE; 2135 2136 /* 2137 * Rule 2: If it's on the list on known subsystems, then it's OK. 2138 * Note: 0x14e41647 should *not* appear in the list, but the code 2139 * doesn't enforce that. 2140 */ 2141 err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo, 2142 DDI_PROP_DONTPASS, knownids_propname, &ids, &i); 2143 if (err == DDI_PROP_SUCCESS) { 2144 /* 2145 * Got the list; scan for a matching subsystem vendor/device 2146 */ 2147 subid = (cidp->subven << 16) | cidp->subdev; 2148 while (i--) 2149 if (ids[i] == subid) 2150 sys_ok = B_TRUE; 2151 ddi_prop_free(ids); 2152 } 2153 2154 /* 2155 * Rule 3: If it's a Taco/ENWS motherboard device, then it's OK 2156 * 2157 * Unfortunately, early SunBlade 1500s and 2500s didn't reprogram 2158 * the Subsystem Vendor ID, so it defaults to Broadcom. Therefore, 2159 * we have to check specially for the exact device paths to the 2160 * motherboard devices on those platforms ;-( 2161 * 2162 * Note: we can't just use the "supported-subsystems" mechanism 2163 * above, because the entry would have to be 0x14e41647 -- which 2164 * would then accept *any* plugin card that *didn't* contain a 2165 * (valid) SEEPROM ;-( 2166 */ 2167 sysname = ddi_node_name(ddi_root_node()); 2168 devname = ddi_pathname(bgep->devinfo, buf); 2169 ASSERT(strlen(devname) > 0); 2170 if (strcmp(sysname, "SUNW,Sun-Blade-1500") == 0) /* Taco */ 2171 if (strcmp(devname, "/pci@1f,700000/network@2") == 0) 2172 sys_ok = B_TRUE; 2173 if (strcmp(sysname, "SUNW,Sun-Blade-2500") == 0) /* ENWS */ 2174 if (strcmp(devname, "/pci@1c,600000/network@3") == 0) 2175 sys_ok = B_TRUE; 2176 2177 /* 2178 * Now check what we've discovered: is this truly a supported 2179 * chip on (the motherboard of) a supported platform? 2180 * 2181 * Possible problems here: 2182 * 1) it's a completely unheard-of chip (e.g. 5761) 2183 * 2) it's a recognised but unsupported chip (e.g. 5701, 5703C-A0) 2184 * 3) it's a chip we would support if it were on the motherboard 2185 * of a Sun platform, but this one isn't ;-( 2186 */ 2187 if (cidp->chip_label == 0) 2188 bge_problem(bgep, 2189 "Device 'pci%04x,%04x' not recognized (%d?)", 2190 cidp->vendor, cidp->device, cidp->device); 2191 else if (!dev_ok) 2192 bge_problem(bgep, 2193 "Device 'pci%04x,%04x' (%d) revision %d not supported", 2194 cidp->vendor, cidp->device, cidp->chip_label, 2195 cidp->revision); 2196 #if BGE_DEBUGGING 2197 else if (!sys_ok) 2198 bge_problem(bgep, 2199 "%d-based subsystem 'pci%04x,%04x' not validated", 2200 cidp->chip_label, cidp->subven, cidp->subdev); 2201 #endif 2202 else 2203 cidp->flags |= CHIP_FLAG_SUPPORTED; 2204 } 2205 2206 void 2207 bge_chip_msi_trig(bge_t *bgep) 2208 { 2209 uint32_t regval; 2210 2211 regval = bgep->param_msi_cnt<<4; 2212 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval); 2213 BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval)); 2214 } 2215 2216 /* 2217 * Various registers that control the chip's internal engines (state 2218 * machines) have a <reset> and <enable> bits (fortunately, in the 2219 * same place in each such register :-). 2220 * 2221 * To reset the state machine, the <reset> bit must be written with 1; 2222 * it will then read back as 1 while the reset is in progress, but 2223 * self-clear to 0 when the reset completes. 2224 * 2225 * To enable a state machine, one must set the <enable> bit, which 2226 * will continue to read back as 0 until the state machine is running. 2227 * 2228 * To disable a state machine, the <enable> bit must be cleared, but 2229 * it will continue to read back as 1 until the state machine actually 2230 * stops. 2231 * 2232 * This routine implements polling for completion of a reset, enable 2233 * or disable operation, returning B_TRUE on success (bit reached the 2234 * required state) or B_FALSE on timeout (200*100us == 20ms). 2235 */ 2236 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2237 uint32_t mask, uint32_t val); 2238 #pragma no_inline(bge_chip_poll_engine) 2239 2240 static boolean_t 2241 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2242 uint32_t mask, uint32_t val) 2243 { 2244 uint32_t regval; 2245 uint32_t n; 2246 2247 BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)", 2248 (void *)bgep, regno, mask, val)); 2249 2250 for (n = 200; n; --n) { 2251 regval = bge_reg_get32(bgep, regno); 2252 if ((regval & mask) == val) 2253 return (B_TRUE); 2254 drv_usecwait(100); 2255 } 2256 2257 return (B_FALSE); 2258 } 2259 2260 /* 2261 * Various registers that control the chip's internal engines (state 2262 * machines) have a <reset> bit (fortunately, in the same place in 2263 * each such register :-). To reset the state machine, this bit must 2264 * be written with 1; it will then read back as 1 while the reset is 2265 * in progress, but self-clear to 0 when the reset completes. 2266 * 2267 * This code sets the bit, then polls for it to read back as zero. 2268 * The return value is B_TRUE on success (reset bit cleared itself), 2269 * or B_FALSE if the state machine didn't recover :( 2270 * 2271 * NOTE: the Core reset is similar to other resets, except that we 2272 * can't poll for completion, since the Core reset disables memory 2273 * access! So we just have to assume that it will all complete in 2274 * 100us. See Broadcom document 570X-PG102-R, p102, steps 4-5. 2275 */ 2276 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno); 2277 #pragma no_inline(bge_chip_reset_engine) 2278 2279 static boolean_t 2280 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno) 2281 { 2282 uint32_t regval; 2283 uint32_t val32; 2284 2285 regval = bge_reg_get32(bgep, regno); 2286 2287 BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)", 2288 (void *)bgep, regno)); 2289 BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x", 2290 regno, regval)); 2291 2292 regval |= STATE_MACHINE_RESET_BIT; 2293 2294 switch (regno) { 2295 case MISC_CONFIG_REG: 2296 /* 2297 * BCM5714/5721/5751 pcie chip special case. In order to avoid 2298 * resetting PCIE block and bringing PCIE link down, bit 29 2299 * in the register needs to be set first, and then set it again 2300 * while the reset bit is written. 2301 * See:P500 of 57xx-PG102-RDS.pdf. 2302 */ 2303 if (DEVICE_5705_SERIES_CHIPSETS(bgep)|| 2304 DEVICE_5721_SERIES_CHIPSETS(bgep)|| 2305 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2306 regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE; 2307 if (bgep->chipid.pci_type == BGE_PCI_E) { 2308 if (bgep->chipid.asic_rev == 2309 MHCR_CHIP_REV_5751_A0 || 2310 bgep->chipid.asic_rev == 2311 MHCR_CHIP_REV_5721_A0) { 2312 val32 = bge_reg_get32(bgep, 2313 PHY_TEST_CTRL_REG); 2314 if (val32 == (PHY_PCIE_SCRAM_MODE | 2315 PHY_PCIE_LTASS_MODE)) 2316 bge_reg_put32(bgep, 2317 PHY_TEST_CTRL_REG, 2318 PHY_PCIE_SCRAM_MODE); 2319 val32 = pci_config_get32 2320 (bgep->cfg_handle, 2321 PCI_CONF_BGE_CLKCTL); 2322 val32 |= CLKCTL_PCIE_A0_FIX; 2323 pci_config_put32(bgep->cfg_handle, 2324 PCI_CONF_BGE_CLKCTL, val32); 2325 } 2326 bge_reg_set32(bgep, regno, 2327 MISC_CONFIG_GRC_RESET_DISABLE); 2328 regval |= MISC_CONFIG_GRC_RESET_DISABLE; 2329 } 2330 } 2331 2332 /* 2333 * Special case - causes Core reset 2334 * 2335 * On SPARC v9 we want to ensure that we don't start 2336 * timing until the I/O access has actually reached 2337 * the chip, otherwise we might make the next access 2338 * too early. And we can't just force the write out 2339 * by following it with a read (even to config space) 2340 * because that would cause the fault we're trying 2341 * to avoid. Hence the need for membar_sync() here. 2342 */ 2343 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval); 2344 #ifdef __sparcv9 2345 membar_sync(); 2346 #endif /* __sparcv9 */ 2347 /* 2348 * On some platforms,system need about 300us for 2349 * link setup. 2350 */ 2351 drv_usecwait(300); 2352 2353 if (bgep->chipid.pci_type == BGE_PCI_E) { 2354 /* PCI-E device need more reset time */ 2355 drv_usecwait(120000); 2356 2357 /* Set PCIE max payload size and clear error status. */ 2358 if (bgep->chipid.chip_label == 5721 || 2359 bgep->chipid.chip_label == 5751) { 2360 pci_config_put16(bgep->cfg_handle, 2361 PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX); 2362 pci_config_put16(bgep->cfg_handle, 2363 PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS); 2364 } 2365 } 2366 2367 BGE_PCICHK(bgep); 2368 return (B_TRUE); 2369 2370 default: 2371 bge_reg_put32(bgep, regno, regval); 2372 return (bge_chip_poll_engine(bgep, regno, 2373 STATE_MACHINE_RESET_BIT, 0)); 2374 } 2375 } 2376 2377 /* 2378 * Various registers that control the chip's internal engines (state 2379 * machines) have an <enable> bit (fortunately, in the same place in 2380 * each such register :-). To stop the state machine, this bit must 2381 * be written with 0, then polled to see when the state machine has 2382 * actually stopped. 2383 * 2384 * The return value is B_TRUE on success (enable bit cleared), or 2385 * B_FALSE if the state machine didn't stop :( 2386 */ 2387 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, 2388 uint32_t morebits); 2389 #pragma no_inline(bge_chip_disable_engine) 2390 2391 static boolean_t 2392 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2393 { 2394 uint32_t regval; 2395 2396 BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)", 2397 (void *)bgep, regno, morebits)); 2398 2399 switch (regno) { 2400 case FTQ_RESET_REG: 2401 /* 2402 * Not quite like the others; it doesn't 2403 * have an <enable> bit, but instead we 2404 * have to set and then clear all the bits 2405 */ 2406 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2407 drv_usecwait(100); 2408 bge_reg_put32(bgep, regno, 0); 2409 return (B_TRUE); 2410 2411 default: 2412 regval = bge_reg_get32(bgep, regno); 2413 regval &= ~STATE_MACHINE_ENABLE_BIT; 2414 regval &= ~morebits; 2415 bge_reg_put32(bgep, regno, regval); 2416 return (bge_chip_poll_engine(bgep, regno, 2417 STATE_MACHINE_ENABLE_BIT, 0)); 2418 } 2419 } 2420 2421 /* 2422 * Various registers that control the chip's internal engines (state 2423 * machines) have an <enable> bit (fortunately, in the same place in 2424 * each such register :-). To start the state machine, this bit must 2425 * be written with 1, then polled to see when the state machine has 2426 * actually started. 2427 * 2428 * The return value is B_TRUE on success (enable bit set), or 2429 * B_FALSE if the state machine didn't start :( 2430 */ 2431 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, 2432 uint32_t morebits); 2433 #pragma no_inline(bge_chip_enable_engine) 2434 2435 static boolean_t 2436 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2437 { 2438 uint32_t regval; 2439 2440 BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)", 2441 (void *)bgep, regno, morebits)); 2442 2443 switch (regno) { 2444 case FTQ_RESET_REG: 2445 /* 2446 * Not quite like the others; it doesn't 2447 * have an <enable> bit, but instead we 2448 * have to set and then clear all the bits 2449 */ 2450 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2451 drv_usecwait(100); 2452 bge_reg_put32(bgep, regno, 0); 2453 return (B_TRUE); 2454 2455 default: 2456 regval = bge_reg_get32(bgep, regno); 2457 regval |= STATE_MACHINE_ENABLE_BIT; 2458 regval |= morebits; 2459 bge_reg_put32(bgep, regno, regval); 2460 return (bge_chip_poll_engine(bgep, regno, 2461 STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT)); 2462 } 2463 } 2464 2465 /* 2466 * Reprogram the Ethernet, Transmit, and Receive MAC 2467 * modes to match the param_* variables 2468 */ 2469 static void bge_sync_mac_modes(bge_t *bgep); 2470 #pragma no_inline(bge_sync_mac_modes) 2471 2472 static void 2473 bge_sync_mac_modes(bge_t *bgep) 2474 { 2475 uint32_t macmode; 2476 uint32_t regval; 2477 2478 ASSERT(mutex_owned(bgep->genlock)); 2479 2480 /* 2481 * Reprogram the Ethernet MAC mode ... 2482 */ 2483 macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG); 2484 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2485 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2486 macmode &= ~ETHERNET_MODE_LINK_POLARITY; 2487 else 2488 macmode |= ETHERNET_MODE_LINK_POLARITY; 2489 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 2490 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2491 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2492 macmode |= ETHERNET_MODE_PORTMODE_TBI; 2493 else if (bgep->param_link_speed == 10 || bgep->param_link_speed == 100) 2494 macmode |= ETHERNET_MODE_PORTMODE_MII; 2495 else 2496 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2497 if (bgep->param_link_duplex == LINK_DUPLEX_HALF) 2498 macmode |= ETHERNET_MODE_HALF_DUPLEX; 2499 else 2500 macmode &= ~ETHERNET_MODE_HALF_DUPLEX; 2501 if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC) 2502 macmode |= ETHERNET_MODE_MAC_LOOPBACK; 2503 else 2504 macmode &= ~ETHERNET_MODE_MAC_LOOPBACK; 2505 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode); 2506 BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x", 2507 (void *)bgep, regval, macmode)); 2508 2509 /* 2510 * ... the Transmit MAC mode ... 2511 */ 2512 macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG); 2513 if (bgep->param_link_tx_pause) 2514 macmode |= TRANSMIT_MODE_FLOW_CONTROL; 2515 else 2516 macmode &= ~TRANSMIT_MODE_FLOW_CONTROL; 2517 bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode); 2518 BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x", 2519 (void *)bgep, regval, macmode)); 2520 2521 /* 2522 * ... and the Receive MAC mode 2523 */ 2524 macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG); 2525 if (bgep->param_link_rx_pause) 2526 macmode |= RECEIVE_MODE_FLOW_CONTROL; 2527 else 2528 macmode &= ~RECEIVE_MODE_FLOW_CONTROL; 2529 bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode); 2530 BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x", 2531 (void *)bgep, regval, macmode)); 2532 } 2533 2534 /* 2535 * bge_chip_sync() -- program the chip with the unicast MAC address, 2536 * the multicast hash table, the required level of promiscuity, and 2537 * the current loopback mode ... 2538 */ 2539 #ifdef BGE_IPMI_ASF 2540 void bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive); 2541 #else 2542 void bge_chip_sync(bge_t *bgep); 2543 #endif 2544 #pragma no_inline(bge_chip_sync) 2545 2546 void 2547 #ifdef BGE_IPMI_ASF 2548 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive) 2549 #else 2550 bge_chip_sync(bge_t *bgep) 2551 #endif 2552 { 2553 void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits); 2554 boolean_t promisc; 2555 uint64_t macaddr; 2556 uint32_t fill; 2557 int i; 2558 2559 BGE_TRACE(("bge_chip_sync($%p)", 2560 (void *)bgep)); 2561 2562 ASSERT(mutex_owned(bgep->genlock)); 2563 2564 promisc = B_FALSE; 2565 fill = ~(uint32_t)0; 2566 2567 if (bgep->promisc) 2568 promisc = B_TRUE; 2569 else 2570 fill = (uint32_t)0; 2571 2572 /* 2573 * If the TX/RX MAC engines are already running, we should stop 2574 * them (and reset the RX engine) before changing the parameters. 2575 * If they're not running, this will have no effect ... 2576 * 2577 * NOTE: this is currently disabled by default because stopping 2578 * and restarting the Tx engine may cause an outgoing packet in 2579 * transit to be truncated. Also, stopping and restarting the 2580 * Rx engine seems to not work correctly on the 5705. Testing 2581 * has not (yet!) revealed any problems with NOT stopping and 2582 * restarting these engines (and Broadcom say their drivers don't 2583 * do this), but if it is found to cause problems, this variable 2584 * can be patched to re-enable the old behaviour ... 2585 */ 2586 if (bge_stop_start_on_sync) { 2587 #ifdef BGE_IPMI_ASF 2588 if (bgep->asf_enabled) { 2589 (void) bge_chip_disable_engine(bgep, 2590 RECEIVE_MAC_MODE_REG, 0); 2591 } else { 2592 (void) bge_chip_disable_engine(bgep, 2593 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG); 2594 } 2595 #else 2596 (void) bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG, 2597 RECEIVE_MODE_KEEP_VLAN_TAG); 2598 #endif 2599 (void) bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0); 2600 (void) bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG); 2601 } 2602 2603 /* 2604 * Reprogram the hashed multicast address table ... 2605 */ 2606 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2607 bge_reg_put32(bgep, MAC_HASH_REG(i), 2608 bgep->mcast_hash[i] | fill); 2609 2610 #ifdef BGE_IPMI_ASF 2611 if (!bgep->asf_enabled || !asf_keeplive) { 2612 #endif 2613 /* 2614 * Transform the MAC address from host to chip format, then 2615 * reprogram the transmit random backoff seed and the unicast 2616 * MAC address(es) ... 2617 */ 2618 for (i = 0, fill = 0, macaddr = 0ull; i < ETHERADDRL; ++i) { 2619 macaddr <<= 8; 2620 macaddr |= bgep->curr_addr.addr[i]; 2621 fill += bgep->curr_addr.addr[i]; 2622 } 2623 bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill); 2624 for (i = 0; i < MAC_ADDRESS_REGS_MAX; ++i) 2625 bge_reg_put64(bgep, MAC_ADDRESS_REG(i), macaddr); 2626 2627 BGE_DEBUG(("bge_chip_sync($%p) setting MAC address %012llx", 2628 (void *)bgep, macaddr)); 2629 #ifdef BGE_IPMI_ASF 2630 } 2631 #endif 2632 2633 /* 2634 * Set or clear the PROMISCUOUS mode bit 2635 */ 2636 opfn = promisc ? bge_reg_set32 : bge_reg_clr32; 2637 (*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS); 2638 2639 /* 2640 * Sync the rest of the MAC modes too ... 2641 */ 2642 bge_sync_mac_modes(bgep); 2643 2644 /* 2645 * Restart RX/TX MAC engines if required ... 2646 */ 2647 if (bgep->bge_chip_state == BGE_CHIP_RUNNING) { 2648 (void) bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0); 2649 #ifdef BGE_IPMI_ASF 2650 if (bgep->asf_enabled) { 2651 (void) bge_chip_enable_engine(bgep, 2652 RECEIVE_MAC_MODE_REG, 0); 2653 } else { 2654 (void) bge_chip_enable_engine(bgep, 2655 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG); 2656 } 2657 #else 2658 (void) bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 2659 RECEIVE_MODE_KEEP_VLAN_TAG); 2660 #endif 2661 } 2662 } 2663 2664 /* 2665 * This array defines the sequence of state machine control registers 2666 * in which the <enable> bit must be cleared to bring the chip to a 2667 * clean stop. Taken from Broadcom document 570X-PG102-R, p116. 2668 */ 2669 static bge_regno_t shutdown_engine_regs[] = { 2670 RECEIVE_MAC_MODE_REG, 2671 RCV_BD_INITIATOR_MODE_REG, 2672 RCV_LIST_PLACEMENT_MODE_REG, 2673 RCV_LIST_SELECTOR_MODE_REG, /* BCM5704 series only */ 2674 RCV_DATA_BD_INITIATOR_MODE_REG, 2675 RCV_DATA_COMPLETION_MODE_REG, 2676 RCV_BD_COMPLETION_MODE_REG, 2677 2678 SEND_BD_SELECTOR_MODE_REG, 2679 SEND_BD_INITIATOR_MODE_REG, 2680 SEND_DATA_INITIATOR_MODE_REG, 2681 READ_DMA_MODE_REG, 2682 SEND_DATA_COMPLETION_MODE_REG, 2683 DMA_COMPLETION_MODE_REG, /* BCM5704 series only */ 2684 SEND_BD_COMPLETION_MODE_REG, 2685 TRANSMIT_MAC_MODE_REG, 2686 2687 HOST_COALESCE_MODE_REG, 2688 WRITE_DMA_MODE_REG, 2689 MBUF_CLUSTER_FREE_MODE_REG, /* BCM5704 series only */ 2690 FTQ_RESET_REG, /* special - see code */ 2691 BUFFER_MANAGER_MODE_REG, /* BCM5704 series only */ 2692 MEMORY_ARBITER_MODE_REG, /* BCM5704 series only */ 2693 BGE_REGNO_NONE /* terminator */ 2694 }; 2695 2696 /* 2697 * bge_chip_stop() -- stop all chip processing 2698 * 2699 * If the <fault> parameter is B_TRUE, we're stopping the chip because 2700 * we've detected a problem internally; otherwise, this is a normal 2701 * (clean) stop (at user request i.e. the last STREAM has been closed). 2702 */ 2703 void bge_chip_stop(bge_t *bgep, boolean_t fault); 2704 #pragma no_inline(bge_chip_stop) 2705 2706 void 2707 bge_chip_stop(bge_t *bgep, boolean_t fault) 2708 { 2709 bge_regno_t regno; 2710 bge_regno_t *rbp; 2711 boolean_t ok; 2712 2713 BGE_TRACE(("bge_chip_stop($%p)", 2714 (void *)bgep)); 2715 2716 ASSERT(mutex_owned(bgep->genlock)); 2717 2718 rbp = shutdown_engine_regs; 2719 /* 2720 * When driver try to shutdown the BCM5705/5788/5721/5751/ 2721 * 5752/5714 and 5715 chipsets,the buffer manager and the mem 2722 * -ory arbiter should not be disabled. 2723 */ 2724 for (ok = B_TRUE; (regno = *rbp) != BGE_REGNO_NONE; ++rbp) { 2725 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 2726 ok &= bge_chip_disable_engine(bgep, regno, 0); 2727 else if ((regno != RCV_LIST_SELECTOR_MODE_REG) && 2728 (regno != DMA_COMPLETION_MODE_REG) && 2729 (regno != MBUF_CLUSTER_FREE_MODE_REG)&& 2730 (regno != BUFFER_MANAGER_MODE_REG) && 2731 (regno != MEMORY_ARBITER_MODE_REG)) 2732 ok &= bge_chip_disable_engine(bgep, 2733 regno, 0); 2734 } 2735 2736 /* 2737 * Finally, disable (all) MAC events & clear the MAC status 2738 */ 2739 bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0); 2740 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0); 2741 2742 /* 2743 * Do we need to check whether everything completed OK? 2744 * Probably not ... it always works anyway. 2745 */ 2746 2747 if (fault) 2748 bgep->bge_chip_state = BGE_CHIP_FAULT; 2749 else 2750 bgep->bge_chip_state = BGE_CHIP_STOPPED; 2751 } 2752 2753 /* 2754 * Poll for completion of chip's ROM firmware; also, at least on the 2755 * first time through, find and return the hardware MAC address, if any. 2756 */ 2757 static uint64_t bge_poll_firmware(bge_t *bgep); 2758 #pragma no_inline(bge_poll_firmware) 2759 2760 static uint64_t 2761 bge_poll_firmware(bge_t *bgep) 2762 { 2763 uint64_t magic; 2764 uint64_t mac; 2765 uint32_t gen; 2766 uint32_t i; 2767 2768 /* 2769 * Step 18: put the T3_MAGIC_NUMBER into the GENCOMM port 2770 * 2771 * Step 19: poll for firmware completion (GENCOMM port set 2772 * to the ones complement of T3_MAGIC_NUMBER). 2773 * 2774 * While we're at it, we also read the MAC address register; 2775 * at some stage the the firmware will load this with the 2776 * factory-set value. 2777 * 2778 * When both the magic number and the MAC address are set, 2779 * we're done; but we impose a time limit of one second 2780 * (1000*1000us) in case the firmware fails in some fashion 2781 * or the SEEPROM that provides that MAC address isn't fitted. 2782 * 2783 * After the first time through (chip state != INITIAL), we 2784 * don't need the MAC address to be set (we've already got it 2785 * or not, from the first time), so we don't wait for it, but 2786 * we still have to wait for the T3_MAGIC_NUMBER. 2787 * 2788 * Note: the magic number is only a 32-bit quantity, but the NIC 2789 * memory is 64-bit (and big-endian) internally. Addressing the 2790 * GENCOMM word as "the upper half of a 64-bit quantity" makes 2791 * it work correctly on both big- and little-endian hosts. 2792 */ 2793 #ifdef BGE_IPMI_ASF 2794 if (!bgep->asf_enabled) { 2795 #endif 2796 magic = (uint64_t)T3_MAGIC_NUMBER << 32; 2797 bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic); 2798 BGE_DEBUG(("bge_poll_firmware: put T3 magic 0x%llx in GENCOMM" 2799 " 0x%lx", magic, NIC_MEM_GENCOMM)); 2800 #ifdef BGE_IPMI_ASF 2801 } 2802 #endif 2803 2804 for (i = 0; i < 1000; ++i) { 2805 drv_usecwait(1000); 2806 gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32; 2807 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 2808 #ifdef BGE_IPMI_ASF 2809 if (!bgep->asf_enabled) { 2810 #endif 2811 if (gen != ~T3_MAGIC_NUMBER) 2812 continue; 2813 #ifdef BGE_IPMI_ASF 2814 } 2815 #endif 2816 if (mac != 0ULL) 2817 break; 2818 if (bgep->bge_chip_state != BGE_CHIP_INITIAL) 2819 break; 2820 } 2821 2822 magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM); 2823 BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops", 2824 (void *)bgep, gen, i)); 2825 BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx", 2826 mac, magic)); 2827 2828 return (mac); 2829 } 2830 2831 #ifdef BGE_IPMI_ASF 2832 void bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode); 2833 #else 2834 void bge_chip_reset(bge_t *bgep, boolean_t enable_dma); 2835 #endif 2836 #pragma no_inline(bge_chip_reset) 2837 2838 void 2839 #ifdef BGE_IPMI_ASF 2840 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode) 2841 #else 2842 bge_chip_reset(bge_t *bgep, boolean_t enable_dma) 2843 #endif 2844 { 2845 chip_id_t chipid; 2846 uint64_t mac; 2847 uint32_t modeflags; 2848 uint32_t mhcr; 2849 uint32_t sx0; 2850 uint32_t i; 2851 #ifdef BGE_IPMI_ASF 2852 uint32_t mailbox; 2853 #endif 2854 2855 BGE_TRACE(("bge_chip_reset($%p, %d)", 2856 (void *)bgep, enable_dma)); 2857 2858 ASSERT(mutex_owned(bgep->genlock)); 2859 2860 BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d", 2861 (void *)bgep, enable_dma, bgep->bge_chip_state)); 2862 2863 /* 2864 * Do we need to stop the chip cleanly before resetting? 2865 */ 2866 switch (bgep->bge_chip_state) { 2867 default: 2868 ASSERT(!"can't get here"); 2869 _NOTE(NOTREACHED) 2870 return; 2871 2872 case BGE_CHIP_INITIAL: 2873 case BGE_CHIP_STOPPED: 2874 case BGE_CHIP_RESET: 2875 break; 2876 2877 case BGE_CHIP_RUNNING: 2878 case BGE_CHIP_ERROR: 2879 case BGE_CHIP_FAULT: 2880 bge_chip_stop(bgep, B_FALSE); 2881 break; 2882 } 2883 2884 #ifdef BGE_IPMI_ASF 2885 if (bgep->asf_enabled) { 2886 if (asf_mode == ASF_MODE_INIT) { 2887 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 2888 } else if (asf_mode == ASF_MODE_SHUTDOWN) { 2889 bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET); 2890 } 2891 } 2892 #endif 2893 /* 2894 * Adapted from Broadcom document 570X-PG102-R, pp 102-116. 2895 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159. 2896 * 2897 * Before reset Core clock,it is 2898 * also required to initialize the Memory Arbiter as specified in step9 2899 * and Misc Host Control Register as specified in step-13 2900 * Step 4-5: reset Core clock & wait for completion 2901 * Steps 6-8: are done by bge_chip_cfg_init() 2902 */ 2903 (void) bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0); 2904 2905 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 2906 MHCR_ENABLE_TAGGED_STATUS_MODE | 2907 MHCR_MASK_INTERRUPT_MODE | 2908 MHCR_MASK_PCI_INT_OUTPUT | 2909 MHCR_CLEAR_INTERRUPT_INTA; 2910 #ifdef _BIG_ENDIAN 2911 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 2912 #endif /* _BIG_ENDIAN */ 2913 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 2914 #ifdef BGE_IPMI_ASF 2915 if (bgep->asf_enabled) 2916 bgep->asf_wordswapped = B_FALSE; 2917 #endif 2918 (void) bge_chip_reset_engine(bgep, MISC_CONFIG_REG); 2919 bge_chip_cfg_init(bgep, &chipid, enable_dma); 2920 2921 /* 2922 * Step 8a: This may belong elsewhere, but BCM5721 needs 2923 * a bit set to avoid a fifo overflow/underflow bug. 2924 */ 2925 if (bgep->chipid.chip_label == 5721 || bgep->chipid.chip_label == 5751) 2926 bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT); 2927 2928 2929 /* 2930 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should 2931 * not be changed. 2932 */ 2933 (void) bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0); 2934 2935 /* 2936 * Steps 10-11: configure PIO endianness options and 2937 * enable indirect register access -- already done 2938 * Steps 12-13: enable writing to the PCI state & clock 2939 * control registers -- not required; we aren't going to 2940 * use those features. 2941 * Steps 14-15: Configure DMA endianness options. See 2942 * the comments on the setting of the MHCR above. 2943 */ 2944 #ifdef _BIG_ENDIAN 2945 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME | 2946 MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME; 2947 #else 2948 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME; 2949 #endif /* _BIG_ENDIAN */ 2950 #ifdef BGE_IPMI_ASF 2951 if (bgep->asf_enabled) 2952 modeflags |= MODE_HOST_STACK_UP; 2953 #endif 2954 bge_reg_put32(bgep, MODE_CONTROL_REG, modeflags); 2955 2956 #ifdef BGE_IPMI_ASF 2957 if (bgep->asf_enabled) { 2958 if (asf_mode != ASF_MODE_NONE) { 2959 /* Wait for NVRAM init */ 2960 i = 0; 2961 drv_usecwait(5000); 2962 mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX); 2963 while ((mailbox != (uint32_t) 2964 ~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) && 2965 (i < 10000)) { 2966 drv_usecwait(100); 2967 mailbox = bge_nic_get32(bgep, 2968 BGE_FIRMWARE_MAILBOX); 2969 i++; 2970 } 2971 if (!bgep->asf_newhandshake) { 2972 if ((asf_mode == ASF_MODE_INIT) || 2973 (asf_mode == ASF_MODE_POST_INIT)) { 2974 2975 bge_asf_post_reset_old_mode(bgep, 2976 BGE_INIT_RESET); 2977 } else { 2978 bge_asf_post_reset_old_mode(bgep, 2979 BGE_SHUTDOWN_RESET); 2980 } 2981 } 2982 } 2983 } 2984 #endif 2985 /* 2986 * Steps 16-17: poll for firmware completion 2987 */ 2988 mac = bge_poll_firmware(bgep); 2989 2990 /* 2991 * Step 18: enable external memory -- doesn't apply. 2992 * 2993 * However we take the opportunity to set the MLCR anyway, as 2994 * this register also controls the SEEPROM auto-access method 2995 * which we may want to use later ... 2996 * 2997 * The proper value here depends on the way the chip is wired 2998 * into the circuit board, as this register *also* controls which 2999 * of the "Miscellaneous I/O" pins are driven as outputs and the 3000 * values driven onto those pins! 3001 * 3002 * See also step 74 in the PRM ... 3003 */ 3004 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, 3005 bgep->chipid.bge_mlcr_default); 3006 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 3007 3008 /* 3009 * Step 20: clear the Ethernet MAC mode register 3010 */ 3011 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0); 3012 3013 /* 3014 * Step 21: restore cache-line-size, latency timer, and 3015 * subsystem ID registers to their original values (not 3016 * those read into the local structure <chipid>, 'cos 3017 * that was after they were cleared by the RESET). 3018 * 3019 * Note: the Subsystem Vendor/Device ID registers are not 3020 * directly writable in config space, so we use the shadow 3021 * copy in "Page Zero" of register space to restore them 3022 * both in one go ... 3023 */ 3024 pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ, 3025 bgep->chipid.clsize); 3026 pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 3027 bgep->chipid.latency); 3028 bge_reg_put32(bgep, PCI_CONF_SUBVENID, 3029 (bgep->chipid.subdev << 16) | bgep->chipid.subven); 3030 3031 /* 3032 * The SEND INDEX registers should be reset to zero by the 3033 * global chip reset; if they're not, there'll be trouble 3034 * later on -- usually in the form of an ASSERTion failure 3035 * in bge_send.c. So let's catch it early ... 3036 */ 3037 sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0)); 3038 if (sx0 != 0) 3039 bge_problem(bgep, "send index %d: device didn't RESET!", sx0); 3040 ASSERT(sx0 == 0); 3041 3042 /* Enable MSI code */ 3043 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3044 bge_reg_set32(bgep, MSI_MODE_REG, 3045 MSI_PRI_HIGHEST|MSI_MSI_ENABLE); 3046 3047 /* 3048 * On the first time through, save the factory-set MAC address 3049 * (if any). If bge_poll_firmware() above didn't return one 3050 * (from a chip register) consider looking in the attached NV 3051 * memory device, if any. Once we have it, we save it in both 3052 * register-image (64-bit) and byte-array forms. All-zero and 3053 * all-one addresses are not valid, and we refuse to stash those. 3054 */ 3055 if (bgep->bge_chip_state == BGE_CHIP_INITIAL) { 3056 if (mac == 0ULL) 3057 mac = bge_get_nvmac(bgep); 3058 if (mac != 0ULL && mac != ~0ULL) { 3059 bgep->chipid.hw_mac_addr = mac; 3060 for (i = ETHERADDRL; i-- != 0; ) { 3061 bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac; 3062 mac >>= 8; 3063 } 3064 bgep->chipid.vendor_addr.set = 1; 3065 } 3066 } 3067 3068 #ifdef BGE_IPMI_ASF 3069 if (bgep->asf_enabled && bgep->asf_newhandshake) { 3070 if (asf_mode != ASF_MODE_NONE) { 3071 if ((asf_mode == ASF_MODE_INIT) || 3072 (asf_mode == ASF_MODE_POST_INIT)) { 3073 3074 bge_asf_post_reset_new_mode(bgep, 3075 BGE_INIT_RESET); 3076 } else { 3077 bge_asf_post_reset_new_mode(bgep, 3078 BGE_SHUTDOWN_RESET); 3079 } 3080 } 3081 } 3082 #endif 3083 3084 /* 3085 * Record the new state 3086 */ 3087 bgep->chip_resets += 1; 3088 bgep->bge_chip_state = BGE_CHIP_RESET; 3089 } 3090 3091 /* 3092 * bge_chip_start() -- start the chip transmitting and/or receiving, 3093 * including enabling interrupts 3094 */ 3095 void bge_chip_start(bge_t *bgep, boolean_t reset_phys); 3096 #pragma no_inline(bge_chip_start) 3097 3098 void 3099 bge_chip_start(bge_t *bgep, boolean_t reset_phys) 3100 { 3101 uint32_t coalmode; 3102 uint32_t ledctl; 3103 uint32_t mtu; 3104 uint32_t maxring; 3105 uint64_t ring; 3106 3107 BGE_TRACE(("bge_chip_start($%p)", 3108 (void *)bgep)); 3109 3110 ASSERT(mutex_owned(bgep->genlock)); 3111 ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET); 3112 ASSERT(bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0)) == 0); 3113 3114 /* 3115 * Taken from Broadcom document 570X-PG102-R, pp 102-116. 3116 * The document specifies 95 separate steps to fully 3117 * initialise the chip!!!! 3118 * 3119 * The reset code above has already got us as far as step 3120 * 21, so we continue with ... 3121 * 3122 * Step 22: clear the MAC statistics block 3123 * (0x0300-0x0aff in NIC-local memory) 3124 */ 3125 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 3126 bge_nic_zero(bgep, NIC_MEM_STATISTICS, 3127 NIC_MEM_STATISTICS_SIZE); 3128 3129 /* 3130 * Step 23: clear the status block (in host memory) 3131 */ 3132 DMA_ZERO(bgep->status_block); 3133 3134 /* 3135 * Step 24: set DMA read/write control register 3136 */ 3137 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR, 3138 bgep->chipid.bge_dma_rwctrl); 3139 3140 /* 3141 * Step 25: Configure DMA endianness -- already done (16/17) 3142 * Step 26: Configure Host-Based Send Rings 3143 * Step 27: Indicate Host Stack Up 3144 */ 3145 bge_reg_set32(bgep, MODE_CONTROL_REG, 3146 MODE_HOST_SEND_BDS | 3147 MODE_HOST_STACK_UP); 3148 3149 /* 3150 * Step 28: Configure checksum options: 3151 * Solaris supports the hardware default checksum options. 3152 * 3153 * Workaround for Incorrect pseudo-header checksum calculation. 3154 */ 3155 if (bgep->macp->m_info.mi_cksum & HCKSUM_INET_PARTIAL) 3156 bge_reg_set32(bgep, MODE_CONTROL_REG, 3157 MODE_SEND_NO_PSEUDO_HDR_CSUM); 3158 3159 /* 3160 * Step 29: configure Timer Prescaler. The value is always the 3161 * same: the Core Clock frequency in MHz (66), minus 1, shifted 3162 * into bits 7-1. Don't set bit 0, 'cos that's the RESET bit 3163 * for the whole chip! 3164 */ 3165 bge_reg_put32(bgep, MISC_CONFIG_REG, MISC_CONFIG_DEFAULT); 3166 3167 /* 3168 * Steps 30-31: Configure MAC local memory pool & DMA pool registers 3169 * 3170 * If the mbuf_length is specified as 0, we just leave these at 3171 * their hardware defaults, rather than explicitly setting them. 3172 * As the Broadcom HRM,driver better not change the parameters 3173 * when the chipsets is 5705/5788/5721/5751/5714 and 5715. 3174 */ 3175 if ((bgep->chipid.mbuf_length != 0) && 3176 (DEVICE_5704_SERIES_CHIPSETS(bgep))) { 3177 bge_reg_put32(bgep, MBUF_POOL_BASE_REG, 3178 bgep->chipid.mbuf_base); 3179 bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG, 3180 bgep->chipid.mbuf_length); 3181 bge_reg_put32(bgep, DMAD_POOL_BASE_REG, 3182 DMAD_POOL_BASE_DEFAULT); 3183 bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG, 3184 DMAD_POOL_LENGTH_DEFAULT); 3185 } 3186 3187 /* 3188 * Step 32: configure MAC memory pool watermarks 3189 */ 3190 bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG, 3191 bgep->chipid.mbuf_lo_water_rdma); 3192 bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG, 3193 bgep->chipid.mbuf_lo_water_rmac); 3194 bge_reg_put32(bgep, MBUF_HIWAT_REG, 3195 bgep->chipid.mbuf_hi_water); 3196 3197 /* 3198 * Step 33: configure DMA resource watermarks 3199 */ 3200 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3201 bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG, 3202 bge_dmad_lo_water); 3203 bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG, 3204 bge_dmad_hi_water); 3205 } 3206 bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames); 3207 3208 /* 3209 * Steps 34-36: enable buffer manager & internal h/w queues 3210 */ 3211 (void) bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG, 3212 STATE_MACHINE_ATTN_ENABLE_BIT); 3213 (void) bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0); 3214 3215 /* 3216 * Steps 37-39: initialise Receive Buffer (Producer) RCBs 3217 */ 3218 bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG, 3219 &bgep->buff[BGE_STD_BUFF_RING].hw_rcb); 3220 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3221 bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG, 3222 &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb); 3223 bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG, 3224 &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb); 3225 } 3226 3227 /* 3228 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds 3229 */ 3230 bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std); 3231 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3232 bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG, 3233 bge_replenish_jumbo); 3234 bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG, 3235 bge_replenish_mini); 3236 } 3237 3238 /* 3239 * Steps 41-43: clear Send Ring Producer Indices and initialise 3240 * Send Producer Rings (0x0100-0x01ff in NIC-local memory) 3241 */ 3242 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3243 maxring = BGE_SEND_RINGS_MAX; 3244 else 3245 maxring = BGE_SEND_RINGS_MAX_5705; 3246 for (ring = 0; ring < maxring; ++ring) { 3247 bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0); 3248 bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0); 3249 bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring), 3250 &bgep->send[ring].hw_rcb); 3251 } 3252 3253 /* 3254 * Steps 44-45: initialise Receive Return Rings 3255 * (0x0200-0x02ff in NIC-local memory) 3256 */ 3257 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3258 maxring = BGE_RECV_RINGS_MAX; 3259 else 3260 maxring = BGE_RECV_RINGS_MAX_5705; 3261 for (ring = 0; ring < maxring; ++ring) 3262 bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring), 3263 &bgep->recv[ring].hw_rcb); 3264 3265 /* 3266 * Step 46: initialise Receive Buffer (Producer) Ring indexes 3267 */ 3268 bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0); 3269 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3270 bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0); 3271 bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0); 3272 } 3273 /* 3274 * Step 47: configure the MAC unicast address 3275 * Step 48: configure the random backoff seed 3276 * Step 96: set up multicast filters 3277 */ 3278 #ifdef BGE_IPMI_ASF 3279 bge_chip_sync(bgep, B_FALSE); 3280 #else 3281 bge_chip_sync(bgep); 3282 #endif 3283 3284 /* 3285 * Step 49: configure the MTU 3286 */ 3287 mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ; 3288 bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu); 3289 3290 /* 3291 * Step 50: configure the IPG et al 3292 */ 3293 bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT); 3294 3295 /* 3296 * Step 51: configure the default Rx Return Ring 3297 */ 3298 bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT); 3299 3300 /* 3301 * Steps 52-54: configure Receive List Placement, 3302 * and enable Receive List Placement Statistics 3303 */ 3304 bge_reg_put32(bgep, RCV_LP_CONFIG_REG, 3305 RCV_LP_CONFIG(bgep->chipid.rx_rings)); 3306 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0); 3307 bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE); 3308 3309 if (bgep->chipid.rx_rings > 1) 3310 bge_init_recv_rule(bgep); 3311 3312 /* 3313 * Steps 55-56: enable Send Data Initiator Statistics 3314 */ 3315 bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0); 3316 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3317 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3318 SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER); 3319 } else { 3320 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3321 SEND_INIT_STATS_ENABLE); 3322 } 3323 /* 3324 * Steps 57-58: stop (?) the Host Coalescing Engine 3325 */ 3326 (void) bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0); 3327 3328 /* 3329 * Steps 59-62: initialise Host Coalescing parameters 3330 */ 3331 bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG, bge_tx_count_norm); 3332 bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG, bge_tx_ticks_norm); 3333 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, bge_rx_count_norm); 3334 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, bge_rx_ticks_norm); 3335 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3336 bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG, 3337 bge_tx_count_intr); 3338 bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG, 3339 bge_tx_ticks_intr); 3340 bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG, 3341 bge_rx_count_intr); 3342 bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG, 3343 bge_rx_ticks_intr); 3344 } 3345 3346 /* 3347 * Steps 63-64: initialise status block & statistics 3348 * host memory addresses 3349 * The statistic block does not exist in some chipsets 3350 * Step 65: initialise Statistics Coalescing Tick Counter 3351 */ 3352 bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG, 3353 bgep->status_block.cookie.dmac_laddress); 3354 3355 /* 3356 * Steps 66-67: initialise status block & statistics 3357 * NIC-local memory addresses 3358 */ 3359 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3360 bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG, 3361 bgep->statistics.cookie.dmac_laddress); 3362 bge_reg_put32(bgep, STATISTICS_TICKS_REG, 3363 STATISTICS_TICKS_DEFAULT); 3364 bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG, 3365 NIC_MEM_STATUS_BLOCK); 3366 bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG, 3367 NIC_MEM_STATISTICS); 3368 } 3369 3370 /* 3371 * Steps 68-71: start the Host Coalescing Engine, the Receive BD 3372 * Completion Engine, the Receive List Placement Engine, and the 3373 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714 3374 * and BCM5715. 3375 */ 3376 if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS && 3377 bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS) 3378 coalmode = COALESCE_64_BYTE_STATUS; 3379 else 3380 coalmode = 0; 3381 (void) bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode); 3382 (void) bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG, 3383 STATE_MACHINE_ATTN_ENABLE_BIT); 3384 (void) bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0); 3385 3386 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3387 (void) bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG, 3388 STATE_MACHINE_ATTN_ENABLE_BIT); 3389 3390 /* 3391 * Step 72: Enable MAC DMA engines 3392 * Step 73: Clear & enable MAC statistics 3393 */ 3394 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3395 ETHERNET_MODE_ENABLE_FHDE | 3396 ETHERNET_MODE_ENABLE_RDE | 3397 ETHERNET_MODE_ENABLE_TDE); 3398 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3399 ETHERNET_MODE_ENABLE_TX_STATS | 3400 ETHERNET_MODE_ENABLE_RX_STATS | 3401 ETHERNET_MODE_CLEAR_TX_STATS | 3402 ETHERNET_MODE_CLEAR_RX_STATS); 3403 3404 /* 3405 * Step 74: configure the MLCR (Miscellaneous Local Control 3406 * Register); not required, as we set up the MLCR in step 10 3407 * (part of the reset code) above. 3408 * 3409 * Step 75: clear Interrupt Mailbox 0 3410 */ 3411 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0); 3412 3413 /* 3414 * Steps 76-87: Gentlemen, start your engines ... 3415 * 3416 * Enable the DMA Completion Engine, the Write DMA Engine, 3417 * the Read DMA Engine, Receive Data Completion Engine, 3418 * the MBuf Cluster Free Engine, the Send Data Completion Engine, 3419 * the Send BD Completion Engine, the Receive BD Initiator Engine, 3420 * the Receive Data Initiator Engine, the Send Data Initiator Engine, 3421 * the Send BD Initiator Engine, and the Send BD Selector Engine. 3422 * 3423 * Beware exhaust fumes? 3424 */ 3425 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3426 (void) bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0); 3427 (void) bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG, 3428 (bge_dma_wrprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS); 3429 (void) bge_chip_enable_engine(bgep, READ_DMA_MODE_REG, 3430 (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS); 3431 (void) bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG, 3432 STATE_MACHINE_ATTN_ENABLE_BIT); 3433 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3434 (void) bge_chip_enable_engine(bgep, 3435 MBUF_CLUSTER_FREE_MODE_REG, 0); 3436 (void) bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0); 3437 (void) bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG, 3438 STATE_MACHINE_ATTN_ENABLE_BIT); 3439 (void) bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG, 3440 RCV_BD_DISABLED_RING_ATTN); 3441 (void) bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG, 3442 RCV_DATA_BD_ILL_RING_ATTN); 3443 (void) bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0); 3444 (void) bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG, 3445 STATE_MACHINE_ATTN_ENABLE_BIT); 3446 (void) bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG, 3447 STATE_MACHINE_ATTN_ENABLE_BIT); 3448 3449 /* 3450 * Step 88: download firmware -- doesn't apply 3451 * Steps 89-90: enable Transmit & Receive MAC Engines 3452 */ 3453 (void) bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0); 3454 #ifdef BGE_IPMI_ASF 3455 if (bgep->asf_enabled) { 3456 (void) bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0); 3457 } else { 3458 (void) bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3459 RECEIVE_MODE_KEEP_VLAN_TAG); 3460 } 3461 #else 3462 (void) bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3463 RECEIVE_MODE_KEEP_VLAN_TAG); 3464 #endif 3465 3466 /* 3467 * Step 91: disable auto-polling of PHY status 3468 */ 3469 bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT); 3470 3471 /* 3472 * Step 92: configure D0 power state (not required) 3473 * Step 93: initialise LED control register () 3474 */ 3475 ledctl = LED_CONTROL_DEFAULT; 3476 switch (bgep->chipid.device) { 3477 case DEVICE_ID_5700: 3478 case DEVICE_ID_5700x: 3479 case DEVICE_ID_5701: 3480 /* 3481 * Switch to 5700 (MAC) mode on these older chips 3482 */ 3483 ledctl &= ~LED_CONTROL_LED_MODE_MASK; 3484 ledctl |= LED_CONTROL_LED_MODE_5700; 3485 break; 3486 3487 default: 3488 break; 3489 } 3490 bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl); 3491 3492 /* 3493 * Step 94: activate link 3494 */ 3495 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK); 3496 3497 /* 3498 * Step 95: set up physical layer (PHY/SerDes) 3499 * restart autoneg (if required) 3500 */ 3501 if (reset_phys) 3502 bge_phys_update(bgep); 3503 3504 /* 3505 * Extra step (DSG): hand over all the Receive Buffers to the chip 3506 */ 3507 for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring) 3508 bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg, 3509 bgep->buff[ring].rf_next); 3510 3511 /* 3512 * MSI bits:The least significant MSI 16-bit word. 3513 * ISR will be triggered different. 3514 */ 3515 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3516 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70); 3517 3518 /* 3519 * Extra step (DSG): select which interrupts are enabled 3520 * 3521 * Program the Ethernet MAC engine to signal attention on 3522 * Link Change events, then enable interrupts on MAC, DMA, 3523 * and FLOW attention signals. 3524 */ 3525 bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 3526 ETHERNET_EVENT_LINK_INT | 3527 ETHERNET_STATUS_PCS_ERROR_INT); 3528 #ifdef BGE_IPMI_ASF 3529 if (bgep->asf_enabled) { 3530 bge_reg_set32(bgep, MODE_CONTROL_REG, 3531 MODE_INT_ON_FLOW_ATTN | 3532 MODE_INT_ON_DMA_ATTN | 3533 MODE_HOST_STACK_UP| 3534 MODE_INT_ON_MAC_ATTN); 3535 } else { 3536 #endif 3537 bge_reg_set32(bgep, MODE_CONTROL_REG, 3538 MODE_INT_ON_FLOW_ATTN | 3539 MODE_INT_ON_DMA_ATTN | 3540 MODE_INT_ON_MAC_ATTN); 3541 #ifdef BGE_IPMI_ASF 3542 } 3543 #endif 3544 3545 /* 3546 * Step 97: enable PCI interrupts!!! 3547 */ 3548 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 3549 bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR, 3550 MHCR_MASK_PCI_INT_OUTPUT); 3551 3552 /* 3553 * All done! 3554 */ 3555 bgep->bge_chip_state = BGE_CHIP_RUNNING; 3556 } 3557 3558 3559 /* 3560 * ========== Hardware interrupt handler ========== 3561 */ 3562 3563 #undef BGE_DBG 3564 #define BGE_DBG BGE_DBG_INT /* debug flag for this code */ 3565 3566 /* 3567 * Sync the status block, then atomically clear the specified bits in 3568 * the <flags-and-tag> field of the status block. 3569 * the <flags> word of the status block, returning the value of the 3570 * <tag> and the <flags> before the bits were cleared. 3571 */ 3572 static uint64_t bge_status_sync(bge_t *bgep, uint64_t bits); 3573 #pragma inline(bge_status_sync) 3574 3575 static uint64_t 3576 bge_status_sync(bge_t *bgep, uint64_t bits) 3577 { 3578 bge_status_t *bsp; 3579 uint64_t flags; 3580 3581 BGE_TRACE(("bge_status_sync($%p, 0x%llx)", 3582 (void *)bgep, bits)); 3583 3584 ASSERT(bgep->bge_guard == BGE_GUARD); 3585 3586 DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL); 3587 bsp = DMA_VPTR(bgep->status_block); 3588 flags = bge_atomic_clr64(&bsp->flags_n_tag, bits); 3589 3590 BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx", 3591 (void *)bgep, bits, flags)); 3592 3593 return (flags); 3594 } 3595 3596 static void bge_wake_factotum(bge_t *bgep); 3597 #pragma inline(bge_wake_factotum) 3598 3599 static void 3600 bge_wake_factotum(bge_t *bgep) 3601 { 3602 mutex_enter(bgep->softintrlock); 3603 if (bgep->factotum_flag == 0) { 3604 bgep->factotum_flag = 1; 3605 ddi_trigger_softintr(bgep->factotum_id); 3606 } 3607 mutex_exit(bgep->softintrlock); 3608 } 3609 3610 /* 3611 * bge_intr() -- handle chip interrupts 3612 */ 3613 uint_t bge_intr(caddr_t arg1, caddr_t arg2); 3614 #pragma no_inline(bge_intr) 3615 3616 uint_t 3617 bge_intr(caddr_t arg1, caddr_t arg2) 3618 { 3619 bge_t *bgep = (bge_t *)arg1; /* private device info */ 3620 bge_status_t *bsp; 3621 uint64_t flags; 3622 uint32_t mlcr = 0; 3623 uint_t result; 3624 3625 BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2)); 3626 3627 /* 3628 * GLD v2 checks that s/w setup is complete before passing 3629 * interrupts to this routine, thus eliminating the old 3630 * (and well-known) race condition around ddi_add_intr() 3631 */ 3632 ASSERT(bgep->progress & PROGRESS_HWINT); 3633 3634 /* 3635 * Check whether chip's says it's asserting #INTA; 3636 * if not, don't process or claim the interrupt. 3637 * 3638 * Note that the PCI signal is active low, so the 3639 * bit is *zero* when the interrupt is asserted. 3640 */ 3641 result = DDI_INTR_UNCLAIMED; 3642 mutex_enter(bgep->genlock); 3643 3644 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 3645 mlcr = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 3646 3647 BGE_DEBUG(("bge_intr($%p) ($%p) mlcr 0x%08x", arg1, arg2, mlcr)); 3648 3649 if ((mlcr & MLCR_INTA_STATE) == 0) { 3650 /* 3651 * Block further PCI interrupts ... 3652 */ 3653 result = DDI_INTR_CLAIMED; 3654 3655 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 3656 bge_cfg_set32(bgep, PCI_CONF_BGE_MHCR, 3657 MHCR_MASK_PCI_INT_OUTPUT); 3658 3659 /* 3660 * Sync the status block and grab the flags-n-tag from it. 3661 * We count the number of interrupts where there doesn't 3662 * seem to have been a DMA update of the status block; if 3663 * it *has* been updated, the counter will be cleared in 3664 * the while() loop below ... 3665 */ 3666 bgep->missed_dmas += 1; 3667 bsp = DMA_VPTR(bgep->status_block); 3668 flags = bge_status_sync(bgep, STATUS_FLAG_UPDATED); 3669 3670 while (flags & STATUS_FLAG_UPDATED) { 3671 /* 3672 * Tell the chip that we're processing the interrupt 3673 */ 3674 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 3675 INTERRUPT_MBOX_DISABLE(flags)); 3676 3677 /* 3678 * Drop the mutex while we: 3679 * Receive any newly-arrived packets 3680 * Recycle any newly-finished send buffers 3681 */ 3682 mutex_exit(bgep->genlock); 3683 bge_receive(bgep, bsp); 3684 bge_recycle(bgep, bsp); 3685 mutex_enter(bgep->genlock); 3686 3687 /* 3688 * Tell the chip we've finished processing, and 3689 * give it the tag that we got from the status 3690 * block earlier, so that it knows just how far 3691 * we've gone. If it's got more for us to do, 3692 * it will now update the status block and try 3693 * to assert an interrupt (but we've got the 3694 * #INTA blocked at present). If we see the 3695 * update, we'll loop around to do some more. 3696 * Eventually we'll get out of here ... 3697 */ 3698 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 3699 INTERRUPT_MBOX_ENABLE(flags)); 3700 bgep->missed_dmas = 0; 3701 flags = bge_status_sync(bgep, STATUS_FLAG_UPDATED); 3702 } 3703 3704 /* 3705 * Check for exceptional conditions that we need to handle 3706 * 3707 * Link status changed 3708 * Status block not updated 3709 */ 3710 if (flags & STATUS_FLAG_LINK_CHANGED) 3711 bge_wake_factotum(bgep); 3712 3713 if (bgep->missed_dmas) { 3714 /* 3715 * Probably due to the internal status tag not 3716 * being reset. Force a status block update now; 3717 * this should ensure that we get an update and 3718 * a new interrupt. After that, we should be in 3719 * sync again ... 3720 */ 3721 BGE_REPORT((bgep, "interrupt: flags 0x%llx - " 3722 "not updated?", flags)); 3723 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 3724 COALESCE_NOW); 3725 3726 if (bgep->missed_dmas >= bge_dma_miss_limit) { 3727 /* 3728 * If this happens multiple times in a row, 3729 * it means DMA is just not working. Maybe 3730 * the chip's failed, or maybe there's a 3731 * problem on the PCI bus or in the host-PCI 3732 * bridge (Tomatillo). 3733 * 3734 * At all events, we want to stop further 3735 * interrupts and let the recovery code take 3736 * over to see whether anything can be done 3737 * about it ... 3738 */ 3739 #ifdef BGE_IPMI_ASF 3740 if (bgep->asf_enabled && 3741 (bgep->asf_status == ASF_STAT_RUN)) { 3742 /* 3743 * We must stop ASF heart beat before 3744 * bge_chip_stop(), otherwise some 3745 * computers (ex. IBM HS20 blade 3746 * server) may crash. 3747 */ 3748 bge_asf_update_status(bgep); 3749 bge_asf_stop_timer(bgep); 3750 bgep->asf_status = ASF_STAT_STOP; 3751 3752 bge_asf_pre_reset_operations(bgep, 3753 BGE_INIT_RESET); 3754 } 3755 #endif 3756 bge_chip_stop(bgep, B_TRUE); 3757 result = DDI_INTR_UNCLAIMED; 3758 } 3759 } 3760 3761 /* 3762 * Reenable assertion of #INTA, unless there's a DMA fault 3763 */ 3764 if (result == DDI_INTR_CLAIMED) { 3765 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 3766 bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR, 3767 MHCR_MASK_PCI_INT_OUTPUT); 3768 } 3769 } 3770 3771 mutex_exit(bgep->genlock); 3772 return (result); 3773 } 3774 3775 /* 3776 * ========== Factotum, implemented as a softint handler ========== 3777 */ 3778 3779 #undef BGE_DBG 3780 #define BGE_DBG BGE_DBG_FACT /* debug flag for this code */ 3781 3782 static void bge_factotum_error_handler(bge_t *bgep); 3783 #pragma no_inline(bge_factotum_error_handler) 3784 3785 static void 3786 bge_factotum_error_handler(bge_t *bgep) 3787 { 3788 uint32_t flow; 3789 uint32_t rdma; 3790 uint32_t wdma; 3791 uint32_t tmac; 3792 uint32_t rmac; 3793 uint32_t rxrs; 3794 uint32_t txrs = 0; 3795 3796 ASSERT(mutex_owned(bgep->genlock)); 3797 3798 /* 3799 * Read all the registers that show the possible 3800 * reasons for the ERROR bit to be asserted 3801 */ 3802 flow = bge_reg_get32(bgep, FLOW_ATTN_REG); 3803 rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG); 3804 wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG); 3805 tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 3806 rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG); 3807 rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG); 3808 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3809 txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG); 3810 3811 BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x", 3812 (void *)bgep, flow, rdma, wdma)); 3813 BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x", 3814 (void *)bgep, tmac, rmac, rxrs, txrs)); 3815 3816 /* 3817 * For now, just clear all the errors ... 3818 */ 3819 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3820 bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0); 3821 bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0); 3822 bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0); 3823 bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0); 3824 bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0); 3825 bge_reg_put32(bgep, FLOW_ATTN_REG, ~0); 3826 } 3827 3828 /* 3829 * Handler for hardware link state change. 3830 * 3831 * When this routine is called, the hardware link state has changed 3832 * and the new state is reflected in the param_* variables. Here 3833 * we must update the softstate, reprogram the MAC to match, and 3834 * record the change in the log and/or on the console. 3835 */ 3836 static void bge_factotum_link_handler(bge_t *bgep); 3837 #pragma no_inline(bge_factotum_link_handler) 3838 3839 static void 3840 bge_factotum_link_handler(bge_t *bgep) 3841 { 3842 void (*logfn)(bge_t *bgep, const char *fmt, ...); 3843 const char *msg; 3844 hrtime_t deltat; 3845 3846 ASSERT(mutex_owned(bgep->genlock)); 3847 3848 /* 3849 * Update the s/w link_state 3850 */ 3851 if (bgep->param_link_up) 3852 bgep->link_state = LINK_STATE_UP; 3853 else 3854 bgep->link_state = LINK_STATE_DOWN; 3855 3856 /* 3857 * Reprogram the MAC modes to match 3858 */ 3859 bge_sync_mac_modes(bgep); 3860 3861 /* 3862 * Finally, we have to decide whether to write a message 3863 * on the console or only in the log. If the PHY has 3864 * been reprogrammed (at user request) "recently", then 3865 * the message only goes in the log. Otherwise it's an 3866 * "unexpected" event, and it goes on the console as well. 3867 */ 3868 deltat = bgep->phys_event_time - bgep->phys_write_time; 3869 if (deltat > BGE_LINK_SETTLE_TIME) 3870 msg = ""; 3871 else if (bgep->param_link_up) 3872 msg = bgep->link_up_msg; 3873 else 3874 msg = bgep->link_down_msg; 3875 3876 logfn = (msg == NULL || *msg == '\0') ? bge_notice : bge_log; 3877 (*logfn)(bgep, "link %s%s", bgep->link_mode_msg, msg); 3878 } 3879 3880 static boolean_t bge_factotum_link_check(bge_t *bgep); 3881 #pragma no_inline(bge_factotum_link_check) 3882 3883 static boolean_t 3884 bge_factotum_link_check(bge_t *bgep) 3885 { 3886 boolean_t check; 3887 uint64_t flags; 3888 uint32_t tmac_status; 3889 3890 ASSERT(mutex_owned(bgep->genlock)); 3891 3892 /* 3893 * Get & clear the writable status bits in the Tx status register 3894 * (some bits are write-1-to-clear, others are just readonly). 3895 */ 3896 tmac_status = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 3897 bge_reg_put32(bgep, TRANSMIT_MAC_STATUS_REG, tmac_status); 3898 3899 /* 3900 * Get & clear the ERROR and LINK_CHANGED bits from the status block 3901 */ 3902 flags = STATUS_FLAG_ERROR | STATUS_FLAG_LINK_CHANGED; 3903 flags = bge_status_sync(bgep, flags); 3904 3905 /* 3906 * Clear any errors flagged in the status block ... 3907 */ 3908 if (flags & STATUS_FLAG_ERROR) 3909 bge_factotum_error_handler(bgep); 3910 3911 /* 3912 * We need to check the link status if: 3913 * the status block says there's been a link change 3914 * or there's any discrepancy between the various 3915 * flags indicating the link state (link_state, 3916 * param_link_up, and the LINK STATE bit in the 3917 * Transmit MAC status register). 3918 */ 3919 check = (flags & STATUS_FLAG_LINK_CHANGED) != 0; 3920 switch (bgep->link_state) { 3921 case LINK_STATE_UP: 3922 check |= (bgep->param_link_up == B_FALSE); 3923 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) == 0); 3924 break; 3925 3926 case LINK_STATE_DOWN: 3927 check |= (bgep->param_link_up != B_FALSE); 3928 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) != 0); 3929 break; 3930 3931 default: 3932 check = B_TRUE; 3933 break; 3934 } 3935 3936 /* 3937 * If <check> is false, we're sure the link hasn't changed. 3938 * If true, however, it's not yet definitive; we have to call 3939 * bge_phys_check() to determine whether the link has settled 3940 * into a new state yet ... and if it has, then call the link 3941 * state change handler.But when the chip is 5700 in Dell 6650 3942 * ,even if check is false, the link may have changed.So we 3943 * have to call bge_phys_check() to determine the link state. 3944 */ 3945 if (check || bgep->chipid.device == DEVICE_ID_5700) { 3946 check = bge_phys_check(bgep); 3947 if (check) 3948 bge_factotum_link_handler(bgep); 3949 } 3950 3951 return (check); 3952 } 3953 3954 /* 3955 * Factotum routine to check for Tx stall, using the 'watchdog' counter 3956 */ 3957 static boolean_t bge_factotum_stall_check(bge_t *bgep); 3958 #pragma no_inline(bge_factotum_stall_check) 3959 3960 static boolean_t 3961 bge_factotum_stall_check(bge_t *bgep) 3962 { 3963 uint32_t dogval; 3964 3965 ASSERT(mutex_owned(bgep->genlock)); 3966 3967 /* 3968 * Specific check for Tx stall ... 3969 * 3970 * The 'watchdog' counter is incremented whenever a packet 3971 * is queued, reset to 1 when some (but not all) buffers 3972 * are reclaimed, reset to 0 (disabled) when all buffers 3973 * are reclaimed, and shifted left here. If it exceeds the 3974 * threshold value, the chip is assumed to have stalled and 3975 * is put into the ERROR state. The factotum will then reset 3976 * it on the next pass. 3977 * 3978 * All of which should ensure that we don't get into a state 3979 * where packets are left pending indefinitely! 3980 */ 3981 dogval = bge_atomic_shl32(&bgep->watchdog, 1); 3982 if (dogval < bge_watchdog_count) 3983 return (B_FALSE); 3984 3985 BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval)); 3986 return (B_TRUE); 3987 } 3988 3989 /* 3990 * The factotum is woken up when there's something to do that we'd rather 3991 * not do from inside a hardware interrupt handler or high-level cyclic. 3992 * Its two main tasks are: 3993 * reset & restart the chip after an error 3994 * check the link status whenever necessary 3995 */ 3996 uint_t bge_chip_factotum(caddr_t arg); 3997 #pragma no_inline(bge_chip_factotum) 3998 3999 uint_t 4000 bge_chip_factotum(caddr_t arg) 4001 { 4002 bge_t *bgep; 4003 uint_t result; 4004 boolean_t error; 4005 boolean_t linkchg; 4006 4007 bgep = (bge_t *)arg; 4008 4009 BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep)); 4010 4011 mutex_enter(bgep->softintrlock); 4012 if (bgep->factotum_flag == 0) { 4013 mutex_exit(bgep->softintrlock); 4014 return (DDI_INTR_UNCLAIMED); 4015 } 4016 bgep->factotum_flag = 0; 4017 mutex_exit(bgep->softintrlock); 4018 4019 result = DDI_INTR_CLAIMED; 4020 error = B_FALSE; 4021 linkchg = B_FALSE; 4022 4023 mutex_enter(bgep->genlock); 4024 switch (bgep->bge_chip_state) { 4025 default: 4026 break; 4027 4028 case BGE_CHIP_RUNNING: 4029 linkchg = bge_factotum_link_check(bgep); 4030 error = bge_factotum_stall_check(bgep); 4031 break; 4032 4033 case BGE_CHIP_ERROR: 4034 error = B_TRUE; 4035 break; 4036 4037 case BGE_CHIP_FAULT: 4038 /* 4039 * Fault detected, time to reset ... 4040 */ 4041 if (bge_autorecover) { 4042 BGE_REPORT((bgep, "automatic recovery activated")); 4043 bge_restart(bgep, B_FALSE); 4044 #ifdef BGE_IPMI_ASF 4045 /* 4046 * Start our ASF heartbeat counter as soon as possible. 4047 */ 4048 if (bgep->asf_enabled) { 4049 if (bgep->asf_status != ASF_STAT_RUN) { 4050 bgep->asf_timeout_id = timeout( 4051 bge_asf_heartbeat, 4052 (void *)bgep, 4053 drv_usectohz( 4054 BGE_ASF_HEARTBEAT_INTERVAL)); 4055 bgep->asf_status = ASF_STAT_RUN; 4056 } 4057 } 4058 #endif 4059 } 4060 break; 4061 } 4062 4063 /* 4064 * If an error is detected, stop the chip now, marking it as 4065 * faulty, so that it will be reset next time through ... 4066 */ 4067 if (error) { 4068 #ifdef BGE_IPMI_ASF 4069 if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) { 4070 /* 4071 * We must stop ASF heart beat before bge_chip_stop(), 4072 * otherwise some computers (ex. IBM HS20 blade server) 4073 * may crash. 4074 */ 4075 bge_asf_update_status(bgep); 4076 bge_asf_stop_timer(bgep); 4077 bgep->asf_status = ASF_STAT_STOP; 4078 4079 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4080 } 4081 #endif 4082 bge_chip_stop(bgep, B_TRUE); 4083 } 4084 mutex_exit(bgep->genlock); 4085 4086 /* 4087 * If the link state changed, tell the world about it. 4088 * Note: can't do this while still holding the mutex. 4089 */ 4090 if (linkchg) 4091 mac_link_update(bgep->macp, bgep->link_state); 4092 4093 return (result); 4094 } 4095 4096 /* 4097 * High-level cyclic handler 4098 * 4099 * This routine schedules a (low-level) softint callback to the 4100 * factotum, and prods the chip to update the status block (which 4101 * will cause a hardware interrupt when complete). 4102 */ 4103 void bge_chip_cyclic(void *arg); 4104 #pragma no_inline(bge_chip_cyclic) 4105 4106 void 4107 bge_chip_cyclic(void *arg) 4108 { 4109 bge_t *bgep; 4110 4111 bgep = arg; 4112 4113 switch (bgep->bge_chip_state) { 4114 default: 4115 return; 4116 4117 case BGE_CHIP_RUNNING: 4118 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW); 4119 break; 4120 4121 case BGE_CHIP_FAULT: 4122 case BGE_CHIP_ERROR: 4123 break; 4124 } 4125 4126 bge_wake_factotum(bgep); 4127 } 4128 4129 4130 /* 4131 * ========== Ioctl subfunctions ========== 4132 */ 4133 4134 #undef BGE_DBG 4135 #define BGE_DBG BGE_DBG_PPIO /* debug flag for this code */ 4136 4137 #if BGE_DEBUGGING || BGE_DO_PPIO 4138 4139 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4140 #pragma no_inline(bge_chip_peek_cfg) 4141 4142 static void 4143 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4144 { 4145 uint64_t regval; 4146 uint64_t regno; 4147 4148 BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)", 4149 (void *)bgep, (void *)ppd)); 4150 4151 regno = ppd->pp_acc_offset; 4152 4153 switch (ppd->pp_acc_size) { 4154 case 1: 4155 regval = pci_config_get8(bgep->cfg_handle, regno); 4156 break; 4157 4158 case 2: 4159 regval = pci_config_get16(bgep->cfg_handle, regno); 4160 break; 4161 4162 case 4: 4163 regval = pci_config_get32(bgep->cfg_handle, regno); 4164 break; 4165 4166 case 8: 4167 regval = pci_config_get64(bgep->cfg_handle, regno); 4168 break; 4169 } 4170 4171 ppd->pp_acc_data = regval; 4172 } 4173 4174 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4175 #pragma no_inline(bge_chip_poke_cfg) 4176 4177 static void 4178 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4179 { 4180 uint64_t regval; 4181 uint64_t regno; 4182 4183 BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)", 4184 (void *)bgep, (void *)ppd)); 4185 4186 regno = ppd->pp_acc_offset; 4187 regval = ppd->pp_acc_data; 4188 4189 switch (ppd->pp_acc_size) { 4190 case 1: 4191 pci_config_put8(bgep->cfg_handle, regno, regval); 4192 break; 4193 4194 case 2: 4195 pci_config_put16(bgep->cfg_handle, regno, regval); 4196 break; 4197 4198 case 4: 4199 pci_config_put32(bgep->cfg_handle, regno, regval); 4200 break; 4201 4202 case 8: 4203 pci_config_put64(bgep->cfg_handle, regno, regval); 4204 break; 4205 } 4206 } 4207 4208 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4209 #pragma no_inline(bge_chip_peek_reg) 4210 4211 static void 4212 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4213 { 4214 uint64_t regval; 4215 void *regaddr; 4216 4217 BGE_TRACE(("bge_chip_peek_reg($%p, $%p)", 4218 (void *)bgep, (void *)ppd)); 4219 4220 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4221 4222 switch (ppd->pp_acc_size) { 4223 case 1: 4224 regval = ddi_get8(bgep->io_handle, regaddr); 4225 break; 4226 4227 case 2: 4228 regval = ddi_get16(bgep->io_handle, regaddr); 4229 break; 4230 4231 case 4: 4232 regval = ddi_get32(bgep->io_handle, regaddr); 4233 break; 4234 4235 case 8: 4236 regval = ddi_get64(bgep->io_handle, regaddr); 4237 break; 4238 } 4239 4240 ppd->pp_acc_data = regval; 4241 } 4242 4243 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4244 #pragma no_inline(bge_chip_peek_reg) 4245 4246 static void 4247 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4248 { 4249 uint64_t regval; 4250 void *regaddr; 4251 4252 BGE_TRACE(("bge_chip_poke_reg($%p, $%p)", 4253 (void *)bgep, (void *)ppd)); 4254 4255 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4256 regval = ppd->pp_acc_data; 4257 4258 switch (ppd->pp_acc_size) { 4259 case 1: 4260 ddi_put8(bgep->io_handle, regaddr, regval); 4261 break; 4262 4263 case 2: 4264 ddi_put16(bgep->io_handle, regaddr, regval); 4265 break; 4266 4267 case 4: 4268 ddi_put32(bgep->io_handle, regaddr, regval); 4269 break; 4270 4271 case 8: 4272 ddi_put64(bgep->io_handle, regaddr, regval); 4273 break; 4274 } 4275 BGE_PCICHK(bgep); 4276 } 4277 4278 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4279 #pragma no_inline(bge_chip_peek_nic) 4280 4281 static void 4282 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4283 { 4284 uint64_t regoff; 4285 uint64_t regval; 4286 void *regaddr; 4287 4288 BGE_TRACE(("bge_chip_peek_nic($%p, $%p)", 4289 (void *)bgep, (void *)ppd)); 4290 4291 regoff = ppd->pp_acc_offset; 4292 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4293 regoff &= MWBAR_GRANULE_MASK; 4294 regoff += NIC_MEM_WINDOW_OFFSET; 4295 regaddr = PIO_ADDR(bgep, regoff); 4296 4297 switch (ppd->pp_acc_size) { 4298 case 1: 4299 regval = ddi_get8(bgep->io_handle, regaddr); 4300 break; 4301 4302 case 2: 4303 regval = ddi_get16(bgep->io_handle, regaddr); 4304 break; 4305 4306 case 4: 4307 regval = ddi_get32(bgep->io_handle, regaddr); 4308 break; 4309 4310 case 8: 4311 regval = ddi_get64(bgep->io_handle, regaddr); 4312 break; 4313 } 4314 4315 ppd->pp_acc_data = regval; 4316 } 4317 4318 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4319 #pragma no_inline(bge_chip_poke_nic) 4320 4321 static void 4322 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4323 { 4324 uint64_t regoff; 4325 uint64_t regval; 4326 void *regaddr; 4327 4328 BGE_TRACE(("bge_chip_poke_nic($%p, $%p)", 4329 (void *)bgep, (void *)ppd)); 4330 4331 regoff = ppd->pp_acc_offset; 4332 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4333 regoff &= MWBAR_GRANULE_MASK; 4334 regoff += NIC_MEM_WINDOW_OFFSET; 4335 regaddr = PIO_ADDR(bgep, regoff); 4336 regval = ppd->pp_acc_data; 4337 4338 switch (ppd->pp_acc_size) { 4339 case 1: 4340 ddi_put8(bgep->io_handle, regaddr, regval); 4341 break; 4342 4343 case 2: 4344 ddi_put16(bgep->io_handle, regaddr, regval); 4345 break; 4346 4347 case 4: 4348 ddi_put32(bgep->io_handle, regaddr, regval); 4349 break; 4350 4351 case 8: 4352 ddi_put64(bgep->io_handle, regaddr, regval); 4353 break; 4354 } 4355 BGE_PCICHK(bgep); 4356 } 4357 4358 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4359 #pragma no_inline(bge_chip_peek_mii) 4360 4361 static void 4362 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4363 { 4364 BGE_TRACE(("bge_chip_peek_mii($%p, $%p)", 4365 (void *)bgep, (void *)ppd)); 4366 4367 ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2); 4368 } 4369 4370 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4371 #pragma no_inline(bge_chip_poke_mii) 4372 4373 static void 4374 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4375 { 4376 BGE_TRACE(("bge_chip_poke_mii($%p, $%p)", 4377 (void *)bgep, (void *)ppd)); 4378 4379 bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 4380 } 4381 4382 #if BGE_SEE_IO32 4383 4384 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4385 #pragma no_inline(bge_chip_peek_seeprom) 4386 4387 static void 4388 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4389 { 4390 uint32_t data; 4391 int err; 4392 4393 BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)", 4394 (void *)bgep, (void *)ppd)); 4395 4396 err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data); 4397 ppd->pp_acc_data = err ? ~0ull : data; 4398 } 4399 4400 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4401 #pragma no_inline(bge_chip_poke_seeprom) 4402 4403 static void 4404 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4405 { 4406 uint32_t data; 4407 4408 BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)", 4409 (void *)bgep, (void *)ppd)); 4410 4411 data = ppd->pp_acc_data; 4412 (void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data); 4413 } 4414 #endif /* BGE_SEE_IO32 */ 4415 4416 #if BGE_FLASH_IO32 4417 4418 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4419 #pragma no_inline(bge_chip_peek_flash) 4420 4421 static void 4422 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd) 4423 { 4424 uint32_t data; 4425 int err; 4426 4427 BGE_TRACE(("bge_chip_peek_flash($%p, $%p)", 4428 (void *)bgep, (void *)ppd)); 4429 4430 err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data); 4431 ppd->pp_acc_data = err ? ~0ull : data; 4432 } 4433 4434 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4435 #pragma no_inline(bge_chip_poke_flash) 4436 4437 static void 4438 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd) 4439 { 4440 uint32_t data; 4441 4442 BGE_TRACE(("bge_chip_poke_flash($%p, $%p)", 4443 (void *)bgep, (void *)ppd)); 4444 4445 data = ppd->pp_acc_data; 4446 (void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE, 4447 ppd->pp_acc_offset, &data); 4448 } 4449 #endif /* BGE_FLASH_IO32 */ 4450 4451 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd); 4452 #pragma no_inline(bge_chip_peek_mem) 4453 4454 static void 4455 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd) 4456 { 4457 uint64_t regval; 4458 void *vaddr; 4459 4460 BGE_TRACE(("bge_chip_peek_bge($%p, $%p)", 4461 (void *)bgep, (void *)ppd)); 4462 4463 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4464 4465 switch (ppd->pp_acc_size) { 4466 case 1: 4467 regval = *(uint8_t *)vaddr; 4468 break; 4469 4470 case 2: 4471 regval = *(uint16_t *)vaddr; 4472 break; 4473 4474 case 4: 4475 regval = *(uint32_t *)vaddr; 4476 break; 4477 4478 case 8: 4479 regval = *(uint64_t *)vaddr; 4480 break; 4481 } 4482 4483 BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 4484 (void *)bgep, (void *)ppd, regval, vaddr)); 4485 4486 ppd->pp_acc_data = regval; 4487 } 4488 4489 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd); 4490 #pragma no_inline(bge_chip_poke_mem) 4491 4492 static void 4493 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd) 4494 { 4495 uint64_t regval; 4496 void *vaddr; 4497 4498 BGE_TRACE(("bge_chip_poke_mem($%p, $%p)", 4499 (void *)bgep, (void *)ppd)); 4500 4501 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4502 regval = ppd->pp_acc_data; 4503 4504 BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 4505 (void *)bgep, (void *)ppd, regval, vaddr)); 4506 4507 switch (ppd->pp_acc_size) { 4508 case 1: 4509 *(uint8_t *)vaddr = (uint8_t)regval; 4510 break; 4511 4512 case 2: 4513 *(uint16_t *)vaddr = (uint16_t)regval; 4514 break; 4515 4516 case 4: 4517 *(uint32_t *)vaddr = (uint32_t)regval; 4518 break; 4519 4520 case 8: 4521 *(uint64_t *)vaddr = (uint64_t)regval; 4522 break; 4523 } 4524 } 4525 4526 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 4527 struct iocblk *iocp); 4528 #pragma no_inline(bge_pp_ioctl) 4529 4530 static enum ioc_reply 4531 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 4532 { 4533 void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd); 4534 bge_peekpoke_t *ppd; 4535 dma_area_t *areap; 4536 uint64_t sizemask; 4537 uint64_t mem_va; 4538 uint64_t maxoff; 4539 boolean_t peek; 4540 4541 switch (cmd) { 4542 default: 4543 /* NOTREACHED */ 4544 bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd); 4545 return (IOC_INVAL); 4546 4547 case BGE_PEEK: 4548 peek = B_TRUE; 4549 break; 4550 4551 case BGE_POKE: 4552 peek = B_FALSE; 4553 break; 4554 } 4555 4556 /* 4557 * Validate format of ioctl 4558 */ 4559 if (iocp->ioc_count != sizeof (bge_peekpoke_t)) 4560 return (IOC_INVAL); 4561 if (mp->b_cont == NULL) 4562 return (IOC_INVAL); 4563 ppd = (bge_peekpoke_t *)mp->b_cont->b_rptr; 4564 4565 /* 4566 * Validate request parameters 4567 */ 4568 switch (ppd->pp_acc_space) { 4569 default: 4570 return (IOC_INVAL); 4571 4572 case BGE_PP_SPACE_CFG: 4573 /* 4574 * Config space 4575 */ 4576 sizemask = 8|4|2|1; 4577 mem_va = 0; 4578 maxoff = PCI_CONF_HDR_SIZE; 4579 ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg; 4580 break; 4581 4582 case BGE_PP_SPACE_REG: 4583 /* 4584 * Memory-mapped I/O space 4585 */ 4586 sizemask = 8|4|2|1; 4587 mem_va = 0; 4588 maxoff = RIAAR_REGISTER_MAX; 4589 ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg; 4590 break; 4591 4592 case BGE_PP_SPACE_NIC: 4593 /* 4594 * NIC on-chip memory 4595 */ 4596 sizemask = 8|4|2|1; 4597 mem_va = 0; 4598 maxoff = MWBAR_ONCHIP_MAX; 4599 ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic; 4600 break; 4601 4602 case BGE_PP_SPACE_MII: 4603 /* 4604 * PHY's MII registers 4605 * NB: all PHY registers are two bytes, but the 4606 * addresses increment in ones (word addressing). 4607 * So we scale the address here, then undo the 4608 * transformation inside the peek/poke functions. 4609 */ 4610 ppd->pp_acc_offset *= 2; 4611 sizemask = 2; 4612 mem_va = 0; 4613 maxoff = (MII_MAXREG+1)*2; 4614 ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii; 4615 break; 4616 4617 #if BGE_SEE_IO32 4618 case BGE_PP_SPACE_SEEPROM: 4619 /* 4620 * Attached SEEPROM(s), if any. 4621 * NB: we use the high-order bits of the 'address' as 4622 * a device select to accommodate multiple SEEPROMS, 4623 * If each one is the maximum size (64kbytes), this 4624 * makes them appear contiguous. Otherwise, there may 4625 * be holes in the mapping. ENxS doesn't have any 4626 * SEEPROMs anyway ... 4627 */ 4628 sizemask = 4; 4629 mem_va = 0; 4630 maxoff = SEEPROM_DEV_AND_ADDR_MASK; 4631 ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom; 4632 break; 4633 #endif /* BGE_SEE_IO32 */ 4634 4635 #if BGE_FLASH_IO32 4636 case BGE_PP_SPACE_FLASH: 4637 /* 4638 * Attached Flash device (if any); a maximum of one device 4639 * is currently supported. But it can be up to 1MB (unlike 4640 * the 64k limit on SEEPROMs) so why would you need more ;-) 4641 */ 4642 sizemask = 4; 4643 mem_va = 0; 4644 maxoff = NVM_FLASH_ADDR_MASK; 4645 ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash; 4646 break; 4647 #endif /* BGE_FLASH_IO32 */ 4648 4649 case BGE_PP_SPACE_BGE: 4650 /* 4651 * BGE data structure! 4652 */ 4653 sizemask = 8|4|2|1; 4654 mem_va = (uintptr_t)bgep; 4655 maxoff = sizeof (*bgep); 4656 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 4657 break; 4658 4659 case BGE_PP_SPACE_STATUS: 4660 case BGE_PP_SPACE_STATISTICS: 4661 case BGE_PP_SPACE_TXDESC: 4662 case BGE_PP_SPACE_TXBUFF: 4663 case BGE_PP_SPACE_RXDESC: 4664 case BGE_PP_SPACE_RXBUFF: 4665 /* 4666 * Various DMA_AREAs 4667 */ 4668 switch (ppd->pp_acc_space) { 4669 case BGE_PP_SPACE_TXDESC: 4670 areap = &bgep->tx_desc; 4671 break; 4672 case BGE_PP_SPACE_TXBUFF: 4673 areap = &bgep->tx_buff[0]; 4674 break; 4675 case BGE_PP_SPACE_RXDESC: 4676 areap = &bgep->rx_desc[0]; 4677 break; 4678 case BGE_PP_SPACE_RXBUFF: 4679 areap = &bgep->rx_buff[0]; 4680 break; 4681 case BGE_PP_SPACE_STATUS: 4682 areap = &bgep->status_block; 4683 break; 4684 case BGE_PP_SPACE_STATISTICS: 4685 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 4686 areap = &bgep->statistics; 4687 break; 4688 } 4689 4690 sizemask = 8|4|2|1; 4691 mem_va = (uintptr_t)areap->mem_va; 4692 maxoff = areap->alength; 4693 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 4694 break; 4695 } 4696 4697 switch (ppd->pp_acc_size) { 4698 default: 4699 return (IOC_INVAL); 4700 4701 case 8: 4702 case 4: 4703 case 2: 4704 case 1: 4705 if ((ppd->pp_acc_size & sizemask) == 0) 4706 return (IOC_INVAL); 4707 break; 4708 } 4709 4710 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 4711 return (IOC_INVAL); 4712 4713 if (ppd->pp_acc_offset >= maxoff) 4714 return (IOC_INVAL); 4715 4716 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 4717 return (IOC_INVAL); 4718 4719 /* 4720 * All OK - go do it! 4721 */ 4722 ppd->pp_acc_offset += mem_va; 4723 (*ppfn)(bgep, ppd); 4724 return (peek ? IOC_REPLY : IOC_ACK); 4725 } 4726 4727 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 4728 struct iocblk *iocp); 4729 #pragma no_inline(bge_diag_ioctl) 4730 4731 static enum ioc_reply 4732 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 4733 { 4734 ASSERT(mutex_owned(bgep->genlock)); 4735 4736 switch (cmd) { 4737 default: 4738 /* NOTREACHED */ 4739 bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd); 4740 return (IOC_INVAL); 4741 4742 case BGE_DIAG: 4743 /* 4744 * Currently a no-op 4745 */ 4746 return (IOC_ACK); 4747 4748 case BGE_PEEK: 4749 case BGE_POKE: 4750 return (bge_pp_ioctl(bgep, cmd, mp, iocp)); 4751 4752 case BGE_PHY_RESET: 4753 return (IOC_RESTART_ACK); 4754 4755 case BGE_SOFT_RESET: 4756 case BGE_HARD_RESET: 4757 /* 4758 * Reset and reinitialise the 570x hardware 4759 */ 4760 bge_restart(bgep, cmd == BGE_HARD_RESET); 4761 return (IOC_ACK); 4762 } 4763 4764 /* NOTREACHED */ 4765 } 4766 4767 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 4768 4769 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 4770 struct iocblk *iocp); 4771 #pragma no_inline(bge_mii_ioctl) 4772 4773 static enum ioc_reply 4774 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 4775 { 4776 struct bge_mii_rw *miirwp; 4777 4778 /* 4779 * Validate format of ioctl 4780 */ 4781 if (iocp->ioc_count != sizeof (struct bge_mii_rw)) 4782 return (IOC_INVAL); 4783 if (mp->b_cont == NULL) 4784 return (IOC_INVAL); 4785 miirwp = (struct bge_mii_rw *)mp->b_cont->b_rptr; 4786 4787 /* 4788 * Validate request parameters ... 4789 */ 4790 if (miirwp->mii_reg > MII_MAXREG) 4791 return (IOC_INVAL); 4792 4793 switch (cmd) { 4794 default: 4795 /* NOTREACHED */ 4796 bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd); 4797 return (IOC_INVAL); 4798 4799 case BGE_MII_READ: 4800 miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg); 4801 return (IOC_REPLY); 4802 4803 case BGE_MII_WRITE: 4804 bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data); 4805 return (IOC_ACK); 4806 } 4807 4808 /* NOTREACHED */ 4809 } 4810 4811 #if BGE_SEE_IO32 4812 4813 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 4814 struct iocblk *iocp); 4815 #pragma no_inline(bge_see_ioctl) 4816 4817 static enum ioc_reply 4818 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 4819 { 4820 struct bge_see_rw *seerwp; 4821 4822 /* 4823 * Validate format of ioctl 4824 */ 4825 if (iocp->ioc_count != sizeof (struct bge_see_rw)) 4826 return (IOC_INVAL); 4827 if (mp->b_cont == NULL) 4828 return (IOC_INVAL); 4829 seerwp = (struct bge_see_rw *)mp->b_cont->b_rptr; 4830 4831 /* 4832 * Validate request parameters ... 4833 */ 4834 if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK) 4835 return (IOC_INVAL); 4836 4837 switch (cmd) { 4838 default: 4839 /* NOTREACHED */ 4840 bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd); 4841 return (IOC_INVAL); 4842 4843 case BGE_SEE_READ: 4844 case BGE_SEE_WRITE: 4845 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 4846 seerwp->see_addr, &seerwp->see_data); 4847 return (IOC_REPLY); 4848 } 4849 4850 /* NOTREACHED */ 4851 } 4852 4853 #endif /* BGE_SEE_IO32 */ 4854 4855 #if BGE_FLASH_IO32 4856 4857 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 4858 struct iocblk *iocp); 4859 #pragma no_inline(bge_flash_ioctl) 4860 4861 static enum ioc_reply 4862 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 4863 { 4864 struct bge_flash_rw *flashrwp; 4865 4866 /* 4867 * Validate format of ioctl 4868 */ 4869 if (iocp->ioc_count != sizeof (struct bge_flash_rw)) 4870 return (IOC_INVAL); 4871 if (mp->b_cont == NULL) 4872 return (IOC_INVAL); 4873 flashrwp = (struct bge_flash_rw *)mp->b_cont->b_rptr; 4874 4875 /* 4876 * Validate request parameters ... 4877 */ 4878 if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK) 4879 return (IOC_INVAL); 4880 4881 switch (cmd) { 4882 default: 4883 /* NOTREACHED */ 4884 bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd); 4885 return (IOC_INVAL); 4886 4887 case BGE_FLASH_READ: 4888 case BGE_FLASH_WRITE: 4889 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 4890 flashrwp->flash_addr, &flashrwp->flash_data); 4891 return (IOC_REPLY); 4892 } 4893 4894 /* NOTREACHED */ 4895 } 4896 4897 #endif /* BGE_FLASH_IO32 */ 4898 4899 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 4900 struct iocblk *iocp); 4901 #pragma no_inline(bge_chip_ioctl) 4902 4903 enum ioc_reply 4904 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 4905 { 4906 int cmd; 4907 4908 BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)", 4909 (void *)bgep, (void *)wq, (void *)mp, (void *)iocp)); 4910 4911 ASSERT(mutex_owned(bgep->genlock)); 4912 4913 cmd = iocp->ioc_cmd; 4914 switch (cmd) { 4915 default: 4916 /* NOTREACHED */ 4917 bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd); 4918 return (IOC_INVAL); 4919 4920 case BGE_DIAG: 4921 case BGE_PEEK: 4922 case BGE_POKE: 4923 case BGE_PHY_RESET: 4924 case BGE_SOFT_RESET: 4925 case BGE_HARD_RESET: 4926 #if BGE_DEBUGGING || BGE_DO_PPIO 4927 return (bge_diag_ioctl(bgep, cmd, mp, iocp)); 4928 #else 4929 return (IOC_INVAL); 4930 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 4931 4932 case BGE_MII_READ: 4933 case BGE_MII_WRITE: 4934 return (bge_mii_ioctl(bgep, cmd, mp, iocp)); 4935 4936 #if BGE_SEE_IO32 4937 case BGE_SEE_READ: 4938 case BGE_SEE_WRITE: 4939 return (bge_see_ioctl(bgep, cmd, mp, iocp)); 4940 #endif /* BGE_SEE_IO32 */ 4941 4942 #if BGE_FLASH_IO32 4943 case BGE_FLASH_READ: 4944 case BGE_FLASH_WRITE: 4945 return (bge_flash_ioctl(bgep, cmd, mp, iocp)); 4946 #endif /* BGE_FLASH_IO32 */ 4947 } 4948 4949 /* NOTREACHED */ 4950 } 4951 4952 void 4953 bge_chip_blank(void *arg, time_t ticks, uint_t count) 4954 { 4955 bge_t *bgep = arg; 4956 4957 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks); 4958 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count); 4959 } 4960 4961 #ifdef BGE_IPMI_ASF 4962 4963 uint32_t 4964 bge_nic_read32(bge_t *bgep, bge_regno_t addr) 4965 { 4966 uint32_t data; 4967 4968 if (!bgep->asf_wordswapped) { 4969 /* a workaround word swap error */ 4970 if (addr & 4) 4971 addr = addr - 4; 4972 else 4973 addr = addr + 4; 4974 } 4975 4976 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 4977 data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR); 4978 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 4979 4980 return (data); 4981 } 4982 4983 4984 void 4985 bge_asf_update_status(bge_t *bgep) 4986 { 4987 uint32_t event; 4988 4989 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE); 4990 bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4); 4991 bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX, 3); 4992 4993 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 4994 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 4995 } 4996 4997 4998 /* 4999 * The driver is supposed to notify ASF that the OS is still running 5000 * every three seconds, otherwise the management server may attempt 5001 * to reboot the machine. If it hasn't actually failed, this is 5002 * not a desireable result. However, this isn't running as a real-time 5003 * thread, and even if it were, it might not be able to generate the 5004 * heartbeat in a timely manner due to system load. As it isn't a 5005 * significant strain on the machine, we will set the interval to half 5006 * of the required value. 5007 */ 5008 void 5009 bge_asf_heartbeat(void *bgep) 5010 { 5011 bge_asf_update_status((bge_t *)bgep); 5012 ((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep, 5013 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL)); 5014 } 5015 5016 5017 void 5018 bge_asf_stop_timer(bge_t *bgep) 5019 { 5020 timeout_id_t tmp_id = 0; 5021 5022 while ((bgep->asf_timeout_id != 0) && 5023 (tmp_id != bgep->asf_timeout_id)) { 5024 tmp_id = bgep->asf_timeout_id; 5025 (void) untimeout(tmp_id); 5026 } 5027 bgep->asf_timeout_id = 0; 5028 } 5029 5030 5031 5032 /* 5033 * This function should be placed at the earliest postion of bge_attach(). 5034 */ 5035 void 5036 bge_asf_get_config(bge_t *bgep) 5037 { 5038 uint32_t nicsig; 5039 uint32_t niccfg; 5040 5041 nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR); 5042 if (nicsig == BGE_NIC_DATA_SIG) { 5043 niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR); 5044 if (niccfg & BGE_NIC_CFG_ENABLE_ASF) 5045 /* 5046 * Here, we don't consider BAXTER, because BGE haven't 5047 * supported BAXTER (that is 5752). Also, as I know, 5048 * BAXTER doesn't support ASF feature. 5049 */ 5050 bgep->asf_enabled = B_TRUE; 5051 else 5052 bgep->asf_enabled = B_FALSE; 5053 } else 5054 bgep->asf_enabled = B_FALSE; 5055 } 5056 5057 5058 void 5059 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode) 5060 { 5061 uint32_t tries; 5062 uint32_t event; 5063 5064 ASSERT(bgep->asf_enabled); 5065 5066 /* Issues "pause firmware" command and wait for ACK */ 5067 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW); 5068 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5069 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5070 5071 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5072 tries = 0; 5073 while ((event & RRER_ASF_EVENT) && (tries < 100)) { 5074 drv_usecwait(1); 5075 tries ++; 5076 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5077 } 5078 5079 bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX, 5080 BGE_MAGIC_NUM_FIRMWARE_INIT_DONE); 5081 5082 if (bgep->asf_newhandshake) { 5083 switch (mode) { 5084 case BGE_INIT_RESET: 5085 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5086 BGE_DRV_STATE_START); 5087 break; 5088 case BGE_SHUTDOWN_RESET: 5089 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5090 BGE_DRV_STATE_UNLOAD); 5091 break; 5092 case BGE_SUSPEND_RESET: 5093 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5094 BGE_DRV_STATE_SUSPEND); 5095 break; 5096 default: 5097 break; 5098 } 5099 } 5100 } 5101 5102 5103 void 5104 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode) 5105 { 5106 switch (mode) { 5107 case BGE_INIT_RESET: 5108 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5109 BGE_DRV_STATE_START); 5110 break; 5111 case BGE_SHUTDOWN_RESET: 5112 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5113 BGE_DRV_STATE_UNLOAD); 5114 break; 5115 case BGE_SUSPEND_RESET: 5116 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5117 BGE_DRV_STATE_SUSPEND); 5118 break; 5119 default: 5120 break; 5121 } 5122 } 5123 5124 5125 void 5126 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode) 5127 { 5128 switch (mode) { 5129 case BGE_INIT_RESET: 5130 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5131 BGE_DRV_STATE_START_DONE); 5132 break; 5133 case BGE_SHUTDOWN_RESET: 5134 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5135 BGE_DRV_STATE_UNLOAD_DONE); 5136 break; 5137 default: 5138 break; 5139 } 5140 } 5141 5142 #endif /* BGE_IPMI_ASF */ 5143