1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include "bge_impl.h" 30 31 #define PIO_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->io_regs+(offset))) 32 33 /* 34 * Future features ... ? 35 */ 36 #define BGE_CFG_IO8 1 /* 8/16-bit cfg space BIS/BIC */ 37 #define BGE_IND_IO32 0 /* indirect access code */ 38 #define BGE_SEE_IO32 1 /* SEEPROM access code */ 39 #define BGE_FLASH_IO32 1 /* FLASH access code */ 40 41 /* 42 * BGE MSI tunable: 43 * 44 * By default MSI is enabled on all supported platforms but it is disabled 45 * for some Broadcom chips due to known MSI hardware issues. Currently MSI 46 * is enabled only for 5714C A2 and 5715C A2 broadcom chips. 47 */ 48 #if defined(__sparc) 49 boolean_t bge_enable_msi = B_TRUE; 50 #else 51 boolean_t bge_enable_msi = B_FALSE; 52 #endif 53 54 /* 55 * Property names 56 */ 57 static char knownids_propname[] = "bge-known-subsystems"; 58 59 /* 60 * Patchable globals: 61 * 62 * bge_autorecover 63 * Enables/disables automatic recovery after fault detection 64 * 65 * bge_mlcr_default 66 * Value to program into the MLCR; controls the chip's GPIO pins 67 * 68 * bge_dma_{rd,wr}prio 69 * Relative priorities of DMA reads & DMA writes respectively. 70 * These may each be patched to any value 0-3. Equal values 71 * will give "fair" (round-robin) arbitration for PCI access. 72 * Unequal values will give one or the other function priority. 73 * 74 * bge_dma_rwctrl 75 * Value to put in the Read/Write DMA control register. See 76 * the Broadcom PRM for things you can fiddle with in this 77 * register ... 78 * 79 * bge_{tx,rx}_{count,ticks}_{norm,intr} 80 * Send/receive interrupt coalescing parameters. Counts are 81 * #s of descriptors, ticks are in microseconds. *norm* values 82 * apply between status updates/interrupts; the *intr* values 83 * refer to the 'during-interrupt' versions - see the PRM. 84 * 85 * NOTE: these values have been determined by measurement. They 86 * differ significantly from the values recommended in the PRM. 87 */ 88 static uint32_t bge_autorecover = 1; 89 static uint32_t bge_mlcr_default = MLCR_DEFAULT; 90 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714; 91 92 static uint32_t bge_dma_rdprio = 1; 93 static uint32_t bge_dma_wrprio = 0; 94 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT; 95 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721; 96 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714; 97 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715; 98 99 uint32_t bge_rx_ticks_norm = 128; 100 uint32_t bge_tx_ticks_norm = 2048; /* 8 for FJ2+ !?!? */ 101 uint32_t bge_rx_count_norm = 8; 102 uint32_t bge_tx_count_norm = 128; 103 104 static uint32_t bge_rx_ticks_intr = 128; 105 static uint32_t bge_tx_ticks_intr = 0; /* 8 for FJ2+ !?!? */ 106 static uint32_t bge_rx_count_intr = 2; 107 static uint32_t bge_tx_count_intr = 0; 108 109 /* 110 * Memory pool configuration parameters. 111 * 112 * These are generally specific to each member of the chip family, since 113 * each one may have a different memory size/configuration. 114 * 115 * Setting the mbuf pool length for a specific type of chip to 0 inhibits 116 * the driver from programming the various registers; instead they are left 117 * at their hardware defaults. This is the preferred option for later chips 118 * (5705+), whereas the older chips *required* these registers to be set, 119 * since the h/w default was 0 ;-( 120 */ 121 static uint32_t bge_mbuf_pool_base = MBUF_POOL_BASE_DEFAULT; 122 static uint32_t bge_mbuf_pool_base_5704 = MBUF_POOL_BASE_5704; 123 static uint32_t bge_mbuf_pool_base_5705 = MBUF_POOL_BASE_5705; 124 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721; 125 static uint32_t bge_mbuf_pool_len = MBUF_POOL_LENGTH_DEFAULT; 126 static uint32_t bge_mbuf_pool_len_5704 = MBUF_POOL_LENGTH_5704; 127 static uint32_t bge_mbuf_pool_len_5705 = 0; /* use h/w default */ 128 static uint32_t bge_mbuf_pool_len_5721 = 0; 129 130 /* 131 * Various high and low water marks, thresholds, etc ... 132 * 133 * Note: these are taken from revision 7 of the PRM, and some are different 134 * from both the values in earlier PRMs *and* those determined experimentally 135 * and used in earlier versions of this driver ... 136 */ 137 static uint32_t bge_mbuf_hi_water = MBUF_HIWAT_DEFAULT; 138 static uint32_t bge_mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_DEFAULT; 139 static uint32_t bge_mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_DEFAULT; 140 141 static uint32_t bge_dmad_lo_water = DMAD_POOL_LOWAT_DEFAULT; 142 static uint32_t bge_dmad_hi_water = DMAD_POOL_HIWAT_DEFAULT; 143 static uint32_t bge_lowat_recv_frames = LOWAT_MAX_RECV_FRAMES_DEFAULT; 144 145 static uint32_t bge_replenish_std = STD_RCV_BD_REPLENISH_DEFAULT; 146 static uint32_t bge_replenish_mini = MINI_RCV_BD_REPLENISH_DEFAULT; 147 static uint32_t bge_replenish_jumbo = JUMBO_RCV_BD_REPLENISH_DEFAULT; 148 149 static uint32_t bge_watchdog_count = 1 << 16; 150 static uint16_t bge_dma_miss_limit = 20; 151 152 static uint32_t bge_stop_start_on_sync = 0; 153 154 boolean_t bge_jumbo_enable = B_TRUE; 155 static uint32_t bge_default_jumbo_size = BGE_JUMBO_BUFF_SIZE; 156 157 /* 158 * ========== Low-level chip & ring buffer manipulation ========== 159 */ 160 161 #define BGE_DBG BGE_DBG_REGS /* debug flag for this code */ 162 163 164 /* 165 * Config space read-modify-write routines 166 */ 167 168 #if BGE_CFG_IO8 169 170 /* 171 * 8- and 16-bit set/clr operations are not used; all the config registers 172 * that we need to do bit-twiddling on are 32 bits wide. I'll leave the 173 * code here, though, in case we ever find that we do want it after all ... 174 */ 175 176 static void bge_cfg_set8(bge_t *bgep, bge_regno_t regno, uint8_t bits); 177 #pragma inline(bge_cfg_set8) 178 179 static void 180 bge_cfg_set8(bge_t *bgep, bge_regno_t regno, uint8_t bits) 181 { 182 uint8_t regval; 183 184 BGE_TRACE(("bge_cfg_set8($%p, 0x%lx, 0x%x)", 185 (void *)bgep, regno, bits)); 186 187 regval = pci_config_get8(bgep->cfg_handle, regno); 188 189 BGE_DEBUG(("bge_cfg_set8($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 190 (void *)bgep, regno, bits, regval, regval | bits)); 191 192 regval |= bits; 193 pci_config_put8(bgep->cfg_handle, regno, regval); 194 } 195 196 static void bge_cfg_clr8(bge_t *bgep, bge_regno_t regno, uint8_t bits); 197 #pragma inline(bge_cfg_clr8) 198 199 static void 200 bge_cfg_clr8(bge_t *bgep, bge_regno_t regno, uint8_t bits) 201 { 202 uint8_t regval; 203 204 BGE_TRACE(("bge_cfg_clr8($%p, 0x%lx, 0x%x)", 205 (void *)bgep, regno, bits)); 206 207 regval = pci_config_get8(bgep->cfg_handle, regno); 208 209 BGE_DEBUG(("bge_cfg_clr8($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 210 (void *)bgep, regno, bits, regval, regval & ~bits)); 211 212 regval &= ~bits; 213 pci_config_put8(bgep->cfg_handle, regno, regval); 214 } 215 216 static void bge_cfg_set16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 217 #pragma inline(bge_cfg_set16) 218 219 static void 220 bge_cfg_set16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 221 { 222 uint16_t regval; 223 224 BGE_TRACE(("bge_cfg_set16($%p, 0x%lx, 0x%x)", 225 (void *)bgep, regno, bits)); 226 227 regval = pci_config_get16(bgep->cfg_handle, regno); 228 229 BGE_DEBUG(("bge_cfg_set16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 230 (void *)bgep, regno, bits, regval, regval | bits)); 231 232 regval |= bits; 233 pci_config_put16(bgep->cfg_handle, regno, regval); 234 } 235 236 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 237 #pragma inline(bge_cfg_clr16) 238 239 static void 240 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 241 { 242 uint16_t regval; 243 244 BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)", 245 (void *)bgep, regno, bits)); 246 247 regval = pci_config_get16(bgep->cfg_handle, regno); 248 249 BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 250 (void *)bgep, regno, bits, regval, regval & ~bits)); 251 252 regval &= ~bits; 253 pci_config_put16(bgep->cfg_handle, regno, regval); 254 } 255 256 #endif /* BGE_CFG_IO8 */ 257 258 static void bge_cfg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 259 #pragma inline(bge_cfg_set32) 260 261 static void 262 bge_cfg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 263 { 264 uint32_t regval; 265 266 BGE_TRACE(("bge_cfg_set32($%p, 0x%lx, 0x%x)", 267 (void *)bgep, regno, bits)); 268 269 regval = pci_config_get32(bgep->cfg_handle, regno); 270 271 BGE_DEBUG(("bge_cfg_set32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 272 (void *)bgep, regno, bits, regval, regval | bits)); 273 274 regval |= bits; 275 pci_config_put32(bgep->cfg_handle, regno, regval); 276 } 277 278 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 279 #pragma inline(bge_cfg_clr32) 280 281 static void 282 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 283 { 284 uint32_t regval; 285 286 BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)", 287 (void *)bgep, regno, bits)); 288 289 regval = pci_config_get32(bgep->cfg_handle, regno); 290 291 BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 292 (void *)bgep, regno, bits, regval, regval & ~bits)); 293 294 regval &= ~bits; 295 pci_config_put32(bgep->cfg_handle, regno, regval); 296 } 297 298 #if BGE_IND_IO32 299 300 /* 301 * Indirect access to registers & RISC scratchpads, using config space 302 * accesses only. 303 * 304 * This isn't currently used, but someday we might want to use it for 305 * restoring the Subsystem Device/Vendor registers (which aren't directly 306 * writable in Config Space), or for downloading firmware into the RISCs 307 * 308 * In any case there are endian issues to be resolved before this code is 309 * enabled; the bizarre way that bytes get twisted by this chip AND by 310 * the PCI bridge in SPARC systems mean that we shouldn't enable it until 311 * it's been thoroughly tested for all access sizes on all supported 312 * architectures (SPARC *and* x86!). 313 */ 314 static uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno); 315 #pragma inline(bge_ind_get32) 316 317 static uint32_t 318 bge_ind_get32(bge_t *bgep, bge_regno_t regno) 319 { 320 uint32_t val; 321 322 BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno)); 323 324 ASSERT(mutex_owned(bgep->genlock)); 325 326 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 327 val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR); 328 329 BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x", 330 (void *)bgep, regno, val)); 331 332 return (val); 333 } 334 335 static void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val); 336 #pragma inline(bge_ind_put32) 337 338 static void 339 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val) 340 { 341 BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)", 342 (void *)bgep, regno, val)); 343 344 ASSERT(mutex_owned(bgep->genlock)); 345 346 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 347 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val); 348 } 349 350 #endif /* BGE_IND_IO32 */ 351 352 #if BGE_DEBUGGING 353 354 static void bge_pci_check(bge_t *bgep); 355 #pragma no_inline(bge_pci_check) 356 357 static void 358 bge_pci_check(bge_t *bgep) 359 { 360 uint16_t pcistatus; 361 362 pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT); 363 if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0) 364 BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x", 365 (void *)bgep, pcistatus)); 366 } 367 368 #endif /* BGE_DEBUGGING */ 369 370 /* 371 * Perform first-stage chip (re-)initialisation, using only config-space 372 * accesses: 373 * 374 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 375 * returning the data in the structure pointed to by <idp>. 376 * + Configure the target-mode endianness (swap) options. 377 * + Disable interrupts and enable Memory Space accesses. 378 * + Enable or disable Bus Mastering according to the <enable_dma> flag. 379 * 380 * This sequence is adapted from Broadcom document 570X-PG102-R, 381 * page 102, steps 1-3, 6-8 and 11-13. The omitted parts of the sequence 382 * are 4 and 5 (Reset Core and wait) which are handled elsewhere. 383 * 384 * This function MUST be called before any non-config-space accesses 385 * are made; on this first call <enable_dma> is B_FALSE, and it 386 * effectively performs steps 3-1(!) of the initialisation sequence 387 * (the rest are not required but should be harmless). 388 * 389 * It MUST also be called after a chip reset, as this disables 390 * Memory Space cycles! In this case, <enable_dma> is B_TRUE, and 391 * it is effectively performing steps 6-8. 392 */ 393 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma); 394 #pragma no_inline(bge_chip_cfg_init) 395 396 void 397 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma) 398 { 399 ddi_acc_handle_t handle; 400 uint16_t command; 401 uint32_t mhcr; 402 uint16_t value16; 403 int i; 404 405 BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)", 406 (void *)bgep, (void *)cidp, enable_dma)); 407 408 /* 409 * Step 3: save PCI cache line size and subsystem vendor ID 410 * 411 * Read all the config-space registers that characterise the 412 * chip, specifically vendor/device/revision/subsystem vendor 413 * and subsystem device id. We expect (but don't check) that 414 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704) 415 * 416 * Also save all bus-transaction related registers (cache-line 417 * size, bus-grant/latency parameters, etc). Some of these are 418 * cleared by reset, so we'll have to restore them later. This 419 * comes from the Broadcom document 570X-PG102-R ... 420 * 421 * Note: Broadcom document 570X-PG102-R seems to be in error 422 * here w.r.t. the offsets of the Subsystem Vendor ID and 423 * Subsystem (Device) ID registers, which are the opposite way 424 * round according to the PCI standard. For good measure, we 425 * save/restore both anyway. 426 */ 427 handle = bgep->cfg_handle; 428 429 mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR); 430 cidp->asic_rev = mhcr & MHCR_CHIP_REV_MASK; 431 cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE); 432 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 433 434 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 435 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 436 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 437 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 438 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 439 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 440 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 441 442 BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s", 443 cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X", 444 cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow", 445 cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide", 446 cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low")); 447 BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 448 cidp->vendor, cidp->device, cidp->revision)); 449 BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x", 450 cidp->subven, cidp->subdev, cidp->asic_rev)); 451 BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x", 452 cidp->clsize, cidp->latency, cidp->command)); 453 454 /* 455 * Step 2 (also step 6): disable and clear interrupts. 456 * Steps 11-13: configure PIO endianness options, and enable 457 * indirect register access. We'll also select any other 458 * options controlled by the MHCR (e.g. tagged status, mask 459 * interrupt mode) at this stage ... 460 * 461 * Note: internally, the chip is 64-bit and BIG-endian, but 462 * since it talks to the host over a (LITTLE-endian) PCI bus, 463 * it normally swaps bytes around at the PCI interface. 464 * However, the PCI host bridge on SPARC systems normally 465 * swaps the byte lanes around too, since SPARCs are also 466 * BIG-endian. So it turns out that on SPARC, the right 467 * option is to tell the chip to swap (and the host bridge 468 * will swap back again), whereas on x86 we ask the chip 469 * NOT to swap, so the natural little-endianness of the 470 * PCI bus is assumed. Then the only thing that doesn't 471 * automatically work right is access to an 8-byte register 472 * by a little-endian host; but we don't want to set the 473 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte 474 * accesses don't go where expected ;-( So we live with 475 * that, and perform word-swaps in software in the few cases 476 * where a chip register is defined as an 8-byte value -- 477 * see the code below for details ... 478 * 479 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't 480 * very clear in the register description in the PRM, but 481 * Broadcom document 570X-PG104-R page 248 explains a little 482 * more (under "Broadcom Mask Mode"). The bit changes the way 483 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE 484 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same 485 * way as the 5700 did, which isn't very convenient. Setting 486 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT 487 * bit do just what its name says -- MASK the PCI #INTA output 488 * (i.e. deassert the signal at the pin) leaving all internal 489 * state unchanged. This is much more convenient for our 490 * interrupt handler, so we set MASK_INTERRUPT_MODE here. 491 * 492 * Note: the inconvenient semantics of the interrupt mailbox 493 * (nonzero disables and acknowledges/clears the interrupt, 494 * zero enables AND CLEARS it) would make race conditions 495 * likely in the interrupt handler: 496 * 497 * (1) acknowledge & disable interrupts 498 * (2) while (more to do) 499 * process packets 500 * (3) enable interrupts -- also clears pending 501 * 502 * If the chip received more packets and internally generated 503 * an interrupt between the check at (2) and the mbox write 504 * at (3), this interrupt would be lost :-( 505 * 506 * The best way to avoid this is to use TAGGED STATUS mode, 507 * where the chip includes a unique tag in each status block 508 * update, and the host, when re-enabling interrupts, passes 509 * the last tag it saw back to the chip; then the chip can 510 * see whether the host is truly up to date, and regenerate 511 * its interrupt if not. 512 */ 513 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 514 MHCR_ENABLE_TAGGED_STATUS_MODE | 515 MHCR_MASK_INTERRUPT_MODE | 516 MHCR_CLEAR_INTERRUPT_INTA; 517 518 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 519 mhcr |= MHCR_MASK_PCI_INT_OUTPUT; 520 521 #ifdef _BIG_ENDIAN 522 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 523 #endif /* _BIG_ENDIAN */ 524 525 pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr); 526 527 #ifdef BGE_IPMI_ASF 528 bgep->asf_wordswapped = B_FALSE; 529 #endif 530 /* 531 * Step 1 (also step 7): Enable PCI Memory Space accesses 532 * Disable Memory Write/Invalidate 533 * Enable or disable Bus Mastering 534 * 535 * Note that all other bits are taken from the original value saved 536 * the first time through here, rather than from the current register 537 * value, 'cos that will have been cleared by a soft RESET since. 538 * In this way we preserve the OBP/nexus-parent's preferred settings 539 * of the parity-error and system-error enable bits across multiple 540 * chip RESETs. 541 */ 542 command = bgep->chipid.command | PCI_COMM_MAE; 543 command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL); 544 if (enable_dma) 545 command |= PCI_COMM_ME; 546 /* 547 * on BCM5714 revision A0, false parity error gets generated 548 * due to a logic bug. Provide a workaround by disabling parity 549 * error. 550 */ 551 if (((cidp->device == DEVICE_ID_5714C) || 552 (cidp->device == DEVICE_ID_5714S)) && 553 (cidp->revision == REVISION_ID_5714_A0)) { 554 command &= ~PCI_COMM_PARITY_DETECT; 555 } 556 pci_config_put16(handle, PCI_CONF_COMM, command); 557 558 /* 559 * On some PCI-E device, there were instances when 560 * the device was still link training. 561 */ 562 if (bgep->chipid.pci_type == BGE_PCI_E) { 563 i = 0; 564 value16 = pci_config_get16(handle, PCI_CONF_COMM); 565 while ((value16 != command) && (i < 100)) { 566 drv_usecwait(200); 567 value16 = pci_config_get16(handle, PCI_CONF_COMM); 568 ++i; 569 } 570 } 571 572 /* 573 * Clear any remaining error status bits 574 */ 575 pci_config_put16(handle, PCI_CONF_STAT, ~0); 576 577 /* 578 * Do following if and only if the device is NOT BCM5714C OR 579 * BCM5715C 580 */ 581 if (!((cidp->device == DEVICE_ID_5714C) || 582 (cidp->device == DEVICE_ID_5715C))) { 583 /* 584 * Make sure these indirect-access registers are sane 585 * rather than random after power-up or reset 586 */ 587 pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0); 588 pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0); 589 } 590 /* 591 * Step 8: Disable PCI-X/PCI-E Relaxed Ordering 592 */ 593 bge_cfg_clr16(bgep, PCIX_CONF_COMM, PCIX_COMM_RELAXED); 594 595 if (cidp->pci_type == BGE_PCI_E) 596 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL, 597 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 598 } 599 600 #ifdef __amd64 601 /* 602 * Distinguish CPU types 603 * 604 * These use to distinguish AMD64 or Intel EM64T of CPU running mode. 605 * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine 606 * for PCI-Express based network interface card. This is the work-around 607 * for those nics. 608 */ 609 static boolean_t bge_get_em64t_type(void); 610 #pragma inline(bge_get_em64t_type) 611 612 static boolean_t 613 bge_get_em64t_type(void) 614 { 615 616 return (x86_vendor == X86_VENDOR_Intel); 617 } 618 #endif 619 620 /* 621 * Operating register get/set access routines 622 */ 623 624 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno); 625 #pragma inline(bge_reg_get32) 626 627 uint32_t 628 bge_reg_get32(bge_t *bgep, bge_regno_t regno) 629 { 630 BGE_TRACE(("bge_reg_get32($%p, 0x%lx)", 631 (void *)bgep, regno)); 632 633 return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno))); 634 } 635 636 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data); 637 #pragma inline(bge_reg_put32) 638 639 void 640 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data) 641 { 642 BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)", 643 (void *)bgep, regno, data)); 644 645 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data); 646 BGE_PCICHK(bgep); 647 } 648 649 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 650 #pragma inline(bge_reg_set32) 651 652 void 653 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 654 { 655 uint32_t regval; 656 657 BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)", 658 (void *)bgep, regno, bits)); 659 660 regval = bge_reg_get32(bgep, regno); 661 regval |= bits; 662 bge_reg_put32(bgep, regno, regval); 663 } 664 665 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 666 #pragma inline(bge_reg_clr32) 667 668 void 669 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 670 { 671 uint32_t regval; 672 673 BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)", 674 (void *)bgep, regno, bits)); 675 676 regval = bge_reg_get32(bgep, regno); 677 regval &= ~bits; 678 bge_reg_put32(bgep, regno, regval); 679 } 680 681 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno); 682 #pragma inline(bge_reg_get64) 683 684 static uint64_t 685 bge_reg_get64(bge_t *bgep, bge_regno_t regno) 686 { 687 uint64_t regval; 688 689 #ifdef __amd64 690 if (bge_get_em64t_type()) { 691 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 692 regval <<= 32; 693 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 694 } else { 695 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 696 } 697 #else 698 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 699 #endif 700 701 #ifdef _LITTLE_ENDIAN 702 regval = (regval >> 32) | (regval << 32); 703 #endif /* _LITTLE_ENDIAN */ 704 705 BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx", 706 (void *)bgep, regno, regval)); 707 708 return (regval); 709 } 710 711 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data); 712 #pragma inline(bge_reg_put64) 713 714 static void 715 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data) 716 { 717 BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)", 718 (void *)bgep, regno, data)); 719 720 #ifdef _LITTLE_ENDIAN 721 data = ((data >> 32) | (data << 32)); 722 #endif /* _LITTLE_ENDIAN */ 723 724 #ifdef __amd64 725 if (bge_get_em64t_type()) { 726 ddi_put32(bgep->io_handle, 727 PIO_ADDR(bgep, regno), (uint32_t)data); 728 BGE_PCICHK(bgep); 729 ddi_put32(bgep->io_handle, 730 PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32)); 731 732 } else { 733 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 734 } 735 #else 736 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 737 #endif 738 739 BGE_PCICHK(bgep); 740 } 741 742 /* 743 * The DDI doesn't provide get/put functions for 128 bit data 744 * so we put RCBs out as two 64-bit chunks instead. 745 */ 746 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 747 #pragma inline(bge_reg_putrcb) 748 749 static void 750 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 751 { 752 uint64_t *p; 753 754 BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 755 (void *)bgep, addr, rcbp->host_ring_addr, 756 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 757 758 ASSERT((addr % sizeof (*rcbp)) == 0); 759 760 p = (void *)rcbp; 761 bge_reg_put64(bgep, addr, *p++); 762 bge_reg_put64(bgep, addr+8, *p); 763 } 764 765 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data); 766 #pragma inline(bge_mbx_put) 767 768 void 769 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data) 770 { 771 BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)", 772 (void *)bgep, regno, data)); 773 774 /* 775 * Mailbox registers are nominally 64 bits on the 5701, but 776 * the MSW isn't used. On the 5703, they're only 32 bits 777 * anyway. So here we just write the lower(!) 32 bits - 778 * remembering that the chip is big-endian, even though the 779 * PCI bus is little-endian ... 780 */ 781 #ifdef _BIG_ENDIAN 782 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data); 783 #else 784 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data); 785 #endif /* _BIG_ENDIAN */ 786 BGE_PCICHK(bgep); 787 } 788 789 #if BGE_DEBUGGING 790 791 void bge_led_mark(bge_t *bgep); 792 #pragma no_inline(bge_led_mark) 793 794 void 795 bge_led_mark(bge_t *bgep) 796 { 797 uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK | 798 LED_CONTROL_1000MBPS_LED | 799 LED_CONTROL_100MBPS_LED | 800 LED_CONTROL_10MBPS_LED; 801 802 /* 803 * Blink all three LINK LEDs on simultaneously, then all off, 804 * then restore to automatic hardware control. This is used 805 * in laboratory testing to trigger a logic analyser or scope. 806 */ 807 bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 808 led_ctrl ^= LED_CONTROL_OVERRIDE_LINK; 809 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 810 led_ctrl = LED_CONTROL_OVERRIDE_LINK; 811 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 812 } 813 814 #endif /* BGE_DEBUGGING */ 815 816 /* 817 * NIC on-chip memory access routines 818 * 819 * Only 32K of NIC memory is visible at a time, controlled by the 820 * Memory Window Base Address Register (in PCI config space). Once 821 * this is set, the 32K region of NIC-local memory that it refers 822 * to can be directly addressed in the upper 32K of the 64K of PCI 823 * memory space used for the device. 824 */ 825 826 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base); 827 #pragma inline(bge_nic_setwin) 828 829 static void 830 bge_nic_setwin(bge_t *bgep, bge_regno_t base) 831 { 832 chip_id_t *cidp; 833 834 BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)", 835 (void *)bgep, base)); 836 837 ASSERT((base & MWBAR_GRANULE_MASK) == 0); 838 839 /* 840 * Don't do repeated zero data writes, 841 * if the device is BCM5714C/15C. 842 */ 843 cidp = &bgep->chipid; 844 if ((cidp->device == DEVICE_ID_5714C) || 845 (cidp->device == DEVICE_ID_5715C)) { 846 if (bgep->lastWriteZeroData && (base == (bge_regno_t)0)) 847 return; 848 /* Adjust lastWriteZeroData */ 849 bgep->lastWriteZeroData = ((base == (bge_regno_t)0) ? 850 B_TRUE : B_FALSE); 851 } 852 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base); 853 } 854 855 856 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr); 857 #pragma inline(bge_nic_get32) 858 859 static uint32_t 860 bge_nic_get32(bge_t *bgep, bge_regno_t addr) 861 { 862 uint32_t data; 863 864 #ifdef BGE_IPMI_ASF 865 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 866 /* workaround for word swap error */ 867 if (addr & 4) 868 addr = addr - 4; 869 else 870 addr = addr + 4; 871 } 872 #endif 873 874 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 875 addr &= MWBAR_GRANULE_MASK; 876 addr += NIC_MEM_WINDOW_OFFSET; 877 878 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 879 880 BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x", 881 (void *)bgep, addr, data)); 882 883 return (data); 884 } 885 886 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data); 887 #pragma inline(bge_nic_put32) 888 889 void 890 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data) 891 { 892 BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)", 893 (void *)bgep, addr, data)); 894 895 #ifdef BGE_IPMI_ASF 896 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 897 /* workaround for word swap error */ 898 if (addr & 4) 899 addr = addr - 4; 900 else 901 addr = addr + 4; 902 } 903 #endif 904 905 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 906 addr &= MWBAR_GRANULE_MASK; 907 addr += NIC_MEM_WINDOW_OFFSET; 908 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data); 909 BGE_PCICHK(bgep); 910 } 911 912 913 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr); 914 #pragma inline(bge_nic_get64) 915 916 static uint64_t 917 bge_nic_get64(bge_t *bgep, bge_regno_t addr) 918 { 919 uint64_t data; 920 921 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 922 addr &= MWBAR_GRANULE_MASK; 923 addr += NIC_MEM_WINDOW_OFFSET; 924 925 #ifdef __amd64 926 if (bge_get_em64t_type()) { 927 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 928 data <<= 32; 929 data |= ddi_get32(bgep->io_handle, 930 PIO_ADDR(bgep, addr + 4)); 931 } else { 932 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 933 } 934 #else 935 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 936 #endif 937 938 BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx", 939 (void *)bgep, addr, data)); 940 941 return (data); 942 } 943 944 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data); 945 #pragma inline(bge_nic_put64) 946 947 static void 948 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data) 949 { 950 BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)", 951 (void *)bgep, addr, data)); 952 953 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 954 addr &= MWBAR_GRANULE_MASK; 955 addr += NIC_MEM_WINDOW_OFFSET; 956 957 #ifdef __amd64 958 if (bge_get_em64t_type()) { 959 ddi_put32(bgep->io_handle, 960 PIO_ADDR(bgep, addr), (uint32_t)data); 961 BGE_PCICHK(bgep); 962 ddi_put32(bgep->io_handle, 963 PIO_ADDR(bgep, addr + 4), (uint32_t)(data >> 32)); 964 } else { 965 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 966 } 967 #else 968 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 969 #endif 970 971 BGE_PCICHK(bgep); 972 } 973 974 /* 975 * The DDI doesn't provide get/put functions for 128 bit data 976 * so we put RCBs out as two 64-bit chunks instead. 977 */ 978 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 979 #pragma inline(bge_nic_putrcb) 980 981 static void 982 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 983 { 984 uint64_t *p; 985 986 BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 987 (void *)bgep, addr, rcbp->host_ring_addr, 988 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 989 990 ASSERT((addr % sizeof (*rcbp)) == 0); 991 992 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 993 addr &= MWBAR_GRANULE_MASK; 994 addr += NIC_MEM_WINDOW_OFFSET; 995 996 p = (void *)rcbp; 997 #ifdef __amd64 998 if (bge_get_em64t_type()) { 999 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 1000 (uint32_t)(*p)); 1001 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 1002 (uint32_t)(*p >> 32)); 1003 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 1004 (uint32_t)(*(p + 1))); 1005 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 1006 (uint32_t)(*p >> 32)); 1007 1008 } else { 1009 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1010 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p); 1011 } 1012 #else 1013 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1014 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 1015 #endif 1016 1017 BGE_PCICHK(bgep); 1018 } 1019 1020 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes); 1021 #pragma inline(bge_nic_zero) 1022 1023 static void 1024 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes) 1025 { 1026 BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)", 1027 (void *)bgep, addr, nbytes)); 1028 1029 ASSERT((addr & ~MWBAR_GRANULE_MASK) == 1030 ((addr+nbytes) & ~MWBAR_GRANULE_MASK)); 1031 1032 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 1033 addr &= MWBAR_GRANULE_MASK; 1034 addr += NIC_MEM_WINDOW_OFFSET; 1035 1036 (void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr), 1037 nbytes, 1, DDI_DATA_SZ08_ACC); 1038 BGE_PCICHK(bgep); 1039 } 1040 1041 /* 1042 * MII (PHY) register get/set access routines 1043 * 1044 * These use the chip's MII auto-access method, controlled by the 1045 * MII Communication register at 0x044c, so the CPU doesn't have 1046 * to fiddle with the individual bits. 1047 */ 1048 1049 #undef BGE_DBG 1050 #define BGE_DBG BGE_DBG_MII /* debug flag for this code */ 1051 1052 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno, 1053 uint16_t data, uint32_t cmd); 1054 #pragma no_inline(bge_mii_access) 1055 1056 static uint16_t 1057 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd) 1058 { 1059 uint32_t timeout; 1060 uint32_t regval1; 1061 uint32_t regval2; 1062 1063 BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)", 1064 (void *)bgep, regno, data, cmd)); 1065 1066 ASSERT(mutex_owned(bgep->genlock)); 1067 1068 /* 1069 * Assemble the command ... 1070 */ 1071 cmd |= data << MI_COMMS_DATA_SHIFT; 1072 cmd |= regno << MI_COMMS_REGISTER_SHIFT; 1073 cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT; 1074 cmd |= MI_COMMS_START; 1075 1076 /* 1077 * Wait for any command already in progress ... 1078 * 1079 * Note: this *shouldn't* ever find that there is a command 1080 * in progress, because we already hold the <genlock> mutex. 1081 * Nonetheless, we have sometimes seen the MI_COMMS_START 1082 * bit set here -- it seems that the chip can initiate MII 1083 * accesses internally, even with polling OFF. 1084 */ 1085 regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1086 for (timeout = 100; ; ) { 1087 if ((regval2 & MI_COMMS_START) == 0) { 1088 bge_reg_put32(bgep, MI_COMMS_REG, cmd); 1089 break; 1090 } 1091 if (--timeout == 0) 1092 break; 1093 drv_usecwait(10); 1094 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1095 } 1096 1097 if (timeout == 0) 1098 return ((uint16_t)~0u); 1099 1100 if (timeout != 100) 1101 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1102 "MI_COMMS_START set for %d us; 0x%x->0x%x", 1103 cmd, 10*(100-timeout), regval1, regval2)); 1104 1105 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1106 for (timeout = 1000; ; ) { 1107 if ((regval1 & MI_COMMS_START) == 0) 1108 break; 1109 if (--timeout == 0) 1110 break; 1111 drv_usecwait(10); 1112 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1113 } 1114 1115 /* 1116 * Drop out early if the READ FAILED bit is set -- this chip 1117 * could be a 5703/4S, with a SerDes instead of a PHY! 1118 */ 1119 if (regval2 & MI_COMMS_READ_FAILED) 1120 return ((uint16_t)~0u); 1121 1122 if (timeout == 0) 1123 return ((uint16_t)~0u); 1124 1125 /* 1126 * The PRM says to wait 5us after seeing the START bit clear 1127 * and then re-read the register to get the final value of the 1128 * data field, in order to avoid a race condition where the 1129 * START bit is clear but the data field isn't yet valid. 1130 * 1131 * Note: we don't actually seem to be encounter this race; 1132 * except when the START bit is seen set again (see below), 1133 * the data field doesn't change during this 5us interval. 1134 */ 1135 drv_usecwait(5); 1136 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1137 1138 /* 1139 * Unfortunately, when following the PRMs instructions above, 1140 * we have occasionally seen the START bit set again(!) in the 1141 * value read after the 5us delay. This seems to be due to the 1142 * chip autonomously starting another MII access internally. 1143 * In such cases, the command/data/etc fields relate to the 1144 * internal command, rather than the one that we thought had 1145 * just finished. So in this case, we fall back to returning 1146 * the data from the original read that showed START clear. 1147 */ 1148 if (regval2 & MI_COMMS_START) { 1149 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1150 "MI_COMMS_START set after transaction; 0x%x->0x%x", 1151 cmd, regval1, regval2)); 1152 regval2 = regval1; 1153 } 1154 1155 if (regval2 & MI_COMMS_START) 1156 return ((uint16_t)~0u); 1157 1158 if (regval2 & MI_COMMS_READ_FAILED) 1159 return ((uint16_t)~0u); 1160 1161 return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT); 1162 } 1163 1164 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno); 1165 #pragma no_inline(bge_mii_get16) 1166 1167 uint16_t 1168 bge_mii_get16(bge_t *bgep, bge_regno_t regno) 1169 { 1170 BGE_TRACE(("bge_mii_get16($%p, 0x%lx)", 1171 (void *)bgep, regno)); 1172 1173 ASSERT(mutex_owned(bgep->genlock)); 1174 1175 return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ)); 1176 } 1177 1178 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data); 1179 #pragma no_inline(bge_mii_put16) 1180 1181 void 1182 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data) 1183 { 1184 BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)", 1185 (void *)bgep, regno, data)); 1186 1187 ASSERT(mutex_owned(bgep->genlock)); 1188 1189 (void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE); 1190 } 1191 1192 #undef BGE_DBG 1193 #define BGE_DBG BGE_DBG_SEEPROM /* debug flag for this code */ 1194 1195 #if BGE_SEE_IO32 || BGE_FLASH_IO32 1196 1197 /* 1198 * Basic SEEPROM get/set access routine 1199 * 1200 * This uses the chip's SEEPROM auto-access method, controlled by the 1201 * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU 1202 * doesn't have to fiddle with the individual bits. 1203 * 1204 * The caller should hold <genlock> and *also* have already acquired 1205 * the right to access the SEEPROM, via bge_nvmem_acquire() above. 1206 * 1207 * Return value: 1208 * 0 on success, 1209 * ENODATA on access timeout (maybe retryable: device may just be busy) 1210 * EPROTO on other h/w or s/w errors. 1211 * 1212 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output 1213 * from a (successful) SEEPROM_ACCESS_READ. 1214 */ 1215 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1216 uint32_t *dp); 1217 #pragma no_inline(bge_seeprom_access) 1218 1219 static int 1220 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1221 { 1222 uint32_t tries; 1223 uint32_t regval; 1224 1225 ASSERT(mutex_owned(bgep->genlock)); 1226 1227 /* 1228 * On the newer chips that support both SEEPROM & Flash, we need 1229 * to specifically enable SEEPROM access (Flash is the default). 1230 * On older chips, we don't; SEEPROM is the only NVtype supported, 1231 * and the NVM control registers don't exist ... 1232 */ 1233 switch (bgep->chipid.nvtype) { 1234 case BGE_NVTYPE_NONE: 1235 case BGE_NVTYPE_UNKNOWN: 1236 _NOTE(NOTREACHED) 1237 case BGE_NVTYPE_SEEPROM: 1238 break; 1239 1240 case BGE_NVTYPE_LEGACY_SEEPROM: 1241 case BGE_NVTYPE_UNBUFFERED_FLASH: 1242 case BGE_NVTYPE_BUFFERED_FLASH: 1243 default: 1244 bge_reg_set32(bgep, NVM_CONFIG1_REG, 1245 NVM_CFG1_LEGACY_SEEPROM_MODE); 1246 break; 1247 } 1248 1249 /* 1250 * Check there's no command in progress. 1251 * 1252 * Note: this *shouldn't* ever find that there is a command 1253 * in progress, because we already hold the <genlock> mutex. 1254 * Also, to ensure we don't have a conflict with the chip's 1255 * internal firmware or a process accessing the same (shared) 1256 * SEEPROM through the other port of a 5704, we've already 1257 * been through the "software arbitration" protocol. 1258 * So this is just a final consistency check: we shouldn't 1259 * see EITHER the START bit (command started but not complete) 1260 * OR the COMPLETE bit (command completed but not cleared). 1261 */ 1262 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1263 if (regval & SEEPROM_ACCESS_START) 1264 return (EPROTO); 1265 if (regval & SEEPROM_ACCESS_COMPLETE) 1266 return (EPROTO); 1267 1268 /* 1269 * Assemble the command ... 1270 */ 1271 cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK; 1272 addr >>= SEEPROM_ACCESS_ADDRESS_SIZE; 1273 addr <<= SEEPROM_ACCESS_DEVID_SHIFT; 1274 cmd |= addr & SEEPROM_ACCESS_DEVID_MASK; 1275 cmd |= SEEPROM_ACCESS_START; 1276 cmd |= SEEPROM_ACCESS_COMPLETE; 1277 cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK; 1278 1279 bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp); 1280 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd); 1281 1282 /* 1283 * By observation, a successful access takes ~20us on a 5703/4, 1284 * but apparently much longer (up to 1000us) on the obsolescent 1285 * BCM5700/BCM5701. We want to be sure we don't get any false 1286 * timeouts here; but OTOH, we don't want a bogus access to lock 1287 * out interrupts for longer than necessary. So we'll allow up 1288 * to 1000us ... 1289 */ 1290 for (tries = 0; tries < 1000; ++tries) { 1291 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1292 if (regval & SEEPROM_ACCESS_COMPLETE) 1293 break; 1294 drv_usecwait(1); 1295 } 1296 1297 if (regval & SEEPROM_ACCESS_COMPLETE) { 1298 /* 1299 * All OK; read the SEEPROM data register, then write back 1300 * the value read from the address register in order to 1301 * clear the <complete> bit and leave the SEEPROM access 1302 * state machine idle, ready for the next access ... 1303 */ 1304 BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries)); 1305 *dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG); 1306 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval); 1307 return (0); 1308 } 1309 1310 /* 1311 * Hmm ... what happened here? 1312 * 1313 * Most likely, the user addressed a non-existent SEEPROM. Or 1314 * maybe the SEEPROM was busy internally (e.g. processing a write) 1315 * and didn't respond to being addressed. Either way, it's left 1316 * the SEEPROM access state machine wedged. So we'll reset it 1317 * before we leave, so it's ready for next time ... 1318 */ 1319 BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries)); 1320 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 1321 return (ENODATA); 1322 } 1323 1324 /* 1325 * Basic Flash get/set access routine 1326 * 1327 * These use the chip's Flash auto-access method, controlled by the 1328 * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to 1329 * fiddle with the individual bits. 1330 * 1331 * The caller should hold <genlock> and *also* have already acquired 1332 * the right to access the Flash, via bge_nvmem_acquire() above. 1333 * 1334 * Return value: 1335 * 0 on success, 1336 * ENODATA on access timeout (maybe retryable: device may just be busy) 1337 * ENODEV if the NVmem device is missing or otherwise unusable 1338 * 1339 * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output 1340 * from a (successful) NVM_FLASH_CMD_RD. 1341 */ 1342 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1343 uint32_t *dp); 1344 #pragma no_inline(bge_flash_access) 1345 1346 static int 1347 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1348 { 1349 uint32_t tries; 1350 uint32_t regval; 1351 1352 ASSERT(mutex_owned(bgep->genlock)); 1353 1354 /* 1355 * On the newer chips that support both SEEPROM & Flash, we need 1356 * to specifically disable SEEPROM access while accessing Flash. 1357 * The older chips don't support Flash, and the NVM registers don't 1358 * exist, so we shouldn't be here at all! 1359 */ 1360 switch (bgep->chipid.nvtype) { 1361 case BGE_NVTYPE_NONE: 1362 case BGE_NVTYPE_UNKNOWN: 1363 _NOTE(NOTREACHED) 1364 case BGE_NVTYPE_SEEPROM: 1365 return (ENODEV); 1366 1367 case BGE_NVTYPE_LEGACY_SEEPROM: 1368 case BGE_NVTYPE_UNBUFFERED_FLASH: 1369 case BGE_NVTYPE_BUFFERED_FLASH: 1370 default: 1371 bge_reg_clr32(bgep, NVM_CONFIG1_REG, 1372 NVM_CFG1_LEGACY_SEEPROM_MODE); 1373 break; 1374 } 1375 1376 /* 1377 * Assemble the command ... 1378 */ 1379 addr &= NVM_FLASH_ADDR_MASK; 1380 cmd |= NVM_FLASH_CMD_DOIT; 1381 cmd |= NVM_FLASH_CMD_FIRST; 1382 cmd |= NVM_FLASH_CMD_LAST; 1383 cmd |= NVM_FLASH_CMD_DONE; 1384 1385 bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp); 1386 bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr); 1387 bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd); 1388 1389 /* 1390 * Allow up to 1000ms ... 1391 */ 1392 for (tries = 0; tries < 1000; ++tries) { 1393 regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG); 1394 if (regval & NVM_FLASH_CMD_DONE) 1395 break; 1396 drv_usecwait(1); 1397 } 1398 1399 if (regval & NVM_FLASH_CMD_DONE) { 1400 /* 1401 * All OK; read the data from the Flash read register 1402 */ 1403 BGE_DEBUG(("bge_flash_access: complete after %d us", tries)); 1404 *dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG); 1405 return (0); 1406 } 1407 1408 /* 1409 * Hmm ... what happened here? 1410 * 1411 * Most likely, the user addressed a non-existent Flash. Or 1412 * maybe the Flash was busy internally (e.g. processing a write) 1413 * and didn't respond to being addressed. Either way, there's 1414 * nothing we can here ... 1415 */ 1416 BGE_DEBUG(("bge_flash_access: timed out after %d us", tries)); 1417 return (ENODATA); 1418 } 1419 1420 /* 1421 * The next two functions regulate access to the NVram (if fitted). 1422 * 1423 * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash 1424 * (SPI) interface, but they can be accessed through either port. These 1425 * are managed by different instance of this driver and have no software 1426 * state in common. 1427 * 1428 * In addition (and even on a single core chip) the chip's internal 1429 * firmware can access the SEEPROM/Flash, most notably after a RESET 1430 * when it may download code to run internally. 1431 * 1432 * So we need to arbitrate between these various software agents. For 1433 * this purpose, the chip provides the Software Arbitration Register, 1434 * which implements hardware(!) arbitration. 1435 * 1436 * This functionality didn't exist on older (5700/5701) chips, so there's 1437 * nothing we can do by way of arbitration on those; also, if there's no 1438 * SEEPROM/Flash fitted (or we couldn't determine what type), there's also 1439 * nothing to do. 1440 * 1441 * The internal firmware appears to use Request 0, which is the highest 1442 * priority. So we'd like to use Request 2, leaving one higher and one 1443 * lower for any future developments ... but apparently this doesn't 1444 * always work. So for now, the code uses Request 1 ;-( 1445 */ 1446 1447 #define NVM_READ_REQ NVM_READ_REQ1 1448 #define NVM_RESET_REQ NVM_RESET_REQ1 1449 #define NVM_SET_REQ NVM_SET_REQ1 1450 1451 static void bge_nvmem_relinquish(bge_t *bgep); 1452 #pragma no_inline(bge_nvmem_relinquish) 1453 1454 static void 1455 bge_nvmem_relinquish(bge_t *bgep) 1456 { 1457 ASSERT(mutex_owned(bgep->genlock)); 1458 1459 switch (bgep->chipid.nvtype) { 1460 case BGE_NVTYPE_NONE: 1461 case BGE_NVTYPE_UNKNOWN: 1462 _NOTE(NOTREACHED) 1463 return; 1464 1465 case BGE_NVTYPE_SEEPROM: 1466 /* 1467 * No arbitration performed, no release needed 1468 */ 1469 return; 1470 1471 case BGE_NVTYPE_LEGACY_SEEPROM: 1472 case BGE_NVTYPE_UNBUFFERED_FLASH: 1473 case BGE_NVTYPE_BUFFERED_FLASH: 1474 default: 1475 break; 1476 } 1477 1478 /* 1479 * Our own request should be present (whether or not granted) ... 1480 */ 1481 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1482 1483 /* 1484 * ... this will make it go away. 1485 */ 1486 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ); 1487 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1488 } 1489 1490 /* 1491 * Arbitrate for access to the NVmem, if necessary 1492 * 1493 * Return value: 1494 * 0 on success 1495 * EAGAIN if the device is in use (retryable) 1496 * ENODEV if the NVmem device is missing or otherwise unusable 1497 */ 1498 static int bge_nvmem_acquire(bge_t *bgep); 1499 #pragma no_inline(bge_nvmem_acquire) 1500 1501 static int 1502 bge_nvmem_acquire(bge_t *bgep) 1503 { 1504 uint32_t regval; 1505 uint32_t tries; 1506 1507 ASSERT(mutex_owned(bgep->genlock)); 1508 1509 switch (bgep->chipid.nvtype) { 1510 case BGE_NVTYPE_NONE: 1511 case BGE_NVTYPE_UNKNOWN: 1512 /* 1513 * Access denied: no (recognisable) device fitted 1514 */ 1515 return (ENODEV); 1516 1517 case BGE_NVTYPE_SEEPROM: 1518 /* 1519 * Access granted: no arbitration needed (or possible) 1520 */ 1521 return (0); 1522 1523 case BGE_NVTYPE_LEGACY_SEEPROM: 1524 case BGE_NVTYPE_UNBUFFERED_FLASH: 1525 case BGE_NVTYPE_BUFFERED_FLASH: 1526 default: 1527 /* 1528 * Access conditional: conduct arbitration protocol 1529 */ 1530 break; 1531 } 1532 1533 /* 1534 * We're holding the per-port mutex <genlock>, so no-one other 1535 * thread can be attempting to access the NVmem through *this* 1536 * port. But it could be in use by the *other* port (of a 5704), 1537 * or by the chip's internal firmware, so we have to go through 1538 * the full (hardware) arbitration protocol ... 1539 * 1540 * Note that *because* we're holding <genlock>, the interrupt handler 1541 * won't be able to progress. So we're only willing to spin for a 1542 * fairly short time. Specifically: 1543 * 1544 * We *must* wait long enough for the hardware to resolve all 1545 * requests and determine the winner. Fortunately, this is 1546 * "almost instantaneous", even as observed by GHz CPUs. 1547 * 1548 * A successful access by another Solaris thread (via either 1549 * port) typically takes ~20us. So waiting a bit longer than 1550 * that will give a good chance of success, if the other user 1551 * *is* another thread on the other port. 1552 * 1553 * However, the internal firmware can hold on to the NVmem 1554 * for *much* longer: at least 10 milliseconds just after a 1555 * RESET, and maybe even longer if the NVmem actually contains 1556 * code to download and run on the internal CPUs. 1557 * 1558 * So, we'll allow 50us; if that's not enough then it's up to the 1559 * caller to retry later (hence the choice of return code EAGAIN). 1560 */ 1561 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1562 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ); 1563 1564 for (tries = 0; tries < 50; ++tries) { 1565 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1566 if (regval & NVM_WON_REQ1) 1567 break; 1568 drv_usecwait(1); 1569 } 1570 1571 if (regval & NVM_WON_REQ1) { 1572 BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries)); 1573 return (0); 1574 } 1575 1576 /* 1577 * Somebody else must be accessing the NVmem, so abandon our 1578 * attempt take control of it. The caller can try again later ... 1579 */ 1580 BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries)); 1581 bge_nvmem_relinquish(bgep); 1582 return (EAGAIN); 1583 } 1584 1585 /* 1586 * This code assumes that the GPIO1 bit has been wired up to the NVmem 1587 * write protect line in such a way that the NVmem is protected when 1588 * GPIO1 is an input, or is an output but driven high. Thus, to make the 1589 * NVmem writable we have to change GPIO1 to an output AND drive it low. 1590 * 1591 * Note: there's only one set of GPIO pins on a 5704, even though they 1592 * can be accessed through either port. So the chip has to resolve what 1593 * happens if the two ports program a single pin differently ... the rule 1594 * it uses is that if the ports disagree about the *direction* of a pin, 1595 * "output" wins over "input", but if they disagree about its *value* as 1596 * an output, then the pin is TRISTATED instead! In such a case, no-one 1597 * wins, and the external signal does whatever the external circuitry 1598 * defines as the default -- which we've assumed is the PROTECTED state. 1599 * So, we always change GPIO1 back to being an *input* whenever we're not 1600 * specifically using it to unprotect the NVmem. This allows either port 1601 * to update the NVmem, although obviously only one at a time! 1602 * 1603 * The caller should hold <genlock> and *also* have already acquired the 1604 * right to access the NVmem, via bge_nvmem_acquire() above. 1605 */ 1606 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect); 1607 #pragma inline(bge_nvmem_protect) 1608 1609 static void 1610 bge_nvmem_protect(bge_t *bgep, boolean_t protect) 1611 { 1612 uint32_t regval; 1613 1614 ASSERT(mutex_owned(bgep->genlock)); 1615 1616 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 1617 if (protect) { 1618 regval |= MLCR_MISC_PINS_OUTPUT_1; 1619 regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1620 } else { 1621 regval &= ~MLCR_MISC_PINS_OUTPUT_1; 1622 regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1623 } 1624 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval); 1625 } 1626 1627 /* 1628 * Now put it all together ... 1629 * 1630 * Try to acquire control of the NVmem; if successful, then: 1631 * unprotect it (if we want to write to it) 1632 * perform the requested access 1633 * reprotect it (after a write) 1634 * relinquish control 1635 * 1636 * Return value: 1637 * 0 on success, 1638 * EAGAIN if the device is in use (retryable) 1639 * ENODATA on access timeout (maybe retryable: device may just be busy) 1640 * ENODEV if the NVmem device is missing or otherwise unusable 1641 * EPROTO on other h/w or s/w errors. 1642 */ 1643 static int 1644 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1645 { 1646 int err; 1647 1648 if ((err = bge_nvmem_acquire(bgep)) == 0) { 1649 switch (cmd) { 1650 case BGE_SEE_READ: 1651 err = bge_seeprom_access(bgep, 1652 SEEPROM_ACCESS_READ, addr, dp); 1653 break; 1654 1655 case BGE_SEE_WRITE: 1656 bge_nvmem_protect(bgep, B_FALSE); 1657 err = bge_seeprom_access(bgep, 1658 SEEPROM_ACCESS_WRITE, addr, dp); 1659 bge_nvmem_protect(bgep, B_TRUE); 1660 break; 1661 1662 case BGE_FLASH_READ: 1663 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1664 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1665 bge_reg_set32(bgep, NVM_ACCESS_REG, 1666 NVM_ACCESS_ENABLE); 1667 } 1668 err = bge_flash_access(bgep, 1669 NVM_FLASH_CMD_RD, addr, dp); 1670 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1671 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1672 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1673 NVM_ACCESS_ENABLE); 1674 } 1675 break; 1676 1677 case BGE_FLASH_WRITE: 1678 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1679 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1680 bge_reg_set32(bgep, NVM_ACCESS_REG, 1681 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1682 } 1683 bge_nvmem_protect(bgep, B_FALSE); 1684 err = bge_flash_access(bgep, 1685 NVM_FLASH_CMD_WR, addr, dp); 1686 bge_nvmem_protect(bgep, B_TRUE); 1687 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1688 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1689 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1690 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1691 } 1692 1693 break; 1694 1695 default: 1696 _NOTE(NOTREACHED) 1697 break; 1698 } 1699 bge_nvmem_relinquish(bgep); 1700 } 1701 1702 BGE_DEBUG(("bge_nvmem_rw32: err %d", err)); 1703 return (err); 1704 } 1705 1706 /* 1707 * Attempt to get a MAC address from the SEEPROM or Flash, if any 1708 */ 1709 static uint64_t bge_get_nvmac(bge_t *bgep); 1710 #pragma no_inline(bge_get_nvmac) 1711 1712 static uint64_t 1713 bge_get_nvmac(bge_t *bgep) 1714 { 1715 uint32_t mac_high; 1716 uint32_t mac_low; 1717 uint32_t addr; 1718 uint32_t cmd; 1719 uint64_t mac; 1720 1721 BGE_TRACE(("bge_get_nvmac($%p)", 1722 (void *)bgep)); 1723 1724 switch (bgep->chipid.nvtype) { 1725 case BGE_NVTYPE_NONE: 1726 case BGE_NVTYPE_UNKNOWN: 1727 default: 1728 return (0ULL); 1729 1730 case BGE_NVTYPE_SEEPROM: 1731 case BGE_NVTYPE_LEGACY_SEEPROM: 1732 cmd = BGE_SEE_READ; 1733 break; 1734 1735 case BGE_NVTYPE_UNBUFFERED_FLASH: 1736 case BGE_NVTYPE_BUFFERED_FLASH: 1737 cmd = BGE_FLASH_READ; 1738 break; 1739 } 1740 1741 addr = NVMEM_DATA_MAC_ADDRESS; 1742 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high)) 1743 return (0ULL); 1744 addr += 4; 1745 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low)) 1746 return (0ULL); 1747 1748 /* 1749 * The Broadcom chip is natively BIG-endian, so that's how the 1750 * MAC address is represented in NVmem. We may need to swap it 1751 * around on a little-endian host ... 1752 */ 1753 #ifdef _BIG_ENDIAN 1754 mac = mac_high; 1755 mac = mac << 32; 1756 mac |= mac_low; 1757 #else 1758 mac = BGE_BSWAP_32(mac_high); 1759 mac = mac << 32; 1760 mac |= BGE_BSWAP_32(mac_low); 1761 #endif /* _BIG_ENDIAN */ 1762 1763 return (mac); 1764 } 1765 1766 #else /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1767 1768 /* 1769 * Dummy version for when we're not supporting NVmem access 1770 */ 1771 static uint64_t bge_get_nvmac(bge_t *bgep); 1772 #pragma inline(bge_get_nvmac) 1773 1774 static uint64_t 1775 bge_get_nvmac(bge_t *bgep) 1776 { 1777 _NOTE(ARGUNUSED(bgep)) 1778 return (0ULL); 1779 } 1780 1781 #endif /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1782 1783 /* 1784 * Determine the type of NVmem that is (or may be) attached to this chip, 1785 */ 1786 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep); 1787 #pragma no_inline(bge_nvmem_id) 1788 1789 static enum bge_nvmem_type 1790 bge_nvmem_id(bge_t *bgep) 1791 { 1792 enum bge_nvmem_type nvtype; 1793 uint32_t config1; 1794 1795 BGE_TRACE(("bge_nvmem_id($%p)", 1796 (void *)bgep)); 1797 1798 switch (bgep->chipid.device) { 1799 default: 1800 /* 1801 * We shouldn't get here; it means we don't recognise 1802 * the chip, which means we don't know how to determine 1803 * what sort of NVmem (if any) it has. So we'll say 1804 * NONE, to disable the NVmem access code ... 1805 */ 1806 nvtype = BGE_NVTYPE_NONE; 1807 break; 1808 1809 case DEVICE_ID_5700: 1810 case DEVICE_ID_5700x: 1811 case DEVICE_ID_5701: 1812 /* 1813 * These devices support *only* SEEPROMs 1814 */ 1815 nvtype = BGE_NVTYPE_SEEPROM; 1816 break; 1817 1818 case DEVICE_ID_5702: 1819 case DEVICE_ID_5702fe: 1820 case DEVICE_ID_5703C: 1821 case DEVICE_ID_5703S: 1822 case DEVICE_ID_5704C: 1823 case DEVICE_ID_5704S: 1824 case DEVICE_ID_5704: 1825 case DEVICE_ID_5705M: 1826 case DEVICE_ID_5705C: 1827 case DEVICE_ID_5706: 1828 case DEVICE_ID_5782: 1829 case DEVICE_ID_5788: 1830 case DEVICE_ID_5789: 1831 case DEVICE_ID_5751: 1832 case DEVICE_ID_5751M: 1833 case DEVICE_ID_5752: 1834 case DEVICE_ID_5752M: 1835 case DEVICE_ID_5721: 1836 case DEVICE_ID_5714C: 1837 case DEVICE_ID_5714S: 1838 case DEVICE_ID_5715C: 1839 config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG); 1840 if (config1 & NVM_CFG1_FLASH_MODE) 1841 if (config1 & NVM_CFG1_BUFFERED_MODE) 1842 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1843 else 1844 nvtype = BGE_NVTYPE_UNBUFFERED_FLASH; 1845 else 1846 nvtype = BGE_NVTYPE_LEGACY_SEEPROM; 1847 break; 1848 } 1849 1850 return (nvtype); 1851 } 1852 1853 #undef BGE_DBG 1854 #define BGE_DBG BGE_DBG_CHIP /* debug flag for this code */ 1855 1856 static void 1857 bge_init_recv_rule(bge_t *bgep) 1858 { 1859 bge_recv_rule_t *rulep; 1860 uint32_t i; 1861 1862 /* 1863 * receive rule: direct all TCP traffic to ring RULE_MATCH_TO_RING 1864 * 1. to direct UDP traffic, set: 1865 * rulep->control = RULE_PROTO_CONTROL; 1866 * rulep->mask_value = RULE_UDP_MASK_VALUE; 1867 * 2. to direct ICMP traffic, set: 1868 * rulep->control = RULE_PROTO_CONTROL; 1869 * rulep->mask_value = RULE_ICMP_MASK_VALUE; 1870 * 3. to direct traffic by source ip, set: 1871 * rulep->control = RULE_SIP_CONTROL; 1872 * rulep->mask_value = RULE_SIP_MASK_VALUE; 1873 */ 1874 rulep = bgep->recv_rules; 1875 rulep->control = RULE_PROTO_CONTROL; 1876 rulep->mask_value = RULE_TCP_MASK_VALUE; 1877 1878 /* 1879 * set receive rule registers 1880 */ 1881 rulep = bgep->recv_rules; 1882 for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) { 1883 bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value); 1884 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control); 1885 } 1886 } 1887 1888 /* 1889 * Using the values captured by bge_chip_cfg_init(), and additional probes 1890 * as required, characterise the chip fully: determine the label by which 1891 * to refer to this chip, the correct settings for various registers, and 1892 * of course whether the device and/or subsystem are supported! 1893 */ 1894 int bge_chip_id_init(bge_t *bgep); 1895 #pragma no_inline(bge_chip_id_init) 1896 1897 int 1898 bge_chip_id_init(bge_t *bgep) 1899 { 1900 char buf[MAXPATHLEN]; /* any risk of stack overflow? */ 1901 boolean_t sys_ok; 1902 boolean_t dev_ok; 1903 chip_id_t *cidp; 1904 uint32_t subid; 1905 char *devname; 1906 char *sysname; 1907 int *ids; 1908 int err; 1909 uint_t i; 1910 1911 ASSERT(bgep->bge_chip_state == BGE_CHIP_INITIAL); 1912 1913 sys_ok = dev_ok = B_FALSE; 1914 cidp = &bgep->chipid; 1915 1916 /* 1917 * Check the PCI device ID to determine the generic chip type and 1918 * select parameters that depend on this. 1919 * 1920 * Note: because the SPARC platforms in general don't fit the 1921 * SEEPROM 'behind' the chip, the PCI revision ID register reads 1922 * as zero - which is why we use <asic_rev> rather than <revision> 1923 * below ... 1924 * 1925 * Note: in general we can't distinguish between the Copper/SerDes 1926 * versions by ID alone, as some Copper devices (e.g. some but not 1927 * all 5703Cs) have the same ID as the SerDes equivalents. So we 1928 * treat them the same here, and the MII code works out the media 1929 * type later on ... 1930 */ 1931 cidp->mbuf_base = bge_mbuf_pool_base; 1932 cidp->mbuf_length = bge_mbuf_pool_len; 1933 cidp->recv_slots = BGE_RECV_SLOTS_USED; 1934 cidp->bge_dma_rwctrl = bge_dma_rwctrl; 1935 cidp->pci_type = BGE_PCI_X; 1936 cidp->statistic_type = BGE_STAT_BLK; 1937 cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma; 1938 cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac; 1939 cidp->mbuf_hi_water = bge_mbuf_hi_water; 1940 1941 if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX) 1942 cidp->rx_rings = BGE_RECV_RINGS_DEFAULT; 1943 if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX) 1944 cidp->tx_rings = BGE_SEND_RINGS_DEFAULT; 1945 1946 cidp->msi_enabled = B_FALSE; 1947 1948 switch (cidp->device) { 1949 case DEVICE_ID_5700: 1950 case DEVICE_ID_5700x: 1951 cidp->chip_label = 5700; 1952 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1953 break; 1954 1955 case DEVICE_ID_5701: 1956 cidp->chip_label = 5701; 1957 dev_ok = B_TRUE; 1958 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1959 break; 1960 1961 case DEVICE_ID_5702: 1962 case DEVICE_ID_5702fe: 1963 cidp->chip_label = 5702; 1964 dev_ok = B_TRUE; 1965 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1966 cidp->pci_type = BGE_PCI; 1967 break; 1968 1969 case DEVICE_ID_5703C: 1970 case DEVICE_ID_5703S: 1971 case DEVICE_ID_5703: 1972 /* 1973 * Revision A0 of the 5703/5793 had various errata 1974 * that we can't or don't work around, so it's not 1975 * supported, but all later versions are 1976 */ 1977 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703; 1978 if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0) 1979 dev_ok = B_TRUE; 1980 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1981 break; 1982 1983 case DEVICE_ID_5704C: 1984 case DEVICE_ID_5704S: 1985 case DEVICE_ID_5704: 1986 /* 1987 * Revision A0 of the 5704/5794 had various errata 1988 * but we have workarounds, so it *is* supported. 1989 */ 1990 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704; 1991 cidp->mbuf_base = bge_mbuf_pool_base_5704; 1992 cidp->mbuf_length = bge_mbuf_pool_len_5704; 1993 dev_ok = B_TRUE; 1994 if (cidp->asic_rev < MHCR_CHIP_REV_5704_B0) 1995 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1996 break; 1997 1998 case DEVICE_ID_5705C: 1999 case DEVICE_ID_5705M: 2000 case DEVICE_ID_5705MA3: 2001 case DEVICE_ID_5705F: 2002 cidp->chip_label = 5705; 2003 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2004 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2005 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2006 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2007 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2008 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2009 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2010 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2011 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2012 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2013 cidp->pci_type = BGE_PCI; 2014 cidp->statistic_type = BGE_STAT_REG; 2015 dev_ok = B_TRUE; 2016 break; 2017 2018 case DEVICE_ID_5706: 2019 cidp->chip_label = 5706; 2020 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2021 break; 2022 2023 case DEVICE_ID_5782: 2024 /* 2025 * Apart from the label, we treat this as a 5705(?) 2026 */ 2027 cidp->chip_label = 5782; 2028 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2029 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2030 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2031 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2032 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2033 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2034 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2035 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2036 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2037 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2038 cidp->statistic_type = BGE_STAT_REG; 2039 dev_ok = B_TRUE; 2040 break; 2041 2042 case DEVICE_ID_5788: 2043 /* 2044 * Apart from the label, we treat this as a 5705(?) 2045 */ 2046 cidp->chip_label = 5788; 2047 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2048 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2049 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2050 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2051 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2052 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2053 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2054 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2055 cidp->statistic_type = BGE_STAT_REG; 2056 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2057 dev_ok = B_TRUE; 2058 break; 2059 2060 case DEVICE_ID_5714C: 2061 if (cidp->revision >= REVISION_ID_5714_A2) 2062 cidp->msi_enabled = bge_enable_msi; 2063 /* FALLTHRU */ 2064 case DEVICE_ID_5714S: 2065 cidp->chip_label = 5714; 2066 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2067 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2068 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2069 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2070 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2071 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2072 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714; 2073 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2074 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2075 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2076 cidp->pci_type = BGE_PCI_E; 2077 cidp->statistic_type = BGE_STAT_REG; 2078 dev_ok = B_TRUE; 2079 break; 2080 2081 case DEVICE_ID_5715C: 2082 cidp->chip_label = 5715; 2083 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2084 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2085 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2086 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2087 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2088 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2089 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715; 2090 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2091 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2092 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2093 cidp->pci_type = BGE_PCI_E; 2094 cidp->statistic_type = BGE_STAT_REG; 2095 if (cidp->revision >= REVISION_ID_5715_A2) 2096 cidp->msi_enabled = bge_enable_msi; 2097 dev_ok = B_TRUE; 2098 break; 2099 2100 case DEVICE_ID_5721: 2101 cidp->chip_label = 5721; 2102 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2103 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2104 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2105 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2106 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2107 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2108 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2109 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2110 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2111 cidp->pci_type = BGE_PCI_E; 2112 cidp->statistic_type = BGE_STAT_REG; 2113 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2114 dev_ok = B_TRUE; 2115 break; 2116 2117 case DEVICE_ID_5751: 2118 case DEVICE_ID_5751M: 2119 cidp->chip_label = 5751; 2120 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2121 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2122 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2123 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2124 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2125 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2126 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2127 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2128 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2129 cidp->pci_type = BGE_PCI_E; 2130 cidp->statistic_type = BGE_STAT_REG; 2131 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2132 dev_ok = B_TRUE; 2133 break; 2134 2135 case DEVICE_ID_5752: 2136 case DEVICE_ID_5752M: 2137 cidp->chip_label = 5752; 2138 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2139 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2140 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2141 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2142 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2143 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2144 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2145 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2146 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2147 cidp->pci_type = BGE_PCI_E; 2148 cidp->statistic_type = BGE_STAT_REG; 2149 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2150 dev_ok = B_TRUE; 2151 break; 2152 2153 case DEVICE_ID_5789: 2154 cidp->chip_label = 5789; 2155 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2156 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2157 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2158 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2159 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2160 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2161 cidp->pci_type = BGE_PCI_E; 2162 cidp->statistic_type = BGE_STAT_REG; 2163 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2164 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2165 cidp->msi_enabled = B_TRUE; 2166 dev_ok = B_TRUE; 2167 break; 2168 2169 } 2170 2171 /* 2172 * Setup the default jumbo parameter. 2173 */ 2174 cidp->ethmax_size = ETHERMAX; 2175 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT; 2176 cidp->std_buf_size = BGE_STD_BUFF_SIZE; 2177 2178 /* 2179 * If jumbo is enabled and this kind of chipset supports jumbo feature, 2180 * setup below jumbo specific parameters. 2181 * 2182 * For BCM5714/5715, there is only one standard receive ring. So the 2183 * std buffer size should be set to BGE_JUMBO_BUFF_SIZE when jumbo 2184 * feature is enabled. 2185 */ 2186 if (bge_jumbo_enable && 2187 !(cidp->flags & CHIP_FLAG_NO_JUMBO) && 2188 (cidp->default_mtu > BGE_DEFAULT_MTU) && 2189 (cidp->default_mtu <= BGE_MAXIMUM_MTU)) { 2190 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2191 cidp->mbuf_lo_water_rdma = 2192 RDMA_MBUF_LOWAT_5714_JUMBO; 2193 cidp->mbuf_lo_water_rmac = 2194 MAC_RX_MBUF_LOWAT_5714_JUMBO; 2195 cidp->mbuf_hi_water = MBUF_HIWAT_5714_JUMBO; 2196 cidp->jumbo_slots = 0; 2197 cidp->std_buf_size = BGE_JUMBO_BUFF_SIZE; 2198 } else { 2199 cidp->mbuf_lo_water_rdma = 2200 RDMA_MBUF_LOWAT_JUMBO; 2201 cidp->mbuf_lo_water_rmac = 2202 MAC_RX_MBUF_LOWAT_JUMBO; 2203 cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO; 2204 cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED; 2205 } 2206 cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE; 2207 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO; 2208 cidp->ethmax_size = cidp->default_mtu + 2209 sizeof (struct ether_header); 2210 } 2211 2212 /* 2213 * Identify the NV memory type: SEEPROM or Flash? 2214 */ 2215 cidp->nvtype = bge_nvmem_id(bgep); 2216 2217 /* 2218 * Now, we want to check whether this device is part of a 2219 * supported subsystem (e.g., on the motherboard of a Sun 2220 * branded platform). 2221 * 2222 * Rule 1: If the Subsystem Vendor ID is "Sun", then it's OK ;-) 2223 */ 2224 if (cidp->subven == VENDOR_ID_SUN) 2225 sys_ok = B_TRUE; 2226 2227 /* 2228 * Rule 2: If it's on the list on known subsystems, then it's OK. 2229 * Note: 0x14e41647 should *not* appear in the list, but the code 2230 * doesn't enforce that. 2231 */ 2232 err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo, 2233 DDI_PROP_DONTPASS, knownids_propname, &ids, &i); 2234 if (err == DDI_PROP_SUCCESS) { 2235 /* 2236 * Got the list; scan for a matching subsystem vendor/device 2237 */ 2238 subid = (cidp->subven << 16) | cidp->subdev; 2239 while (i--) 2240 if (ids[i] == subid) 2241 sys_ok = B_TRUE; 2242 ddi_prop_free(ids); 2243 } 2244 2245 /* 2246 * Rule 3: If it's a Taco/ENWS motherboard device, then it's OK 2247 * 2248 * Unfortunately, early SunBlade 1500s and 2500s didn't reprogram 2249 * the Subsystem Vendor ID, so it defaults to Broadcom. Therefore, 2250 * we have to check specially for the exact device paths to the 2251 * motherboard devices on those platforms ;-( 2252 * 2253 * Note: we can't just use the "supported-subsystems" mechanism 2254 * above, because the entry would have to be 0x14e41647 -- which 2255 * would then accept *any* plugin card that *didn't* contain a 2256 * (valid) SEEPROM ;-( 2257 */ 2258 sysname = ddi_node_name(ddi_root_node()); 2259 devname = ddi_pathname(bgep->devinfo, buf); 2260 ASSERT(strlen(devname) > 0); 2261 if (strcmp(sysname, "SUNW,Sun-Blade-1500") == 0) /* Taco */ 2262 if (strcmp(devname, "/pci@1f,700000/network@2") == 0) 2263 sys_ok = B_TRUE; 2264 if (strcmp(sysname, "SUNW,Sun-Blade-2500") == 0) /* ENWS */ 2265 if (strcmp(devname, "/pci@1c,600000/network@3") == 0) 2266 sys_ok = B_TRUE; 2267 2268 /* 2269 * Now check what we've discovered: is this truly a supported 2270 * chip on (the motherboard of) a supported platform? 2271 * 2272 * Possible problems here: 2273 * 1) it's a completely unheard-of chip (e.g. 5761) 2274 * 2) it's a recognised but unsupported chip (e.g. 5701, 5703C-A0) 2275 * 3) it's a chip we would support if it were on the motherboard 2276 * of a Sun platform, but this one isn't ;-( 2277 */ 2278 if (cidp->chip_label == 0) 2279 bge_problem(bgep, 2280 "Device 'pci%04x,%04x' not recognized (%d?)", 2281 cidp->vendor, cidp->device, cidp->device); 2282 else if (!dev_ok) 2283 bge_problem(bgep, 2284 "Device 'pci%04x,%04x' (%d) revision %d not supported", 2285 cidp->vendor, cidp->device, cidp->chip_label, 2286 cidp->revision); 2287 #if BGE_DEBUGGING 2288 else if (!sys_ok) 2289 bge_problem(bgep, 2290 "%d-based subsystem 'pci%04x,%04x' not validated", 2291 cidp->chip_label, cidp->subven, cidp->subdev); 2292 #endif 2293 else 2294 cidp->flags |= CHIP_FLAG_SUPPORTED; 2295 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 2296 return (EIO); 2297 return (0); 2298 } 2299 2300 void 2301 bge_chip_msi_trig(bge_t *bgep) 2302 { 2303 uint32_t regval; 2304 2305 regval = bgep->param_msi_cnt<<4; 2306 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval); 2307 BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval)); 2308 } 2309 2310 /* 2311 * Various registers that control the chip's internal engines (state 2312 * machines) have a <reset> and <enable> bits (fortunately, in the 2313 * same place in each such register :-). 2314 * 2315 * To reset the state machine, the <reset> bit must be written with 1; 2316 * it will then read back as 1 while the reset is in progress, but 2317 * self-clear to 0 when the reset completes. 2318 * 2319 * To enable a state machine, one must set the <enable> bit, which 2320 * will continue to read back as 0 until the state machine is running. 2321 * 2322 * To disable a state machine, the <enable> bit must be cleared, but 2323 * it will continue to read back as 1 until the state machine actually 2324 * stops. 2325 * 2326 * This routine implements polling for completion of a reset, enable 2327 * or disable operation, returning B_TRUE on success (bit reached the 2328 * required state) or B_FALSE on timeout (200*100us == 20ms). 2329 */ 2330 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2331 uint32_t mask, uint32_t val); 2332 #pragma no_inline(bge_chip_poll_engine) 2333 2334 static boolean_t 2335 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2336 uint32_t mask, uint32_t val) 2337 { 2338 uint32_t regval; 2339 uint32_t n; 2340 2341 BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)", 2342 (void *)bgep, regno, mask, val)); 2343 2344 for (n = 200; n; --n) { 2345 regval = bge_reg_get32(bgep, regno); 2346 if ((regval & mask) == val) 2347 return (B_TRUE); 2348 drv_usecwait(100); 2349 } 2350 2351 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE); 2352 return (B_FALSE); 2353 } 2354 2355 /* 2356 * Various registers that control the chip's internal engines (state 2357 * machines) have a <reset> bit (fortunately, in the same place in 2358 * each such register :-). To reset the state machine, this bit must 2359 * be written with 1; it will then read back as 1 while the reset is 2360 * in progress, but self-clear to 0 when the reset completes. 2361 * 2362 * This code sets the bit, then polls for it to read back as zero. 2363 * The return value is B_TRUE on success (reset bit cleared itself), 2364 * or B_FALSE if the state machine didn't recover :( 2365 * 2366 * NOTE: the Core reset is similar to other resets, except that we 2367 * can't poll for completion, since the Core reset disables memory 2368 * access! So we just have to assume that it will all complete in 2369 * 100us. See Broadcom document 570X-PG102-R, p102, steps 4-5. 2370 */ 2371 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno); 2372 #pragma no_inline(bge_chip_reset_engine) 2373 2374 static boolean_t 2375 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno) 2376 { 2377 uint32_t regval; 2378 uint32_t val32; 2379 2380 regval = bge_reg_get32(bgep, regno); 2381 2382 BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)", 2383 (void *)bgep, regno)); 2384 BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x", 2385 regno, regval)); 2386 2387 regval |= STATE_MACHINE_RESET_BIT; 2388 2389 switch (regno) { 2390 case MISC_CONFIG_REG: 2391 /* 2392 * BCM5714/5721/5751 pcie chip special case. In order to avoid 2393 * resetting PCIE block and bringing PCIE link down, bit 29 2394 * in the register needs to be set first, and then set it again 2395 * while the reset bit is written. 2396 * See:P500 of 57xx-PG102-RDS.pdf. 2397 */ 2398 if (DEVICE_5705_SERIES_CHIPSETS(bgep)|| 2399 DEVICE_5721_SERIES_CHIPSETS(bgep)|| 2400 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2401 regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE; 2402 if (bgep->chipid.pci_type == BGE_PCI_E) { 2403 if (bgep->chipid.asic_rev == 2404 MHCR_CHIP_REV_5751_A0 || 2405 bgep->chipid.asic_rev == 2406 MHCR_CHIP_REV_5721_A0) { 2407 val32 = bge_reg_get32(bgep, 2408 PHY_TEST_CTRL_REG); 2409 if (val32 == (PHY_PCIE_SCRAM_MODE | 2410 PHY_PCIE_LTASS_MODE)) 2411 bge_reg_put32(bgep, 2412 PHY_TEST_CTRL_REG, 2413 PHY_PCIE_SCRAM_MODE); 2414 val32 = pci_config_get32 2415 (bgep->cfg_handle, 2416 PCI_CONF_BGE_CLKCTL); 2417 val32 |= CLKCTL_PCIE_A0_FIX; 2418 pci_config_put32(bgep->cfg_handle, 2419 PCI_CONF_BGE_CLKCTL, val32); 2420 } 2421 bge_reg_set32(bgep, regno, 2422 MISC_CONFIG_GRC_RESET_DISABLE); 2423 regval |= MISC_CONFIG_GRC_RESET_DISABLE; 2424 } 2425 } 2426 2427 /* 2428 * Special case - causes Core reset 2429 * 2430 * On SPARC v9 we want to ensure that we don't start 2431 * timing until the I/O access has actually reached 2432 * the chip, otherwise we might make the next access 2433 * too early. And we can't just force the write out 2434 * by following it with a read (even to config space) 2435 * because that would cause the fault we're trying 2436 * to avoid. Hence the need for membar_sync() here. 2437 */ 2438 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval); 2439 #ifdef __sparcv9 2440 membar_sync(); 2441 #endif /* __sparcv9 */ 2442 /* 2443 * On some platforms,system need about 300us for 2444 * link setup. 2445 */ 2446 drv_usecwait(300); 2447 2448 if (bgep->chipid.pci_type == BGE_PCI_E) { 2449 /* PCI-E device need more reset time */ 2450 drv_usecwait(120000); 2451 2452 /* Set PCIE max payload size and clear error status. */ 2453 if ((bgep->chipid.chip_label == 5721) || 2454 (bgep->chipid.chip_label == 5751) || 2455 (bgep->chipid.chip_label == 5752) || 2456 (bgep->chipid.chip_label == 5789)) { 2457 pci_config_put16(bgep->cfg_handle, 2458 PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX); 2459 pci_config_put16(bgep->cfg_handle, 2460 PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS); 2461 } 2462 } 2463 2464 BGE_PCICHK(bgep); 2465 return (B_TRUE); 2466 2467 default: 2468 bge_reg_put32(bgep, regno, regval); 2469 return (bge_chip_poll_engine(bgep, regno, 2470 STATE_MACHINE_RESET_BIT, 0)); 2471 } 2472 } 2473 2474 /* 2475 * Various registers that control the chip's internal engines (state 2476 * machines) have an <enable> bit (fortunately, in the same place in 2477 * each such register :-). To stop the state machine, this bit must 2478 * be written with 0, then polled to see when the state machine has 2479 * actually stopped. 2480 * 2481 * The return value is B_TRUE on success (enable bit cleared), or 2482 * B_FALSE if the state machine didn't stop :( 2483 */ 2484 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, 2485 uint32_t morebits); 2486 #pragma no_inline(bge_chip_disable_engine) 2487 2488 static boolean_t 2489 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2490 { 2491 uint32_t regval; 2492 2493 BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)", 2494 (void *)bgep, regno, morebits)); 2495 2496 switch (regno) { 2497 case FTQ_RESET_REG: 2498 /* 2499 * Not quite like the others; it doesn't 2500 * have an <enable> bit, but instead we 2501 * have to set and then clear all the bits 2502 */ 2503 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2504 drv_usecwait(100); 2505 bge_reg_put32(bgep, regno, 0); 2506 return (B_TRUE); 2507 2508 default: 2509 regval = bge_reg_get32(bgep, regno); 2510 regval &= ~STATE_MACHINE_ENABLE_BIT; 2511 regval &= ~morebits; 2512 bge_reg_put32(bgep, regno, regval); 2513 return (bge_chip_poll_engine(bgep, regno, 2514 STATE_MACHINE_ENABLE_BIT, 0)); 2515 } 2516 } 2517 2518 /* 2519 * Various registers that control the chip's internal engines (state 2520 * machines) have an <enable> bit (fortunately, in the same place in 2521 * each such register :-). To start the state machine, this bit must 2522 * be written with 1, then polled to see when the state machine has 2523 * actually started. 2524 * 2525 * The return value is B_TRUE on success (enable bit set), or 2526 * B_FALSE if the state machine didn't start :( 2527 */ 2528 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, 2529 uint32_t morebits); 2530 #pragma no_inline(bge_chip_enable_engine) 2531 2532 static boolean_t 2533 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2534 { 2535 uint32_t regval; 2536 2537 BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)", 2538 (void *)bgep, regno, morebits)); 2539 2540 switch (regno) { 2541 case FTQ_RESET_REG: 2542 /* 2543 * Not quite like the others; it doesn't 2544 * have an <enable> bit, but instead we 2545 * have to set and then clear all the bits 2546 */ 2547 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2548 drv_usecwait(100); 2549 bge_reg_put32(bgep, regno, 0); 2550 return (B_TRUE); 2551 2552 default: 2553 regval = bge_reg_get32(bgep, regno); 2554 regval |= STATE_MACHINE_ENABLE_BIT; 2555 regval |= morebits; 2556 bge_reg_put32(bgep, regno, regval); 2557 return (bge_chip_poll_engine(bgep, regno, 2558 STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT)); 2559 } 2560 } 2561 2562 /* 2563 * Reprogram the Ethernet, Transmit, and Receive MAC 2564 * modes to match the param_* variables 2565 */ 2566 static void bge_sync_mac_modes(bge_t *bgep); 2567 #pragma no_inline(bge_sync_mac_modes) 2568 2569 static void 2570 bge_sync_mac_modes(bge_t *bgep) 2571 { 2572 uint32_t macmode; 2573 uint32_t regval; 2574 2575 ASSERT(mutex_owned(bgep->genlock)); 2576 2577 /* 2578 * Reprogram the Ethernet MAC mode ... 2579 */ 2580 macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG); 2581 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2582 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2583 macmode &= ~ETHERNET_MODE_LINK_POLARITY; 2584 else 2585 macmode |= ETHERNET_MODE_LINK_POLARITY; 2586 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 2587 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2588 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2589 macmode |= ETHERNET_MODE_PORTMODE_TBI; 2590 else if (bgep->param_link_speed == 10 || bgep->param_link_speed == 100) 2591 macmode |= ETHERNET_MODE_PORTMODE_MII; 2592 else 2593 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2594 if (bgep->param_link_duplex == LINK_DUPLEX_HALF) 2595 macmode |= ETHERNET_MODE_HALF_DUPLEX; 2596 else 2597 macmode &= ~ETHERNET_MODE_HALF_DUPLEX; 2598 if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC) 2599 macmode |= ETHERNET_MODE_MAC_LOOPBACK; 2600 else 2601 macmode &= ~ETHERNET_MODE_MAC_LOOPBACK; 2602 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode); 2603 BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x", 2604 (void *)bgep, regval, macmode)); 2605 2606 /* 2607 * ... the Transmit MAC mode ... 2608 */ 2609 macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG); 2610 if (bgep->param_link_tx_pause) 2611 macmode |= TRANSMIT_MODE_FLOW_CONTROL; 2612 else 2613 macmode &= ~TRANSMIT_MODE_FLOW_CONTROL; 2614 bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode); 2615 BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x", 2616 (void *)bgep, regval, macmode)); 2617 2618 /* 2619 * ... and the Receive MAC mode 2620 */ 2621 macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG); 2622 if (bgep->param_link_rx_pause) 2623 macmode |= RECEIVE_MODE_FLOW_CONTROL; 2624 else 2625 macmode &= ~RECEIVE_MODE_FLOW_CONTROL; 2626 bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode); 2627 BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x", 2628 (void *)bgep, regval, macmode)); 2629 } 2630 2631 /* 2632 * bge_chip_sync() -- program the chip with the unicast MAC address, 2633 * the multicast hash table, the required level of promiscuity, and 2634 * the current loopback mode ... 2635 */ 2636 #ifdef BGE_IPMI_ASF 2637 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive); 2638 #else 2639 int bge_chip_sync(bge_t *bgep); 2640 #endif 2641 #pragma no_inline(bge_chip_sync) 2642 2643 int 2644 #ifdef BGE_IPMI_ASF 2645 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive) 2646 #else 2647 bge_chip_sync(bge_t *bgep) 2648 #endif 2649 { 2650 void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits); 2651 boolean_t promisc; 2652 uint64_t macaddr; 2653 uint32_t fill; 2654 int i, j; 2655 int retval = DDI_SUCCESS; 2656 2657 BGE_TRACE(("bge_chip_sync($%p)", 2658 (void *)bgep)); 2659 2660 ASSERT(mutex_owned(bgep->genlock)); 2661 2662 promisc = B_FALSE; 2663 fill = ~(uint32_t)0; 2664 2665 if (bgep->promisc) 2666 promisc = B_TRUE; 2667 else 2668 fill = (uint32_t)0; 2669 2670 /* 2671 * If the TX/RX MAC engines are already running, we should stop 2672 * them (and reset the RX engine) before changing the parameters. 2673 * If they're not running, this will have no effect ... 2674 * 2675 * NOTE: this is currently disabled by default because stopping 2676 * and restarting the Tx engine may cause an outgoing packet in 2677 * transit to be truncated. Also, stopping and restarting the 2678 * Rx engine seems to not work correctly on the 5705. Testing 2679 * has not (yet!) revealed any problems with NOT stopping and 2680 * restarting these engines (and Broadcom say their drivers don't 2681 * do this), but if it is found to cause problems, this variable 2682 * can be patched to re-enable the old behaviour ... 2683 */ 2684 if (bge_stop_start_on_sync) { 2685 #ifdef BGE_IPMI_ASF 2686 if (!bgep->asf_enabled) { 2687 if (!bge_chip_disable_engine(bgep, 2688 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2689 retval = DDI_FAILURE; 2690 } else { 2691 if (!bge_chip_disable_engine(bgep, 2692 RECEIVE_MAC_MODE_REG, 0)) 2693 retval = DDI_FAILURE; 2694 } 2695 #else 2696 if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG, 2697 RECEIVE_MODE_KEEP_VLAN_TAG)) 2698 retval = DDI_FAILURE; 2699 #endif 2700 if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2701 retval = DDI_FAILURE; 2702 if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG)) 2703 retval = DDI_FAILURE; 2704 } 2705 2706 /* 2707 * Reprogram the hashed multicast address table ... 2708 */ 2709 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2710 bge_reg_put32(bgep, MAC_HASH_REG(i), 2711 bgep->mcast_hash[i] | fill); 2712 2713 #ifdef BGE_IPMI_ASF 2714 if (!bgep->asf_enabled || !asf_keeplive) { 2715 #endif 2716 /* 2717 * Transform the MAC address(es) from host to chip format, then 2718 * reprogram the transmit random backoff seed and the unicast 2719 * MAC address(es) ... 2720 */ 2721 for (j = 0; j < MAC_ADDRESS_REGS_MAX; j++) { 2722 for (i = 0, fill = 0, macaddr = 0ull; 2723 i < ETHERADDRL; ++i) { 2724 macaddr <<= 8; 2725 macaddr |= bgep->curr_addr[j].addr[i]; 2726 fill += bgep->curr_addr[j].addr[i]; 2727 } 2728 bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill); 2729 bge_reg_put64(bgep, MAC_ADDRESS_REG(j), macaddr); 2730 } 2731 2732 BGE_DEBUG(("bge_chip_sync($%p) setting MAC address %012llx", 2733 (void *)bgep, macaddr)); 2734 #ifdef BGE_IPMI_ASF 2735 } 2736 #endif 2737 2738 /* 2739 * Set or clear the PROMISCUOUS mode bit 2740 */ 2741 opfn = promisc ? bge_reg_set32 : bge_reg_clr32; 2742 (*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS); 2743 2744 /* 2745 * Sync the rest of the MAC modes too ... 2746 */ 2747 bge_sync_mac_modes(bgep); 2748 2749 /* 2750 * Restart RX/TX MAC engines if required ... 2751 */ 2752 if (bgep->bge_chip_state == BGE_CHIP_RUNNING) { 2753 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2754 retval = DDI_FAILURE; 2755 #ifdef BGE_IPMI_ASF 2756 if (!bgep->asf_enabled) { 2757 if (!bge_chip_enable_engine(bgep, 2758 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2759 retval = DDI_FAILURE; 2760 } else { 2761 if (!bge_chip_enable_engine(bgep, 2762 RECEIVE_MAC_MODE_REG, 0)) 2763 retval = DDI_FAILURE; 2764 } 2765 #else 2766 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 2767 RECEIVE_MODE_KEEP_VLAN_TAG)) 2768 retval = DDI_FAILURE; 2769 #endif 2770 } 2771 return (retval); 2772 } 2773 2774 /* 2775 * This array defines the sequence of state machine control registers 2776 * in which the <enable> bit must be cleared to bring the chip to a 2777 * clean stop. Taken from Broadcom document 570X-PG102-R, p116. 2778 */ 2779 static bge_regno_t shutdown_engine_regs[] = { 2780 RECEIVE_MAC_MODE_REG, 2781 RCV_BD_INITIATOR_MODE_REG, 2782 RCV_LIST_PLACEMENT_MODE_REG, 2783 RCV_LIST_SELECTOR_MODE_REG, /* BCM5704 series only */ 2784 RCV_DATA_BD_INITIATOR_MODE_REG, 2785 RCV_DATA_COMPLETION_MODE_REG, 2786 RCV_BD_COMPLETION_MODE_REG, 2787 2788 SEND_BD_SELECTOR_MODE_REG, 2789 SEND_BD_INITIATOR_MODE_REG, 2790 SEND_DATA_INITIATOR_MODE_REG, 2791 READ_DMA_MODE_REG, 2792 SEND_DATA_COMPLETION_MODE_REG, 2793 DMA_COMPLETION_MODE_REG, /* BCM5704 series only */ 2794 SEND_BD_COMPLETION_MODE_REG, 2795 TRANSMIT_MAC_MODE_REG, 2796 2797 HOST_COALESCE_MODE_REG, 2798 WRITE_DMA_MODE_REG, 2799 MBUF_CLUSTER_FREE_MODE_REG, /* BCM5704 series only */ 2800 FTQ_RESET_REG, /* special - see code */ 2801 BUFFER_MANAGER_MODE_REG, /* BCM5704 series only */ 2802 MEMORY_ARBITER_MODE_REG, /* BCM5704 series only */ 2803 BGE_REGNO_NONE /* terminator */ 2804 }; 2805 2806 /* 2807 * bge_chip_stop() -- stop all chip processing 2808 * 2809 * If the <fault> parameter is B_TRUE, we're stopping the chip because 2810 * we've detected a problem internally; otherwise, this is a normal 2811 * (clean) stop (at user request i.e. the last STREAM has been closed). 2812 */ 2813 void bge_chip_stop(bge_t *bgep, boolean_t fault); 2814 #pragma no_inline(bge_chip_stop) 2815 2816 void 2817 bge_chip_stop(bge_t *bgep, boolean_t fault) 2818 { 2819 bge_regno_t regno; 2820 bge_regno_t *rbp; 2821 boolean_t ok; 2822 2823 BGE_TRACE(("bge_chip_stop($%p)", 2824 (void *)bgep)); 2825 2826 ASSERT(mutex_owned(bgep->genlock)); 2827 2828 rbp = shutdown_engine_regs; 2829 /* 2830 * When driver try to shutdown the BCM5705/5788/5721/5751/ 2831 * 5752/5714 and 5715 chipsets,the buffer manager and the mem 2832 * -ory arbiter should not be disabled. 2833 */ 2834 for (ok = B_TRUE; (regno = *rbp) != BGE_REGNO_NONE; ++rbp) { 2835 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 2836 ok &= bge_chip_disable_engine(bgep, regno, 0); 2837 else if ((regno != RCV_LIST_SELECTOR_MODE_REG) && 2838 (regno != DMA_COMPLETION_MODE_REG) && 2839 (regno != MBUF_CLUSTER_FREE_MODE_REG)&& 2840 (regno != BUFFER_MANAGER_MODE_REG) && 2841 (regno != MEMORY_ARBITER_MODE_REG)) 2842 ok &= bge_chip_disable_engine(bgep, 2843 regno, 0); 2844 } 2845 2846 if (!ok && !fault) 2847 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 2848 2849 /* 2850 * Finally, disable (all) MAC events & clear the MAC status 2851 */ 2852 bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0); 2853 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0); 2854 2855 /* 2856 * if we're stopping the chip because of a detected fault then do 2857 * appropriate actions 2858 */ 2859 if (fault) { 2860 if (bgep->bge_chip_state != BGE_CHIP_FAULT) { 2861 bgep->bge_chip_state = BGE_CHIP_FAULT; 2862 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST); 2863 if (bgep->bge_dma_error) { 2864 /* 2865 * need to free buffers in case the fault was 2866 * due to a memory error in a buffer - got to 2867 * do a fair bit of tidying first 2868 */ 2869 if (bgep->progress & PROGRESS_KSTATS) { 2870 bge_fini_kstats(bgep); 2871 bgep->progress &= ~PROGRESS_KSTATS; 2872 } 2873 if (bgep->progress & PROGRESS_INTR) { 2874 bge_intr_disable(bgep); 2875 rw_enter(bgep->errlock, RW_WRITER); 2876 bge_fini_rings(bgep); 2877 rw_exit(bgep->errlock); 2878 bgep->progress &= ~PROGRESS_INTR; 2879 } 2880 if (bgep->progress & PROGRESS_BUFS) { 2881 bge_free_bufs(bgep); 2882 bgep->progress &= ~PROGRESS_BUFS; 2883 } 2884 bgep->bge_dma_error = B_FALSE; 2885 } 2886 } 2887 } else 2888 bgep->bge_chip_state = BGE_CHIP_STOPPED; 2889 } 2890 2891 /* 2892 * Poll for completion of chip's ROM firmware; also, at least on the 2893 * first time through, find and return the hardware MAC address, if any. 2894 */ 2895 static uint64_t bge_poll_firmware(bge_t *bgep); 2896 #pragma no_inline(bge_poll_firmware) 2897 2898 static uint64_t 2899 bge_poll_firmware(bge_t *bgep) 2900 { 2901 uint64_t magic; 2902 uint64_t mac; 2903 uint32_t gen; 2904 uint32_t i; 2905 2906 /* 2907 * Step 19: poll for firmware completion (GENCOMM port set 2908 * to the ones complement of T3_MAGIC_NUMBER). 2909 * 2910 * While we're at it, we also read the MAC address register; 2911 * at some stage the firmware will load this with the 2912 * factory-set value. 2913 * 2914 * When both the magic number and the MAC address are set, 2915 * we're done; but we impose a time limit of one second 2916 * (1000*1000us) in case the firmware fails in some fashion 2917 * or the SEEPROM that provides that MAC address isn't fitted. 2918 * 2919 * After the first time through (chip state != INITIAL), we 2920 * don't need the MAC address to be set (we've already got it 2921 * or not, from the first time), so we don't wait for it, but 2922 * we still have to wait for the T3_MAGIC_NUMBER. 2923 * 2924 * Note: the magic number is only a 32-bit quantity, but the NIC 2925 * memory is 64-bit (and big-endian) internally. Addressing the 2926 * GENCOMM word as "the upper half of a 64-bit quantity" makes 2927 * it work correctly on both big- and little-endian hosts. 2928 */ 2929 for (i = 0; i < 1000; ++i) { 2930 drv_usecwait(1000); 2931 gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32; 2932 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 2933 #ifdef BGE_IPMI_ASF 2934 if (!bgep->asf_enabled) { 2935 #endif 2936 if (gen != ~T3_MAGIC_NUMBER) 2937 continue; 2938 #ifdef BGE_IPMI_ASF 2939 } 2940 #endif 2941 if (mac != 0ULL) 2942 break; 2943 if (bgep->bge_chip_state != BGE_CHIP_INITIAL) 2944 break; 2945 } 2946 2947 magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM); 2948 BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops", 2949 (void *)bgep, gen, i)); 2950 BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx", 2951 mac, magic)); 2952 2953 return (mac); 2954 } 2955 2956 #ifdef BGE_IPMI_ASF 2957 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode); 2958 #else 2959 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma); 2960 #endif 2961 #pragma no_inline(bge_chip_reset) 2962 2963 int 2964 #ifdef BGE_IPMI_ASF 2965 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode) 2966 #else 2967 bge_chip_reset(bge_t *bgep, boolean_t enable_dma) 2968 #endif 2969 { 2970 chip_id_t chipid; 2971 uint64_t mac; 2972 uint64_t magic; 2973 uint32_t modeflags; 2974 uint32_t mhcr; 2975 uint32_t sx0; 2976 uint32_t i; 2977 #ifdef BGE_IPMI_ASF 2978 uint32_t mailbox; 2979 #endif 2980 int retval = DDI_SUCCESS; 2981 2982 BGE_TRACE(("bge_chip_reset($%p, %d)", 2983 (void *)bgep, enable_dma)); 2984 2985 ASSERT(mutex_owned(bgep->genlock)); 2986 2987 BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d", 2988 (void *)bgep, enable_dma, bgep->bge_chip_state)); 2989 2990 /* 2991 * Do we need to stop the chip cleanly before resetting? 2992 */ 2993 switch (bgep->bge_chip_state) { 2994 default: 2995 _NOTE(NOTREACHED) 2996 return (DDI_FAILURE); 2997 2998 case BGE_CHIP_INITIAL: 2999 case BGE_CHIP_STOPPED: 3000 case BGE_CHIP_RESET: 3001 break; 3002 3003 case BGE_CHIP_RUNNING: 3004 case BGE_CHIP_ERROR: 3005 case BGE_CHIP_FAULT: 3006 bge_chip_stop(bgep, B_FALSE); 3007 break; 3008 } 3009 3010 #ifdef BGE_IPMI_ASF 3011 if (bgep->asf_enabled) { 3012 if (asf_mode == ASF_MODE_INIT) { 3013 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 3014 } else if (asf_mode == ASF_MODE_SHUTDOWN) { 3015 bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET); 3016 } 3017 } 3018 #endif 3019 /* 3020 * Adapted from Broadcom document 570X-PG102-R, pp 102-116. 3021 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159. 3022 * 3023 * Before reset Core clock,it is 3024 * also required to initialize the Memory Arbiter as specified in step9 3025 * and Misc Host Control Register as specified in step-13 3026 * Step 4-5: reset Core clock & wait for completion 3027 * Steps 6-8: are done by bge_chip_cfg_init() 3028 * put the T3_MAGIC_NUMBER into the GENCOMM port before reset 3029 */ 3030 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3031 retval = DDI_FAILURE; 3032 3033 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3034 MHCR_ENABLE_TAGGED_STATUS_MODE | 3035 MHCR_MASK_INTERRUPT_MODE | 3036 MHCR_MASK_PCI_INT_OUTPUT | 3037 MHCR_CLEAR_INTERRUPT_INTA; 3038 #ifdef _BIG_ENDIAN 3039 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3040 #endif /* _BIG_ENDIAN */ 3041 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3042 #ifdef BGE_IPMI_ASF 3043 if (bgep->asf_enabled) 3044 bgep->asf_wordswapped = B_FALSE; 3045 #endif 3046 /* 3047 * NVRAM Corruption Workaround 3048 */ 3049 for (i = 0; i < 600; i++) 3050 if (bge_nvmem_acquire(bgep) == 0) 3051 break; 3052 if (i >= 600) 3053 BGE_DEBUG(("%s: fail to acquire nvram lock", 3054 bgep->ifname)); 3055 3056 #ifdef BGE_IPMI_ASF 3057 if (!bgep->asf_enabled) { 3058 #endif 3059 magic = (uint64_t)T3_MAGIC_NUMBER << 32; 3060 bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic); 3061 #ifdef BGE_IPMI_ASF 3062 } 3063 #endif 3064 3065 if (!bge_chip_reset_engine(bgep, MISC_CONFIG_REG)) 3066 retval = DDI_FAILURE; 3067 bge_chip_cfg_init(bgep, &chipid, enable_dma); 3068 3069 /* 3070 * Step 8a: This may belong elsewhere, but BCM5721 needs 3071 * a bit set to avoid a fifo overflow/underflow bug. 3072 */ 3073 if ((bgep->chipid.chip_label == 5721) || 3074 (bgep->chipid.chip_label == 5751) || 3075 (bgep->chipid.chip_label == 5752) || 3076 (bgep->chipid.chip_label == 5789)) 3077 bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT); 3078 3079 3080 /* 3081 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should 3082 * not be changed. 3083 */ 3084 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3085 retval = DDI_FAILURE; 3086 3087 /* 3088 * Steps 10-11: configure PIO endianness options and 3089 * enable indirect register access -- already done 3090 * Steps 12-13: enable writing to the PCI state & clock 3091 * control registers -- not required; we aren't going to 3092 * use those features. 3093 * Steps 14-15: Configure DMA endianness options. See 3094 * the comments on the setting of the MHCR above. 3095 */ 3096 #ifdef _BIG_ENDIAN 3097 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME | 3098 MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME; 3099 #else 3100 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME; 3101 #endif /* _BIG_ENDIAN */ 3102 #ifdef BGE_IPMI_ASF 3103 if (bgep->asf_enabled) 3104 modeflags |= MODE_HOST_STACK_UP; 3105 #endif 3106 bge_reg_put32(bgep, MODE_CONTROL_REG, modeflags); 3107 3108 #ifdef BGE_IPMI_ASF 3109 if (bgep->asf_enabled) { 3110 if (asf_mode != ASF_MODE_NONE) { 3111 /* Wait for NVRAM init */ 3112 i = 0; 3113 drv_usecwait(5000); 3114 mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX); 3115 while ((mailbox != (uint32_t) 3116 ~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) && 3117 (i < 10000)) { 3118 drv_usecwait(100); 3119 mailbox = bge_nic_get32(bgep, 3120 BGE_FIRMWARE_MAILBOX); 3121 i++; 3122 } 3123 if (!bgep->asf_newhandshake) { 3124 if ((asf_mode == ASF_MODE_INIT) || 3125 (asf_mode == ASF_MODE_POST_INIT)) { 3126 3127 bge_asf_post_reset_old_mode(bgep, 3128 BGE_INIT_RESET); 3129 } else { 3130 bge_asf_post_reset_old_mode(bgep, 3131 BGE_SHUTDOWN_RESET); 3132 } 3133 } 3134 } 3135 } 3136 #endif 3137 /* 3138 * Steps 16-17: poll for firmware completion 3139 */ 3140 mac = bge_poll_firmware(bgep); 3141 3142 /* 3143 * Step 18: enable external memory -- doesn't apply. 3144 * 3145 * However we take the opportunity to set the MLCR anyway, as 3146 * this register also controls the SEEPROM auto-access method 3147 * which we may want to use later ... 3148 * 3149 * The proper value here depends on the way the chip is wired 3150 * into the circuit board, as this register *also* controls which 3151 * of the "Miscellaneous I/O" pins are driven as outputs and the 3152 * values driven onto those pins! 3153 * 3154 * See also step 74 in the PRM ... 3155 */ 3156 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, 3157 bgep->chipid.bge_mlcr_default); 3158 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 3159 3160 /* 3161 * Step 20: clear the Ethernet MAC mode register 3162 */ 3163 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0); 3164 3165 /* 3166 * Step 21: restore cache-line-size, latency timer, and 3167 * subsystem ID registers to their original values (not 3168 * those read into the local structure <chipid>, 'cos 3169 * that was after they were cleared by the RESET). 3170 * 3171 * Note: the Subsystem Vendor/Device ID registers are not 3172 * directly writable in config space, so we use the shadow 3173 * copy in "Page Zero" of register space to restore them 3174 * both in one go ... 3175 */ 3176 pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ, 3177 bgep->chipid.clsize); 3178 pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 3179 bgep->chipid.latency); 3180 bge_reg_put32(bgep, PCI_CONF_SUBVENID, 3181 (bgep->chipid.subdev << 16) | bgep->chipid.subven); 3182 3183 /* 3184 * The SEND INDEX registers should be reset to zero by the 3185 * global chip reset; if they're not, there'll be trouble 3186 * later on. 3187 */ 3188 sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0)); 3189 if (sx0 != 0) { 3190 BGE_REPORT((bgep, "SEND INDEX - device didn't RESET")); 3191 bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE); 3192 return (DDI_FAILURE); 3193 } 3194 3195 /* Enable MSI code */ 3196 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3197 bge_reg_set32(bgep, MSI_MODE_REG, 3198 MSI_PRI_HIGHEST|MSI_MSI_ENABLE); 3199 3200 /* 3201 * On the first time through, save the factory-set MAC address 3202 * (if any). If bge_poll_firmware() above didn't return one 3203 * (from a chip register) consider looking in the attached NV 3204 * memory device, if any. Once we have it, we save it in both 3205 * register-image (64-bit) and byte-array forms. All-zero and 3206 * all-one addresses are not valid, and we refuse to stash those. 3207 */ 3208 if (bgep->bge_chip_state == BGE_CHIP_INITIAL) { 3209 if (mac == 0ULL) 3210 mac = bge_get_nvmac(bgep); 3211 if (mac != 0ULL && mac != ~0ULL) { 3212 bgep->chipid.hw_mac_addr = mac; 3213 for (i = ETHERADDRL; i-- != 0; ) { 3214 bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac; 3215 mac >>= 8; 3216 } 3217 bgep->chipid.vendor_addr.set = B_TRUE; 3218 } 3219 } 3220 3221 #ifdef BGE_IPMI_ASF 3222 if (bgep->asf_enabled && bgep->asf_newhandshake) { 3223 if (asf_mode != ASF_MODE_NONE) { 3224 if ((asf_mode == ASF_MODE_INIT) || 3225 (asf_mode == ASF_MODE_POST_INIT)) { 3226 3227 bge_asf_post_reset_new_mode(bgep, 3228 BGE_INIT_RESET); 3229 } else { 3230 bge_asf_post_reset_new_mode(bgep, 3231 BGE_SHUTDOWN_RESET); 3232 } 3233 } 3234 } 3235 #endif 3236 3237 /* 3238 * Record the new state 3239 */ 3240 bgep->chip_resets += 1; 3241 bgep->bge_chip_state = BGE_CHIP_RESET; 3242 return (retval); 3243 } 3244 3245 /* 3246 * bge_chip_start() -- start the chip transmitting and/or receiving, 3247 * including enabling interrupts 3248 */ 3249 int bge_chip_start(bge_t *bgep, boolean_t reset_phys); 3250 #pragma no_inline(bge_chip_start) 3251 3252 int 3253 bge_chip_start(bge_t *bgep, boolean_t reset_phys) 3254 { 3255 uint32_t coalmode; 3256 uint32_t ledctl; 3257 uint32_t mtu; 3258 uint32_t maxring; 3259 uint64_t ring; 3260 int retval = DDI_SUCCESS; 3261 3262 BGE_TRACE(("bge_chip_start($%p)", 3263 (void *)bgep)); 3264 3265 ASSERT(mutex_owned(bgep->genlock)); 3266 ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET); 3267 3268 /* 3269 * Taken from Broadcom document 570X-PG102-R, pp 102-116. 3270 * The document specifies 95 separate steps to fully 3271 * initialise the chip!!!! 3272 * 3273 * The reset code above has already got us as far as step 3274 * 21, so we continue with ... 3275 * 3276 * Step 22: clear the MAC statistics block 3277 * (0x0300-0x0aff in NIC-local memory) 3278 */ 3279 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 3280 bge_nic_zero(bgep, NIC_MEM_STATISTICS, 3281 NIC_MEM_STATISTICS_SIZE); 3282 3283 /* 3284 * Step 23: clear the status block (in host memory) 3285 */ 3286 DMA_ZERO(bgep->status_block); 3287 3288 /* 3289 * Step 24: set DMA read/write control register 3290 */ 3291 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR, 3292 bgep->chipid.bge_dma_rwctrl); 3293 3294 /* 3295 * Step 25: Configure DMA endianness -- already done (16/17) 3296 * Step 26: Configure Host-Based Send Rings 3297 * Step 27: Indicate Host Stack Up 3298 */ 3299 bge_reg_set32(bgep, MODE_CONTROL_REG, 3300 MODE_HOST_SEND_BDS | 3301 MODE_HOST_STACK_UP); 3302 3303 /* 3304 * Step 28: Configure checksum options: 3305 * Solaris supports the hardware default checksum options. 3306 * 3307 * Workaround for Incorrect pseudo-header checksum calculation. 3308 */ 3309 if (bgep->chipid.flags & CHIP_FLAG_PARTIAL_CSUM) 3310 bge_reg_set32(bgep, MODE_CONTROL_REG, 3311 MODE_SEND_NO_PSEUDO_HDR_CSUM); 3312 3313 /* 3314 * Step 29: configure Timer Prescaler. The value is always the 3315 * same: the Core Clock frequency in MHz (66), minus 1, shifted 3316 * into bits 7-1. Don't set bit 0, 'cos that's the RESET bit 3317 * for the whole chip! 3318 */ 3319 bge_reg_put32(bgep, MISC_CONFIG_REG, MISC_CONFIG_DEFAULT); 3320 3321 /* 3322 * Steps 30-31: Configure MAC local memory pool & DMA pool registers 3323 * 3324 * If the mbuf_length is specified as 0, we just leave these at 3325 * their hardware defaults, rather than explicitly setting them. 3326 * As the Broadcom HRM,driver better not change the parameters 3327 * when the chipsets is 5705/5788/5721/5751/5714 and 5715. 3328 */ 3329 if ((bgep->chipid.mbuf_length != 0) && 3330 (DEVICE_5704_SERIES_CHIPSETS(bgep))) { 3331 bge_reg_put32(bgep, MBUF_POOL_BASE_REG, 3332 bgep->chipid.mbuf_base); 3333 bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG, 3334 bgep->chipid.mbuf_length); 3335 bge_reg_put32(bgep, DMAD_POOL_BASE_REG, 3336 DMAD_POOL_BASE_DEFAULT); 3337 bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG, 3338 DMAD_POOL_LENGTH_DEFAULT); 3339 } 3340 3341 /* 3342 * Step 32: configure MAC memory pool watermarks 3343 */ 3344 bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG, 3345 bgep->chipid.mbuf_lo_water_rdma); 3346 bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG, 3347 bgep->chipid.mbuf_lo_water_rmac); 3348 bge_reg_put32(bgep, MBUF_HIWAT_REG, 3349 bgep->chipid.mbuf_hi_water); 3350 3351 /* 3352 * Step 33: configure DMA resource watermarks 3353 */ 3354 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3355 bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG, 3356 bge_dmad_lo_water); 3357 bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG, 3358 bge_dmad_hi_water); 3359 } 3360 bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames); 3361 3362 /* 3363 * Steps 34-36: enable buffer manager & internal h/w queues 3364 */ 3365 if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG, 3366 STATE_MACHINE_ATTN_ENABLE_BIT)) 3367 retval = DDI_FAILURE; 3368 if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0)) 3369 retval = DDI_FAILURE; 3370 3371 /* 3372 * Steps 37-39: initialise Receive Buffer (Producer) RCBs 3373 */ 3374 bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG, 3375 &bgep->buff[BGE_STD_BUFF_RING].hw_rcb); 3376 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3377 bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG, 3378 &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb); 3379 bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG, 3380 &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb); 3381 } 3382 3383 /* 3384 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds 3385 */ 3386 bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std); 3387 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3388 bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG, 3389 bge_replenish_jumbo); 3390 bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG, 3391 bge_replenish_mini); 3392 } 3393 3394 /* 3395 * Steps 41-43: clear Send Ring Producer Indices and initialise 3396 * Send Producer Rings (0x0100-0x01ff in NIC-local memory) 3397 */ 3398 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3399 maxring = BGE_SEND_RINGS_MAX; 3400 else 3401 maxring = BGE_SEND_RINGS_MAX_5705; 3402 for (ring = 0; ring < maxring; ++ring) { 3403 bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0); 3404 bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0); 3405 bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring), 3406 &bgep->send[ring].hw_rcb); 3407 } 3408 3409 /* 3410 * Steps 44-45: initialise Receive Return Rings 3411 * (0x0200-0x02ff in NIC-local memory) 3412 */ 3413 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3414 maxring = BGE_RECV_RINGS_MAX; 3415 else 3416 maxring = BGE_RECV_RINGS_MAX_5705; 3417 for (ring = 0; ring < maxring; ++ring) 3418 bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring), 3419 &bgep->recv[ring].hw_rcb); 3420 3421 /* 3422 * Step 46: initialise Receive Buffer (Producer) Ring indexes 3423 */ 3424 bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0); 3425 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3426 bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0); 3427 bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0); 3428 } 3429 /* 3430 * Step 47: configure the MAC unicast address 3431 * Step 48: configure the random backoff seed 3432 * Step 96: set up multicast filters 3433 */ 3434 #ifdef BGE_IPMI_ASF 3435 if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE) 3436 #else 3437 if (bge_chip_sync(bgep) == DDI_FAILURE) 3438 #endif 3439 retval = DDI_FAILURE; 3440 3441 /* 3442 * Step 49: configure the MTU 3443 */ 3444 mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ; 3445 bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu); 3446 3447 /* 3448 * Step 50: configure the IPG et al 3449 */ 3450 bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT); 3451 3452 /* 3453 * Step 51: configure the default Rx Return Ring 3454 */ 3455 bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT); 3456 3457 /* 3458 * Steps 52-54: configure Receive List Placement, 3459 * and enable Receive List Placement Statistics 3460 */ 3461 bge_reg_put32(bgep, RCV_LP_CONFIG_REG, 3462 RCV_LP_CONFIG(bgep->chipid.rx_rings)); 3463 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0); 3464 bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE); 3465 3466 if (bgep->chipid.rx_rings > 1) 3467 bge_init_recv_rule(bgep); 3468 3469 /* 3470 * Steps 55-56: enable Send Data Initiator Statistics 3471 */ 3472 bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0); 3473 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3474 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3475 SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER); 3476 } else { 3477 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3478 SEND_INIT_STATS_ENABLE); 3479 } 3480 /* 3481 * Steps 57-58: stop (?) the Host Coalescing Engine 3482 */ 3483 if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0)) 3484 retval = DDI_FAILURE; 3485 3486 /* 3487 * Steps 59-62: initialise Host Coalescing parameters 3488 */ 3489 bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG, bge_tx_count_norm); 3490 bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG, bge_tx_ticks_norm); 3491 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, bge_rx_count_norm); 3492 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, bge_rx_ticks_norm); 3493 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3494 bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG, 3495 bge_tx_count_intr); 3496 bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG, 3497 bge_tx_ticks_intr); 3498 bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG, 3499 bge_rx_count_intr); 3500 bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG, 3501 bge_rx_ticks_intr); 3502 } 3503 3504 /* 3505 * Steps 63-64: initialise status block & statistics 3506 * host memory addresses 3507 * The statistic block does not exist in some chipsets 3508 * Step 65: initialise Statistics Coalescing Tick Counter 3509 */ 3510 bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG, 3511 bgep->status_block.cookie.dmac_laddress); 3512 3513 /* 3514 * Steps 66-67: initialise status block & statistics 3515 * NIC-local memory addresses 3516 */ 3517 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3518 bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG, 3519 bgep->statistics.cookie.dmac_laddress); 3520 bge_reg_put32(bgep, STATISTICS_TICKS_REG, 3521 STATISTICS_TICKS_DEFAULT); 3522 bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG, 3523 NIC_MEM_STATUS_BLOCK); 3524 bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG, 3525 NIC_MEM_STATISTICS); 3526 } 3527 3528 /* 3529 * Steps 68-71: start the Host Coalescing Engine, the Receive BD 3530 * Completion Engine, the Receive List Placement Engine, and the 3531 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714 3532 * and BCM5715. 3533 */ 3534 if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS && 3535 bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS) 3536 coalmode = COALESCE_64_BYTE_STATUS; 3537 else 3538 coalmode = 0; 3539 if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode)) 3540 retval = DDI_FAILURE; 3541 if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG, 3542 STATE_MACHINE_ATTN_ENABLE_BIT)) 3543 retval = DDI_FAILURE; 3544 if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0)) 3545 retval = DDI_FAILURE; 3546 3547 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3548 if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG, 3549 STATE_MACHINE_ATTN_ENABLE_BIT)) 3550 retval = DDI_FAILURE; 3551 3552 /* 3553 * Step 72: Enable MAC DMA engines 3554 * Step 73: Clear & enable MAC statistics 3555 */ 3556 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3557 ETHERNET_MODE_ENABLE_FHDE | 3558 ETHERNET_MODE_ENABLE_RDE | 3559 ETHERNET_MODE_ENABLE_TDE); 3560 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3561 ETHERNET_MODE_ENABLE_TX_STATS | 3562 ETHERNET_MODE_ENABLE_RX_STATS | 3563 ETHERNET_MODE_CLEAR_TX_STATS | 3564 ETHERNET_MODE_CLEAR_RX_STATS); 3565 3566 /* 3567 * Step 74: configure the MLCR (Miscellaneous Local Control 3568 * Register); not required, as we set up the MLCR in step 10 3569 * (part of the reset code) above. 3570 * 3571 * Step 75: clear Interrupt Mailbox 0 3572 */ 3573 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0); 3574 3575 /* 3576 * Steps 76-87: Gentlemen, start your engines ... 3577 * 3578 * Enable the DMA Completion Engine, the Write DMA Engine, 3579 * the Read DMA Engine, Receive Data Completion Engine, 3580 * the MBuf Cluster Free Engine, the Send Data Completion Engine, 3581 * the Send BD Completion Engine, the Receive BD Initiator Engine, 3582 * the Receive Data Initiator Engine, the Send Data Initiator Engine, 3583 * the Send BD Initiator Engine, and the Send BD Selector Engine. 3584 * 3585 * Beware exhaust fumes? 3586 */ 3587 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3588 if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0)) 3589 retval = DDI_FAILURE; 3590 if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG, 3591 (bge_dma_wrprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS)) 3592 retval = DDI_FAILURE; 3593 if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG, 3594 (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS)) 3595 retval = DDI_FAILURE; 3596 if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG, 3597 STATE_MACHINE_ATTN_ENABLE_BIT)) 3598 retval = DDI_FAILURE; 3599 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3600 if (!bge_chip_enable_engine(bgep, 3601 MBUF_CLUSTER_FREE_MODE_REG, 0)) 3602 retval = DDI_FAILURE; 3603 if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0)) 3604 retval = DDI_FAILURE; 3605 if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG, 3606 STATE_MACHINE_ATTN_ENABLE_BIT)) 3607 retval = DDI_FAILURE; 3608 if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG, 3609 RCV_BD_DISABLED_RING_ATTN)) 3610 retval = DDI_FAILURE; 3611 if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG, 3612 RCV_DATA_BD_ILL_RING_ATTN)) 3613 retval = DDI_FAILURE; 3614 if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0)) 3615 retval = DDI_FAILURE; 3616 if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG, 3617 STATE_MACHINE_ATTN_ENABLE_BIT)) 3618 retval = DDI_FAILURE; 3619 if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG, 3620 STATE_MACHINE_ATTN_ENABLE_BIT)) 3621 retval = DDI_FAILURE; 3622 3623 /* 3624 * Step 88: download firmware -- doesn't apply 3625 * Steps 89-90: enable Transmit & Receive MAC Engines 3626 */ 3627 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 3628 retval = DDI_FAILURE; 3629 #ifdef BGE_IPMI_ASF 3630 if (!bgep->asf_enabled) { 3631 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3632 RECEIVE_MODE_KEEP_VLAN_TAG)) 3633 retval = DDI_FAILURE; 3634 } else { 3635 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0)) 3636 retval = DDI_FAILURE; 3637 } 3638 #else 3639 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3640 RECEIVE_MODE_KEEP_VLAN_TAG)) 3641 retval = DDI_FAILURE; 3642 #endif 3643 3644 /* 3645 * Step 91: disable auto-polling of PHY status 3646 */ 3647 bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT); 3648 3649 /* 3650 * Step 92: configure D0 power state (not required) 3651 * Step 93: initialise LED control register () 3652 */ 3653 ledctl = LED_CONTROL_DEFAULT; 3654 switch (bgep->chipid.device) { 3655 case DEVICE_ID_5700: 3656 case DEVICE_ID_5700x: 3657 case DEVICE_ID_5701: 3658 /* 3659 * Switch to 5700 (MAC) mode on these older chips 3660 */ 3661 ledctl &= ~LED_CONTROL_LED_MODE_MASK; 3662 ledctl |= LED_CONTROL_LED_MODE_5700; 3663 break; 3664 3665 default: 3666 break; 3667 } 3668 bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl); 3669 3670 /* 3671 * Step 94: activate link 3672 */ 3673 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK); 3674 3675 /* 3676 * Step 95: set up physical layer (PHY/SerDes) 3677 * restart autoneg (if required) 3678 */ 3679 if (reset_phys) 3680 if (bge_phys_update(bgep) == DDI_FAILURE) 3681 retval = DDI_FAILURE; 3682 3683 /* 3684 * Extra step (DSG): hand over all the Receive Buffers to the chip 3685 */ 3686 for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring) 3687 bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg, 3688 bgep->buff[ring].rf_next); 3689 3690 /* 3691 * MSI bits:The least significant MSI 16-bit word. 3692 * ISR will be triggered different. 3693 */ 3694 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3695 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70); 3696 3697 /* 3698 * Extra step (DSG): select which interrupts are enabled 3699 * 3700 * Program the Ethernet MAC engine to signal attention on 3701 * Link Change events, then enable interrupts on MAC, DMA, 3702 * and FLOW attention signals. 3703 */ 3704 bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 3705 ETHERNET_EVENT_LINK_INT | 3706 ETHERNET_STATUS_PCS_ERROR_INT); 3707 #ifdef BGE_IPMI_ASF 3708 if (bgep->asf_enabled) { 3709 bge_reg_set32(bgep, MODE_CONTROL_REG, 3710 MODE_INT_ON_FLOW_ATTN | 3711 MODE_INT_ON_DMA_ATTN | 3712 MODE_HOST_STACK_UP| 3713 MODE_INT_ON_MAC_ATTN); 3714 } else { 3715 #endif 3716 bge_reg_set32(bgep, MODE_CONTROL_REG, 3717 MODE_INT_ON_FLOW_ATTN | 3718 MODE_INT_ON_DMA_ATTN | 3719 MODE_INT_ON_MAC_ATTN); 3720 #ifdef BGE_IPMI_ASF 3721 } 3722 #endif 3723 3724 /* 3725 * Step 97: enable PCI interrupts!!! 3726 */ 3727 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 3728 bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR, 3729 MHCR_MASK_PCI_INT_OUTPUT); 3730 3731 /* 3732 * All done! 3733 */ 3734 bgep->bge_chip_state = BGE_CHIP_RUNNING; 3735 return (retval); 3736 } 3737 3738 3739 /* 3740 * ========== Hardware interrupt handler ========== 3741 */ 3742 3743 #undef BGE_DBG 3744 #define BGE_DBG BGE_DBG_INT /* debug flag for this code */ 3745 3746 /* 3747 * Sync the status block, then atomically clear the specified bits in 3748 * the <flags-and-tag> field of the status block. 3749 * the <flags> word of the status block, returning the value of the 3750 * <tag> and the <flags> before the bits were cleared. 3751 */ 3752 static int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags); 3753 #pragma inline(bge_status_sync) 3754 3755 static int 3756 bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags) 3757 { 3758 bge_status_t *bsp; 3759 int retval; 3760 3761 BGE_TRACE(("bge_status_sync($%p, 0x%llx)", 3762 (void *)bgep, bits)); 3763 3764 ASSERT(bgep->bge_guard == BGE_GUARD); 3765 3766 DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL); 3767 retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl); 3768 if (retval != DDI_FM_OK) 3769 return (retval); 3770 3771 bsp = DMA_VPTR(bgep->status_block); 3772 *flags = bge_atomic_clr64(&bsp->flags_n_tag, bits); 3773 3774 BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx", 3775 (void *)bgep, bits, *flags)); 3776 3777 return (retval); 3778 } 3779 3780 static void bge_wake_factotum(bge_t *bgep); 3781 #pragma inline(bge_wake_factotum) 3782 3783 static void 3784 bge_wake_factotum(bge_t *bgep) 3785 { 3786 mutex_enter(bgep->softintrlock); 3787 if (bgep->factotum_flag == 0) { 3788 bgep->factotum_flag = 1; 3789 ddi_trigger_softintr(bgep->factotum_id); 3790 } 3791 mutex_exit(bgep->softintrlock); 3792 } 3793 3794 /* 3795 * bge_intr() -- handle chip interrupts 3796 */ 3797 uint_t bge_intr(caddr_t arg1, caddr_t arg2); 3798 #pragma no_inline(bge_intr) 3799 3800 uint_t 3801 bge_intr(caddr_t arg1, caddr_t arg2) 3802 { 3803 bge_t *bgep = (bge_t *)arg1; /* private device info */ 3804 bge_status_t *bsp; 3805 uint64_t flags; 3806 uint32_t mlcr = 0; 3807 uint_t result; 3808 int retval; 3809 3810 BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2)); 3811 3812 /* 3813 * GLD v2 checks that s/w setup is complete before passing 3814 * interrupts to this routine, thus eliminating the old 3815 * (and well-known) race condition around ddi_add_intr() 3816 */ 3817 ASSERT(bgep->progress & PROGRESS_HWINT); 3818 3819 /* 3820 * Check whether chip's says it's asserting #INTA; 3821 * if not, don't process or claim the interrupt. 3822 * 3823 * Note that the PCI signal is active low, so the 3824 * bit is *zero* when the interrupt is asserted. 3825 */ 3826 result = DDI_INTR_UNCLAIMED; 3827 mutex_enter(bgep->genlock); 3828 3829 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 3830 mlcr = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 3831 3832 BGE_DEBUG(("bge_intr($%p) ($%p) mlcr 0x%08x", arg1, arg2, mlcr)); 3833 3834 if ((mlcr & MLCR_INTA_STATE) == 0) { 3835 /* 3836 * Block further PCI interrupts ... 3837 */ 3838 result = DDI_INTR_CLAIMED; 3839 3840 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 3841 bge_reg_set32(bgep, PCI_CONF_BGE_MHCR, 3842 MHCR_MASK_PCI_INT_OUTPUT); 3843 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 3844 DDI_FM_OK) 3845 goto chip_stop; 3846 } 3847 3848 /* 3849 * Sync the status block and grab the flags-n-tag from it. 3850 * We count the number of interrupts where there doesn't 3851 * seem to have been a DMA update of the status block; if 3852 * it *has* been updated, the counter will be cleared in 3853 * the while() loop below ... 3854 */ 3855 bgep->missed_dmas += 1; 3856 bsp = DMA_VPTR(bgep->status_block); 3857 for (;;) { 3858 if (bgep->bge_chip_state != BGE_CHIP_RUNNING) { 3859 /* 3860 * bge_chip_stop() may have freed dma area etc 3861 * while we were in this interrupt handler - 3862 * better not call bge_status_sync() 3863 */ 3864 (void) bge_check_acc_handle(bgep, 3865 bgep->io_handle); 3866 mutex_exit(bgep->genlock); 3867 return (DDI_INTR_CLAIMED); 3868 } 3869 retval = bge_status_sync(bgep, STATUS_FLAG_UPDATED, 3870 &flags); 3871 if (retval != DDI_FM_OK) { 3872 bgep->bge_dma_error = B_TRUE; 3873 goto chip_stop; 3874 } 3875 3876 if (!(flags & STATUS_FLAG_UPDATED)) 3877 break; 3878 3879 /* 3880 * Tell the chip that we're processing the interrupt 3881 */ 3882 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 3883 INTERRUPT_MBOX_DISABLE(flags)); 3884 if (bge_check_acc_handle(bgep, bgep->io_handle) != 3885 DDI_FM_OK) 3886 goto chip_stop; 3887 3888 /* 3889 * Drop the mutex while we: 3890 * Receive any newly-arrived packets 3891 * Recycle any newly-finished send buffers 3892 */ 3893 bgep->bge_intr_running = B_TRUE; 3894 mutex_exit(bgep->genlock); 3895 bge_receive(bgep, bsp); 3896 bge_recycle(bgep, bsp); 3897 mutex_enter(bgep->genlock); 3898 bgep->bge_intr_running = B_FALSE; 3899 3900 /* 3901 * Tell the chip we've finished processing, and 3902 * give it the tag that we got from the status 3903 * block earlier, so that it knows just how far 3904 * we've gone. If it's got more for us to do, 3905 * it will now update the status block and try 3906 * to assert an interrupt (but we've got the 3907 * #INTA blocked at present). If we see the 3908 * update, we'll loop around to do some more. 3909 * Eventually we'll get out of here ... 3910 */ 3911 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 3912 INTERRUPT_MBOX_ENABLE(flags)); 3913 bgep->missed_dmas = 0; 3914 } 3915 3916 /* 3917 * Check for exceptional conditions that we need to handle 3918 * 3919 * Link status changed 3920 * Status block not updated 3921 */ 3922 if (flags & STATUS_FLAG_LINK_CHANGED) 3923 bge_wake_factotum(bgep); 3924 3925 if (bgep->missed_dmas) { 3926 /* 3927 * Probably due to the internal status tag not 3928 * being reset. Force a status block update now; 3929 * this should ensure that we get an update and 3930 * a new interrupt. After that, we should be in 3931 * sync again ... 3932 */ 3933 BGE_REPORT((bgep, "interrupt: flags 0x%llx - " 3934 "not updated?", flags)); 3935 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 3936 COALESCE_NOW); 3937 3938 if (bgep->missed_dmas >= bge_dma_miss_limit) { 3939 /* 3940 * If this happens multiple times in a row, 3941 * it means DMA is just not working. Maybe 3942 * the chip's failed, or maybe there's a 3943 * problem on the PCI bus or in the host-PCI 3944 * bridge (Tomatillo). 3945 * 3946 * At all events, we want to stop further 3947 * interrupts and let the recovery code take 3948 * over to see whether anything can be done 3949 * about it ... 3950 */ 3951 bge_fm_ereport(bgep, 3952 DDI_FM_DEVICE_BADINT_LIMIT); 3953 goto chip_stop; 3954 } 3955 } 3956 3957 /* 3958 * Reenable assertion of #INTA, unless there's a DMA fault 3959 */ 3960 if (result == DDI_INTR_CLAIMED) { 3961 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 3962 bge_reg_clr32(bgep, PCI_CONF_BGE_MHCR, 3963 MHCR_MASK_PCI_INT_OUTPUT); 3964 if (bge_check_acc_handle(bgep, 3965 bgep->cfg_handle) != DDI_FM_OK) 3966 goto chip_stop; 3967 } 3968 } 3969 } 3970 3971 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 3972 goto chip_stop; 3973 3974 mutex_exit(bgep->genlock); 3975 return (result); 3976 3977 chip_stop: 3978 #ifdef BGE_IPMI_ASF 3979 if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) { 3980 /* 3981 * We must stop ASF heart beat before 3982 * bge_chip_stop(), otherwise some 3983 * computers (ex. IBM HS20 blade 3984 * server) may crash. 3985 */ 3986 bge_asf_update_status(bgep); 3987 bge_asf_stop_timer(bgep); 3988 bgep->asf_status = ASF_STAT_STOP; 3989 3990 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 3991 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 3992 } 3993 #endif 3994 bge_chip_stop(bgep, B_TRUE); 3995 (void) bge_check_acc_handle(bgep, bgep->io_handle); 3996 mutex_exit(bgep->genlock); 3997 return (result); 3998 } 3999 4000 /* 4001 * ========== Factotum, implemented as a softint handler ========== 4002 */ 4003 4004 #undef BGE_DBG 4005 #define BGE_DBG BGE_DBG_FACT /* debug flag for this code */ 4006 4007 static void bge_factotum_error_handler(bge_t *bgep); 4008 #pragma no_inline(bge_factotum_error_handler) 4009 4010 static void 4011 bge_factotum_error_handler(bge_t *bgep) 4012 { 4013 uint32_t flow; 4014 uint32_t rdma; 4015 uint32_t wdma; 4016 uint32_t tmac; 4017 uint32_t rmac; 4018 uint32_t rxrs; 4019 uint32_t txrs = 0; 4020 4021 ASSERT(mutex_owned(bgep->genlock)); 4022 4023 /* 4024 * Read all the registers that show the possible 4025 * reasons for the ERROR bit to be asserted 4026 */ 4027 flow = bge_reg_get32(bgep, FLOW_ATTN_REG); 4028 rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG); 4029 wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG); 4030 tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4031 rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG); 4032 rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG); 4033 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4034 txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG); 4035 4036 BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x", 4037 (void *)bgep, flow, rdma, wdma)); 4038 BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x", 4039 (void *)bgep, tmac, rmac, rxrs, txrs)); 4040 4041 /* 4042 * For now, just clear all the errors ... 4043 */ 4044 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4045 bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0); 4046 bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0); 4047 bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0); 4048 bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0); 4049 bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0); 4050 bge_reg_put32(bgep, FLOW_ATTN_REG, ~0); 4051 } 4052 4053 /* 4054 * Handler for hardware link state change. 4055 * 4056 * When this routine is called, the hardware link state has changed 4057 * and the new state is reflected in the param_* variables. Here 4058 * we must update the softstate, reprogram the MAC to match, and 4059 * record the change in the log and/or on the console. 4060 */ 4061 static void bge_factotum_link_handler(bge_t *bgep); 4062 #pragma no_inline(bge_factotum_link_handler) 4063 4064 static void 4065 bge_factotum_link_handler(bge_t *bgep) 4066 { 4067 void (*logfn)(bge_t *bgep, const char *fmt, ...); 4068 const char *msg; 4069 hrtime_t deltat; 4070 4071 ASSERT(mutex_owned(bgep->genlock)); 4072 4073 /* 4074 * Update the s/w link_state 4075 */ 4076 if (bgep->param_link_up) 4077 bgep->link_state = LINK_STATE_UP; 4078 else 4079 bgep->link_state = LINK_STATE_DOWN; 4080 4081 /* 4082 * Reprogram the MAC modes to match 4083 */ 4084 bge_sync_mac_modes(bgep); 4085 4086 /* 4087 * Finally, we have to decide whether to write a message 4088 * on the console or only in the log. If the PHY has 4089 * been reprogrammed (at user request) "recently", then 4090 * the message only goes in the log. Otherwise it's an 4091 * "unexpected" event, and it goes on the console as well. 4092 */ 4093 deltat = bgep->phys_event_time - bgep->phys_write_time; 4094 if (deltat > BGE_LINK_SETTLE_TIME) 4095 msg = ""; 4096 else if (bgep->param_link_up) 4097 msg = bgep->link_up_msg; 4098 else 4099 msg = bgep->link_down_msg; 4100 4101 logfn = (msg == NULL || *msg == '\0') ? bge_notice : bge_log; 4102 (*logfn)(bgep, "link %s%s", bgep->link_mode_msg, msg); 4103 } 4104 4105 static boolean_t bge_factotum_link_check(bge_t *bgep, int *dma_state); 4106 #pragma no_inline(bge_factotum_link_check) 4107 4108 static boolean_t 4109 bge_factotum_link_check(bge_t *bgep, int *dma_state) 4110 { 4111 boolean_t check; 4112 uint64_t flags; 4113 uint32_t tmac_status; 4114 4115 ASSERT(mutex_owned(bgep->genlock)); 4116 4117 /* 4118 * Get & clear the writable status bits in the Tx status register 4119 * (some bits are write-1-to-clear, others are just readonly). 4120 */ 4121 tmac_status = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4122 bge_reg_put32(bgep, TRANSMIT_MAC_STATUS_REG, tmac_status); 4123 4124 /* 4125 * Get & clear the ERROR and LINK_CHANGED bits from the status block 4126 */ 4127 *dma_state = bge_status_sync(bgep, STATUS_FLAG_ERROR | 4128 STATUS_FLAG_LINK_CHANGED, &flags); 4129 if (*dma_state != DDI_FM_OK) 4130 return (B_FALSE); 4131 4132 /* 4133 * Clear any errors flagged in the status block ... 4134 */ 4135 if (flags & STATUS_FLAG_ERROR) 4136 bge_factotum_error_handler(bgep); 4137 4138 /* 4139 * We need to check the link status if: 4140 * the status block says there's been a link change 4141 * or there's any discrepancy between the various 4142 * flags indicating the link state (link_state, 4143 * param_link_up, and the LINK STATE bit in the 4144 * Transmit MAC status register). 4145 */ 4146 check = (flags & STATUS_FLAG_LINK_CHANGED) != 0; 4147 switch (bgep->link_state) { 4148 case LINK_STATE_UP: 4149 check |= (bgep->param_link_up == B_FALSE); 4150 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) == 0); 4151 break; 4152 4153 case LINK_STATE_DOWN: 4154 check |= (bgep->param_link_up != B_FALSE); 4155 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) != 0); 4156 break; 4157 4158 default: 4159 check = B_TRUE; 4160 break; 4161 } 4162 4163 /* 4164 * If <check> is false, we're sure the link hasn't changed. 4165 * If true, however, it's not yet definitive; we have to call 4166 * bge_phys_check() to determine whether the link has settled 4167 * into a new state yet ... and if it has, then call the link 4168 * state change handler.But when the chip is 5700 in Dell 6650 4169 * ,even if check is false, the link may have changed.So we 4170 * have to call bge_phys_check() to determine the link state. 4171 */ 4172 if (check || bgep->chipid.device == DEVICE_ID_5700) { 4173 check = bge_phys_check(bgep); 4174 if (check) 4175 bge_factotum_link_handler(bgep); 4176 } 4177 4178 return (check); 4179 } 4180 4181 /* 4182 * Factotum routine to check for Tx stall, using the 'watchdog' counter 4183 */ 4184 static boolean_t bge_factotum_stall_check(bge_t *bgep); 4185 #pragma no_inline(bge_factotum_stall_check) 4186 4187 static boolean_t 4188 bge_factotum_stall_check(bge_t *bgep) 4189 { 4190 uint32_t dogval; 4191 4192 ASSERT(mutex_owned(bgep->genlock)); 4193 4194 /* 4195 * Specific check for Tx stall ... 4196 * 4197 * The 'watchdog' counter is incremented whenever a packet 4198 * is queued, reset to 1 when some (but not all) buffers 4199 * are reclaimed, reset to 0 (disabled) when all buffers 4200 * are reclaimed, and shifted left here. If it exceeds the 4201 * threshold value, the chip is assumed to have stalled and 4202 * is put into the ERROR state. The factotum will then reset 4203 * it on the next pass. 4204 * 4205 * All of which should ensure that we don't get into a state 4206 * where packets are left pending indefinitely! 4207 */ 4208 dogval = bge_atomic_shl32(&bgep->watchdog, 1); 4209 if (dogval < bge_watchdog_count) 4210 return (B_FALSE); 4211 4212 BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval)); 4213 bge_fm_ereport(bgep, DDI_FM_DEVICE_STALL); 4214 return (B_TRUE); 4215 } 4216 4217 /* 4218 * The factotum is woken up when there's something to do that we'd rather 4219 * not do from inside a hardware interrupt handler or high-level cyclic. 4220 * Its two main tasks are: 4221 * reset & restart the chip after an error 4222 * check the link status whenever necessary 4223 */ 4224 uint_t bge_chip_factotum(caddr_t arg); 4225 #pragma no_inline(bge_chip_factotum) 4226 4227 uint_t 4228 bge_chip_factotum(caddr_t arg) 4229 { 4230 bge_t *bgep; 4231 uint_t result; 4232 boolean_t error; 4233 boolean_t linkchg; 4234 int dma_state; 4235 4236 bgep = (bge_t *)arg; 4237 4238 BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep)); 4239 4240 mutex_enter(bgep->softintrlock); 4241 if (bgep->factotum_flag == 0) { 4242 mutex_exit(bgep->softintrlock); 4243 return (DDI_INTR_UNCLAIMED); 4244 } 4245 bgep->factotum_flag = 0; 4246 mutex_exit(bgep->softintrlock); 4247 4248 result = DDI_INTR_CLAIMED; 4249 error = B_FALSE; 4250 linkchg = B_FALSE; 4251 4252 mutex_enter(bgep->genlock); 4253 switch (bgep->bge_chip_state) { 4254 default: 4255 break; 4256 4257 case BGE_CHIP_RUNNING: 4258 linkchg = bge_factotum_link_check(bgep, &dma_state); 4259 error = bge_factotum_stall_check(bgep); 4260 if (dma_state != DDI_FM_OK) { 4261 bgep->bge_dma_error = B_TRUE; 4262 error = B_TRUE; 4263 } 4264 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4265 error = B_TRUE; 4266 if (error) 4267 bgep->bge_chip_state = BGE_CHIP_ERROR; 4268 break; 4269 4270 case BGE_CHIP_ERROR: 4271 error = B_TRUE; 4272 break; 4273 4274 case BGE_CHIP_FAULT: 4275 /* 4276 * Fault detected, time to reset ... 4277 */ 4278 if (bge_autorecover) { 4279 if (!(bgep->progress & PROGRESS_BUFS)) { 4280 /* 4281 * if we can't allocate the ring buffers, 4282 * try later 4283 */ 4284 if (bge_alloc_bufs(bgep) != DDI_SUCCESS) { 4285 mutex_exit(bgep->genlock); 4286 return (result); 4287 } 4288 bgep->progress |= PROGRESS_BUFS; 4289 } 4290 if (!(bgep->progress & PROGRESS_INTR)) { 4291 bge_init_rings(bgep); 4292 bge_intr_enable(bgep); 4293 bgep->progress |= PROGRESS_INTR; 4294 } 4295 if (!(bgep->progress & PROGRESS_KSTATS)) { 4296 bge_init_kstats(bgep, 4297 ddi_get_instance(bgep->devinfo)); 4298 bgep->progress |= PROGRESS_KSTATS; 4299 } 4300 4301 BGE_REPORT((bgep, "automatic recovery activated")); 4302 4303 if (bge_restart(bgep, B_FALSE) != DDI_SUCCESS) { 4304 bgep->bge_chip_state = BGE_CHIP_ERROR; 4305 error = B_TRUE; 4306 } 4307 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4308 DDI_FM_OK) { 4309 bgep->bge_chip_state = BGE_CHIP_ERROR; 4310 error = B_TRUE; 4311 } 4312 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4313 DDI_FM_OK) { 4314 bgep->bge_chip_state = BGE_CHIP_ERROR; 4315 error = B_TRUE; 4316 } 4317 if (error == B_FALSE) { 4318 #ifdef BGE_IPMI_ASF 4319 if (bgep->asf_enabled && 4320 bgep->asf_status != ASF_STAT_RUN) { 4321 bgep->asf_timeout_id = timeout( 4322 bge_asf_heartbeat, (void *)bgep, 4323 drv_usectohz( 4324 BGE_ASF_HEARTBEAT_INTERVAL)); 4325 bgep->asf_status = ASF_STAT_RUN; 4326 } 4327 #endif 4328 ddi_fm_service_impact(bgep->devinfo, 4329 DDI_SERVICE_RESTORED); 4330 } 4331 } 4332 break; 4333 } 4334 4335 4336 /* 4337 * If an error is detected, stop the chip now, marking it as 4338 * faulty, so that it will be reset next time through ... 4339 * 4340 * Note that if intr_running is set, then bge_intr() has dropped 4341 * genlock to call bge_receive/bge_recycle. Can't stop the chip at 4342 * this point so have to wait until the next time the factotum runs. 4343 */ 4344 if (error && !bgep->bge_intr_running) { 4345 #ifdef BGE_IPMI_ASF 4346 if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) { 4347 /* 4348 * We must stop ASF heart beat before bge_chip_stop(), 4349 * otherwise some computers (ex. IBM HS20 blade server) 4350 * may crash. 4351 */ 4352 bge_asf_update_status(bgep); 4353 bge_asf_stop_timer(bgep); 4354 bgep->asf_status = ASF_STAT_STOP; 4355 4356 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4357 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4358 } 4359 #endif 4360 bge_chip_stop(bgep, B_TRUE); 4361 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4362 } 4363 mutex_exit(bgep->genlock); 4364 4365 /* 4366 * If the link state changed, tell the world about it. 4367 * Note: can't do this while still holding the mutex. 4368 */ 4369 if (linkchg) 4370 mac_link_update(bgep->mh, bgep->link_state); 4371 4372 return (result); 4373 } 4374 4375 /* 4376 * High-level cyclic handler 4377 * 4378 * This routine schedules a (low-level) softint callback to the 4379 * factotum, and prods the chip to update the status block (which 4380 * will cause a hardware interrupt when complete). 4381 */ 4382 void bge_chip_cyclic(void *arg); 4383 #pragma no_inline(bge_chip_cyclic) 4384 4385 void 4386 bge_chip_cyclic(void *arg) 4387 { 4388 bge_t *bgep; 4389 4390 bgep = arg; 4391 4392 switch (bgep->bge_chip_state) { 4393 default: 4394 return; 4395 4396 case BGE_CHIP_RUNNING: 4397 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW); 4398 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4399 ddi_fm_service_impact(bgep->devinfo, 4400 DDI_SERVICE_UNAFFECTED); 4401 break; 4402 4403 case BGE_CHIP_FAULT: 4404 case BGE_CHIP_ERROR: 4405 break; 4406 } 4407 4408 bge_wake_factotum(bgep); 4409 } 4410 4411 4412 /* 4413 * ========== Ioctl subfunctions ========== 4414 */ 4415 4416 #undef BGE_DBG 4417 #define BGE_DBG BGE_DBG_PPIO /* debug flag for this code */ 4418 4419 #if BGE_DEBUGGING || BGE_DO_PPIO 4420 4421 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4422 #pragma no_inline(bge_chip_peek_cfg) 4423 4424 static void 4425 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4426 { 4427 uint64_t regval; 4428 uint64_t regno; 4429 4430 BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)", 4431 (void *)bgep, (void *)ppd)); 4432 4433 regno = ppd->pp_acc_offset; 4434 4435 switch (ppd->pp_acc_size) { 4436 case 1: 4437 regval = pci_config_get8(bgep->cfg_handle, regno); 4438 break; 4439 4440 case 2: 4441 regval = pci_config_get16(bgep->cfg_handle, regno); 4442 break; 4443 4444 case 4: 4445 regval = pci_config_get32(bgep->cfg_handle, regno); 4446 break; 4447 4448 case 8: 4449 regval = pci_config_get64(bgep->cfg_handle, regno); 4450 break; 4451 } 4452 4453 ppd->pp_acc_data = regval; 4454 } 4455 4456 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4457 #pragma no_inline(bge_chip_poke_cfg) 4458 4459 static void 4460 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4461 { 4462 uint64_t regval; 4463 uint64_t regno; 4464 4465 BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)", 4466 (void *)bgep, (void *)ppd)); 4467 4468 regno = ppd->pp_acc_offset; 4469 regval = ppd->pp_acc_data; 4470 4471 switch (ppd->pp_acc_size) { 4472 case 1: 4473 pci_config_put8(bgep->cfg_handle, regno, regval); 4474 break; 4475 4476 case 2: 4477 pci_config_put16(bgep->cfg_handle, regno, regval); 4478 break; 4479 4480 case 4: 4481 pci_config_put32(bgep->cfg_handle, regno, regval); 4482 break; 4483 4484 case 8: 4485 pci_config_put64(bgep->cfg_handle, regno, regval); 4486 break; 4487 } 4488 } 4489 4490 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4491 #pragma no_inline(bge_chip_peek_reg) 4492 4493 static void 4494 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4495 { 4496 uint64_t regval; 4497 void *regaddr; 4498 4499 BGE_TRACE(("bge_chip_peek_reg($%p, $%p)", 4500 (void *)bgep, (void *)ppd)); 4501 4502 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4503 4504 switch (ppd->pp_acc_size) { 4505 case 1: 4506 regval = ddi_get8(bgep->io_handle, regaddr); 4507 break; 4508 4509 case 2: 4510 regval = ddi_get16(bgep->io_handle, regaddr); 4511 break; 4512 4513 case 4: 4514 regval = ddi_get32(bgep->io_handle, regaddr); 4515 break; 4516 4517 case 8: 4518 regval = ddi_get64(bgep->io_handle, regaddr); 4519 break; 4520 } 4521 4522 ppd->pp_acc_data = regval; 4523 } 4524 4525 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4526 #pragma no_inline(bge_chip_peek_reg) 4527 4528 static void 4529 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4530 { 4531 uint64_t regval; 4532 void *regaddr; 4533 4534 BGE_TRACE(("bge_chip_poke_reg($%p, $%p)", 4535 (void *)bgep, (void *)ppd)); 4536 4537 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4538 regval = ppd->pp_acc_data; 4539 4540 switch (ppd->pp_acc_size) { 4541 case 1: 4542 ddi_put8(bgep->io_handle, regaddr, regval); 4543 break; 4544 4545 case 2: 4546 ddi_put16(bgep->io_handle, regaddr, regval); 4547 break; 4548 4549 case 4: 4550 ddi_put32(bgep->io_handle, regaddr, regval); 4551 break; 4552 4553 case 8: 4554 ddi_put64(bgep->io_handle, regaddr, regval); 4555 break; 4556 } 4557 BGE_PCICHK(bgep); 4558 } 4559 4560 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4561 #pragma no_inline(bge_chip_peek_nic) 4562 4563 static void 4564 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4565 { 4566 uint64_t regoff; 4567 uint64_t regval; 4568 void *regaddr; 4569 4570 BGE_TRACE(("bge_chip_peek_nic($%p, $%p)", 4571 (void *)bgep, (void *)ppd)); 4572 4573 regoff = ppd->pp_acc_offset; 4574 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4575 regoff &= MWBAR_GRANULE_MASK; 4576 regoff += NIC_MEM_WINDOW_OFFSET; 4577 regaddr = PIO_ADDR(bgep, regoff); 4578 4579 switch (ppd->pp_acc_size) { 4580 case 1: 4581 regval = ddi_get8(bgep->io_handle, regaddr); 4582 break; 4583 4584 case 2: 4585 regval = ddi_get16(bgep->io_handle, regaddr); 4586 break; 4587 4588 case 4: 4589 regval = ddi_get32(bgep->io_handle, regaddr); 4590 break; 4591 4592 case 8: 4593 regval = ddi_get64(bgep->io_handle, regaddr); 4594 break; 4595 } 4596 4597 ppd->pp_acc_data = regval; 4598 } 4599 4600 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4601 #pragma no_inline(bge_chip_poke_nic) 4602 4603 static void 4604 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4605 { 4606 uint64_t regoff; 4607 uint64_t regval; 4608 void *regaddr; 4609 4610 BGE_TRACE(("bge_chip_poke_nic($%p, $%p)", 4611 (void *)bgep, (void *)ppd)); 4612 4613 regoff = ppd->pp_acc_offset; 4614 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4615 regoff &= MWBAR_GRANULE_MASK; 4616 regoff += NIC_MEM_WINDOW_OFFSET; 4617 regaddr = PIO_ADDR(bgep, regoff); 4618 regval = ppd->pp_acc_data; 4619 4620 switch (ppd->pp_acc_size) { 4621 case 1: 4622 ddi_put8(bgep->io_handle, regaddr, regval); 4623 break; 4624 4625 case 2: 4626 ddi_put16(bgep->io_handle, regaddr, regval); 4627 break; 4628 4629 case 4: 4630 ddi_put32(bgep->io_handle, regaddr, regval); 4631 break; 4632 4633 case 8: 4634 ddi_put64(bgep->io_handle, regaddr, regval); 4635 break; 4636 } 4637 BGE_PCICHK(bgep); 4638 } 4639 4640 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4641 #pragma no_inline(bge_chip_peek_mii) 4642 4643 static void 4644 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4645 { 4646 BGE_TRACE(("bge_chip_peek_mii($%p, $%p)", 4647 (void *)bgep, (void *)ppd)); 4648 4649 ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2); 4650 } 4651 4652 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4653 #pragma no_inline(bge_chip_poke_mii) 4654 4655 static void 4656 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4657 { 4658 BGE_TRACE(("bge_chip_poke_mii($%p, $%p)", 4659 (void *)bgep, (void *)ppd)); 4660 4661 bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 4662 } 4663 4664 #if BGE_SEE_IO32 4665 4666 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4667 #pragma no_inline(bge_chip_peek_seeprom) 4668 4669 static void 4670 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4671 { 4672 uint32_t data; 4673 int err; 4674 4675 BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)", 4676 (void *)bgep, (void *)ppd)); 4677 4678 err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data); 4679 ppd->pp_acc_data = err ? ~0ull : data; 4680 } 4681 4682 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4683 #pragma no_inline(bge_chip_poke_seeprom) 4684 4685 static void 4686 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4687 { 4688 uint32_t data; 4689 4690 BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)", 4691 (void *)bgep, (void *)ppd)); 4692 4693 data = ppd->pp_acc_data; 4694 (void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data); 4695 } 4696 #endif /* BGE_SEE_IO32 */ 4697 4698 #if BGE_FLASH_IO32 4699 4700 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4701 #pragma no_inline(bge_chip_peek_flash) 4702 4703 static void 4704 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd) 4705 { 4706 uint32_t data; 4707 int err; 4708 4709 BGE_TRACE(("bge_chip_peek_flash($%p, $%p)", 4710 (void *)bgep, (void *)ppd)); 4711 4712 err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data); 4713 ppd->pp_acc_data = err ? ~0ull : data; 4714 } 4715 4716 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4717 #pragma no_inline(bge_chip_poke_flash) 4718 4719 static void 4720 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd) 4721 { 4722 uint32_t data; 4723 4724 BGE_TRACE(("bge_chip_poke_flash($%p, $%p)", 4725 (void *)bgep, (void *)ppd)); 4726 4727 data = ppd->pp_acc_data; 4728 (void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE, 4729 ppd->pp_acc_offset, &data); 4730 } 4731 #endif /* BGE_FLASH_IO32 */ 4732 4733 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd); 4734 #pragma no_inline(bge_chip_peek_mem) 4735 4736 static void 4737 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd) 4738 { 4739 uint64_t regval; 4740 void *vaddr; 4741 4742 BGE_TRACE(("bge_chip_peek_bge($%p, $%p)", 4743 (void *)bgep, (void *)ppd)); 4744 4745 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4746 4747 switch (ppd->pp_acc_size) { 4748 case 1: 4749 regval = *(uint8_t *)vaddr; 4750 break; 4751 4752 case 2: 4753 regval = *(uint16_t *)vaddr; 4754 break; 4755 4756 case 4: 4757 regval = *(uint32_t *)vaddr; 4758 break; 4759 4760 case 8: 4761 regval = *(uint64_t *)vaddr; 4762 break; 4763 } 4764 4765 BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 4766 (void *)bgep, (void *)ppd, regval, vaddr)); 4767 4768 ppd->pp_acc_data = regval; 4769 } 4770 4771 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd); 4772 #pragma no_inline(bge_chip_poke_mem) 4773 4774 static void 4775 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd) 4776 { 4777 uint64_t regval; 4778 void *vaddr; 4779 4780 BGE_TRACE(("bge_chip_poke_mem($%p, $%p)", 4781 (void *)bgep, (void *)ppd)); 4782 4783 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4784 regval = ppd->pp_acc_data; 4785 4786 BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 4787 (void *)bgep, (void *)ppd, regval, vaddr)); 4788 4789 switch (ppd->pp_acc_size) { 4790 case 1: 4791 *(uint8_t *)vaddr = (uint8_t)regval; 4792 break; 4793 4794 case 2: 4795 *(uint16_t *)vaddr = (uint16_t)regval; 4796 break; 4797 4798 case 4: 4799 *(uint32_t *)vaddr = (uint32_t)regval; 4800 break; 4801 4802 case 8: 4803 *(uint64_t *)vaddr = (uint64_t)regval; 4804 break; 4805 } 4806 } 4807 4808 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 4809 struct iocblk *iocp); 4810 #pragma no_inline(bge_pp_ioctl) 4811 4812 static enum ioc_reply 4813 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 4814 { 4815 void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd); 4816 bge_peekpoke_t *ppd; 4817 dma_area_t *areap; 4818 uint64_t sizemask; 4819 uint64_t mem_va; 4820 uint64_t maxoff; 4821 boolean_t peek; 4822 4823 switch (cmd) { 4824 default: 4825 /* NOTREACHED */ 4826 bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd); 4827 return (IOC_INVAL); 4828 4829 case BGE_PEEK: 4830 peek = B_TRUE; 4831 break; 4832 4833 case BGE_POKE: 4834 peek = B_FALSE; 4835 break; 4836 } 4837 4838 /* 4839 * Validate format of ioctl 4840 */ 4841 if (iocp->ioc_count != sizeof (bge_peekpoke_t)) 4842 return (IOC_INVAL); 4843 if (mp->b_cont == NULL) 4844 return (IOC_INVAL); 4845 ppd = (bge_peekpoke_t *)mp->b_cont->b_rptr; 4846 4847 /* 4848 * Validate request parameters 4849 */ 4850 switch (ppd->pp_acc_space) { 4851 default: 4852 return (IOC_INVAL); 4853 4854 case BGE_PP_SPACE_CFG: 4855 /* 4856 * Config space 4857 */ 4858 sizemask = 8|4|2|1; 4859 mem_va = 0; 4860 maxoff = PCI_CONF_HDR_SIZE; 4861 ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg; 4862 break; 4863 4864 case BGE_PP_SPACE_REG: 4865 /* 4866 * Memory-mapped I/O space 4867 */ 4868 sizemask = 8|4|2|1; 4869 mem_va = 0; 4870 maxoff = RIAAR_REGISTER_MAX; 4871 ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg; 4872 break; 4873 4874 case BGE_PP_SPACE_NIC: 4875 /* 4876 * NIC on-chip memory 4877 */ 4878 sizemask = 8|4|2|1; 4879 mem_va = 0; 4880 maxoff = MWBAR_ONCHIP_MAX; 4881 ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic; 4882 break; 4883 4884 case BGE_PP_SPACE_MII: 4885 /* 4886 * PHY's MII registers 4887 * NB: all PHY registers are two bytes, but the 4888 * addresses increment in ones (word addressing). 4889 * So we scale the address here, then undo the 4890 * transformation inside the peek/poke functions. 4891 */ 4892 ppd->pp_acc_offset *= 2; 4893 sizemask = 2; 4894 mem_va = 0; 4895 maxoff = (MII_MAXREG+1)*2; 4896 ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii; 4897 break; 4898 4899 #if BGE_SEE_IO32 4900 case BGE_PP_SPACE_SEEPROM: 4901 /* 4902 * Attached SEEPROM(s), if any. 4903 * NB: we use the high-order bits of the 'address' as 4904 * a device select to accommodate multiple SEEPROMS, 4905 * If each one is the maximum size (64kbytes), this 4906 * makes them appear contiguous. Otherwise, there may 4907 * be holes in the mapping. ENxS doesn't have any 4908 * SEEPROMs anyway ... 4909 */ 4910 sizemask = 4; 4911 mem_va = 0; 4912 maxoff = SEEPROM_DEV_AND_ADDR_MASK; 4913 ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom; 4914 break; 4915 #endif /* BGE_SEE_IO32 */ 4916 4917 #if BGE_FLASH_IO32 4918 case BGE_PP_SPACE_FLASH: 4919 /* 4920 * Attached Flash device (if any); a maximum of one device 4921 * is currently supported. But it can be up to 1MB (unlike 4922 * the 64k limit on SEEPROMs) so why would you need more ;-) 4923 */ 4924 sizemask = 4; 4925 mem_va = 0; 4926 maxoff = NVM_FLASH_ADDR_MASK; 4927 ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash; 4928 break; 4929 #endif /* BGE_FLASH_IO32 */ 4930 4931 case BGE_PP_SPACE_BGE: 4932 /* 4933 * BGE data structure! 4934 */ 4935 sizemask = 8|4|2|1; 4936 mem_va = (uintptr_t)bgep; 4937 maxoff = sizeof (*bgep); 4938 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 4939 break; 4940 4941 case BGE_PP_SPACE_STATUS: 4942 case BGE_PP_SPACE_STATISTICS: 4943 case BGE_PP_SPACE_TXDESC: 4944 case BGE_PP_SPACE_TXBUFF: 4945 case BGE_PP_SPACE_RXDESC: 4946 case BGE_PP_SPACE_RXBUFF: 4947 /* 4948 * Various DMA_AREAs 4949 */ 4950 switch (ppd->pp_acc_space) { 4951 case BGE_PP_SPACE_TXDESC: 4952 areap = &bgep->tx_desc; 4953 break; 4954 case BGE_PP_SPACE_TXBUFF: 4955 areap = &bgep->tx_buff[0]; 4956 break; 4957 case BGE_PP_SPACE_RXDESC: 4958 areap = &bgep->rx_desc[0]; 4959 break; 4960 case BGE_PP_SPACE_RXBUFF: 4961 areap = &bgep->rx_buff[0]; 4962 break; 4963 case BGE_PP_SPACE_STATUS: 4964 areap = &bgep->status_block; 4965 break; 4966 case BGE_PP_SPACE_STATISTICS: 4967 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 4968 areap = &bgep->statistics; 4969 break; 4970 } 4971 4972 sizemask = 8|4|2|1; 4973 mem_va = (uintptr_t)areap->mem_va; 4974 maxoff = areap->alength; 4975 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 4976 break; 4977 } 4978 4979 switch (ppd->pp_acc_size) { 4980 default: 4981 return (IOC_INVAL); 4982 4983 case 8: 4984 case 4: 4985 case 2: 4986 case 1: 4987 if ((ppd->pp_acc_size & sizemask) == 0) 4988 return (IOC_INVAL); 4989 break; 4990 } 4991 4992 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 4993 return (IOC_INVAL); 4994 4995 if (ppd->pp_acc_offset >= maxoff) 4996 return (IOC_INVAL); 4997 4998 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 4999 return (IOC_INVAL); 5000 5001 /* 5002 * All OK - go do it! 5003 */ 5004 ppd->pp_acc_offset += mem_va; 5005 (*ppfn)(bgep, ppd); 5006 return (peek ? IOC_REPLY : IOC_ACK); 5007 } 5008 5009 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5010 struct iocblk *iocp); 5011 #pragma no_inline(bge_diag_ioctl) 5012 5013 static enum ioc_reply 5014 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5015 { 5016 ASSERT(mutex_owned(bgep->genlock)); 5017 5018 switch (cmd) { 5019 default: 5020 /* NOTREACHED */ 5021 bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd); 5022 return (IOC_INVAL); 5023 5024 case BGE_DIAG: 5025 /* 5026 * Currently a no-op 5027 */ 5028 return (IOC_ACK); 5029 5030 case BGE_PEEK: 5031 case BGE_POKE: 5032 return (bge_pp_ioctl(bgep, cmd, mp, iocp)); 5033 5034 case BGE_PHY_RESET: 5035 return (IOC_RESTART_ACK); 5036 5037 case BGE_SOFT_RESET: 5038 case BGE_HARD_RESET: 5039 /* 5040 * Reset and reinitialise the 570x hardware 5041 */ 5042 (void) bge_restart(bgep, cmd == BGE_HARD_RESET); 5043 return (IOC_ACK); 5044 } 5045 5046 /* NOTREACHED */ 5047 } 5048 5049 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5050 5051 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5052 struct iocblk *iocp); 5053 #pragma no_inline(bge_mii_ioctl) 5054 5055 static enum ioc_reply 5056 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5057 { 5058 struct bge_mii_rw *miirwp; 5059 5060 /* 5061 * Validate format of ioctl 5062 */ 5063 if (iocp->ioc_count != sizeof (struct bge_mii_rw)) 5064 return (IOC_INVAL); 5065 if (mp->b_cont == NULL) 5066 return (IOC_INVAL); 5067 miirwp = (struct bge_mii_rw *)mp->b_cont->b_rptr; 5068 5069 /* 5070 * Validate request parameters ... 5071 */ 5072 if (miirwp->mii_reg > MII_MAXREG) 5073 return (IOC_INVAL); 5074 5075 switch (cmd) { 5076 default: 5077 /* NOTREACHED */ 5078 bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd); 5079 return (IOC_INVAL); 5080 5081 case BGE_MII_READ: 5082 miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg); 5083 return (IOC_REPLY); 5084 5085 case BGE_MII_WRITE: 5086 bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data); 5087 return (IOC_ACK); 5088 } 5089 5090 /* NOTREACHED */ 5091 } 5092 5093 #if BGE_SEE_IO32 5094 5095 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5096 struct iocblk *iocp); 5097 #pragma no_inline(bge_see_ioctl) 5098 5099 static enum ioc_reply 5100 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5101 { 5102 struct bge_see_rw *seerwp; 5103 5104 /* 5105 * Validate format of ioctl 5106 */ 5107 if (iocp->ioc_count != sizeof (struct bge_see_rw)) 5108 return (IOC_INVAL); 5109 if (mp->b_cont == NULL) 5110 return (IOC_INVAL); 5111 seerwp = (struct bge_see_rw *)mp->b_cont->b_rptr; 5112 5113 /* 5114 * Validate request parameters ... 5115 */ 5116 if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK) 5117 return (IOC_INVAL); 5118 5119 switch (cmd) { 5120 default: 5121 /* NOTREACHED */ 5122 bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd); 5123 return (IOC_INVAL); 5124 5125 case BGE_SEE_READ: 5126 case BGE_SEE_WRITE: 5127 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5128 seerwp->see_addr, &seerwp->see_data); 5129 return (IOC_REPLY); 5130 } 5131 5132 /* NOTREACHED */ 5133 } 5134 5135 #endif /* BGE_SEE_IO32 */ 5136 5137 #if BGE_FLASH_IO32 5138 5139 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5140 struct iocblk *iocp); 5141 #pragma no_inline(bge_flash_ioctl) 5142 5143 static enum ioc_reply 5144 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5145 { 5146 struct bge_flash_rw *flashrwp; 5147 5148 /* 5149 * Validate format of ioctl 5150 */ 5151 if (iocp->ioc_count != sizeof (struct bge_flash_rw)) 5152 return (IOC_INVAL); 5153 if (mp->b_cont == NULL) 5154 return (IOC_INVAL); 5155 flashrwp = (struct bge_flash_rw *)mp->b_cont->b_rptr; 5156 5157 /* 5158 * Validate request parameters ... 5159 */ 5160 if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK) 5161 return (IOC_INVAL); 5162 5163 switch (cmd) { 5164 default: 5165 /* NOTREACHED */ 5166 bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd); 5167 return (IOC_INVAL); 5168 5169 case BGE_FLASH_READ: 5170 case BGE_FLASH_WRITE: 5171 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5172 flashrwp->flash_addr, &flashrwp->flash_data); 5173 return (IOC_REPLY); 5174 } 5175 5176 /* NOTREACHED */ 5177 } 5178 5179 #endif /* BGE_FLASH_IO32 */ 5180 5181 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 5182 struct iocblk *iocp); 5183 #pragma no_inline(bge_chip_ioctl) 5184 5185 enum ioc_reply 5186 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 5187 { 5188 int cmd; 5189 5190 BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)", 5191 (void *)bgep, (void *)wq, (void *)mp, (void *)iocp)); 5192 5193 ASSERT(mutex_owned(bgep->genlock)); 5194 5195 cmd = iocp->ioc_cmd; 5196 switch (cmd) { 5197 default: 5198 /* NOTREACHED */ 5199 bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd); 5200 return (IOC_INVAL); 5201 5202 case BGE_DIAG: 5203 case BGE_PEEK: 5204 case BGE_POKE: 5205 case BGE_PHY_RESET: 5206 case BGE_SOFT_RESET: 5207 case BGE_HARD_RESET: 5208 #if BGE_DEBUGGING || BGE_DO_PPIO 5209 return (bge_diag_ioctl(bgep, cmd, mp, iocp)); 5210 #else 5211 return (IOC_INVAL); 5212 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5213 5214 case BGE_MII_READ: 5215 case BGE_MII_WRITE: 5216 return (bge_mii_ioctl(bgep, cmd, mp, iocp)); 5217 5218 #if BGE_SEE_IO32 5219 case BGE_SEE_READ: 5220 case BGE_SEE_WRITE: 5221 return (bge_see_ioctl(bgep, cmd, mp, iocp)); 5222 #endif /* BGE_SEE_IO32 */ 5223 5224 #if BGE_FLASH_IO32 5225 case BGE_FLASH_READ: 5226 case BGE_FLASH_WRITE: 5227 return (bge_flash_ioctl(bgep, cmd, mp, iocp)); 5228 #endif /* BGE_FLASH_IO32 */ 5229 } 5230 5231 /* NOTREACHED */ 5232 } 5233 5234 void 5235 bge_chip_blank(void *arg, time_t ticks, uint_t count) 5236 { 5237 bge_t *bgep = arg; 5238 5239 mutex_enter(bgep->genlock); 5240 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks); 5241 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count); 5242 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5243 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 5244 mutex_exit(bgep->genlock); 5245 } 5246 5247 #ifdef BGE_IPMI_ASF 5248 5249 uint32_t 5250 bge_nic_read32(bge_t *bgep, bge_regno_t addr) 5251 { 5252 uint32_t data; 5253 5254 if (!bgep->asf_wordswapped) { 5255 /* a workaround word swap error */ 5256 if (addr & 4) 5257 addr = addr - 4; 5258 else 5259 addr = addr + 4; 5260 } 5261 5262 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 5263 data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR); 5264 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 5265 5266 return (data); 5267 } 5268 5269 5270 void 5271 bge_asf_update_status(bge_t *bgep) 5272 { 5273 uint32_t event; 5274 5275 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE); 5276 bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4); 5277 bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX, 3); 5278 5279 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5280 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5281 } 5282 5283 5284 /* 5285 * The driver is supposed to notify ASF that the OS is still running 5286 * every three seconds, otherwise the management server may attempt 5287 * to reboot the machine. If it hasn't actually failed, this is 5288 * not a desirable result. However, this isn't running as a real-time 5289 * thread, and even if it were, it might not be able to generate the 5290 * heartbeat in a timely manner due to system load. As it isn't a 5291 * significant strain on the machine, we will set the interval to half 5292 * of the required value. 5293 */ 5294 void 5295 bge_asf_heartbeat(void *arg) 5296 { 5297 bge_t *bgep = (bge_t *)arg; 5298 5299 mutex_enter(bgep->genlock); 5300 bge_asf_update_status((bge_t *)bgep); 5301 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5302 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5303 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) 5304 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5305 mutex_exit(bgep->genlock); 5306 ((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep, 5307 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL)); 5308 } 5309 5310 5311 void 5312 bge_asf_stop_timer(bge_t *bgep) 5313 { 5314 timeout_id_t tmp_id = 0; 5315 5316 while ((bgep->asf_timeout_id != 0) && 5317 (tmp_id != bgep->asf_timeout_id)) { 5318 tmp_id = bgep->asf_timeout_id; 5319 (void) untimeout(tmp_id); 5320 } 5321 bgep->asf_timeout_id = 0; 5322 } 5323 5324 5325 5326 /* 5327 * This function should be placed at the earliest position of bge_attach(). 5328 */ 5329 void 5330 bge_asf_get_config(bge_t *bgep) 5331 { 5332 uint32_t nicsig; 5333 uint32_t niccfg; 5334 5335 nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR); 5336 if (nicsig == BGE_NIC_DATA_SIG) { 5337 niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR); 5338 if (niccfg & BGE_NIC_CFG_ENABLE_ASF) 5339 /* 5340 * Here, we don't consider BAXTER, because BGE haven't 5341 * supported BAXTER (that is 5752). Also, as I know, 5342 * BAXTER doesn't support ASF feature. 5343 */ 5344 bgep->asf_enabled = B_TRUE; 5345 else 5346 bgep->asf_enabled = B_FALSE; 5347 } else 5348 bgep->asf_enabled = B_FALSE; 5349 } 5350 5351 5352 void 5353 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode) 5354 { 5355 uint32_t tries; 5356 uint32_t event; 5357 5358 ASSERT(bgep->asf_enabled); 5359 5360 /* Issues "pause firmware" command and wait for ACK */ 5361 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW); 5362 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5363 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5364 5365 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5366 tries = 0; 5367 while ((event & RRER_ASF_EVENT) && (tries < 100)) { 5368 drv_usecwait(1); 5369 tries ++; 5370 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5371 } 5372 5373 bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX, 5374 BGE_MAGIC_NUM_FIRMWARE_INIT_DONE); 5375 5376 if (bgep->asf_newhandshake) { 5377 switch (mode) { 5378 case BGE_INIT_RESET: 5379 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5380 BGE_DRV_STATE_START); 5381 break; 5382 case BGE_SHUTDOWN_RESET: 5383 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5384 BGE_DRV_STATE_UNLOAD); 5385 break; 5386 case BGE_SUSPEND_RESET: 5387 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5388 BGE_DRV_STATE_SUSPEND); 5389 break; 5390 default: 5391 break; 5392 } 5393 } 5394 } 5395 5396 5397 void 5398 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode) 5399 { 5400 switch (mode) { 5401 case BGE_INIT_RESET: 5402 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5403 BGE_DRV_STATE_START); 5404 break; 5405 case BGE_SHUTDOWN_RESET: 5406 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5407 BGE_DRV_STATE_UNLOAD); 5408 break; 5409 case BGE_SUSPEND_RESET: 5410 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5411 BGE_DRV_STATE_SUSPEND); 5412 break; 5413 default: 5414 break; 5415 } 5416 } 5417 5418 5419 void 5420 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode) 5421 { 5422 switch (mode) { 5423 case BGE_INIT_RESET: 5424 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5425 BGE_DRV_STATE_START_DONE); 5426 break; 5427 case BGE_SHUTDOWN_RESET: 5428 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5429 BGE_DRV_STATE_UNLOAD_DONE); 5430 break; 5431 default: 5432 break; 5433 } 5434 } 5435 5436 #endif /* BGE_IPMI_ASF */ 5437