xref: /titanic_41/usr/src/uts/common/io/bge/bge_chip2.c (revision 09cb82ca24006b806e9f17e2135eef96364facfe)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #pragma ident	"%Z%%M%	%I%	%E% SMI"
28 
29 #include "bge_impl.h"
30 
31 #define	PIO_ADDR(bgep, offset)	((void *)((caddr_t)(bgep)->io_regs+(offset)))
32 
33 /*
34  * Future features ... ?
35  */
36 #define	BGE_CFG_IO8	1	/* 8/16-bit cfg space BIS/BIC	*/
37 #define	BGE_IND_IO32	1	/* indirect access code		*/
38 #define	BGE_SEE_IO32	1	/* SEEPROM access code		*/
39 #define	BGE_FLASH_IO32	1	/* FLASH access code		*/
40 
41 /*
42  * BGE MSI tunable:
43  *
44  * By default MSI is enabled on all supported platforms but it is disabled
45  * for some Broadcom chips due to known MSI hardware issues. Currently MSI
46  * is enabled only for 5714C A2 and 5715C A2 broadcom chips.
47  */
48 #if defined(__sparc)
49 boolean_t bge_enable_msi = B_TRUE;
50 #else
51 boolean_t bge_enable_msi = B_FALSE;
52 #endif
53 
54 /*
55  * PCI-X/PCI-E relaxed ordering tunable for OS/Nexus driver
56  */
57 boolean_t bge_relaxed_ordering = B_TRUE;
58 
59 /*
60  * Property names
61  */
62 static char knownids_propname[] = "bge-known-subsystems";
63 
64 /*
65  * Patchable globals:
66  *
67  *	bge_autorecover
68  *		Enables/disables automatic recovery after fault detection
69  *
70  *	bge_mlcr_default
71  *		Value to program into the MLCR; controls the chip's GPIO pins
72  *
73  *	bge_dma_{rd,wr}prio
74  *		Relative priorities of DMA reads & DMA writes respectively.
75  *		These may each be patched to any value 0-3.  Equal values
76  *		will give "fair" (round-robin) arbitration for PCI access.
77  *		Unequal values will give one or the other function priority.
78  *
79  *	bge_dma_rwctrl
80  *		Value to put in the Read/Write DMA control register.  See
81  *	        the Broadcom PRM for things you can fiddle with in this
82  *		register ...
83  *
84  *	bge_{tx,rx}_{count,ticks}_{norm,intr}
85  *		Send/receive interrupt coalescing parameters.  Counts are
86  *		#s of descriptors, ticks are in microseconds.  *norm* values
87  *		apply between status updates/interrupts; the *intr* values
88  *		refer to the 'during-interrupt' versions - see the PRM.
89  *
90  *		NOTE: these values have been determined by measurement. They
91  *		differ significantly from the values recommended in the PRM.
92  */
93 static uint32_t bge_autorecover = 1;
94 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714;
95 
96 static uint32_t bge_dma_rdprio = 1;
97 static uint32_t bge_dma_wrprio = 0;
98 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT;
99 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721;
100 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714;
101 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715;
102 
103 uint32_t bge_rx_ticks_norm = 128;
104 uint32_t bge_tx_ticks_norm = 2048;		/* 8 for FJ2+ !?!?	*/
105 uint32_t bge_rx_count_norm = 8;
106 uint32_t bge_tx_count_norm = 128;
107 
108 static uint32_t bge_rx_ticks_intr = 128;
109 static uint32_t bge_tx_ticks_intr = 0;		/* 8 for FJ2+ !?!?	*/
110 static uint32_t bge_rx_count_intr = 2;
111 static uint32_t bge_tx_count_intr = 0;
112 
113 /*
114  * Memory pool configuration parameters.
115  *
116  * These are generally specific to each member of the chip family, since
117  * each one may have a different memory size/configuration.
118  *
119  * Setting the mbuf pool length for a specific type of chip to 0 inhibits
120  * the driver from programming the various registers; instead they are left
121  * at their hardware defaults.  This is the preferred option for later chips
122  * (5705+), whereas the older chips *required* these registers to be set,
123  * since the h/w default was 0 ;-(
124  */
125 static uint32_t bge_mbuf_pool_base	= MBUF_POOL_BASE_DEFAULT;
126 static uint32_t bge_mbuf_pool_base_5704	= MBUF_POOL_BASE_5704;
127 static uint32_t bge_mbuf_pool_base_5705	= MBUF_POOL_BASE_5705;
128 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721;
129 static uint32_t bge_mbuf_pool_len	= MBUF_POOL_LENGTH_DEFAULT;
130 static uint32_t bge_mbuf_pool_len_5704	= MBUF_POOL_LENGTH_5704;
131 static uint32_t bge_mbuf_pool_len_5705	= 0;	/* use h/w default	*/
132 static uint32_t bge_mbuf_pool_len_5721	= 0;
133 
134 /*
135  * Various high and low water marks, thresholds, etc ...
136  *
137  * Note: these are taken from revision 7 of the PRM, and some are different
138  * from both the values in earlier PRMs *and* those determined experimentally
139  * and used in earlier versions of this driver ...
140  */
141 static uint32_t bge_mbuf_hi_water	= MBUF_HIWAT_DEFAULT;
142 static uint32_t bge_mbuf_lo_water_rmac	= MAC_RX_MBUF_LOWAT_DEFAULT;
143 static uint32_t bge_mbuf_lo_water_rdma	= RDMA_MBUF_LOWAT_DEFAULT;
144 
145 static uint32_t bge_dmad_lo_water	= DMAD_POOL_LOWAT_DEFAULT;
146 static uint32_t bge_dmad_hi_water	= DMAD_POOL_HIWAT_DEFAULT;
147 static uint32_t bge_lowat_recv_frames	= LOWAT_MAX_RECV_FRAMES_DEFAULT;
148 
149 static uint32_t bge_replenish_std	= STD_RCV_BD_REPLENISH_DEFAULT;
150 static uint32_t bge_replenish_mini	= MINI_RCV_BD_REPLENISH_DEFAULT;
151 static uint32_t bge_replenish_jumbo	= JUMBO_RCV_BD_REPLENISH_DEFAULT;
152 
153 static uint32_t	bge_watchdog_count	= 1 << 16;
154 static uint16_t bge_dma_miss_limit	= 20;
155 
156 static uint32_t bge_stop_start_on_sync	= 0;
157 
158 boolean_t bge_jumbo_enable		= B_TRUE;
159 
160 /*
161  * bge_intr_max_loop controls the maximum loop number within bge_intr.
162  * When loading NIC with heavy network traffic, it is useful.
163  * Increasing this value could have positive effect to throughput,
164  * but it might also increase ticks of a bge ISR stick on CPU, which might
165  * lead to bad UI interactive experience. So tune this with caution.
166  */
167 static int bge_intr_max_loop = 1;
168 
169 /*
170  * ========== Low-level chip & ring buffer manipulation ==========
171  */
172 
173 #define	BGE_DBG		BGE_DBG_REGS	/* debug flag for this code	*/
174 
175 
176 /*
177  * Config space read-modify-write routines
178  */
179 
180 #if	BGE_CFG_IO8
181 
182 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits);
183 #pragma	inline(bge_cfg_clr16)
184 
185 static void
186 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits)
187 {
188 	uint16_t regval;
189 
190 	BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)",
191 	    (void *)bgep, regno, bits));
192 
193 	regval = pci_config_get16(bgep->cfg_handle, regno);
194 
195 	BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x",
196 	    (void *)bgep, regno, bits, regval, regval & ~bits));
197 
198 	regval &= ~bits;
199 	pci_config_put16(bgep->cfg_handle, regno, regval);
200 }
201 
202 #endif	/* BGE_CFG_IO8 */
203 
204 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
205 #pragma	inline(bge_cfg_clr32)
206 
207 static void
208 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits)
209 {
210 	uint32_t regval;
211 
212 	BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)",
213 	    (void *)bgep, regno, bits));
214 
215 	regval = pci_config_get32(bgep->cfg_handle, regno);
216 
217 	BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x",
218 	    (void *)bgep, regno, bits, regval, regval & ~bits));
219 
220 	regval &= ~bits;
221 	pci_config_put32(bgep->cfg_handle, regno, regval);
222 }
223 
224 #if	BGE_IND_IO32
225 
226 /*
227  * Indirect access to registers & RISC scratchpads, using config space
228  * accesses only.
229  *
230  * This isn't currently used, but someday we might want to use it for
231  * restoring the Subsystem Device/Vendor registers (which aren't directly
232  * writable in Config Space), or for downloading firmware into the RISCs
233  *
234  * In any case there are endian issues to be resolved before this code is
235  * enabled; the bizarre way that bytes get twisted by this chip AND by
236  * the PCI bridge in SPARC systems mean that we shouldn't enable it until
237  * it's been thoroughly tested for all access sizes on all supported
238  * architectures (SPARC *and* x86!).
239  */
240 uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno);
241 #pragma	inline(bge_ind_get32)
242 
243 uint32_t
244 bge_ind_get32(bge_t *bgep, bge_regno_t regno)
245 {
246 	uint32_t val;
247 
248 	BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno));
249 
250 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno);
251 	val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR);
252 
253 	BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x",
254 	    (void *)bgep, regno, val));
255 
256 	val = LE_32(val);
257 
258 	return (val);
259 }
260 
261 void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val);
262 #pragma	inline(bge_ind_put32)
263 
264 void
265 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val)
266 {
267 	BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)",
268 	    (void *)bgep, regno, val));
269 
270 	val = LE_32(val);
271 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno);
272 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val);
273 }
274 
275 #endif	/* BGE_IND_IO32 */
276 
277 #if	BGE_DEBUGGING
278 
279 static void bge_pci_check(bge_t *bgep);
280 #pragma	no_inline(bge_pci_check)
281 
282 static void
283 bge_pci_check(bge_t *bgep)
284 {
285 	uint16_t pcistatus;
286 
287 	pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT);
288 	if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0)
289 		BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x",
290 		    (void *)bgep, pcistatus));
291 }
292 
293 #endif	/* BGE_DEBUGGING */
294 
295 /*
296  * Perform first-stage chip (re-)initialisation, using only config-space
297  * accesses:
298  *
299  * + Read the vendor/device/revision/subsystem/cache-line-size registers,
300  *   returning the data in the structure pointed to by <idp>.
301  * + Configure the target-mode endianness (swap) options.
302  * + Disable interrupts and enable Memory Space accesses.
303  * + Enable or disable Bus Mastering according to the <enable_dma> flag.
304  *
305  * This sequence is adapted from Broadcom document 570X-PG102-R,
306  * page 102, steps 1-3, 6-8 and 11-13.  The omitted parts of the sequence
307  * are 4 and 5 (Reset Core and wait) which are handled elsewhere.
308  *
309  * This function MUST be called before any non-config-space accesses
310  * are made; on this first call <enable_dma> is B_FALSE, and it
311  * effectively performs steps 3-1(!) of the initialisation sequence
312  * (the rest are not required but should be harmless).
313  *
314  * It MUST also be called after a chip reset, as this disables
315  * Memory Space cycles!  In this case, <enable_dma> is B_TRUE, and
316  * it is effectively performing steps 6-8.
317  */
318 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma);
319 #pragma	no_inline(bge_chip_cfg_init)
320 
321 void
322 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma)
323 {
324 	ddi_acc_handle_t handle;
325 	uint16_t command;
326 	uint32_t mhcr;
327 	uint16_t value16;
328 	int i;
329 
330 	BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)",
331 	    (void *)bgep, (void *)cidp, enable_dma));
332 
333 	/*
334 	 * Step 3: save PCI cache line size and subsystem vendor ID
335 	 *
336 	 * Read all the config-space registers that characterise the
337 	 * chip, specifically vendor/device/revision/subsystem vendor
338 	 * and subsystem device id.  We expect (but don't check) that
339 	 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704)
340 	 *
341 	 * Also save all bus-transaction related registers (cache-line
342 	 * size, bus-grant/latency parameters, etc).  Some of these are
343 	 * cleared by reset, so we'll have to restore them later.  This
344 	 * comes from the Broadcom document 570X-PG102-R ...
345 	 *
346 	 * Note: Broadcom document 570X-PG102-R seems to be in error
347 	 * here w.r.t. the offsets of the Subsystem Vendor ID and
348 	 * Subsystem (Device) ID registers, which are the opposite way
349 	 * round according to the PCI standard.  For good measure, we
350 	 * save/restore both anyway.
351 	 */
352 	handle = bgep->cfg_handle;
353 
354 	mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR);
355 	cidp->asic_rev = mhcr & MHCR_CHIP_REV_MASK;
356 	cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE);
357 	cidp->command = pci_config_get16(handle, PCI_CONF_COMM);
358 
359 	cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID);
360 	cidp->device = pci_config_get16(handle, PCI_CONF_DEVID);
361 	cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID);
362 	cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID);
363 	cidp->revision = pci_config_get8(handle, PCI_CONF_REVID);
364 	cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ);
365 	cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER);
366 
367 	BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s",
368 	    cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X",
369 	    cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow",
370 	    cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide",
371 	    cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low"));
372 	BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x",
373 	    cidp->vendor, cidp->device, cidp->revision));
374 	BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x",
375 	    cidp->subven, cidp->subdev, cidp->asic_rev));
376 	BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x",
377 	    cidp->clsize, cidp->latency, cidp->command));
378 
379 	/*
380 	 * Step 2 (also step 6): disable and clear interrupts.
381 	 * Steps 11-13: configure PIO endianness options, and enable
382 	 * indirect register access.  We'll also select any other
383 	 * options controlled by the MHCR (e.g. tagged status, mask
384 	 * interrupt mode) at this stage ...
385 	 *
386 	 * Note: internally, the chip is 64-bit and BIG-endian, but
387 	 * since it talks to the host over a (LITTLE-endian) PCI bus,
388 	 * it normally swaps bytes around at the PCI interface.
389 	 * However, the PCI host bridge on SPARC systems normally
390 	 * swaps the byte lanes around too, since SPARCs are also
391 	 * BIG-endian.  So it turns out that on SPARC, the right
392 	 * option is to tell the chip to swap (and the host bridge
393 	 * will swap back again), whereas on x86 we ask the chip
394 	 * NOT to swap, so the natural little-endianness of the
395 	 * PCI bus is assumed.  Then the only thing that doesn't
396 	 * automatically work right is access to an 8-byte register
397 	 * by a little-endian host; but we don't want to set the
398 	 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte
399 	 * accesses don't go where expected ;-(  So we live with
400 	 * that, and perform word-swaps in software in the few cases
401 	 * where a chip register is defined as an 8-byte value --
402 	 * see the code below for details ...
403 	 *
404 	 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't
405 	 * very clear in the register description in the PRM, but
406 	 * Broadcom document 570X-PG104-R page 248 explains a little
407 	 * more (under "Broadcom Mask Mode").  The bit changes the way
408 	 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE
409 	 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same
410 	 * way as the 5700 did, which isn't very convenient.  Setting
411 	 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT
412 	 * bit do just what its name says -- MASK the PCI #INTA output
413 	 * (i.e. deassert the signal at the pin) leaving all internal
414 	 * state unchanged.  This is much more convenient for our
415 	 * interrupt handler, so we set MASK_INTERRUPT_MODE here.
416 	 *
417 	 * Note: the inconvenient semantics of the interrupt mailbox
418 	 * (nonzero disables and acknowledges/clears the interrupt,
419 	 * zero enables AND CLEARS it) would make race conditions
420 	 * likely in the interrupt handler:
421 	 *
422 	 * (1)	acknowledge & disable interrupts
423 	 * (2)	while (more to do)
424 	 * 		process packets
425 	 * (3)	enable interrupts -- also clears pending
426 	 *
427 	 * If the chip received more packets and internally generated
428 	 * an interrupt between the check at (2) and the mbox write
429 	 * at (3), this interrupt would be lost :-(
430 	 *
431 	 * The best way to avoid this is to use TAGGED STATUS mode,
432 	 * where the chip includes a unique tag in each status block
433 	 * update, and the host, when re-enabling interrupts, passes
434 	 * the last tag it saw back to the chip; then the chip can
435 	 * see whether the host is truly up to date, and regenerate
436 	 * its interrupt if not.
437 	 */
438 	mhcr =	MHCR_ENABLE_INDIRECT_ACCESS |
439 	    MHCR_ENABLE_TAGGED_STATUS_MODE |
440 	    MHCR_MASK_INTERRUPT_MODE |
441 	    MHCR_CLEAR_INTERRUPT_INTA;
442 
443 	if (bgep->intr_type == DDI_INTR_TYPE_FIXED)
444 		mhcr |= MHCR_MASK_PCI_INT_OUTPUT;
445 
446 #ifdef	_BIG_ENDIAN
447 	mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP;
448 #endif	/* _BIG_ENDIAN */
449 
450 	pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr);
451 
452 #ifdef BGE_IPMI_ASF
453 	bgep->asf_wordswapped = B_FALSE;
454 #endif
455 	/*
456 	 * Step 1 (also step 7): Enable PCI Memory Space accesses
457 	 *			 Disable Memory Write/Invalidate
458 	 *			 Enable or disable Bus Mastering
459 	 *
460 	 * Note that all other bits are taken from the original value saved
461 	 * the first time through here, rather than from the current register
462 	 * value, 'cos that will have been cleared by a soft RESET since.
463 	 * In this way we preserve the OBP/nexus-parent's preferred settings
464 	 * of the parity-error and system-error enable bits across multiple
465 	 * chip RESETs.
466 	 */
467 	command = bgep->chipid.command | PCI_COMM_MAE;
468 	command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL);
469 	if (enable_dma)
470 		command |= PCI_COMM_ME;
471 	/*
472 	 * on BCM5714 revision A0, false parity error gets generated
473 	 * due to a logic bug. Provide a workaround by disabling parity
474 	 * error.
475 	 */
476 	if (((cidp->device == DEVICE_ID_5714C) ||
477 	    (cidp->device == DEVICE_ID_5714S)) &&
478 	    (cidp->revision == REVISION_ID_5714_A0)) {
479 		command &= ~PCI_COMM_PARITY_DETECT;
480 	}
481 	pci_config_put16(handle, PCI_CONF_COMM, command);
482 
483 	/*
484 	 * On some PCI-E device, there were instances when
485 	 * the device was still link training.
486 	 */
487 	if (bgep->chipid.pci_type == BGE_PCI_E) {
488 		i = 0;
489 		value16 = pci_config_get16(handle, PCI_CONF_COMM);
490 		while ((value16 != command) && (i < 100)) {
491 			drv_usecwait(200);
492 			value16 = pci_config_get16(handle, PCI_CONF_COMM);
493 			++i;
494 		}
495 	}
496 
497 	/*
498 	 * Clear any remaining error status bits
499 	 */
500 	pci_config_put16(handle, PCI_CONF_STAT, ~0);
501 
502 	/*
503 	 * Do following if and only if the device is NOT BCM5714C OR
504 	 * BCM5715C
505 	 */
506 	if (!((cidp->device == DEVICE_ID_5714C) ||
507 	    (cidp->device == DEVICE_ID_5715C))) {
508 		/*
509 		 * Make sure these indirect-access registers are sane
510 		 * rather than random after power-up or reset
511 		 */
512 		pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0);
513 		pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0);
514 	}
515 	/*
516 	 * Step 8: Disable PCI-X/PCI-E Relaxed Ordering
517 	 */
518 	bge_cfg_clr16(bgep, PCIX_CONF_COMM, PCIX_COMM_RELAXED);
519 
520 	if (cidp->pci_type == BGE_PCI_E)
521 		bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL,
522 		    DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED);
523 }
524 
525 #ifdef __amd64
526 /*
527  * Distinguish CPU types
528  *
529  * These use to  distinguish AMD64 or Intel EM64T of CPU running mode.
530  * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine
531  * for PCI-Express based network interface card. This is the work-around
532  * for those nics.
533  */
534 static boolean_t bge_get_em64t_type(void);
535 #pragma	inline(bge_get_em64t_type)
536 
537 static boolean_t
538 bge_get_em64t_type(void)
539 {
540 
541 	return (x86_vendor == X86_VENDOR_Intel);
542 }
543 #endif
544 
545 /*
546  * Operating register get/set access routines
547  */
548 
549 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno);
550 #pragma	inline(bge_reg_get32)
551 
552 uint32_t
553 bge_reg_get32(bge_t *bgep, bge_regno_t regno)
554 {
555 	BGE_TRACE(("bge_reg_get32($%p, 0x%lx)",
556 	    (void *)bgep, regno));
557 
558 	return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)));
559 }
560 
561 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data);
562 #pragma	inline(bge_reg_put32)
563 
564 void
565 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data)
566 {
567 	BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)",
568 	    (void *)bgep, regno, data));
569 
570 	ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data);
571 	BGE_PCICHK(bgep);
572 }
573 
574 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
575 #pragma	inline(bge_reg_set32)
576 
577 void
578 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits)
579 {
580 	uint32_t regval;
581 
582 	BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)",
583 	    (void *)bgep, regno, bits));
584 
585 	regval = bge_reg_get32(bgep, regno);
586 	regval |= bits;
587 	bge_reg_put32(bgep, regno, regval);
588 }
589 
590 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
591 #pragma	inline(bge_reg_clr32)
592 
593 void
594 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits)
595 {
596 	uint32_t regval;
597 
598 	BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)",
599 	    (void *)bgep, regno, bits));
600 
601 	regval = bge_reg_get32(bgep, regno);
602 	regval &= ~bits;
603 	bge_reg_put32(bgep, regno, regval);
604 }
605 
606 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno);
607 #pragma	inline(bge_reg_get64)
608 
609 static uint64_t
610 bge_reg_get64(bge_t *bgep, bge_regno_t regno)
611 {
612 	uint64_t regval;
613 
614 #ifdef	__amd64
615 	if (bge_get_em64t_type()) {
616 		regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4));
617 		regval <<= 32;
618 		regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno));
619 	} else {
620 		regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno));
621 	}
622 #else
623 	regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno));
624 #endif
625 
626 #ifdef	_LITTLE_ENDIAN
627 	regval = (regval >> 32) | (regval << 32);
628 #endif	/* _LITTLE_ENDIAN */
629 
630 	BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx",
631 	    (void *)bgep, regno, regval));
632 
633 	return (regval);
634 }
635 
636 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data);
637 #pragma	inline(bge_reg_put64)
638 
639 static void
640 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data)
641 {
642 	BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)",
643 	    (void *)bgep, regno, data));
644 
645 #ifdef	_LITTLE_ENDIAN
646 	data = ((data >> 32) | (data << 32));
647 #endif	/* _LITTLE_ENDIAN */
648 
649 #ifdef	__amd64
650 	if (bge_get_em64t_type()) {
651 		ddi_put32(bgep->io_handle,
652 		    PIO_ADDR(bgep, regno), (uint32_t)data);
653 		BGE_PCICHK(bgep);
654 		ddi_put32(bgep->io_handle,
655 		    PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32));
656 
657 	} else {
658 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data);
659 	}
660 #else
661 	ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data);
662 #endif
663 
664 	BGE_PCICHK(bgep);
665 }
666 
667 /*
668  * The DDI doesn't provide get/put functions for 128 bit data
669  * so we put RCBs out as two 64-bit chunks instead.
670  */
671 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp);
672 #pragma	inline(bge_reg_putrcb)
673 
674 static void
675 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp)
676 {
677 	uint64_t *p;
678 
679 	BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)",
680 	    (void *)bgep, addr, rcbp->host_ring_addr,
681 	    rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr));
682 
683 	ASSERT((addr % sizeof (*rcbp)) == 0);
684 
685 	p = (void *)rcbp;
686 	bge_reg_put64(bgep, addr, *p++);
687 	bge_reg_put64(bgep, addr+8, *p);
688 }
689 
690 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data);
691 #pragma	inline(bge_mbx_put)
692 
693 void
694 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data)
695 {
696 	BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)",
697 	    (void *)bgep, regno, data));
698 
699 	/*
700 	 * Mailbox registers are nominally 64 bits on the 5701, but
701 	 * the MSW isn't used.  On the 5703, they're only 32 bits
702 	 * anyway.  So here we just write the lower(!) 32 bits -
703 	 * remembering that the chip is big-endian, even though the
704 	 * PCI bus is little-endian ...
705 	 */
706 #ifdef	_BIG_ENDIAN
707 	ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data);
708 #else
709 	ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data);
710 #endif	/* _BIG_ENDIAN */
711 	BGE_PCICHK(bgep);
712 }
713 
714 uint32_t bge_mbx_get(bge_t *bgep, bge_regno_t regno);
715 #pragma inline(bge_mbx_get)
716 
717 uint32_t
718 bge_mbx_get(bge_t *bgep, bge_regno_t regno)
719 {
720 	uint32_t val32;
721 
722 	BGE_TRACE(("bge_mbx_get($%p, 0x%lx)",
723 	    (void *)bgep, regno));
724 
725 #ifdef	_BIG_ENDIAN
726 	val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno+4));
727 #else
728 	val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno));
729 #endif	/* _BIG_ENDIAN */
730 	BGE_PCICHK(bgep);
731 
732 	return (val32);
733 }
734 
735 
736 #if	BGE_DEBUGGING
737 
738 void bge_led_mark(bge_t *bgep);
739 #pragma	no_inline(bge_led_mark)
740 
741 void
742 bge_led_mark(bge_t *bgep)
743 {
744 	uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK |
745 	    LED_CONTROL_1000MBPS_LED |
746 	    LED_CONTROL_100MBPS_LED |
747 	    LED_CONTROL_10MBPS_LED;
748 
749 	/*
750 	 * Blink all three LINK LEDs on simultaneously, then all off,
751 	 * then restore to automatic hardware control.  This is used
752 	 * in laboratory testing to trigger a logic analyser or scope.
753 	 */
754 	bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl);
755 	led_ctrl ^= LED_CONTROL_OVERRIDE_LINK;
756 	bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl);
757 	led_ctrl = LED_CONTROL_OVERRIDE_LINK;
758 	bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl);
759 }
760 
761 #endif	/* BGE_DEBUGGING */
762 
763 /*
764  * NIC on-chip memory access routines
765  *
766  * Only 32K of NIC memory is visible at a time, controlled by the
767  * Memory Window Base Address Register (in PCI config space).  Once
768  * this is set, the 32K region of NIC-local memory that it refers
769  * to can be directly addressed in the upper 32K of the 64K of PCI
770  * memory space used for the device.
771  */
772 
773 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base);
774 #pragma	inline(bge_nic_setwin)
775 
776 static void
777 bge_nic_setwin(bge_t *bgep, bge_regno_t base)
778 {
779 	chip_id_t *cidp;
780 
781 	BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)",
782 	    (void *)bgep, base));
783 
784 	ASSERT((base & MWBAR_GRANULE_MASK) == 0);
785 
786 	/*
787 	 * Don't do repeated zero data writes,
788 	 * if the device is BCM5714C/15C.
789 	 */
790 	cidp = &bgep->chipid;
791 	if ((cidp->device == DEVICE_ID_5714C) ||
792 	    (cidp->device == DEVICE_ID_5715C)) {
793 		if (bgep->lastWriteZeroData && (base == (bge_regno_t)0))
794 			return;
795 		/* Adjust lastWriteZeroData */
796 		bgep->lastWriteZeroData = ((base == (bge_regno_t)0) ?
797 		    B_TRUE : B_FALSE);
798 	}
799 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base);
800 }
801 
802 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr);
803 #pragma	inline(bge_nic_get32)
804 
805 static uint32_t
806 bge_nic_get32(bge_t *bgep, bge_regno_t addr)
807 {
808 	uint32_t data;
809 
810 #if defined(BGE_IPMI_ASF) && !defined(__sparc)
811 	if (bgep->asf_enabled && !bgep->asf_wordswapped) {
812 		/* workaround for word swap error */
813 		if (addr & 4)
814 			addr = addr - 4;
815 		else
816 			addr = addr + 4;
817 	}
818 #endif
819 
820 #ifdef __sparc
821 	data = bge_nic_read32(bgep, addr);
822 #else
823 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
824 	addr &= MWBAR_GRANULE_MASK;
825 	addr += NIC_MEM_WINDOW_OFFSET;
826 
827 	data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr));
828 #endif
829 
830 	BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x",
831 	    (void *)bgep, addr, data));
832 
833 	return (data);
834 }
835 
836 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data);
837 #pragma inline(bge_nic_put32)
838 
839 void
840 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data)
841 {
842 	BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)",
843 	    (void *)bgep, addr, data));
844 
845 #if defined(BGE_IPMI_ASF) && !defined(__sparc)
846 	if (bgep->asf_enabled && !bgep->asf_wordswapped) {
847 		/* workaround for word swap error */
848 		if (addr & 4)
849 			addr = addr - 4;
850 		else
851 			addr = addr + 4;
852 	}
853 #endif
854 
855 #ifdef __sparc
856 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr);
857 	data = LE_32(data);
858 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR, data);
859 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0);
860 #else
861 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
862 	addr &= MWBAR_GRANULE_MASK;
863 	addr += NIC_MEM_WINDOW_OFFSET;
864 	ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data);
865 	BGE_PCICHK(bgep);
866 #endif
867 }
868 
869 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr);
870 #pragma	inline(bge_nic_get64)
871 
872 static uint64_t
873 bge_nic_get64(bge_t *bgep, bge_regno_t addr)
874 {
875 	uint64_t data;
876 
877 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
878 	addr &= MWBAR_GRANULE_MASK;
879 	addr += NIC_MEM_WINDOW_OFFSET;
880 
881 #ifdef	__amd64
882 		if (bge_get_em64t_type()) {
883 			data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr));
884 			data <<= 32;
885 			data |= ddi_get32(bgep->io_handle,
886 			    PIO_ADDR(bgep, addr + 4));
887 		} else {
888 			data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr));
889 		}
890 #else
891 		data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr));
892 #endif
893 
894 	BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx",
895 	    (void *)bgep, addr, data));
896 
897 	return (data);
898 }
899 
900 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data);
901 #pragma	inline(bge_nic_put64)
902 
903 static void
904 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data)
905 {
906 	BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)",
907 	    (void *)bgep, addr, data));
908 
909 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
910 	addr &= MWBAR_GRANULE_MASK;
911 	addr += NIC_MEM_WINDOW_OFFSET;
912 
913 #ifdef	__amd64
914 	if (bge_get_em64t_type()) {
915 		ddi_put32(bgep->io_handle,
916 		    PIO_ADDR(bgep, addr), (uint32_t)data);
917 		BGE_PCICHK(bgep);
918 		ddi_put32(bgep->io_handle,
919 		    PIO_ADDR(bgep, addr + 4), (uint32_t)(data >> 32));
920 	} else {
921 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data);
922 	}
923 #else
924 	ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data);
925 #endif
926 
927 	BGE_PCICHK(bgep);
928 }
929 
930 /*
931  * The DDI doesn't provide get/put functions for 128 bit data
932  * so we put RCBs out as two 64-bit chunks instead.
933  */
934 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp);
935 #pragma	inline(bge_nic_putrcb)
936 
937 static void
938 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp)
939 {
940 	uint64_t *p;
941 
942 	BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)",
943 	    (void *)bgep, addr, rcbp->host_ring_addr,
944 	    rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr));
945 
946 	ASSERT((addr % sizeof (*rcbp)) == 0);
947 
948 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
949 	addr &= MWBAR_GRANULE_MASK;
950 	addr += NIC_MEM_WINDOW_OFFSET;
951 
952 	p = (void *)rcbp;
953 #ifdef	__amd64
954 	if (bge_get_em64t_type()) {
955 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr),
956 		    (uint32_t)(*p));
957 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4),
958 		    (uint32_t)(*p >> 32));
959 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8),
960 		    (uint32_t)(*(p + 1)));
961 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12),
962 		    (uint32_t)(*p >> 32));
963 
964 	} else {
965 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++);
966 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p);
967 	}
968 #else
969 	ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++);
970 	ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p);
971 #endif
972 
973 	BGE_PCICHK(bgep);
974 }
975 
976 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes);
977 #pragma	inline(bge_nic_zero)
978 
979 static void
980 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes)
981 {
982 	BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)",
983 	    (void *)bgep, addr, nbytes));
984 
985 	ASSERT((addr & ~MWBAR_GRANULE_MASK) ==
986 	    ((addr+nbytes) & ~MWBAR_GRANULE_MASK));
987 
988 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
989 	addr &= MWBAR_GRANULE_MASK;
990 	addr += NIC_MEM_WINDOW_OFFSET;
991 
992 	(void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr),
993 	    nbytes, 1, DDI_DATA_SZ08_ACC);
994 	BGE_PCICHK(bgep);
995 }
996 
997 /*
998  * MII (PHY) register get/set access routines
999  *
1000  * These use the chip's MII auto-access method, controlled by the
1001  * MII Communication register at 0x044c, so the CPU doesn't have
1002  * to fiddle with the individual bits.
1003  */
1004 
1005 #undef	BGE_DBG
1006 #define	BGE_DBG		BGE_DBG_MII	/* debug flag for this code	*/
1007 
1008 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno,
1009 				uint16_t data, uint32_t cmd);
1010 #pragma	no_inline(bge_mii_access)
1011 
1012 static uint16_t
1013 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd)
1014 {
1015 	uint32_t timeout;
1016 	uint32_t regval1;
1017 	uint32_t regval2;
1018 
1019 	BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)",
1020 	    (void *)bgep, regno, data, cmd));
1021 
1022 	ASSERT(mutex_owned(bgep->genlock));
1023 
1024 	/*
1025 	 * Assemble the command ...
1026 	 */
1027 	cmd |= data << MI_COMMS_DATA_SHIFT;
1028 	cmd |= regno << MI_COMMS_REGISTER_SHIFT;
1029 	cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT;
1030 	cmd |= MI_COMMS_START;
1031 
1032 	/*
1033 	 * Wait for any command already in progress ...
1034 	 *
1035 	 * Note: this *shouldn't* ever find that there is a command
1036 	 * in progress, because we already hold the <genlock> mutex.
1037 	 * Nonetheless, we have sometimes seen the MI_COMMS_START
1038 	 * bit set here -- it seems that the chip can initiate MII
1039 	 * accesses internally, even with polling OFF.
1040 	 */
1041 	regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG);
1042 	for (timeout = 100; ; ) {
1043 		if ((regval2 & MI_COMMS_START) == 0) {
1044 			bge_reg_put32(bgep, MI_COMMS_REG, cmd);
1045 			break;
1046 		}
1047 		if (--timeout == 0)
1048 			break;
1049 		drv_usecwait(10);
1050 		regval2 = bge_reg_get32(bgep, MI_COMMS_REG);
1051 	}
1052 
1053 	if (timeout == 0)
1054 		return ((uint16_t)~0u);
1055 
1056 	if (timeout != 100)
1057 		BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- "
1058 		    "MI_COMMS_START set for %d us; 0x%x->0x%x",
1059 		    cmd, 10*(100-timeout), regval1, regval2));
1060 
1061 	regval1 = bge_reg_get32(bgep, MI_COMMS_REG);
1062 	for (timeout = 1000; ; ) {
1063 		if ((regval1 & MI_COMMS_START) == 0)
1064 			break;
1065 		if (--timeout == 0)
1066 			break;
1067 		drv_usecwait(10);
1068 		regval1 = bge_reg_get32(bgep, MI_COMMS_REG);
1069 	}
1070 
1071 	/*
1072 	 * Drop out early if the READ FAILED bit is set -- this chip
1073 	 * could be a 5703/4S, with a SerDes instead of a PHY!
1074 	 */
1075 	if (regval2 & MI_COMMS_READ_FAILED)
1076 		return ((uint16_t)~0u);
1077 
1078 	if (timeout == 0)
1079 		return ((uint16_t)~0u);
1080 
1081 	/*
1082 	 * The PRM says to wait 5us after seeing the START bit clear
1083 	 * and then re-read the register to get the final value of the
1084 	 * data field, in order to avoid a race condition where the
1085 	 * START bit is clear but the data field isn't yet valid.
1086 	 *
1087 	 * Note: we don't actually seem to be encounter this race;
1088 	 * except when the START bit is seen set again (see below),
1089 	 * the data field doesn't change during this 5us interval.
1090 	 */
1091 	drv_usecwait(5);
1092 	regval2 = bge_reg_get32(bgep, MI_COMMS_REG);
1093 
1094 	/*
1095 	 * Unfortunately, when following the PRMs instructions above,
1096 	 * we have occasionally seen the START bit set again(!) in the
1097 	 * value read after the 5us delay. This seems to be due to the
1098 	 * chip autonomously starting another MII access internally.
1099 	 * In such cases, the command/data/etc fields relate to the
1100 	 * internal command, rather than the one that we thought had
1101 	 * just finished.  So in this case, we fall back to returning
1102 	 * the data from the original read that showed START clear.
1103 	 */
1104 	if (regval2 & MI_COMMS_START) {
1105 		BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- "
1106 		    "MI_COMMS_START set after transaction; 0x%x->0x%x",
1107 		    cmd, regval1, regval2));
1108 		regval2 = regval1;
1109 	}
1110 
1111 	if (regval2 & MI_COMMS_START)
1112 		return ((uint16_t)~0u);
1113 
1114 	if (regval2 & MI_COMMS_READ_FAILED)
1115 		return ((uint16_t)~0u);
1116 
1117 	return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT);
1118 }
1119 
1120 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno);
1121 #pragma	no_inline(bge_mii_get16)
1122 
1123 uint16_t
1124 bge_mii_get16(bge_t *bgep, bge_regno_t regno)
1125 {
1126 	BGE_TRACE(("bge_mii_get16($%p, 0x%lx)",
1127 	    (void *)bgep, regno));
1128 
1129 	ASSERT(mutex_owned(bgep->genlock));
1130 
1131 	return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ));
1132 }
1133 
1134 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data);
1135 #pragma	no_inline(bge_mii_put16)
1136 
1137 void
1138 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data)
1139 {
1140 	BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)",
1141 	    (void *)bgep, regno, data));
1142 
1143 	ASSERT(mutex_owned(bgep->genlock));
1144 
1145 	(void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE);
1146 }
1147 
1148 #undef	BGE_DBG
1149 #define	BGE_DBG		BGE_DBG_SEEPROM	/* debug flag for this code	*/
1150 
1151 #if	BGE_SEE_IO32 || BGE_FLASH_IO32
1152 
1153 /*
1154  * Basic SEEPROM get/set access routine
1155  *
1156  * This uses the chip's SEEPROM auto-access method, controlled by the
1157  * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU
1158  * doesn't have to fiddle with the individual bits.
1159  *
1160  * The caller should hold <genlock> and *also* have already acquired
1161  * the right to access the SEEPROM, via bge_nvmem_acquire() above.
1162  *
1163  * Return value:
1164  *	0 on success,
1165  *	ENODATA on access timeout (maybe retryable: device may just be busy)
1166  *	EPROTO on other h/w or s/w errors.
1167  *
1168  * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output
1169  * from a (successful) SEEPROM_ACCESS_READ.
1170  */
1171 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr,
1172 				uint32_t *dp);
1173 #pragma	no_inline(bge_seeprom_access)
1174 
1175 static int
1176 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp)
1177 {
1178 	uint32_t tries;
1179 	uint32_t regval;
1180 
1181 	ASSERT(mutex_owned(bgep->genlock));
1182 
1183 	/*
1184 	 * On the newer chips that support both SEEPROM & Flash, we need
1185 	 * to specifically enable SEEPROM access (Flash is the default).
1186 	 * On older chips, we don't; SEEPROM is the only NVtype supported,
1187 	 * and the NVM control registers don't exist ...
1188 	 */
1189 	switch (bgep->chipid.nvtype) {
1190 	case BGE_NVTYPE_NONE:
1191 	case BGE_NVTYPE_UNKNOWN:
1192 		_NOTE(NOTREACHED)
1193 	case BGE_NVTYPE_SEEPROM:
1194 		break;
1195 
1196 	case BGE_NVTYPE_LEGACY_SEEPROM:
1197 	case BGE_NVTYPE_UNBUFFERED_FLASH:
1198 	case BGE_NVTYPE_BUFFERED_FLASH:
1199 	default:
1200 		bge_reg_set32(bgep, NVM_CONFIG1_REG,
1201 		    NVM_CFG1_LEGACY_SEEPROM_MODE);
1202 		break;
1203 	}
1204 
1205 	/*
1206 	 * Check there's no command in progress.
1207 	 *
1208 	 * Note: this *shouldn't* ever find that there is a command
1209 	 * in progress, because we already hold the <genlock> mutex.
1210 	 * Also, to ensure we don't have a conflict with the chip's
1211 	 * internal firmware or a process accessing the same (shared)
1212 	 * SEEPROM through the other port of a 5704, we've already
1213 	 * been through the "software arbitration" protocol.
1214 	 * So this is just a final consistency check: we shouldn't
1215 	 * see EITHER the START bit (command started but not complete)
1216 	 * OR the COMPLETE bit (command completed but not cleared).
1217 	 */
1218 	regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG);
1219 	if (regval & SEEPROM_ACCESS_START)
1220 		return (EPROTO);
1221 	if (regval & SEEPROM_ACCESS_COMPLETE)
1222 		return (EPROTO);
1223 
1224 	/*
1225 	 * Assemble the command ...
1226 	 */
1227 	cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK;
1228 	addr >>= SEEPROM_ACCESS_ADDRESS_SIZE;
1229 	addr <<= SEEPROM_ACCESS_DEVID_SHIFT;
1230 	cmd |= addr & SEEPROM_ACCESS_DEVID_MASK;
1231 	cmd |= SEEPROM_ACCESS_START;
1232 	cmd |= SEEPROM_ACCESS_COMPLETE;
1233 	cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK;
1234 
1235 	bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp);
1236 	bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd);
1237 
1238 	/*
1239 	 * By observation, a successful access takes ~20us on a 5703/4,
1240 	 * but apparently much longer (up to 1000us) on the obsolescent
1241 	 * BCM5700/BCM5701.  We want to be sure we don't get any false
1242 	 * timeouts here; but OTOH, we don't want a bogus access to lock
1243 	 * out interrupts for longer than necessary. So we'll allow up
1244 	 * to 1000us ...
1245 	 */
1246 	for (tries = 0; tries < 1000; ++tries) {
1247 		regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG);
1248 		if (regval & SEEPROM_ACCESS_COMPLETE)
1249 			break;
1250 		drv_usecwait(1);
1251 	}
1252 
1253 	if (regval & SEEPROM_ACCESS_COMPLETE) {
1254 		/*
1255 		 * All OK; read the SEEPROM data register, then write back
1256 		 * the value read from the address register in order to
1257 		 * clear the <complete> bit and leave the SEEPROM access
1258 		 * state machine idle, ready for the next access ...
1259 		 */
1260 		BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries));
1261 		*dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG);
1262 		bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval);
1263 		return (0);
1264 	}
1265 
1266 	/*
1267 	 * Hmm ... what happened here?
1268 	 *
1269 	 * Most likely, the user addressed a non-existent SEEPROM. Or
1270 	 * maybe the SEEPROM was busy internally (e.g. processing a write)
1271 	 * and didn't respond to being addressed. Either way, it's left
1272 	 * the SEEPROM access state machine wedged. So we'll reset it
1273 	 * before we leave, so it's ready for next time ...
1274 	 */
1275 	BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries));
1276 	bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT);
1277 	return (ENODATA);
1278 }
1279 
1280 /*
1281  * Basic Flash get/set access routine
1282  *
1283  * These use the chip's Flash auto-access method, controlled by the
1284  * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to
1285  * fiddle with the individual bits.
1286  *
1287  * The caller should hold <genlock> and *also* have already acquired
1288  * the right to access the Flash, via bge_nvmem_acquire() above.
1289  *
1290  * Return value:
1291  *	0 on success,
1292  *	ENODATA on access timeout (maybe retryable: device may just be busy)
1293  *	ENODEV if the NVmem device is missing or otherwise unusable
1294  *
1295  * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output
1296  * from a (successful) NVM_FLASH_CMD_RD.
1297  */
1298 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr,
1299 				uint32_t *dp);
1300 #pragma	no_inline(bge_flash_access)
1301 
1302 static int
1303 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp)
1304 {
1305 	uint32_t tries;
1306 	uint32_t regval;
1307 
1308 	ASSERT(mutex_owned(bgep->genlock));
1309 
1310 	/*
1311 	 * On the newer chips that support both SEEPROM & Flash, we need
1312 	 * to specifically disable SEEPROM access while accessing Flash.
1313 	 * The older chips don't support Flash, and the NVM registers don't
1314 	 * exist, so we shouldn't be here at all!
1315 	 */
1316 	switch (bgep->chipid.nvtype) {
1317 	case BGE_NVTYPE_NONE:
1318 	case BGE_NVTYPE_UNKNOWN:
1319 		_NOTE(NOTREACHED)
1320 	case BGE_NVTYPE_SEEPROM:
1321 		return (ENODEV);
1322 
1323 	case BGE_NVTYPE_LEGACY_SEEPROM:
1324 	case BGE_NVTYPE_UNBUFFERED_FLASH:
1325 	case BGE_NVTYPE_BUFFERED_FLASH:
1326 	default:
1327 		bge_reg_clr32(bgep, NVM_CONFIG1_REG,
1328 		    NVM_CFG1_LEGACY_SEEPROM_MODE);
1329 		break;
1330 	}
1331 
1332 	/*
1333 	 * Assemble the command ...
1334 	 */
1335 	addr &= NVM_FLASH_ADDR_MASK;
1336 	cmd |= NVM_FLASH_CMD_DOIT;
1337 	cmd |= NVM_FLASH_CMD_FIRST;
1338 	cmd |= NVM_FLASH_CMD_LAST;
1339 	cmd |= NVM_FLASH_CMD_DONE;
1340 
1341 	bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp);
1342 	bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr);
1343 	bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd);
1344 
1345 	/*
1346 	 * Allow up to 1000ms ...
1347 	 */
1348 	for (tries = 0; tries < 1000; ++tries) {
1349 		regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG);
1350 		if (regval & NVM_FLASH_CMD_DONE)
1351 			break;
1352 		drv_usecwait(1);
1353 	}
1354 
1355 	if (regval & NVM_FLASH_CMD_DONE) {
1356 		/*
1357 		 * All OK; read the data from the Flash read register
1358 		 */
1359 		BGE_DEBUG(("bge_flash_access: complete after %d us", tries));
1360 		*dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG);
1361 		return (0);
1362 	}
1363 
1364 	/*
1365 	 * Hmm ... what happened here?
1366 	 *
1367 	 * Most likely, the user addressed a non-existent Flash. Or
1368 	 * maybe the Flash was busy internally (e.g. processing a write)
1369 	 * and didn't respond to being addressed. Either way, there's
1370 	 * nothing we can here ...
1371 	 */
1372 	BGE_DEBUG(("bge_flash_access: timed out after %d us", tries));
1373 	return (ENODATA);
1374 }
1375 
1376 /*
1377  * The next two functions regulate access to the NVram (if fitted).
1378  *
1379  * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash
1380  * (SPI) interface, but they can be accessed through either port. These
1381  * are managed by different instance of this driver and have no software
1382  * state in common.
1383  *
1384  * In addition (and even on a single core chip) the chip's internal
1385  * firmware can access the SEEPROM/Flash, most notably after a RESET
1386  * when it may download code to run internally.
1387  *
1388  * So we need to arbitrate between these various software agents.  For
1389  * this purpose, the chip provides the Software Arbitration Register,
1390  * which implements hardware(!) arbitration.
1391  *
1392  * This functionality didn't exist on older (5700/5701) chips, so there's
1393  * nothing we can do by way of arbitration on those; also, if there's no
1394  * SEEPROM/Flash fitted (or we couldn't determine what type), there's also
1395  * nothing to do.
1396  *
1397  * The internal firmware appears to use Request 0, which is the highest
1398  * priority.  So we'd like to use Request 2, leaving one higher and one
1399  * lower for any future developments ... but apparently this doesn't
1400  * always work.  So for now, the code uses Request 1 ;-(
1401  */
1402 
1403 #define	NVM_READ_REQ	NVM_READ_REQ1
1404 #define	NVM_RESET_REQ	NVM_RESET_REQ1
1405 #define	NVM_SET_REQ	NVM_SET_REQ1
1406 
1407 static void bge_nvmem_relinquish(bge_t *bgep);
1408 #pragma	no_inline(bge_nvmem_relinquish)
1409 
1410 static void
1411 bge_nvmem_relinquish(bge_t *bgep)
1412 {
1413 	ASSERT(mutex_owned(bgep->genlock));
1414 
1415 	switch (bgep->chipid.nvtype) {
1416 	case BGE_NVTYPE_NONE:
1417 	case BGE_NVTYPE_UNKNOWN:
1418 		_NOTE(NOTREACHED)
1419 		return;
1420 
1421 	case BGE_NVTYPE_SEEPROM:
1422 		/*
1423 		 * No arbitration performed, no release needed
1424 		 */
1425 		return;
1426 
1427 	case BGE_NVTYPE_LEGACY_SEEPROM:
1428 	case BGE_NVTYPE_UNBUFFERED_FLASH:
1429 	case BGE_NVTYPE_BUFFERED_FLASH:
1430 	default:
1431 		break;
1432 	}
1433 
1434 	/*
1435 	 * Our own request should be present (whether or not granted) ...
1436 	 */
1437 	(void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1438 
1439 	/*
1440 	 * ... this will make it go away.
1441 	 */
1442 	bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ);
1443 	(void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1444 }
1445 
1446 /*
1447  * Arbitrate for access to the NVmem, if necessary
1448  *
1449  * Return value:
1450  *	0 on success
1451  *	EAGAIN if the device is in use (retryable)
1452  *	ENODEV if the NVmem device is missing or otherwise unusable
1453  */
1454 static int bge_nvmem_acquire(bge_t *bgep);
1455 #pragma	no_inline(bge_nvmem_acquire)
1456 
1457 static int
1458 bge_nvmem_acquire(bge_t *bgep)
1459 {
1460 	uint32_t regval;
1461 	uint32_t tries;
1462 
1463 	ASSERT(mutex_owned(bgep->genlock));
1464 
1465 	switch (bgep->chipid.nvtype) {
1466 	case BGE_NVTYPE_NONE:
1467 	case BGE_NVTYPE_UNKNOWN:
1468 		/*
1469 		 * Access denied: no (recognisable) device fitted
1470 		 */
1471 		return (ENODEV);
1472 
1473 	case BGE_NVTYPE_SEEPROM:
1474 		/*
1475 		 * Access granted: no arbitration needed (or possible)
1476 		 */
1477 		return (0);
1478 
1479 	case BGE_NVTYPE_LEGACY_SEEPROM:
1480 	case BGE_NVTYPE_UNBUFFERED_FLASH:
1481 	case BGE_NVTYPE_BUFFERED_FLASH:
1482 	default:
1483 		/*
1484 		 * Access conditional: conduct arbitration protocol
1485 		 */
1486 		break;
1487 	}
1488 
1489 	/*
1490 	 * We're holding the per-port mutex <genlock>, so no-one other
1491 	 * thread can be attempting to access the NVmem through *this*
1492 	 * port. But it could be in use by the *other* port (of a 5704),
1493 	 * or by the chip's internal firmware, so we have to go through
1494 	 * the full (hardware) arbitration protocol ...
1495 	 *
1496 	 * Note that *because* we're holding <genlock>, the interrupt handler
1497 	 * won't be able to progress.  So we're only willing to spin for a
1498 	 * fairly short time.  Specifically:
1499 	 *
1500 	 *	We *must* wait long enough for the hardware to resolve all
1501 	 *	requests and determine the winner.  Fortunately, this is
1502 	 *	"almost instantaneous", even as observed by GHz CPUs.
1503 	 *
1504 	 *	A successful access by another Solaris thread (via either
1505 	 *	port) typically takes ~20us.  So waiting a bit longer than
1506 	 *	that will give a good chance of success, if the other user
1507 	 *	*is* another thread on the other port.
1508 	 *
1509 	 *	However, the internal firmware can hold on to the NVmem
1510 	 *	for *much* longer: at least 10 milliseconds just after a
1511 	 *	RESET, and maybe even longer if the NVmem actually contains
1512 	 *	code to download and run on the internal CPUs.
1513 	 *
1514 	 * So, we'll allow 50us; if that's not enough then it's up to the
1515 	 * caller to retry later (hence the choice of return code EAGAIN).
1516 	 */
1517 	regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1518 	bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ);
1519 
1520 	for (tries = 0; tries < 50; ++tries) {
1521 		regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1522 		if (regval & NVM_WON_REQ1)
1523 			break;
1524 		drv_usecwait(1);
1525 	}
1526 
1527 	if (regval & NVM_WON_REQ1) {
1528 		BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries));
1529 		return (0);
1530 	}
1531 
1532 	/*
1533 	 * Somebody else must be accessing the NVmem, so abandon our
1534 	 * attempt take control of it.  The caller can try again later ...
1535 	 */
1536 	BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries));
1537 	bge_nvmem_relinquish(bgep);
1538 	return (EAGAIN);
1539 }
1540 
1541 /*
1542  * This code assumes that the GPIO1 bit has been wired up to the NVmem
1543  * write protect line in such a way that the NVmem is protected when
1544  * GPIO1 is an input, or is an output but driven high.  Thus, to make the
1545  * NVmem writable we have to change GPIO1 to an output AND drive it low.
1546  *
1547  * Note: there's only one set of GPIO pins on a 5704, even though they
1548  * can be accessed through either port.  So the chip has to resolve what
1549  * happens if the two ports program a single pin differently ... the rule
1550  * it uses is that if the ports disagree about the *direction* of a pin,
1551  * "output" wins over "input", but if they disagree about its *value* as
1552  * an output, then the pin is TRISTATED instead!  In such a case, no-one
1553  * wins, and the external signal does whatever the external circuitry
1554  * defines as the default -- which we've assumed is the PROTECTED state.
1555  * So, we always change GPIO1 back to being an *input* whenever we're not
1556  * specifically using it to unprotect the NVmem. This allows either port
1557  * to update the NVmem, although obviously only one at a time!
1558  *
1559  * The caller should hold <genlock> and *also* have already acquired the
1560  * right to access the NVmem, via bge_nvmem_acquire() above.
1561  */
1562 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect);
1563 #pragma	inline(bge_nvmem_protect)
1564 
1565 static void
1566 bge_nvmem_protect(bge_t *bgep, boolean_t protect)
1567 {
1568 	uint32_t regval;
1569 
1570 	ASSERT(mutex_owned(bgep->genlock));
1571 
1572 	regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG);
1573 	if (protect) {
1574 		regval |= MLCR_MISC_PINS_OUTPUT_1;
1575 		regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1;
1576 	} else {
1577 		regval &= ~MLCR_MISC_PINS_OUTPUT_1;
1578 		regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
1579 	}
1580 	bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval);
1581 }
1582 
1583 /*
1584  * Now put it all together ...
1585  *
1586  * Try to acquire control of the NVmem; if successful, then:
1587  *	unprotect it (if we want to write to it)
1588  *	perform the requested access
1589  *	reprotect it (after a write)
1590  *	relinquish control
1591  *
1592  * Return value:
1593  *	0 on success,
1594  *	EAGAIN if the device is in use (retryable)
1595  *	ENODATA on access timeout (maybe retryable: device may just be busy)
1596  *	ENODEV if the NVmem device is missing or otherwise unusable
1597  *	EPROTO on other h/w or s/w errors.
1598  */
1599 static int
1600 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp)
1601 {
1602 	int err;
1603 
1604 	if ((err = bge_nvmem_acquire(bgep)) == 0) {
1605 		switch (cmd) {
1606 		case BGE_SEE_READ:
1607 			err = bge_seeprom_access(bgep,
1608 			    SEEPROM_ACCESS_READ, addr, dp);
1609 			break;
1610 
1611 		case BGE_SEE_WRITE:
1612 			bge_nvmem_protect(bgep, B_FALSE);
1613 			err = bge_seeprom_access(bgep,
1614 			    SEEPROM_ACCESS_WRITE, addr, dp);
1615 			bge_nvmem_protect(bgep, B_TRUE);
1616 			break;
1617 
1618 		case BGE_FLASH_READ:
1619 			if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1620 			    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1621 				bge_reg_set32(bgep, NVM_ACCESS_REG,
1622 				    NVM_ACCESS_ENABLE);
1623 			}
1624 			err = bge_flash_access(bgep,
1625 			    NVM_FLASH_CMD_RD, addr, dp);
1626 			if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1627 			    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1628 				bge_reg_clr32(bgep, NVM_ACCESS_REG,
1629 				    NVM_ACCESS_ENABLE);
1630 			}
1631 			break;
1632 
1633 		case BGE_FLASH_WRITE:
1634 			if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1635 			    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1636 				bge_reg_set32(bgep, NVM_ACCESS_REG,
1637 				    NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE);
1638 			}
1639 			bge_nvmem_protect(bgep, B_FALSE);
1640 			err = bge_flash_access(bgep,
1641 			    NVM_FLASH_CMD_WR, addr, dp);
1642 			bge_nvmem_protect(bgep, B_TRUE);
1643 			if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1644 			    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1645 				bge_reg_clr32(bgep, NVM_ACCESS_REG,
1646 				    NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE);
1647 			}
1648 
1649 			break;
1650 
1651 		default:
1652 			_NOTE(NOTREACHED)
1653 			break;
1654 		}
1655 		bge_nvmem_relinquish(bgep);
1656 	}
1657 
1658 	BGE_DEBUG(("bge_nvmem_rw32: err %d", err));
1659 	return (err);
1660 }
1661 
1662 /*
1663  * Attempt to get a MAC address from the SEEPROM or Flash, if any
1664  */
1665 static uint64_t bge_get_nvmac(bge_t *bgep);
1666 #pragma no_inline(bge_get_nvmac)
1667 
1668 static uint64_t
1669 bge_get_nvmac(bge_t *bgep)
1670 {
1671 	uint32_t mac_high;
1672 	uint32_t mac_low;
1673 	uint32_t addr;
1674 	uint32_t cmd;
1675 	uint64_t mac;
1676 
1677 	BGE_TRACE(("bge_get_nvmac($%p)",
1678 	    (void *)bgep));
1679 
1680 	switch (bgep->chipid.nvtype) {
1681 	case BGE_NVTYPE_NONE:
1682 	case BGE_NVTYPE_UNKNOWN:
1683 	default:
1684 		return (0ULL);
1685 
1686 	case BGE_NVTYPE_SEEPROM:
1687 	case BGE_NVTYPE_LEGACY_SEEPROM:
1688 		cmd = BGE_SEE_READ;
1689 		break;
1690 
1691 	case BGE_NVTYPE_UNBUFFERED_FLASH:
1692 	case BGE_NVTYPE_BUFFERED_FLASH:
1693 		cmd = BGE_FLASH_READ;
1694 		break;
1695 	}
1696 
1697 	addr = NVMEM_DATA_MAC_ADDRESS;
1698 	if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high))
1699 		return (0ULL);
1700 	addr += 4;
1701 	if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low))
1702 		return (0ULL);
1703 
1704 	/*
1705 	 * The Broadcom chip is natively BIG-endian, so that's how the
1706 	 * MAC address is represented in NVmem.  We may need to swap it
1707 	 * around on a little-endian host ...
1708 	 */
1709 #ifdef	_BIG_ENDIAN
1710 	mac = mac_high;
1711 	mac = mac << 32;
1712 	mac |= mac_low;
1713 #else
1714 	mac = BGE_BSWAP_32(mac_high);
1715 	mac = mac << 32;
1716 	mac |= BGE_BSWAP_32(mac_low);
1717 #endif	/* _BIG_ENDIAN */
1718 
1719 	return (mac);
1720 }
1721 
1722 #else	/* BGE_SEE_IO32 || BGE_FLASH_IO32 */
1723 
1724 /*
1725  * Dummy version for when we're not supporting NVmem access
1726  */
1727 static uint64_t bge_get_nvmac(bge_t *bgep);
1728 #pragma inline(bge_get_nvmac)
1729 
1730 static uint64_t
1731 bge_get_nvmac(bge_t *bgep)
1732 {
1733 	_NOTE(ARGUNUSED(bgep))
1734 	return (0ULL);
1735 }
1736 
1737 #endif	/* BGE_SEE_IO32 || BGE_FLASH_IO32 */
1738 
1739 /*
1740  * Determine the type of NVmem that is (or may be) attached to this chip,
1741  */
1742 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep);
1743 #pragma no_inline(bge_nvmem_id)
1744 
1745 static enum bge_nvmem_type
1746 bge_nvmem_id(bge_t *bgep)
1747 {
1748 	enum bge_nvmem_type nvtype;
1749 	uint32_t config1;
1750 
1751 	BGE_TRACE(("bge_nvmem_id($%p)",
1752 	    (void *)bgep));
1753 
1754 	switch (bgep->chipid.device) {
1755 	default:
1756 		/*
1757 		 * We shouldn't get here; it means we don't recognise
1758 		 * the chip, which means we don't know how to determine
1759 		 * what sort of NVmem (if any) it has.  So we'll say
1760 		 * NONE, to disable the NVmem access code ...
1761 		 */
1762 		nvtype = BGE_NVTYPE_NONE;
1763 		break;
1764 
1765 	case DEVICE_ID_5700:
1766 	case DEVICE_ID_5700x:
1767 	case DEVICE_ID_5701:
1768 		/*
1769 		 * These devices support *only* SEEPROMs
1770 		 */
1771 		nvtype = BGE_NVTYPE_SEEPROM;
1772 		break;
1773 
1774 	case DEVICE_ID_5702:
1775 	case DEVICE_ID_5702fe:
1776 	case DEVICE_ID_5703C:
1777 	case DEVICE_ID_5703S:
1778 	case DEVICE_ID_5704C:
1779 	case DEVICE_ID_5704S:
1780 	case DEVICE_ID_5704:
1781 	case DEVICE_ID_5705M:
1782 	case DEVICE_ID_5705C:
1783 	case DEVICE_ID_5705_2:
1784 	case DEVICE_ID_5706:
1785 	case DEVICE_ID_5782:
1786 	case DEVICE_ID_5787:
1787 	case DEVICE_ID_5787M:
1788 	case DEVICE_ID_5788:
1789 	case DEVICE_ID_5789:
1790 	case DEVICE_ID_5751:
1791 	case DEVICE_ID_5751M:
1792 	case DEVICE_ID_5752:
1793 	case DEVICE_ID_5752M:
1794 	case DEVICE_ID_5754:
1795 	case DEVICE_ID_5755:
1796 	case DEVICE_ID_5755M:
1797 	case DEVICE_ID_5721:
1798 	case DEVICE_ID_5714C:
1799 	case DEVICE_ID_5714S:
1800 	case DEVICE_ID_5715C:
1801 	case DEVICE_ID_5715S:
1802 		config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG);
1803 		if (config1 & NVM_CFG1_FLASH_MODE)
1804 			if (config1 & NVM_CFG1_BUFFERED_MODE)
1805 				nvtype = BGE_NVTYPE_BUFFERED_FLASH;
1806 			else
1807 				nvtype = BGE_NVTYPE_UNBUFFERED_FLASH;
1808 		else
1809 			nvtype = BGE_NVTYPE_LEGACY_SEEPROM;
1810 		break;
1811 	}
1812 
1813 	return (nvtype);
1814 }
1815 
1816 #undef	BGE_DBG
1817 #define	BGE_DBG		BGE_DBG_CHIP	/* debug flag for this code	*/
1818 
1819 static void
1820 bge_init_recv_rule(bge_t *bgep)
1821 {
1822 	bge_recv_rule_t *rulep;
1823 	uint32_t i;
1824 
1825 	/*
1826 	 * receive rule: direct all TCP traffic to ring RULE_MATCH_TO_RING
1827 	 * 1. to direct UDP traffic, set:
1828 	 * 	rulep->control = RULE_PROTO_CONTROL;
1829 	 * 	rulep->mask_value = RULE_UDP_MASK_VALUE;
1830 	 * 2. to direct ICMP traffic, set:
1831 	 * 	rulep->control = RULE_PROTO_CONTROL;
1832 	 * 	rulep->mask_value = RULE_ICMP_MASK_VALUE;
1833 	 * 3. to direct traffic by source ip, set:
1834 	 * 	rulep->control = RULE_SIP_CONTROL;
1835 	 * 	rulep->mask_value = RULE_SIP_MASK_VALUE;
1836 	 */
1837 	rulep = bgep->recv_rules;
1838 	rulep->control = RULE_PROTO_CONTROL;
1839 	rulep->mask_value = RULE_TCP_MASK_VALUE;
1840 
1841 	/*
1842 	 * set receive rule registers
1843 	 */
1844 	rulep = bgep->recv_rules;
1845 	for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) {
1846 		bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value);
1847 		bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control);
1848 	}
1849 }
1850 
1851 /*
1852  * Using the values captured by bge_chip_cfg_init(), and additional probes
1853  * as required, characterise the chip fully: determine the label by which
1854  * to refer to this chip, the correct settings for various registers, and
1855  * of course whether the device and/or subsystem are supported!
1856  */
1857 int bge_chip_id_init(bge_t *bgep);
1858 #pragma	no_inline(bge_chip_id_init)
1859 
1860 int
1861 bge_chip_id_init(bge_t *bgep)
1862 {
1863 	char buf[MAXPATHLEN];		/* any risk of stack overflow?	*/
1864 	boolean_t sys_ok;
1865 	boolean_t dev_ok;
1866 	chip_id_t *cidp;
1867 	uint32_t subid;
1868 	char *devname;
1869 	char *sysname;
1870 	int *ids;
1871 	int err;
1872 	uint_t i;
1873 
1874 	sys_ok = dev_ok = B_FALSE;
1875 	cidp = &bgep->chipid;
1876 
1877 	/*
1878 	 * Check the PCI device ID to determine the generic chip type and
1879 	 * select parameters that depend on this.
1880 	 *
1881 	 * Note: because the SPARC platforms in general don't fit the
1882 	 * SEEPROM 'behind' the chip, the PCI revision ID register reads
1883 	 * as zero - which is why we use <asic_rev> rather than <revision>
1884 	 * below ...
1885 	 *
1886 	 * Note: in general we can't distinguish between the Copper/SerDes
1887 	 * versions by ID alone, as some Copper devices (e.g. some but not
1888 	 * all 5703Cs) have the same ID as the SerDes equivalents.  So we
1889 	 * treat them the same here, and the MII code works out the media
1890 	 * type later on ...
1891 	 */
1892 	cidp->mbuf_base = bge_mbuf_pool_base;
1893 	cidp->mbuf_length = bge_mbuf_pool_len;
1894 	cidp->recv_slots = BGE_RECV_SLOTS_USED;
1895 	cidp->bge_dma_rwctrl = bge_dma_rwctrl;
1896 	cidp->pci_type = BGE_PCI_X;
1897 	cidp->statistic_type = BGE_STAT_BLK;
1898 	cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma;
1899 	cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac;
1900 	cidp->mbuf_hi_water = bge_mbuf_hi_water;
1901 	cidp->rx_ticks_norm = bge_rx_ticks_norm;
1902 	cidp->rx_count_norm = bge_rx_count_norm;
1903 
1904 	if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX)
1905 		cidp->rx_rings = BGE_RECV_RINGS_DEFAULT;
1906 	if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX)
1907 		cidp->tx_rings = BGE_SEND_RINGS_DEFAULT;
1908 
1909 	cidp->msi_enabled = B_FALSE;
1910 
1911 	switch (cidp->device) {
1912 	case DEVICE_ID_5700:
1913 	case DEVICE_ID_5700x:
1914 		cidp->chip_label = 5700;
1915 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
1916 		break;
1917 
1918 	case DEVICE_ID_5701:
1919 		cidp->chip_label = 5701;
1920 		dev_ok = B_TRUE;
1921 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
1922 		break;
1923 
1924 	case DEVICE_ID_5702:
1925 	case DEVICE_ID_5702fe:
1926 		cidp->chip_label = 5702;
1927 		dev_ok = B_TRUE;
1928 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
1929 		cidp->pci_type = BGE_PCI;
1930 		break;
1931 
1932 	case DEVICE_ID_5703C:
1933 	case DEVICE_ID_5703S:
1934 	case DEVICE_ID_5703:
1935 		/*
1936 		 * Revision A0 of the 5703/5793 had various errata
1937 		 * that we can't or don't work around, so it's not
1938 		 * supported, but all later versions are
1939 		 */
1940 		cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703;
1941 		if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0)
1942 			dev_ok = B_TRUE;
1943 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
1944 		break;
1945 
1946 	case DEVICE_ID_5704C:
1947 	case DEVICE_ID_5704S:
1948 	case DEVICE_ID_5704:
1949 		cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704;
1950 		cidp->mbuf_base = bge_mbuf_pool_base_5704;
1951 		cidp->mbuf_length = bge_mbuf_pool_len_5704;
1952 		dev_ok = B_TRUE;
1953 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
1954 		break;
1955 
1956 	case DEVICE_ID_5705C:
1957 	case DEVICE_ID_5705M:
1958 	case DEVICE_ID_5705MA3:
1959 	case DEVICE_ID_5705F:
1960 	case DEVICE_ID_5705_2:
1961 	case DEVICE_ID_5754:
1962 		if (cidp->device == DEVICE_ID_5754) {
1963 			cidp->chip_label = 5754;
1964 			cidp->pci_type = BGE_PCI_E;
1965 		} else {
1966 			cidp->chip_label = 5705;
1967 			cidp->pci_type = BGE_PCI;
1968 		}
1969 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
1970 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
1971 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
1972 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
1973 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
1974 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
1975 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
1976 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
1977 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
1978 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
1979 		cidp->statistic_type = BGE_STAT_REG;
1980 		dev_ok = B_TRUE;
1981 		break;
1982 
1983 	case DEVICE_ID_5753:
1984 		cidp->chip_label = 5753;
1985 		cidp->pci_type = BGE_PCI_E;
1986 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
1987 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
1988 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
1989 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
1990 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
1991 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
1992 		cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
1993 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
1994 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
1995 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
1996 		cidp->statistic_type = BGE_STAT_REG;
1997 		dev_ok = B_TRUE;
1998 		break;
1999 
2000 	case DEVICE_ID_5755:
2001 	case DEVICE_ID_5755M:
2002 		cidp->chip_label = 5755;
2003 		cidp->pci_type = BGE_PCI_E;
2004 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2005 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2006 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2007 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2008 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2009 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2010 		cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2011 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2012 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2013 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2014 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2015 		cidp->statistic_type = BGE_STAT_REG;
2016 		dev_ok = B_TRUE;
2017 		break;
2018 
2019 	case DEVICE_ID_5787:
2020 	case DEVICE_ID_5787M:
2021 		cidp->chip_label = 5787;
2022 		cidp->pci_type = BGE_PCI_E;
2023 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2024 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2025 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2026 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2027 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2028 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2029 		cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2030 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2031 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2032 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2033 		cidp->statistic_type = BGE_STAT_REG;
2034 		dev_ok = B_TRUE;
2035 		break;
2036 
2037 	case DEVICE_ID_5706:
2038 		cidp->chip_label = 5706;
2039 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2040 		break;
2041 
2042 	case DEVICE_ID_5782:
2043 		/*
2044 		 * Apart from the label, we treat this as a 5705(?)
2045 		 */
2046 		cidp->chip_label = 5782;
2047 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2048 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2049 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2050 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2051 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2052 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2053 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2054 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2055 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2056 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2057 		cidp->statistic_type = BGE_STAT_REG;
2058 		dev_ok = B_TRUE;
2059 		break;
2060 
2061 	case DEVICE_ID_5788:
2062 		/*
2063 		 * Apart from the label, we treat this as a 5705(?)
2064 		 */
2065 		cidp->chip_label = 5788;
2066 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2067 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2068 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2069 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2070 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2071 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2072 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2073 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2074 		cidp->statistic_type = BGE_STAT_REG;
2075 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2076 		dev_ok = B_TRUE;
2077 		break;
2078 
2079 	case DEVICE_ID_5714C:
2080 		if (cidp->revision >= REVISION_ID_5714_A2)
2081 			cidp->msi_enabled = bge_enable_msi;
2082 		/* FALLTHRU */
2083 	case DEVICE_ID_5714S:
2084 		cidp->chip_label = 5714;
2085 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2086 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2087 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2088 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2089 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2090 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2091 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714;
2092 		cidp->bge_mlcr_default = bge_mlcr_default_5714;
2093 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2094 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2095 		cidp->pci_type = BGE_PCI_E;
2096 		cidp->statistic_type = BGE_STAT_REG;
2097 		dev_ok = B_TRUE;
2098 		break;
2099 
2100 	case DEVICE_ID_5715C:
2101 	case DEVICE_ID_5715S:
2102 		cidp->chip_label = 5715;
2103 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2104 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2105 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2106 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2107 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2108 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2109 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715;
2110 		cidp->bge_mlcr_default = bge_mlcr_default_5714;
2111 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2112 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2113 		cidp->pci_type = BGE_PCI_E;
2114 		cidp->statistic_type = BGE_STAT_REG;
2115 		if (cidp->revision >= REVISION_ID_5715_A2)
2116 			cidp->msi_enabled = bge_enable_msi;
2117 		dev_ok = B_TRUE;
2118 		break;
2119 
2120 	case DEVICE_ID_5721:
2121 		cidp->chip_label = 5721;
2122 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2123 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2124 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2125 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2126 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2127 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2128 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
2129 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2130 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2131 		cidp->pci_type = BGE_PCI_E;
2132 		cidp->statistic_type = BGE_STAT_REG;
2133 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2134 		dev_ok = B_TRUE;
2135 		break;
2136 
2137 	case DEVICE_ID_5751:
2138 	case DEVICE_ID_5751M:
2139 		cidp->chip_label = 5751;
2140 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2141 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2142 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2143 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2144 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2145 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2146 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
2147 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2148 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2149 		cidp->pci_type = BGE_PCI_E;
2150 		cidp->statistic_type = BGE_STAT_REG;
2151 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2152 		dev_ok = B_TRUE;
2153 		break;
2154 
2155 	case DEVICE_ID_5752:
2156 	case DEVICE_ID_5752M:
2157 		cidp->chip_label = 5752;
2158 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2159 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2160 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2161 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2162 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2163 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2164 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
2165 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2166 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2167 		cidp->pci_type = BGE_PCI_E;
2168 		cidp->statistic_type = BGE_STAT_REG;
2169 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2170 		dev_ok = B_TRUE;
2171 		break;
2172 
2173 	case DEVICE_ID_5789:
2174 		cidp->chip_label = 5789;
2175 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2176 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2177 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2178 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
2179 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2180 		cidp->tx_rings = BGE_RECV_RINGS_MAX_5705;
2181 		cidp->pci_type = BGE_PCI_E;
2182 		cidp->statistic_type = BGE_STAT_REG;
2183 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2184 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2185 		cidp->msi_enabled = B_TRUE;
2186 		dev_ok = B_TRUE;
2187 		break;
2188 
2189 	}
2190 
2191 	/*
2192 	 * Setup the default jumbo parameter.
2193 	 */
2194 	cidp->ethmax_size = ETHERMAX;
2195 	cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT;
2196 	cidp->std_buf_size = BGE_STD_BUFF_SIZE;
2197 
2198 	/*
2199 	 * If jumbo is enabled and this kind of chipset supports jumbo feature,
2200 	 * setup below jumbo specific parameters.
2201 	 *
2202 	 * For BCM5714/5715, there is only one standard receive ring. So the
2203 	 * std buffer size should be set to BGE_JUMBO_BUFF_SIZE when jumbo
2204 	 * feature is enabled.
2205 	 */
2206 	if (bge_jumbo_enable &&
2207 	    !(cidp->flags & CHIP_FLAG_NO_JUMBO) &&
2208 	    (cidp->default_mtu > BGE_DEFAULT_MTU) &&
2209 	    (cidp->default_mtu <= BGE_MAXIMUM_MTU)) {
2210 		if (DEVICE_5714_SERIES_CHIPSETS(bgep)) {
2211 			cidp->mbuf_lo_water_rdma =
2212 			    RDMA_MBUF_LOWAT_5714_JUMBO;
2213 			cidp->mbuf_lo_water_rmac =
2214 			    MAC_RX_MBUF_LOWAT_5714_JUMBO;
2215 			cidp->mbuf_hi_water = MBUF_HIWAT_5714_JUMBO;
2216 			cidp->jumbo_slots = 0;
2217 			cidp->std_buf_size = BGE_JUMBO_BUFF_SIZE;
2218 		} else {
2219 			cidp->mbuf_lo_water_rdma =
2220 			    RDMA_MBUF_LOWAT_JUMBO;
2221 			cidp->mbuf_lo_water_rmac =
2222 			    MAC_RX_MBUF_LOWAT_JUMBO;
2223 			cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO;
2224 			cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED;
2225 		}
2226 		cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE;
2227 		cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO;
2228 		cidp->ethmax_size = cidp->default_mtu +
2229 		    sizeof (struct ether_header);
2230 	}
2231 
2232 	/*
2233 	 * Identify the NV memory type: SEEPROM or Flash?
2234 	 */
2235 	cidp->nvtype = bge_nvmem_id(bgep);
2236 
2237 	/*
2238 	 * Now, we want to check whether this device is part of a
2239 	 * supported subsystem (e.g., on the motherboard of a Sun
2240 	 * branded platform).
2241 	 *
2242 	 * Rule 1: If the Subsystem Vendor ID is "Sun", then it's OK ;-)
2243 	 */
2244 	if (cidp->subven == VENDOR_ID_SUN)
2245 		sys_ok = B_TRUE;
2246 
2247 	/*
2248 	 * Rule 2: If it's on the list on known subsystems, then it's OK.
2249 	 * Note: 0x14e41647 should *not* appear in the list, but the code
2250 	 * doesn't enforce that.
2251 	 */
2252 	err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo,
2253 	    DDI_PROP_DONTPASS, knownids_propname, &ids, &i);
2254 	if (err == DDI_PROP_SUCCESS) {
2255 		/*
2256 		 * Got the list; scan for a matching subsystem vendor/device
2257 		 */
2258 		subid = (cidp->subven << 16) | cidp->subdev;
2259 		while (i--)
2260 			if (ids[i] == subid)
2261 				sys_ok = B_TRUE;
2262 		ddi_prop_free(ids);
2263 	}
2264 
2265 	/*
2266 	 * Rule 3: If it's a Taco/ENWS motherboard device, then it's OK
2267 	 *
2268 	 * Unfortunately, early SunBlade 1500s and 2500s didn't reprogram
2269 	 * the Subsystem Vendor ID, so it defaults to Broadcom.  Therefore,
2270 	 * we have to check specially for the exact device paths to the
2271 	 * motherboard devices on those platforms ;-(
2272 	 *
2273 	 * Note: we can't just use the "supported-subsystems" mechanism
2274 	 * above, because the entry would have to be 0x14e41647 -- which
2275 	 * would then accept *any* plugin card that *didn't* contain a
2276 	 * (valid) SEEPROM ;-(
2277 	 */
2278 	sysname = ddi_node_name(ddi_root_node());
2279 	devname = ddi_pathname(bgep->devinfo, buf);
2280 	ASSERT(strlen(devname) > 0);
2281 	if (strcmp(sysname, "SUNW,Sun-Blade-1500") == 0)	/* Taco */
2282 		if (strcmp(devname, "/pci@1f,700000/network@2") == 0)
2283 			sys_ok = B_TRUE;
2284 	if (strcmp(sysname, "SUNW,Sun-Blade-2500") == 0)	/* ENWS */
2285 		if (strcmp(devname, "/pci@1c,600000/network@3") == 0)
2286 			sys_ok = B_TRUE;
2287 
2288 	/*
2289 	 * Now check what we've discovered: is this truly a supported
2290 	 * chip on (the motherboard of) a supported platform?
2291 	 *
2292 	 * Possible problems here:
2293 	 * 1)	it's a completely unheard-of chip (e.g. 5761)
2294 	 * 2)	it's a recognised but unsupported chip (e.g. 5701, 5703C-A0)
2295 	 * 3)	it's a chip we would support if it were on the motherboard
2296 	 *	of a Sun platform, but this one isn't ;-(
2297 	 */
2298 	if (cidp->chip_label == 0)
2299 		bge_problem(bgep,
2300 		    "Device 'pci%04x,%04x' not recognized (%d?)",
2301 		    cidp->vendor, cidp->device, cidp->device);
2302 	else if (!dev_ok)
2303 		bge_problem(bgep,
2304 		    "Device 'pci%04x,%04x' (%d) revision %d not supported",
2305 		    cidp->vendor, cidp->device, cidp->chip_label,
2306 		    cidp->revision);
2307 #if	BGE_DEBUGGING
2308 	else if (!sys_ok)
2309 		bge_problem(bgep,
2310 		    "%d-based subsystem 'pci%04x,%04x' not validated",
2311 		    cidp->chip_label, cidp->subven, cidp->subdev);
2312 #endif
2313 	else
2314 		cidp->flags |= CHIP_FLAG_SUPPORTED;
2315 	if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
2316 		return (EIO);
2317 	return (0);
2318 }
2319 
2320 void
2321 bge_chip_msi_trig(bge_t *bgep)
2322 {
2323 	uint32_t	regval;
2324 
2325 	regval = bgep->param_msi_cnt<<4;
2326 	bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval);
2327 	BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval));
2328 }
2329 
2330 /*
2331  * Various registers that control the chip's internal engines (state
2332  * machines) have a <reset> and <enable> bits (fortunately, in the
2333  * same place in each such register :-).
2334  *
2335  * To reset the state machine, the <reset> bit must be written with 1;
2336  * it will then read back as 1 while the reset is in progress, but
2337  * self-clear to 0 when the reset completes.
2338  *
2339  * To enable a state machine, one must set the <enable> bit, which
2340  * will continue to read back as 0 until the state machine is running.
2341  *
2342  * To disable a state machine, the <enable> bit must be cleared, but
2343  * it will continue to read back as 1 until the state machine actually
2344  * stops.
2345  *
2346  * This routine implements polling for completion of a reset, enable
2347  * or disable operation, returning B_TRUE on success (bit reached the
2348  * required state) or B_FALSE on timeout (200*100us == 20ms).
2349  */
2350 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno,
2351 					uint32_t mask, uint32_t val);
2352 #pragma	no_inline(bge_chip_poll_engine)
2353 
2354 static boolean_t
2355 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno,
2356 	uint32_t mask, uint32_t val)
2357 {
2358 	uint32_t regval;
2359 	uint32_t n;
2360 
2361 	BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)",
2362 	    (void *)bgep, regno, mask, val));
2363 
2364 	for (n = 200; n; --n) {
2365 		regval = bge_reg_get32(bgep, regno);
2366 		if ((regval & mask) == val)
2367 			return (B_TRUE);
2368 		drv_usecwait(100);
2369 	}
2370 
2371 	bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE);
2372 	return (B_FALSE);
2373 }
2374 
2375 /*
2376  * Various registers that control the chip's internal engines (state
2377  * machines) have a <reset> bit (fortunately, in the same place in
2378  * each such register :-).  To reset the state machine, this bit must
2379  * be written with 1; it will then read back as 1 while the reset is
2380  * in progress, but self-clear to 0 when the reset completes.
2381  *
2382  * This code sets the bit, then polls for it to read back as zero.
2383  * The return value is B_TRUE on success (reset bit cleared itself),
2384  * or B_FALSE if the state machine didn't recover :(
2385  *
2386  * NOTE: the Core reset is similar to other resets, except that we
2387  * can't poll for completion, since the Core reset disables memory
2388  * access!  So we just have to assume that it will all complete in
2389  * 100us.  See Broadcom document 570X-PG102-R, p102, steps 4-5.
2390  */
2391 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno);
2392 #pragma	no_inline(bge_chip_reset_engine)
2393 
2394 static boolean_t
2395 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno)
2396 {
2397 	uint32_t regval;
2398 	uint32_t val32;
2399 
2400 	regval = bge_reg_get32(bgep, regno);
2401 
2402 	BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)",
2403 	    (void *)bgep, regno));
2404 	BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x",
2405 	    regno, regval));
2406 
2407 	regval |= STATE_MACHINE_RESET_BIT;
2408 
2409 	switch (regno) {
2410 	case MISC_CONFIG_REG:
2411 		/*
2412 		 * BCM5714/5721/5751 pcie chip special case. In order to avoid
2413 		 * resetting PCIE block and bringing PCIE link down, bit 29
2414 		 * in the register needs to be set first, and then set it again
2415 		 * while the reset bit is written.
2416 		 * See:P500 of 57xx-PG102-RDS.pdf.
2417 		 */
2418 		if (DEVICE_5705_SERIES_CHIPSETS(bgep)||
2419 		    DEVICE_5721_SERIES_CHIPSETS(bgep)||
2420 		    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
2421 			regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE;
2422 			if (bgep->chipid.pci_type == BGE_PCI_E) {
2423 				if (bgep->chipid.asic_rev ==
2424 				    MHCR_CHIP_REV_5751_A0 ||
2425 				    bgep->chipid.asic_rev ==
2426 				    MHCR_CHIP_REV_5721_A0 ||
2427 				    bgep->chipid.asic_rev ==
2428 				    MHCR_CHIP_REV_5755_A0) {
2429 					val32 = bge_reg_get32(bgep,
2430 					    PHY_TEST_CTRL_REG);
2431 					if (val32 == (PHY_PCIE_SCRAM_MODE |
2432 					    PHY_PCIE_LTASS_MODE))
2433 						bge_reg_put32(bgep,
2434 						    PHY_TEST_CTRL_REG,
2435 						    PHY_PCIE_SCRAM_MODE);
2436 					val32 = pci_config_get32
2437 					    (bgep->cfg_handle,
2438 					    PCI_CONF_BGE_CLKCTL);
2439 					val32 |= CLKCTL_PCIE_A0_FIX;
2440 					pci_config_put32(bgep->cfg_handle,
2441 					    PCI_CONF_BGE_CLKCTL, val32);
2442 				}
2443 				bge_reg_set32(bgep, regno,
2444 				    MISC_CONFIG_GRC_RESET_DISABLE);
2445 				regval |= MISC_CONFIG_GRC_RESET_DISABLE;
2446 			}
2447 		}
2448 
2449 		/*
2450 		 * Special case - causes Core reset
2451 		 *
2452 		 * On SPARC v9 we want to ensure that we don't start
2453 		 * timing until the I/O access has actually reached
2454 		 * the chip, otherwise we might make the next access
2455 		 * too early.  And we can't just force the write out
2456 		 * by following it with a read (even to config space)
2457 		 * because that would cause the fault we're trying
2458 		 * to avoid.  Hence the need for membar_sync() here.
2459 		 */
2460 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval);
2461 #ifdef	__sparcv9
2462 		membar_sync();
2463 #endif	/* __sparcv9 */
2464 		/*
2465 		 * On some platforms,system need about 300us for
2466 		 * link setup.
2467 		 */
2468 		drv_usecwait(300);
2469 
2470 		if (bgep->chipid.pci_type == BGE_PCI_E) {
2471 			/* PCI-E device need more reset time */
2472 			drv_usecwait(120000);
2473 
2474 			/* Set PCIE max payload size and clear error status. */
2475 			if ((bgep->chipid.chip_label == 5721) ||
2476 			    (bgep->chipid.chip_label == 5751) ||
2477 			    (bgep->chipid.chip_label == 5752) ||
2478 			    (bgep->chipid.chip_label == 5789)) {
2479 				pci_config_put16(bgep->cfg_handle,
2480 				    PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX);
2481 				pci_config_put16(bgep->cfg_handle,
2482 				    PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS);
2483 			}
2484 		}
2485 
2486 		BGE_PCICHK(bgep);
2487 		return (B_TRUE);
2488 
2489 	default:
2490 		bge_reg_put32(bgep, regno, regval);
2491 		return (bge_chip_poll_engine(bgep, regno,
2492 		    STATE_MACHINE_RESET_BIT, 0));
2493 	}
2494 }
2495 
2496 /*
2497  * Various registers that control the chip's internal engines (state
2498  * machines) have an <enable> bit (fortunately, in the same place in
2499  * each such register :-).  To stop the state machine, this bit must
2500  * be written with 0, then polled to see when the state machine has
2501  * actually stopped.
2502  *
2503  * The return value is B_TRUE on success (enable bit cleared), or
2504  * B_FALSE if the state machine didn't stop :(
2505  */
2506 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno,
2507 						uint32_t morebits);
2508 #pragma	no_inline(bge_chip_disable_engine)
2509 
2510 static boolean_t
2511 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits)
2512 {
2513 	uint32_t regval;
2514 
2515 	BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)",
2516 	    (void *)bgep, regno, morebits));
2517 
2518 	switch (regno) {
2519 	case FTQ_RESET_REG:
2520 		/*
2521 		 * For Schumacher's bugfix CR6490108
2522 		 */
2523 #ifdef BGE_IPMI_ASF
2524 #ifdef BGE_NETCONSOLE
2525 		if (bgep->asf_enabled)
2526 			return (B_TRUE);
2527 #endif
2528 #endif
2529 		/*
2530 		 * Not quite like the others; it doesn't
2531 		 * have an <enable> bit, but instead we
2532 		 * have to set and then clear all the bits
2533 		 */
2534 		bge_reg_put32(bgep, regno, ~(uint32_t)0);
2535 		drv_usecwait(100);
2536 		bge_reg_put32(bgep, regno, 0);
2537 		return (B_TRUE);
2538 
2539 	default:
2540 		regval = bge_reg_get32(bgep, regno);
2541 		regval &= ~STATE_MACHINE_ENABLE_BIT;
2542 		regval &= ~morebits;
2543 		bge_reg_put32(bgep, regno, regval);
2544 		return (bge_chip_poll_engine(bgep, regno,
2545 		    STATE_MACHINE_ENABLE_BIT, 0));
2546 	}
2547 }
2548 
2549 /*
2550  * Various registers that control the chip's internal engines (state
2551  * machines) have an <enable> bit (fortunately, in the same place in
2552  * each such register :-).  To start the state machine, this bit must
2553  * be written with 1, then polled to see when the state machine has
2554  * actually started.
2555  *
2556  * The return value is B_TRUE on success (enable bit set), or
2557  * B_FALSE if the state machine didn't start :(
2558  */
2559 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno,
2560 					uint32_t morebits);
2561 #pragma	no_inline(bge_chip_enable_engine)
2562 
2563 static boolean_t
2564 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits)
2565 {
2566 	uint32_t regval;
2567 
2568 	BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)",
2569 	    (void *)bgep, regno, morebits));
2570 
2571 	switch (regno) {
2572 	case FTQ_RESET_REG:
2573 #ifdef BGE_IPMI_ASF
2574 #ifdef BGE_NETCONSOLE
2575 		if (bgep->asf_enabled)
2576 			return (B_TRUE);
2577 #endif
2578 #endif
2579 		/*
2580 		 * Not quite like the others; it doesn't
2581 		 * have an <enable> bit, but instead we
2582 		 * have to set and then clear all the bits
2583 		 */
2584 		bge_reg_put32(bgep, regno, ~(uint32_t)0);
2585 		drv_usecwait(100);
2586 		bge_reg_put32(bgep, regno, 0);
2587 		return (B_TRUE);
2588 
2589 	default:
2590 		regval = bge_reg_get32(bgep, regno);
2591 		regval |= STATE_MACHINE_ENABLE_BIT;
2592 		regval |= morebits;
2593 		bge_reg_put32(bgep, regno, regval);
2594 		return (bge_chip_poll_engine(bgep, regno,
2595 		    STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT));
2596 	}
2597 }
2598 
2599 /*
2600  * Reprogram the Ethernet, Transmit, and Receive MAC
2601  * modes to match the param_* variables
2602  */
2603 void bge_sync_mac_modes(bge_t *bgep);
2604 #pragma	no_inline(bge_sync_mac_modes)
2605 
2606 void
2607 bge_sync_mac_modes(bge_t *bgep)
2608 {
2609 	uint32_t macmode;
2610 	uint32_t regval;
2611 
2612 	ASSERT(mutex_owned(bgep->genlock));
2613 
2614 	/*
2615 	 * Reprogram the Ethernet MAC mode ...
2616 	 */
2617 	macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG);
2618 	if ((bgep->chipid.flags & CHIP_FLAG_SERDES) &&
2619 	    (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC))
2620 		macmode &= ~ETHERNET_MODE_LINK_POLARITY;
2621 	else
2622 		macmode |= ETHERNET_MODE_LINK_POLARITY;
2623 	macmode &= ~ETHERNET_MODE_PORTMODE_MASK;
2624 	if ((bgep->chipid.flags & CHIP_FLAG_SERDES) &&
2625 	    (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC))
2626 		macmode |= ETHERNET_MODE_PORTMODE_TBI;
2627 	else if (bgep->param_link_speed == 10 || bgep->param_link_speed == 100)
2628 		macmode |= ETHERNET_MODE_PORTMODE_MII;
2629 	else
2630 		macmode |= ETHERNET_MODE_PORTMODE_GMII;
2631 	if (bgep->param_link_duplex == LINK_DUPLEX_HALF)
2632 		macmode |= ETHERNET_MODE_HALF_DUPLEX;
2633 	else
2634 		macmode &= ~ETHERNET_MODE_HALF_DUPLEX;
2635 	if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC)
2636 		macmode |= ETHERNET_MODE_MAC_LOOPBACK;
2637 	else
2638 		macmode &= ~ETHERNET_MODE_MAC_LOOPBACK;
2639 	bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode);
2640 	BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x",
2641 	    (void *)bgep, regval, macmode));
2642 
2643 	/*
2644 	 * ... the Transmit MAC mode ...
2645 	 */
2646 	macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG);
2647 	if (bgep->param_link_tx_pause)
2648 		macmode |= TRANSMIT_MODE_FLOW_CONTROL;
2649 	else
2650 		macmode &= ~TRANSMIT_MODE_FLOW_CONTROL;
2651 	bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode);
2652 	BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x",
2653 	    (void *)bgep, regval, macmode));
2654 
2655 	/*
2656 	 * ... and the Receive MAC mode
2657 	 */
2658 	macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG);
2659 	if (bgep->param_link_rx_pause)
2660 		macmode |= RECEIVE_MODE_FLOW_CONTROL;
2661 	else
2662 		macmode &= ~RECEIVE_MODE_FLOW_CONTROL;
2663 	bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode);
2664 	BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x",
2665 	    (void *)bgep, regval, macmode));
2666 }
2667 
2668 /*
2669  * bge_chip_sync() -- program the chip with the unicast MAC address,
2670  * the multicast hash table, the required level of promiscuity, and
2671  * the current loopback mode ...
2672  */
2673 #ifdef BGE_IPMI_ASF
2674 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive);
2675 #else
2676 int bge_chip_sync(bge_t *bgep);
2677 #endif
2678 #pragma	no_inline(bge_chip_sync)
2679 
2680 int
2681 #ifdef BGE_IPMI_ASF
2682 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive)
2683 #else
2684 bge_chip_sync(bge_t *bgep)
2685 #endif
2686 {
2687 	void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits);
2688 	boolean_t promisc;
2689 	uint64_t macaddr;
2690 	uint32_t fill;
2691 	int i, j;
2692 	int retval = DDI_SUCCESS;
2693 
2694 	BGE_TRACE(("bge_chip_sync($%p)",
2695 	    (void *)bgep));
2696 
2697 	ASSERT(mutex_owned(bgep->genlock));
2698 
2699 	promisc = B_FALSE;
2700 	fill = ~(uint32_t)0;
2701 
2702 	if (bgep->promisc)
2703 		promisc = B_TRUE;
2704 	else
2705 		fill = (uint32_t)0;
2706 
2707 	/*
2708 	 * If the TX/RX MAC engines are already running, we should stop
2709 	 * them (and reset the RX engine) before changing the parameters.
2710 	 * If they're not running, this will have no effect ...
2711 	 *
2712 	 * NOTE: this is currently disabled by default because stopping
2713 	 * and restarting the Tx engine may cause an outgoing packet in
2714 	 * transit to be truncated.  Also, stopping and restarting the
2715 	 * Rx engine seems to not work correctly on the 5705.  Testing
2716 	 * has not (yet!) revealed any problems with NOT stopping and
2717 	 * restarting these engines (and Broadcom say their drivers don't
2718 	 * do this), but if it is found to cause problems, this variable
2719 	 * can be patched to re-enable the old behaviour ...
2720 	 */
2721 	if (bge_stop_start_on_sync) {
2722 #ifdef BGE_IPMI_ASF
2723 		if (!bgep->asf_enabled) {
2724 			if (!bge_chip_disable_engine(bgep,
2725 			    RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG))
2726 				retval = DDI_FAILURE;
2727 		} else {
2728 			if (!bge_chip_disable_engine(bgep,
2729 			    RECEIVE_MAC_MODE_REG, 0))
2730 				retval = DDI_FAILURE;
2731 		}
2732 #else
2733 		if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG,
2734 		    RECEIVE_MODE_KEEP_VLAN_TAG))
2735 			retval = DDI_FAILURE;
2736 #endif
2737 		if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0))
2738 			retval = DDI_FAILURE;
2739 		if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG))
2740 			retval = DDI_FAILURE;
2741 	}
2742 
2743 	/*
2744 	 * Reprogram the hashed multicast address table ...
2745 	 */
2746 	for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i)
2747 		bge_reg_put32(bgep, MAC_HASH_REG(i), 0);
2748 
2749 	for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i)
2750 		bge_reg_put32(bgep, MAC_HASH_REG(i),
2751 			bgep->mcast_hash[i] | fill);
2752 
2753 #ifdef BGE_IPMI_ASF
2754 	if (!bgep->asf_enabled || !asf_keeplive) {
2755 #endif
2756 		/*
2757 		 * Transform the MAC address(es) from host to chip format, then
2758 		 * reprogram the transmit random backoff seed and the unicast
2759 		 * MAC address(es) ...
2760 		 */
2761 		for (j = 0; j < MAC_ADDRESS_REGS_MAX; j++) {
2762 			for (i = 0, fill = 0, macaddr = 0ull;
2763 			    i < ETHERADDRL; ++i) {
2764 				macaddr <<= 8;
2765 				macaddr |= bgep->curr_addr[j].addr[i];
2766 				fill += bgep->curr_addr[j].addr[i];
2767 			}
2768 			bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill);
2769 			bge_reg_put64(bgep, MAC_ADDRESS_REG(j), macaddr);
2770 		}
2771 
2772 		BGE_DEBUG(("bge_chip_sync($%p) setting MAC address %012llx",
2773 			(void *)bgep, macaddr));
2774 #ifdef BGE_IPMI_ASF
2775 	}
2776 #endif
2777 
2778 	/*
2779 	 * Set or clear the PROMISCUOUS mode bit
2780 	 */
2781 	opfn = promisc ? bge_reg_set32 : bge_reg_clr32;
2782 	(*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS);
2783 
2784 	/*
2785 	 * Sync the rest of the MAC modes too ...
2786 	 */
2787 	bge_sync_mac_modes(bgep);
2788 
2789 	/*
2790 	 * Restart RX/TX MAC engines if required ...
2791 	 */
2792 	if (bgep->bge_chip_state == BGE_CHIP_RUNNING) {
2793 		if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0))
2794 			retval = DDI_FAILURE;
2795 #ifdef BGE_IPMI_ASF
2796 		if (!bgep->asf_enabled) {
2797 			if (!bge_chip_enable_engine(bgep,
2798 			    RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG))
2799 				retval = DDI_FAILURE;
2800 		} else {
2801 			if (!bge_chip_enable_engine(bgep,
2802 			    RECEIVE_MAC_MODE_REG, 0))
2803 				retval = DDI_FAILURE;
2804 		}
2805 #else
2806 		if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG,
2807 		    RECEIVE_MODE_KEEP_VLAN_TAG))
2808 			retval = DDI_FAILURE;
2809 #endif
2810 	}
2811 	return (retval);
2812 }
2813 
2814 /*
2815  * This array defines the sequence of state machine control registers
2816  * in which the <enable> bit must be cleared to bring the chip to a
2817  * clean stop.  Taken from Broadcom document 570X-PG102-R, p116.
2818  */
2819 static bge_regno_t shutdown_engine_regs[] = {
2820 	RECEIVE_MAC_MODE_REG,
2821 	RCV_BD_INITIATOR_MODE_REG,
2822 	RCV_LIST_PLACEMENT_MODE_REG,
2823 	RCV_LIST_SELECTOR_MODE_REG,		/* BCM5704 series only	*/
2824 	RCV_DATA_BD_INITIATOR_MODE_REG,
2825 	RCV_DATA_COMPLETION_MODE_REG,
2826 	RCV_BD_COMPLETION_MODE_REG,
2827 
2828 	SEND_BD_SELECTOR_MODE_REG,
2829 	SEND_BD_INITIATOR_MODE_REG,
2830 	SEND_DATA_INITIATOR_MODE_REG,
2831 	READ_DMA_MODE_REG,
2832 	SEND_DATA_COMPLETION_MODE_REG,
2833 	DMA_COMPLETION_MODE_REG,		/* BCM5704 series only	*/
2834 	SEND_BD_COMPLETION_MODE_REG,
2835 	TRANSMIT_MAC_MODE_REG,
2836 
2837 	HOST_COALESCE_MODE_REG,
2838 	WRITE_DMA_MODE_REG,
2839 	MBUF_CLUSTER_FREE_MODE_REG,		/* BCM5704 series only	*/
2840 	FTQ_RESET_REG,		/* special - see code	*/
2841 	BUFFER_MANAGER_MODE_REG,		/* BCM5704 series only	*/
2842 	MEMORY_ARBITER_MODE_REG,		/* BCM5704 series only	*/
2843 	BGE_REGNO_NONE		/* terminator		*/
2844 };
2845 
2846 /*
2847  * bge_chip_stop() -- stop all chip processing
2848  *
2849  * If the <fault> parameter is B_TRUE, we're stopping the chip because
2850  * we've detected a problem internally; otherwise, this is a normal
2851  * (clean) stop (at user request i.e. the last STREAM has been closed).
2852  */
2853 void bge_chip_stop(bge_t *bgep, boolean_t fault);
2854 #pragma	no_inline(bge_chip_stop)
2855 
2856 void
2857 bge_chip_stop(bge_t *bgep, boolean_t fault)
2858 {
2859 	bge_regno_t regno;
2860 	bge_regno_t *rbp;
2861 	boolean_t ok;
2862 
2863 	BGE_TRACE(("bge_chip_stop($%p)",
2864 	    (void *)bgep));
2865 
2866 	ASSERT(mutex_owned(bgep->genlock));
2867 
2868 	rbp = shutdown_engine_regs;
2869 	/*
2870 	 * When driver try to shutdown the BCM5705/5788/5721/5751/
2871 	 * 5752/5714 and 5715 chipsets,the buffer manager and the mem
2872 	 * -ory arbiter should not be disabled.
2873 	 */
2874 	for (ok = B_TRUE; (regno = *rbp) != BGE_REGNO_NONE; ++rbp) {
2875 			if (DEVICE_5704_SERIES_CHIPSETS(bgep))
2876 				ok &= bge_chip_disable_engine(bgep, regno, 0);
2877 			else if ((regno != RCV_LIST_SELECTOR_MODE_REG) &&
2878 			    (regno != DMA_COMPLETION_MODE_REG) &&
2879 			    (regno != MBUF_CLUSTER_FREE_MODE_REG)&&
2880 			    (regno != BUFFER_MANAGER_MODE_REG) &&
2881 			    (regno != MEMORY_ARBITER_MODE_REG))
2882 				ok &= bge_chip_disable_engine(bgep,
2883 				    regno, 0);
2884 	}
2885 
2886 	if (!ok && !fault)
2887 		ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED);
2888 
2889 	/*
2890 	 * Finally, disable (all) MAC events & clear the MAC status
2891 	 */
2892 	bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0);
2893 	bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0);
2894 
2895 	/*
2896 	 * if we're stopping the chip because of a detected fault then do
2897 	 * appropriate actions
2898 	 */
2899 	if (fault) {
2900 		if (bgep->bge_chip_state != BGE_CHIP_FAULT) {
2901 			bgep->bge_chip_state = BGE_CHIP_FAULT;
2902 			if (!bgep->manual_reset)
2903 				ddi_fm_service_impact(bgep->devinfo,
2904 				    DDI_SERVICE_LOST);
2905 			if (bgep->bge_dma_error) {
2906 				/*
2907 				 * need to free buffers in case the fault was
2908 				 * due to a memory error in a buffer - got to
2909 				 * do a fair bit of tidying first
2910 				 */
2911 				if (bgep->progress & PROGRESS_KSTATS) {
2912 					bge_fini_kstats(bgep);
2913 					bgep->progress &= ~PROGRESS_KSTATS;
2914 				}
2915 				if (bgep->progress & PROGRESS_INTR) {
2916 					bge_intr_disable(bgep);
2917 					rw_enter(bgep->errlock, RW_WRITER);
2918 					bge_fini_rings(bgep);
2919 					rw_exit(bgep->errlock);
2920 					bgep->progress &= ~PROGRESS_INTR;
2921 				}
2922 				if (bgep->progress & PROGRESS_BUFS) {
2923 					bge_free_bufs(bgep);
2924 					bgep->progress &= ~PROGRESS_BUFS;
2925 				}
2926 				bgep->bge_dma_error = B_FALSE;
2927 			}
2928 		}
2929 	} else
2930 		bgep->bge_chip_state = BGE_CHIP_STOPPED;
2931 }
2932 
2933 /*
2934  * Poll for completion of chip's ROM firmware; also, at least on the
2935  * first time through, find and return the hardware MAC address, if any.
2936  */
2937 static uint64_t bge_poll_firmware(bge_t *bgep);
2938 #pragma	no_inline(bge_poll_firmware)
2939 
2940 static uint64_t
2941 bge_poll_firmware(bge_t *bgep)
2942 {
2943 	uint64_t magic;
2944 	uint64_t mac;
2945 	uint32_t gen;
2946 	uint32_t i;
2947 
2948 	/*
2949 	 * Step 19: poll for firmware completion (GENCOMM port set
2950 	 * to the ones complement of T3_MAGIC_NUMBER).
2951 	 *
2952 	 * While we're at it, we also read the MAC address register;
2953 	 * at some stage the firmware will load this with the
2954 	 * factory-set value.
2955 	 *
2956 	 * When both the magic number and the MAC address are set,
2957 	 * we're done; but we impose a time limit of one second
2958 	 * (1000*1000us) in case the firmware fails in some fashion
2959 	 * or the SEEPROM that provides that MAC address isn't fitted.
2960 	 *
2961 	 * After the first time through (chip state != INITIAL), we
2962 	 * don't need the MAC address to be set (we've already got it
2963 	 * or not, from the first time), so we don't wait for it, but
2964 	 * we still have to wait for the T3_MAGIC_NUMBER.
2965 	 *
2966 	 * Note: the magic number is only a 32-bit quantity, but the NIC
2967 	 * memory is 64-bit (and big-endian) internally.  Addressing the
2968 	 * GENCOMM word as "the upper half of a 64-bit quantity" makes
2969 	 * it work correctly on both big- and little-endian hosts.
2970 	 */
2971 	for (i = 0; i < 1000; ++i) {
2972 		drv_usecwait(1000);
2973 		gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32;
2974 		if (DEVICE_5704_SERIES_CHIPSETS(bgep))
2975 			drv_usecwait(100000);
2976 		mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0));
2977 #ifdef BGE_IPMI_ASF
2978 		if (!bgep->asf_enabled) {
2979 #endif
2980 			if (gen != ~T3_MAGIC_NUMBER)
2981 				continue;
2982 #ifdef BGE_IPMI_ASF
2983 		}
2984 #endif
2985 		if (mac != 0ULL)
2986 			break;
2987 		if (bgep->bge_chip_state != BGE_CHIP_INITIAL)
2988 			break;
2989 	}
2990 
2991 	magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM);
2992 	BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops",
2993 	    (void *)bgep, gen, i));
2994 	BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx",
2995 	    mac, magic));
2996 
2997 	return (mac);
2998 }
2999 
3000 /*
3001  * Maximum times of trying to get the NVRAM access lock
3002  * by calling bge_nvmem_acquire()
3003  */
3004 #define	MAX_TRY_NVMEM_ACQUIRE	10000
3005 
3006 #ifdef BGE_IPMI_ASF
3007 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode);
3008 #else
3009 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma);
3010 #endif
3011 #pragma	no_inline(bge_chip_reset)
3012 
3013 int
3014 #ifdef BGE_IPMI_ASF
3015 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode)
3016 #else
3017 bge_chip_reset(bge_t *bgep, boolean_t enable_dma)
3018 #endif
3019 {
3020 	chip_id_t chipid;
3021 	uint64_t mac;
3022 	uint64_t magic;
3023 	uint32_t modeflags;
3024 	uint32_t mhcr;
3025 	uint32_t sx0;
3026 	uint32_t i, tries;
3027 #ifdef BGE_IPMI_ASF
3028 	uint32_t mailbox;
3029 #endif
3030 	int retval = DDI_SUCCESS;
3031 
3032 	BGE_TRACE(("bge_chip_reset($%p, %d)",
3033 		(void *)bgep, enable_dma));
3034 
3035 	ASSERT(mutex_owned(bgep->genlock));
3036 
3037 	BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d",
3038 		(void *)bgep, enable_dma, bgep->bge_chip_state));
3039 
3040 	/*
3041 	 * Do we need to stop the chip cleanly before resetting?
3042 	 */
3043 	switch (bgep->bge_chip_state) {
3044 	default:
3045 		_NOTE(NOTREACHED)
3046 		return (DDI_FAILURE);
3047 
3048 	case BGE_CHIP_INITIAL:
3049 	case BGE_CHIP_STOPPED:
3050 	case BGE_CHIP_RESET:
3051 		break;
3052 
3053 	case BGE_CHIP_RUNNING:
3054 	case BGE_CHIP_ERROR:
3055 	case BGE_CHIP_FAULT:
3056 		bge_chip_stop(bgep, B_FALSE);
3057 		break;
3058 	}
3059 
3060 #ifdef BGE_IPMI_ASF
3061 	if (bgep->asf_enabled) {
3062 #ifdef __sparc
3063 		mhcr = MHCR_ENABLE_INDIRECT_ACCESS |
3064 			MHCR_ENABLE_TAGGED_STATUS_MODE |
3065 			MHCR_MASK_INTERRUPT_MODE |
3066 			MHCR_MASK_PCI_INT_OUTPUT |
3067 			MHCR_CLEAR_INTERRUPT_INTA |
3068 			MHCR_ENABLE_ENDIAN_WORD_SWAP |
3069 			MHCR_ENABLE_ENDIAN_BYTE_SWAP;
3070 		pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr);
3071 		bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG,
3072 			bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG) |
3073 			MEMORY_ARBITER_ENABLE);
3074 #endif
3075 		if (asf_mode == ASF_MODE_INIT) {
3076 			bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET);
3077 		} else if (asf_mode == ASF_MODE_SHUTDOWN) {
3078 			bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET);
3079 		}
3080 	}
3081 #endif
3082 	/*
3083 	 * Adapted from Broadcom document 570X-PG102-R, pp 102-116.
3084 	 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159.
3085 	 *
3086 	 * Before reset Core clock,it is
3087 	 * also required to initialize the Memory Arbiter as specified in step9
3088 	 * and Misc Host Control Register as specified in step-13
3089 	 * Step 4-5: reset Core clock & wait for completion
3090 	 * Steps 6-8: are done by bge_chip_cfg_init()
3091 	 * put the T3_MAGIC_NUMBER into the GENCOMM port before reset
3092 	 */
3093 	if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0))
3094 		retval = DDI_FAILURE;
3095 
3096 	mhcr = MHCR_ENABLE_INDIRECT_ACCESS |
3097 	    MHCR_ENABLE_TAGGED_STATUS_MODE |
3098 	    MHCR_MASK_INTERRUPT_MODE |
3099 	    MHCR_MASK_PCI_INT_OUTPUT |
3100 	    MHCR_CLEAR_INTERRUPT_INTA;
3101 #ifdef  _BIG_ENDIAN
3102 	mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP;
3103 #endif  /* _BIG_ENDIAN */
3104 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr);
3105 #ifdef BGE_IPMI_ASF
3106 	if (bgep->asf_enabled)
3107 		bgep->asf_wordswapped = B_FALSE;
3108 #endif
3109 	/*
3110 	 * NVRAM Corruption Workaround
3111 	 */
3112 	for (tries = 0; tries < MAX_TRY_NVMEM_ACQUIRE; tries++)
3113 		if (bge_nvmem_acquire(bgep) != EAGAIN)
3114 			break;
3115 	if (tries >= MAX_TRY_NVMEM_ACQUIRE)
3116 		BGE_DEBUG(("%s: fail to acquire nvram lock",
3117 			bgep->ifname));
3118 
3119 #ifdef BGE_IPMI_ASF
3120 	if (!bgep->asf_enabled) {
3121 #endif
3122 		magic = (uint64_t)T3_MAGIC_NUMBER << 32;
3123 		bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic);
3124 #ifdef BGE_IPMI_ASF
3125 	}
3126 #endif
3127 
3128 	if (!bge_chip_reset_engine(bgep, MISC_CONFIG_REG))
3129 		retval = DDI_FAILURE;
3130 	bge_chip_cfg_init(bgep, &chipid, enable_dma);
3131 
3132 	/*
3133 	 * Step 8a: This may belong elsewhere, but BCM5721 needs
3134 	 * a bit set to avoid a fifo overflow/underflow bug.
3135 	 */
3136 	if ((bgep->chipid.chip_label == 5721) ||
3137 		(bgep->chipid.chip_label == 5751) ||
3138 		(bgep->chipid.chip_label == 5752) ||
3139 		(bgep->chipid.chip_label == 5755) ||
3140 		(bgep->chipid.chip_label == 5789))
3141 		bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT);
3142 
3143 
3144 	/*
3145 	 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should
3146 	 * not be changed.
3147 	 */
3148 	if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0))
3149 		retval = DDI_FAILURE;
3150 
3151 	/*
3152 	 * Steps 10-11: configure PIO endianness options and
3153 	 * enable indirect register access -- already done
3154 	 * Steps 12-13: enable writing to the PCI state & clock
3155 	 * control registers -- not required; we aren't going to
3156 	 * use those features.
3157 	 * Steps 14-15: Configure DMA endianness options.  See
3158 	 * the comments on the setting of the MHCR above.
3159 	 */
3160 #ifdef	_BIG_ENDIAN
3161 	modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME |
3162 		    MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME;
3163 #else
3164 	modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME;
3165 #endif	/* _BIG_ENDIAN */
3166 #ifdef BGE_IPMI_ASF
3167 	if (bgep->asf_enabled)
3168 		modeflags |= MODE_HOST_STACK_UP;
3169 #endif
3170 	bge_reg_put32(bgep, MODE_CONTROL_REG, modeflags);
3171 
3172 #ifdef BGE_IPMI_ASF
3173 	if (bgep->asf_enabled) {
3174 #ifdef __sparc
3175 		bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG,
3176 			MEMORY_ARBITER_ENABLE |
3177 			bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG));
3178 #endif
3179 
3180 #ifdef  BGE_NETCONSOLE
3181 		if (!bgep->asf_newhandshake) {
3182 			if ((asf_mode == ASF_MODE_INIT) ||
3183 			(asf_mode == ASF_MODE_POST_INIT)) {
3184 				bge_asf_post_reset_old_mode(bgep,
3185 					BGE_INIT_RESET);
3186 			} else {
3187 				bge_asf_post_reset_old_mode(bgep,
3188 					BGE_SHUTDOWN_RESET);
3189 			}
3190 		}
3191 #endif
3192 
3193 		/* Wait for NVRAM init */
3194 		i = 0;
3195 		drv_usecwait(5000);
3196 		mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX);
3197 
3198 		while ((mailbox != (uint32_t)
3199 			~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) &&
3200 			(i < 10000)) {
3201 			drv_usecwait(100);
3202 			mailbox = bge_nic_get32(bgep,
3203 				BGE_FIRMWARE_MAILBOX);
3204 			i++;
3205 		}
3206 
3207 #ifndef BGE_NETCONSOLE
3208 		if (!bgep->asf_newhandshake) {
3209 			if ((asf_mode == ASF_MODE_INIT) ||
3210 				(asf_mode == ASF_MODE_POST_INIT)) {
3211 
3212 				bge_asf_post_reset_old_mode(bgep,
3213 					BGE_INIT_RESET);
3214 			} else {
3215 				bge_asf_post_reset_old_mode(bgep,
3216 					BGE_SHUTDOWN_RESET);
3217 			}
3218 		}
3219 #endif
3220 	}
3221 #endif
3222 	/*
3223 	 * Steps 16-17: poll for firmware completion
3224 	 */
3225 	mac = bge_poll_firmware(bgep);
3226 
3227 	/*
3228 	 * Step 18: enable external memory -- doesn't apply.
3229 	 *
3230 	 * However we take the opportunity to set the MLCR anyway, as
3231 	 * this register also controls the SEEPROM auto-access method
3232 	 * which we may want to use later ...
3233 	 *
3234 	 * The proper value here depends on the way the chip is wired
3235 	 * into the circuit board, as this register *also* controls which
3236 	 * of the "Miscellaneous I/O" pins are driven as outputs and the
3237 	 * values driven onto those pins!
3238 	 *
3239 	 * See also step 74 in the PRM ...
3240 	 */
3241 	bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG,
3242 	    bgep->chipid.bge_mlcr_default);
3243 	bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT);
3244 
3245 	/*
3246 	 * Step 20: clear the Ethernet MAC mode register
3247 	 */
3248 	bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0);
3249 
3250 	/*
3251 	 * Step 21: restore cache-line-size, latency timer, and
3252 	 * subsystem ID registers to their original values (not
3253 	 * those read into the local structure <chipid>, 'cos
3254 	 * that was after they were cleared by the RESET).
3255 	 *
3256 	 * Note: the Subsystem Vendor/Device ID registers are not
3257 	 * directly writable in config space, so we use the shadow
3258 	 * copy in "Page Zero" of register space to restore them
3259 	 * both in one go ...
3260 	 */
3261 	pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ,
3262 		bgep->chipid.clsize);
3263 	pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER,
3264 		bgep->chipid.latency);
3265 	bge_reg_put32(bgep, PCI_CONF_SUBVENID,
3266 		(bgep->chipid.subdev << 16) | bgep->chipid.subven);
3267 
3268 	/*
3269 	 * The SEND INDEX registers should be reset to zero by the
3270 	 * global chip reset; if they're not, there'll be trouble
3271 	 * later on.
3272 	 */
3273 	sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0));
3274 	if (sx0 != 0) {
3275 		BGE_REPORT((bgep, "SEND INDEX - device didn't RESET"));
3276 		bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE);
3277 		retval = DDI_FAILURE;
3278 	}
3279 
3280 	/* Enable MSI code */
3281 	if (bgep->intr_type == DDI_INTR_TYPE_MSI)
3282 		bge_reg_set32(bgep, MSI_MODE_REG,
3283 		    MSI_PRI_HIGHEST|MSI_MSI_ENABLE|MSI_ERROR_ATTENTION);
3284 
3285 	/*
3286 	 * On the first time through, save the factory-set MAC address
3287 	 * (if any).  If bge_poll_firmware() above didn't return one
3288 	 * (from a chip register) consider looking in the attached NV
3289 	 * memory device, if any.  Once we have it, we save it in both
3290 	 * register-image (64-bit) and byte-array forms.  All-zero and
3291 	 * all-one addresses are not valid, and we refuse to stash those.
3292 	 */
3293 	if (bgep->bge_chip_state == BGE_CHIP_INITIAL) {
3294 		if (mac == 0ULL)
3295 			mac = bge_get_nvmac(bgep);
3296 		if (mac != 0ULL && mac != ~0ULL) {
3297 			bgep->chipid.hw_mac_addr = mac;
3298 			for (i = ETHERADDRL; i-- != 0; ) {
3299 				bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac;
3300 				mac >>= 8;
3301 			}
3302 			bgep->chipid.vendor_addr.set = B_TRUE;
3303 		}
3304 	}
3305 
3306 #ifdef BGE_IPMI_ASF
3307 	if (bgep->asf_enabled && bgep->asf_newhandshake) {
3308 		if (asf_mode != ASF_MODE_NONE) {
3309 			if ((asf_mode == ASF_MODE_INIT) ||
3310 				(asf_mode == ASF_MODE_POST_INIT)) {
3311 
3312 				bge_asf_post_reset_new_mode(bgep,
3313 					BGE_INIT_RESET);
3314 			} else {
3315 				bge_asf_post_reset_new_mode(bgep,
3316 					BGE_SHUTDOWN_RESET);
3317 			}
3318 		}
3319 	}
3320 #endif
3321 
3322 	/*
3323 	 * Record the new state
3324 	 */
3325 	bgep->chip_resets += 1;
3326 	bgep->bge_chip_state = BGE_CHIP_RESET;
3327 	return (retval);
3328 }
3329 
3330 /*
3331  * bge_chip_start() -- start the chip transmitting and/or receiving,
3332  * including enabling interrupts
3333  */
3334 int bge_chip_start(bge_t *bgep, boolean_t reset_phys);
3335 #pragma	no_inline(bge_chip_start)
3336 
3337 int
3338 bge_chip_start(bge_t *bgep, boolean_t reset_phys)
3339 {
3340 	uint32_t coalmode;
3341 	uint32_t ledctl;
3342 	uint32_t mtu;
3343 	uint32_t maxring;
3344 	uint32_t stats_mask;
3345 	uint32_t dma_wrprio;
3346 	uint64_t ring;
3347 	int retval = DDI_SUCCESS;
3348 
3349 	BGE_TRACE(("bge_chip_start($%p)",
3350 	    (void *)bgep));
3351 
3352 	ASSERT(mutex_owned(bgep->genlock));
3353 	ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET);
3354 
3355 	/*
3356 	 * Taken from Broadcom document 570X-PG102-R, pp 102-116.
3357 	 * The document specifies 95 separate steps to fully
3358 	 * initialise the chip!!!!
3359 	 *
3360 	 * The reset code above has already got us as far as step
3361 	 * 21, so we continue with ...
3362 	 *
3363 	 * Step 22: clear the MAC statistics block
3364 	 * (0x0300-0x0aff in NIC-local memory)
3365 	 */
3366 	if (bgep->chipid.statistic_type == BGE_STAT_BLK)
3367 		bge_nic_zero(bgep, NIC_MEM_STATISTICS,
3368 		    NIC_MEM_STATISTICS_SIZE);
3369 
3370 	/*
3371 	 * Step 23: clear the status block (in host memory)
3372 	 */
3373 	DMA_ZERO(bgep->status_block);
3374 
3375 	/*
3376 	 * Step 24: set DMA read/write control register
3377 	 */
3378 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR,
3379 	    bgep->chipid.bge_dma_rwctrl);
3380 
3381 	/*
3382 	 * Step 25: Configure DMA endianness -- already done (16/17)
3383 	 * Step 26: Configure Host-Based Send Rings
3384 	 * Step 27: Indicate Host Stack Up
3385 	 */
3386 	bge_reg_set32(bgep, MODE_CONTROL_REG,
3387 	    MODE_HOST_SEND_BDS |
3388 	    MODE_HOST_STACK_UP);
3389 
3390 	/*
3391 	 * Step 28: Configure checksum options:
3392 	 *	Solaris supports the hardware default checksum options.
3393 	 *
3394 	 *	Workaround for Incorrect pseudo-header checksum calculation.
3395 	 */
3396 	if (bgep->chipid.flags & CHIP_FLAG_PARTIAL_CSUM)
3397 		bge_reg_set32(bgep, MODE_CONTROL_REG,
3398 		    MODE_SEND_NO_PSEUDO_HDR_CSUM);
3399 
3400 	/*
3401 	 * Step 29: configure Timer Prescaler.  The value is always the
3402 	 * same: the Core Clock frequency in MHz (66), minus 1, shifted
3403 	 * into bits 7-1.  Don't set bit 0, 'cos that's the RESET bit
3404 	 * for the whole chip!
3405 	 */
3406 	bge_reg_put32(bgep, MISC_CONFIG_REG, MISC_CONFIG_DEFAULT);
3407 
3408 	/*
3409 	 * Steps 30-31: Configure MAC local memory pool & DMA pool registers
3410 	 *
3411 	 * If the mbuf_length is specified as 0, we just leave these at
3412 	 * their hardware defaults, rather than explicitly setting them.
3413 	 * As the Broadcom HRM,driver better not change the parameters
3414 	 * when the chipsets is 5705/5788/5721/5751/5714 and 5715.
3415 	 */
3416 	if ((bgep->chipid.mbuf_length != 0) &&
3417 	    (DEVICE_5704_SERIES_CHIPSETS(bgep))) {
3418 			bge_reg_put32(bgep, MBUF_POOL_BASE_REG,
3419 			    bgep->chipid.mbuf_base);
3420 			bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG,
3421 			    bgep->chipid.mbuf_length);
3422 			bge_reg_put32(bgep, DMAD_POOL_BASE_REG,
3423 			    DMAD_POOL_BASE_DEFAULT);
3424 			bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG,
3425 			    DMAD_POOL_LENGTH_DEFAULT);
3426 	}
3427 
3428 	/*
3429 	 * Step 32: configure MAC memory pool watermarks
3430 	 */
3431 	bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG,
3432 	    bgep->chipid.mbuf_lo_water_rdma);
3433 	bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG,
3434 	    bgep->chipid.mbuf_lo_water_rmac);
3435 	bge_reg_put32(bgep, MBUF_HIWAT_REG,
3436 	    bgep->chipid.mbuf_hi_water);
3437 
3438 	/*
3439 	 * Step 33: configure DMA resource watermarks
3440 	 */
3441 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3442 		bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG,
3443 		    bge_dmad_lo_water);
3444 		bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG,
3445 		    bge_dmad_hi_water);
3446 	}
3447 	bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames);
3448 
3449 	/*
3450 	 * Steps 34-36: enable buffer manager & internal h/w queues
3451 	 */
3452 	if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG,
3453 	    STATE_MACHINE_ATTN_ENABLE_BIT))
3454 		retval = DDI_FAILURE;
3455 	if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0))
3456 		retval = DDI_FAILURE;
3457 
3458 	/*
3459 	 * Steps 37-39: initialise Receive Buffer (Producer) RCBs
3460 	 */
3461 	bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG,
3462 	    &bgep->buff[BGE_STD_BUFF_RING].hw_rcb);
3463 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3464 		bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG,
3465 		    &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb);
3466 		bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG,
3467 		    &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb);
3468 	}
3469 
3470 	/*
3471 	 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds
3472 	 */
3473 	bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std);
3474 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3475 		bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG,
3476 		    bge_replenish_jumbo);
3477 		bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG,
3478 		    bge_replenish_mini);
3479 	}
3480 
3481 	/*
3482 	 * Steps 41-43: clear Send Ring Producer Indices and initialise
3483 	 * Send Producer Rings (0x0100-0x01ff in NIC-local memory)
3484 	 */
3485 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
3486 		maxring = BGE_SEND_RINGS_MAX;
3487 	else
3488 		maxring = BGE_SEND_RINGS_MAX_5705;
3489 	for (ring = 0; ring < maxring; ++ring) {
3490 		bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0);
3491 		bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0);
3492 		bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring),
3493 		    &bgep->send[ring].hw_rcb);
3494 	}
3495 
3496 	/*
3497 	 * Steps 44-45: initialise Receive Return Rings
3498 	 * (0x0200-0x02ff in NIC-local memory)
3499 	 */
3500 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
3501 		maxring = BGE_RECV_RINGS_MAX;
3502 	else
3503 		maxring = BGE_RECV_RINGS_MAX_5705;
3504 	for (ring = 0; ring < maxring; ++ring)
3505 		bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring),
3506 		    &bgep->recv[ring].hw_rcb);
3507 
3508 	/*
3509 	 * Step 46: initialise Receive Buffer (Producer) Ring indexes
3510 	 */
3511 	bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0);
3512 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3513 		bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0);
3514 		bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0);
3515 	}
3516 	/*
3517 	 * Step 47: configure the MAC unicast address
3518 	 * Step 48: configure the random backoff seed
3519 	 * Step 96: set up multicast filters
3520 	 */
3521 #ifdef BGE_IPMI_ASF
3522 	if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE)
3523 #else
3524 	if (bge_chip_sync(bgep) == DDI_FAILURE)
3525 #endif
3526 		retval = DDI_FAILURE;
3527 
3528 	/*
3529 	 * Step 49: configure the MTU
3530 	 */
3531 	mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ;
3532 	bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu);
3533 
3534 	/*
3535 	 * Step 50: configure the IPG et al
3536 	 */
3537 	bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT);
3538 
3539 	/*
3540 	 * Step 51: configure the default Rx Return Ring
3541 	 */
3542 	bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT);
3543 
3544 	/*
3545 	 * Steps 52-54: configure Receive List Placement,
3546 	 * and enable Receive List Placement Statistics
3547 	 */
3548 	bge_reg_put32(bgep, RCV_LP_CONFIG_REG,
3549 	    RCV_LP_CONFIG(bgep->chipid.rx_rings));
3550 	switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) {
3551 	case MHCR_CHIP_ASIC_REV_5700:
3552 	case MHCR_CHIP_ASIC_REV_5701:
3553 	case MHCR_CHIP_ASIC_REV_5703:
3554 	case MHCR_CHIP_ASIC_REV_5704:
3555 		bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0);
3556 		break;
3557 	case MHCR_CHIP_ASIC_REV_5705:
3558 		break;
3559 	default:
3560 		stats_mask = bge_reg_get32(bgep, RCV_LP_STATS_ENABLE_MASK_REG);
3561 		stats_mask &= ~RCV_LP_STATS_DISABLE_MACTQ;
3562 		bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, stats_mask);
3563 		break;
3564 	}
3565 	bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE);
3566 
3567 	if (bgep->chipid.rx_rings > 1)
3568 		bge_init_recv_rule(bgep);
3569 
3570 	/*
3571 	 * Steps 55-56: enable Send Data Initiator Statistics
3572 	 */
3573 	bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0);
3574 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3575 		bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG,
3576 		    SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER);
3577 	} else {
3578 		bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG,
3579 		    SEND_INIT_STATS_ENABLE);
3580 	}
3581 	/*
3582 	 * Steps 57-58: stop (?) the Host Coalescing Engine
3583 	 */
3584 	if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0))
3585 		retval = DDI_FAILURE;
3586 
3587 	/*
3588 	 * Steps 59-62: initialise Host Coalescing parameters
3589 	 */
3590 	bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG, bge_tx_count_norm);
3591 	bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG, bge_tx_ticks_norm);
3592 	bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, bge_rx_count_norm);
3593 	bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, bge_rx_ticks_norm);
3594 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3595 		bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG,
3596 		    bge_tx_count_intr);
3597 		bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG,
3598 		    bge_tx_ticks_intr);
3599 		bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG,
3600 		    bge_rx_count_intr);
3601 		bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG,
3602 		    bge_rx_ticks_intr);
3603 	}
3604 
3605 	/*
3606 	 * Steps 63-64: initialise status block & statistics
3607 	 * host memory addresses
3608 	 * The statistic block does not exist in some chipsets
3609 	 * Step 65: initialise Statistics Coalescing Tick Counter
3610 	 */
3611 	bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG,
3612 	    bgep->status_block.cookie.dmac_laddress);
3613 
3614 	/*
3615 	 * Steps 66-67: initialise status block & statistics
3616 	 * NIC-local memory addresses
3617 	 */
3618 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3619 		bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG,
3620 		    bgep->statistics.cookie.dmac_laddress);
3621 		bge_reg_put32(bgep, STATISTICS_TICKS_REG,
3622 		    STATISTICS_TICKS_DEFAULT);
3623 		bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG,
3624 		    NIC_MEM_STATUS_BLOCK);
3625 		bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG,
3626 		    NIC_MEM_STATISTICS);
3627 	}
3628 
3629 	/*
3630 	 * Steps 68-71: start the Host Coalescing Engine, the Receive BD
3631 	 * Completion Engine, the Receive List Placement Engine, and the
3632 	 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714
3633 	 * and BCM5715.
3634 	 */
3635 	if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS &&
3636 	    bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS)
3637 		coalmode = COALESCE_64_BYTE_STATUS;
3638 	else
3639 		coalmode = 0;
3640 	if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode))
3641 		retval = DDI_FAILURE;
3642 	if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG,
3643 	    STATE_MACHINE_ATTN_ENABLE_BIT))
3644 		retval = DDI_FAILURE;
3645 	if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0))
3646 		retval = DDI_FAILURE;
3647 
3648 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
3649 		if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG,
3650 		    STATE_MACHINE_ATTN_ENABLE_BIT))
3651 			retval = DDI_FAILURE;
3652 
3653 	/*
3654 	 * Step 72: Enable MAC DMA engines
3655 	 * Step 73: Clear & enable MAC statistics
3656 	 */
3657 	bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG,
3658 	    ETHERNET_MODE_ENABLE_FHDE |
3659 	    ETHERNET_MODE_ENABLE_RDE |
3660 	    ETHERNET_MODE_ENABLE_TDE);
3661 	bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG,
3662 	    ETHERNET_MODE_ENABLE_TX_STATS |
3663 	    ETHERNET_MODE_ENABLE_RX_STATS |
3664 	    ETHERNET_MODE_CLEAR_TX_STATS |
3665 	    ETHERNET_MODE_CLEAR_RX_STATS);
3666 
3667 	/*
3668 	 * Step 74: configure the MLCR (Miscellaneous Local Control
3669 	 * Register); not required, as we set up the MLCR in step 10
3670 	 * (part of the reset code) above.
3671 	 *
3672 	 * Step 75: clear Interrupt Mailbox 0
3673 	 */
3674 	bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0);
3675 
3676 	/*
3677 	 * Steps 76-87: Gentlemen, start your engines ...
3678 	 *
3679 	 * Enable the DMA Completion Engine, the Write DMA Engine,
3680 	 * the Read DMA Engine, Receive Data Completion Engine,
3681 	 * the MBuf Cluster Free Engine, the Send Data Completion Engine,
3682 	 * the Send BD Completion Engine, the Receive BD Initiator Engine,
3683 	 * the Receive Data Initiator Engine, the Send Data Initiator Engine,
3684 	 * the Send BD Initiator Engine, and the Send BD Selector Engine.
3685 	 *
3686 	 * Beware exhaust fumes?
3687 	 */
3688 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
3689 		if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0))
3690 			retval = DDI_FAILURE;
3691 	dma_wrprio = (bge_dma_wrprio << DMA_PRIORITY_SHIFT) |
3692 	    ALL_DMA_ATTN_BITS;
3693 	if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
3694 	    MHCR_CHIP_ASIC_REV_5755) {
3695 		dma_wrprio |= DMA_STATUS_TAG_FIX_CQ12384;
3696 	}
3697 	if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG,
3698 	    dma_wrprio))
3699 		retval = DDI_FAILURE;
3700 	if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG,
3701 	    (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS))
3702 		retval = DDI_FAILURE;
3703 	if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG,
3704 	    STATE_MACHINE_ATTN_ENABLE_BIT))
3705 		retval = DDI_FAILURE;
3706 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
3707 		if (!bge_chip_enable_engine(bgep,
3708 		    MBUF_CLUSTER_FREE_MODE_REG, 0))
3709 			retval = DDI_FAILURE;
3710 	if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0))
3711 		retval = DDI_FAILURE;
3712 	if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG,
3713 	    STATE_MACHINE_ATTN_ENABLE_BIT))
3714 		retval = DDI_FAILURE;
3715 	if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG,
3716 	    RCV_BD_DISABLED_RING_ATTN))
3717 		retval = DDI_FAILURE;
3718 	if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG,
3719 	    RCV_DATA_BD_ILL_RING_ATTN))
3720 		retval = DDI_FAILURE;
3721 	if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0))
3722 		retval = DDI_FAILURE;
3723 	if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG,
3724 	    STATE_MACHINE_ATTN_ENABLE_BIT))
3725 		retval = DDI_FAILURE;
3726 	if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG,
3727 	    STATE_MACHINE_ATTN_ENABLE_BIT))
3728 		retval = DDI_FAILURE;
3729 
3730 	/*
3731 	 * Step 88: download firmware -- doesn't apply
3732 	 * Steps 89-90: enable Transmit & Receive MAC Engines
3733 	 */
3734 	if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0))
3735 		retval = DDI_FAILURE;
3736 #ifdef BGE_IPMI_ASF
3737 	if (!bgep->asf_enabled) {
3738 		if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG,
3739 		    RECEIVE_MODE_KEEP_VLAN_TAG))
3740 			retval = DDI_FAILURE;
3741 	} else {
3742 		if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0))
3743 			retval = DDI_FAILURE;
3744 	}
3745 #else
3746 	if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG,
3747 	    RECEIVE_MODE_KEEP_VLAN_TAG))
3748 		retval = DDI_FAILURE;
3749 #endif
3750 
3751 	/*
3752 	 * Step 91: disable auto-polling of PHY status
3753 	 */
3754 	bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT);
3755 
3756 	/*
3757 	 * Step 92: configure D0 power state (not required)
3758 	 * Step 93: initialise LED control register ()
3759 	 */
3760 	ledctl = LED_CONTROL_DEFAULT;
3761 	switch (bgep->chipid.device) {
3762 	case DEVICE_ID_5700:
3763 	case DEVICE_ID_5700x:
3764 	case DEVICE_ID_5701:
3765 		/*
3766 		 * Switch to 5700 (MAC) mode on these older chips
3767 		 */
3768 		ledctl &= ~LED_CONTROL_LED_MODE_MASK;
3769 		ledctl |= LED_CONTROL_LED_MODE_5700;
3770 		break;
3771 
3772 	default:
3773 		break;
3774 	}
3775 	bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl);
3776 
3777 	/*
3778 	 * Step 94: activate link
3779 	 */
3780 	bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK);
3781 
3782 	/*
3783 	 * Step 95: set up physical layer (PHY/SerDes)
3784 	 * restart autoneg (if required)
3785 	 */
3786 	if (reset_phys)
3787 		if (bge_phys_update(bgep) == DDI_FAILURE)
3788 			retval = DDI_FAILURE;
3789 
3790 	/*
3791 	 * Extra step (DSG): hand over all the Receive Buffers to the chip
3792 	 */
3793 	for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring)
3794 		bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg,
3795 		    bgep->buff[ring].rf_next);
3796 
3797 	/*
3798 	 * MSI bits:The least significant MSI 16-bit word.
3799 	 * ISR will be triggered different.
3800 	 */
3801 	if (bgep->intr_type == DDI_INTR_TYPE_MSI)
3802 		bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70);
3803 
3804 	/*
3805 	 * Extra step (DSG): select which interrupts are enabled
3806 	 *
3807 	 * Program the Ethernet MAC engine to signal attention on
3808 	 * Link Change events, then enable interrupts on MAC, DMA,
3809 	 * and FLOW attention signals.
3810 	 */
3811 	bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG,
3812 	    ETHERNET_EVENT_LINK_INT |
3813 	    ETHERNET_STATUS_PCS_ERROR_INT);
3814 #ifdef BGE_IPMI_ASF
3815 	if (bgep->asf_enabled) {
3816 		bge_reg_set32(bgep, MODE_CONTROL_REG,
3817 		    MODE_INT_ON_FLOW_ATTN |
3818 		    MODE_INT_ON_DMA_ATTN |
3819 		    MODE_HOST_STACK_UP|
3820 		    MODE_INT_ON_MAC_ATTN);
3821 	} else {
3822 #endif
3823 		bge_reg_set32(bgep, MODE_CONTROL_REG,
3824 		    MODE_INT_ON_FLOW_ATTN |
3825 		    MODE_INT_ON_DMA_ATTN |
3826 		    MODE_INT_ON_MAC_ATTN);
3827 #ifdef BGE_IPMI_ASF
3828 	}
3829 #endif
3830 
3831 	/*
3832 	 * Step 97: enable PCI interrupts!!!
3833 	 */
3834 	if (bgep->intr_type == DDI_INTR_TYPE_FIXED)
3835 		bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR,
3836 		    MHCR_MASK_PCI_INT_OUTPUT);
3837 
3838 	/*
3839 	 * All done!
3840 	 */
3841 	bgep->bge_chip_state = BGE_CHIP_RUNNING;
3842 	return (retval);
3843 }
3844 
3845 
3846 /*
3847  * ========== Hardware interrupt handler ==========
3848  */
3849 
3850 #undef	BGE_DBG
3851 #define	BGE_DBG		BGE_DBG_INT	/* debug flag for this code	*/
3852 
3853 /*
3854  * Sync the status block, then atomically clear the specified bits in
3855  * the <flags-and-tag> field of the status block.
3856  * the <flags> word of the status block, returning the value of the
3857  * <tag> and the <flags> before the bits were cleared.
3858  */
3859 static int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags);
3860 #pragma	inline(bge_status_sync)
3861 
3862 static int
3863 bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags)
3864 {
3865 	bge_status_t *bsp;
3866 	int retval;
3867 
3868 	BGE_TRACE(("bge_status_sync($%p, 0x%llx)",
3869 	    (void *)bgep, bits));
3870 
3871 	ASSERT(bgep->bge_guard == BGE_GUARD);
3872 
3873 	DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL);
3874 	retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl);
3875 	if (retval != DDI_FM_OK)
3876 		return (retval);
3877 
3878 	bsp = DMA_VPTR(bgep->status_block);
3879 	*flags = bge_atomic_clr64(&bsp->flags_n_tag, bits);
3880 
3881 	BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx",
3882 	    (void *)bgep, bits, *flags));
3883 
3884 	return (retval);
3885 }
3886 
3887 void bge_wake_factotum(bge_t *bgep);
3888 #pragma	inline(bge_wake_factotum)
3889 
3890 void
3891 bge_wake_factotum(bge_t *bgep)
3892 {
3893 	mutex_enter(bgep->softintrlock);
3894 	if (bgep->factotum_flag == 0) {
3895 		bgep->factotum_flag = 1;
3896 		ddi_trigger_softintr(bgep->factotum_id);
3897 	}
3898 	mutex_exit(bgep->softintrlock);
3899 }
3900 
3901 /*
3902  *	bge_intr() -- handle chip interrupts
3903  */
3904 uint_t bge_intr(caddr_t arg1, caddr_t arg2);
3905 #pragma	no_inline(bge_intr)
3906 
3907 uint_t
3908 bge_intr(caddr_t arg1, caddr_t arg2)
3909 {
3910 	bge_t *bgep = (void *)arg1;		/* private device info	*/
3911 	bge_status_t *bsp;
3912 	uint64_t flags;
3913 	uint32_t regval;
3914 	uint_t result;
3915 	int retval, loop_cnt = 0;
3916 
3917 	BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2));
3918 
3919 	/*
3920 	 * GLD v2 checks that s/w setup is complete before passing
3921 	 * interrupts to this routine, thus eliminating the old
3922 	 * (and well-known) race condition around ddi_add_intr()
3923 	 */
3924 	ASSERT(bgep->progress & PROGRESS_HWINT);
3925 
3926 	result = DDI_INTR_UNCLAIMED;
3927 	mutex_enter(bgep->genlock);
3928 
3929 	if (bgep->intr_type == DDI_INTR_TYPE_FIXED) {
3930 		/*
3931 		 * Check whether chip's says it's asserting #INTA;
3932 		 * if not, don't process or claim the interrupt.
3933 		 *
3934 		 * Note that the PCI signal is active low, so the
3935 		 * bit is *zero* when the interrupt is asserted.
3936 		 */
3937 		regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG);
3938 		if (regval & MLCR_INTA_STATE) {
3939 			if (bge_check_acc_handle(bgep, bgep->io_handle)
3940 			    != DDI_FM_OK)
3941 				goto chip_stop;
3942 			mutex_exit(bgep->genlock);
3943 			return (result);
3944 		}
3945 
3946 		/*
3947 		 * Block further PCI interrupts ...
3948 		 */
3949 		bge_reg_set32(bgep, PCI_CONF_BGE_MHCR,
3950 		    MHCR_MASK_PCI_INT_OUTPUT);
3951 
3952 	} else {
3953 		/*
3954 		 * Check MSI status
3955 		 */
3956 		regval = bge_reg_get32(bgep, MSI_STATUS_REG);
3957 		if (regval & MSI_ERROR_ATTENTION) {
3958 			BGE_REPORT((bgep, "msi error attention,"
3959 			    " status=0x%x", regval));
3960 			bge_reg_put32(bgep, MSI_STATUS_REG, regval);
3961 		}
3962 	}
3963 
3964 	result = DDI_INTR_CLAIMED;
3965 
3966 	BGE_DEBUG(("bge_intr($%p) ($%p) regval 0x%08x", arg1, arg2, regval));
3967 
3968 	/*
3969 	 * Sync the status block and grab the flags-n-tag from it.
3970 	 * We count the number of interrupts where there doesn't
3971 	 * seem to have been a DMA update of the status block; if
3972 	 * it *has* been updated, the counter will be cleared in
3973 	 * the while() loop below ...
3974 	 */
3975 	bgep->missed_dmas += 1;
3976 	bsp = DMA_VPTR(bgep->status_block);
3977 	for (loop_cnt = 0; loop_cnt < bge_intr_max_loop; loop_cnt++) {
3978 		if (bgep->bge_chip_state != BGE_CHIP_RUNNING) {
3979 			/*
3980 			 * bge_chip_stop() may have freed dma area etc
3981 			 * while we were in this interrupt handler -
3982 			 * better not call bge_status_sync()
3983 			 */
3984 			(void) bge_check_acc_handle(bgep,
3985 			    bgep->io_handle);
3986 			mutex_exit(bgep->genlock);
3987 			return (DDI_INTR_CLAIMED);
3988 		}
3989 		retval = bge_status_sync(bgep, STATUS_FLAG_UPDATED,
3990 		    &flags);
3991 		if (retval != DDI_FM_OK) {
3992 			bgep->bge_dma_error = B_TRUE;
3993 			goto chip_stop;
3994 		}
3995 
3996 		if (!(flags & STATUS_FLAG_UPDATED))
3997 			break;
3998 
3999 		/*
4000 		 * Tell the chip that we're processing the interrupt
4001 		 */
4002 		bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG,
4003 		    INTERRUPT_MBOX_DISABLE(flags));
4004 		if (bge_check_acc_handle(bgep, bgep->io_handle) !=
4005 		    DDI_FM_OK)
4006 			goto chip_stop;
4007 
4008 		/*
4009 		 * Drop the mutex while we:
4010 		 * 	Receive any newly-arrived packets
4011 		 *	Recycle any newly-finished send buffers
4012 		 */
4013 		bgep->bge_intr_running = B_TRUE;
4014 		mutex_exit(bgep->genlock);
4015 		bge_receive(bgep, bsp);
4016 		bge_recycle(bgep, bsp);
4017 		mutex_enter(bgep->genlock);
4018 		bgep->bge_intr_running = B_FALSE;
4019 
4020 		/*
4021 		 * Tell the chip we've finished processing, and
4022 		 * give it the tag that we got from the status
4023 		 * block earlier, so that it knows just how far
4024 		 * we've gone.  If it's got more for us to do,
4025 		 * it will now update the status block and try
4026 		 * to assert an interrupt (but we've got the
4027 		 * #INTA blocked at present).  If we see the
4028 		 * update, we'll loop around to do some more.
4029 		 * Eventually we'll get out of here ...
4030 		 */
4031 		bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG,
4032 		    INTERRUPT_MBOX_ENABLE(flags));
4033 		if (bgep->chipid.pci_type == BGE_PCI_E)
4034 			(void) bge_mbx_get(bgep, INTERRUPT_MBOX_0_REG);
4035 		bgep->missed_dmas = 0;
4036 	}
4037 
4038 	/*
4039 	 * Check for exceptional conditions that we need to handle
4040 	 *
4041 	 * Link status changed
4042 	 * Status block not updated
4043 	 */
4044 	if (flags & STATUS_FLAG_LINK_CHANGED)
4045 		bge_wake_factotum(bgep);
4046 
4047 	if (bgep->missed_dmas) {
4048 		/*
4049 		 * Probably due to the internal status tag not
4050 		 * being reset.  Force a status block update now;
4051 		 * this should ensure that we get an update and
4052 		 * a new interrupt.  After that, we should be in
4053 		 * sync again ...
4054 		 */
4055 		BGE_REPORT((bgep, "interrupt: flags 0x%llx - "
4056 		    "not updated?", flags));
4057 		bgep->missed_updates++;
4058 		bge_reg_set32(bgep, HOST_COALESCE_MODE_REG,
4059 		    COALESCE_NOW);
4060 
4061 		if (bgep->missed_dmas >= bge_dma_miss_limit) {
4062 			/*
4063 			 * If this happens multiple times in a row,
4064 			 * it means DMA is just not working.  Maybe
4065 			 * the chip's failed, or maybe there's a
4066 			 * problem on the PCI bus or in the host-PCI
4067 			 * bridge (Tomatillo).
4068 			 *
4069 			 * At all events, we want to stop further
4070 			 * interrupts and let the recovery code take
4071 			 * over to see whether anything can be done
4072 			 * about it ...
4073 			 */
4074 			bge_fm_ereport(bgep,
4075 			    DDI_FM_DEVICE_BADINT_LIMIT);
4076 			goto chip_stop;
4077 		}
4078 	}
4079 
4080 	/*
4081 	 * Reenable assertion of #INTA, unless there's a DMA fault
4082 	 */
4083 	if (bgep->intr_type == DDI_INTR_TYPE_FIXED) {
4084 		bge_reg_clr32(bgep, PCI_CONF_BGE_MHCR,
4085 		    MHCR_MASK_PCI_INT_OUTPUT);
4086 		if (bge_check_acc_handle(bgep, bgep->cfg_handle) !=
4087 		    DDI_FM_OK)
4088 			goto chip_stop;
4089 	}
4090 
4091 	if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
4092 		goto chip_stop;
4093 
4094 	mutex_exit(bgep->genlock);
4095 	return (result);
4096 
4097 chip_stop:
4098 #ifdef BGE_IPMI_ASF
4099 	if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) {
4100 		/*
4101 		 * We must stop ASF heart beat before
4102 		 * bge_chip_stop(), otherwise some
4103 		 * computers (ex. IBM HS20 blade
4104 		 * server) may crash.
4105 		 */
4106 		bge_asf_update_status(bgep);
4107 		bge_asf_stop_timer(bgep);
4108 		bgep->asf_status = ASF_STAT_STOP;
4109 
4110 		bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET);
4111 		(void) bge_check_acc_handle(bgep, bgep->cfg_handle);
4112 	}
4113 #endif
4114 	bge_chip_stop(bgep, B_TRUE);
4115 	(void) bge_check_acc_handle(bgep, bgep->io_handle);
4116 	mutex_exit(bgep->genlock);
4117 	return (result);
4118 }
4119 
4120 /*
4121  * ========== Factotum, implemented as a softint handler ==========
4122  */
4123 
4124 #undef	BGE_DBG
4125 #define	BGE_DBG		BGE_DBG_FACT	/* debug flag for this code	*/
4126 
4127 static void bge_factotum_error_handler(bge_t *bgep);
4128 #pragma	no_inline(bge_factotum_error_handler)
4129 
4130 static void
4131 bge_factotum_error_handler(bge_t *bgep)
4132 {
4133 	uint32_t flow;
4134 	uint32_t rdma;
4135 	uint32_t wdma;
4136 	uint32_t tmac;
4137 	uint32_t rmac;
4138 	uint32_t rxrs;
4139 	uint32_t txrs = 0;
4140 
4141 	ASSERT(mutex_owned(bgep->genlock));
4142 
4143 	/*
4144 	 * Read all the registers that show the possible
4145 	 * reasons for the ERROR bit to be asserted
4146 	 */
4147 	flow = bge_reg_get32(bgep, FLOW_ATTN_REG);
4148 	rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG);
4149 	wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG);
4150 	tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG);
4151 	rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG);
4152 	rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG);
4153 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4154 		txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG);
4155 
4156 	BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x",
4157 	    (void *)bgep, flow, rdma, wdma));
4158 	BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x",
4159 	    (void *)bgep, tmac, rmac, rxrs, txrs));
4160 
4161 	/*
4162 	 * For now, just clear all the errors ...
4163 	 */
4164 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4165 		bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0);
4166 	bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0);
4167 	bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0);
4168 	bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0);
4169 	bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0);
4170 	bge_reg_put32(bgep, FLOW_ATTN_REG, ~0);
4171 }
4172 
4173 /*
4174  * Handler for hardware link state change.
4175  *
4176  * When this routine is called, the hardware link state has changed
4177  * and the new state is reflected in the param_* variables.  Here
4178  * we must update the softstate and reprogram the MAC to match.
4179  */
4180 static void bge_factotum_link_handler(bge_t *bgep);
4181 #pragma	no_inline(bge_factotum_link_handler)
4182 
4183 static void
4184 bge_factotum_link_handler(bge_t *bgep)
4185 {
4186 	ASSERT(mutex_owned(bgep->genlock));
4187 
4188 	/*
4189 	 * Update the s/w link_state
4190 	 */
4191 	if (bgep->param_link_up)
4192 		bgep->link_state = LINK_STATE_UP;
4193 	else
4194 		bgep->link_state = LINK_STATE_DOWN;
4195 
4196 	/*
4197 	 * Reprogram the MAC modes to match
4198 	 */
4199 	bge_sync_mac_modes(bgep);
4200 }
4201 
4202 static boolean_t bge_factotum_link_check(bge_t *bgep, int *dma_state);
4203 #pragma	no_inline(bge_factotum_link_check)
4204 
4205 static boolean_t
4206 bge_factotum_link_check(bge_t *bgep, int *dma_state)
4207 {
4208 	boolean_t check;
4209 	uint64_t flags;
4210 	uint32_t tmac_status;
4211 
4212 	ASSERT(mutex_owned(bgep->genlock));
4213 
4214 	/*
4215 	 * Get & clear the writable status bits in the Tx status register
4216 	 * (some bits are write-1-to-clear, others are just readonly).
4217 	 */
4218 	tmac_status = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG);
4219 	bge_reg_put32(bgep, TRANSMIT_MAC_STATUS_REG, tmac_status);
4220 
4221 	/*
4222 	 * Get & clear the ERROR and LINK_CHANGED bits from the status block
4223 	 */
4224 	*dma_state = bge_status_sync(bgep, STATUS_FLAG_ERROR |
4225 	    STATUS_FLAG_LINK_CHANGED, &flags);
4226 	if (*dma_state != DDI_FM_OK)
4227 		return (B_FALSE);
4228 
4229 	/*
4230 	 * Clear any errors flagged in the status block ...
4231 	 */
4232 	if (flags & STATUS_FLAG_ERROR)
4233 		bge_factotum_error_handler(bgep);
4234 
4235 	/*
4236 	 * We need to check the link status if:
4237 	 *	the status block says there's been a link change
4238 	 *	or there's any discrepancy between the various
4239 	 *	flags indicating the link state (link_state,
4240 	 *	param_link_up, and the LINK STATE bit in the
4241 	 *	Transmit MAC status register).
4242 	 */
4243 	check = (flags & STATUS_FLAG_LINK_CHANGED) != 0;
4244 	switch (bgep->link_state) {
4245 	case LINK_STATE_UP:
4246 		check |= (bgep->param_link_up == B_FALSE);
4247 		check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) == 0);
4248 		break;
4249 
4250 	case LINK_STATE_DOWN:
4251 		check |= (bgep->param_link_up != B_FALSE);
4252 		check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) != 0);
4253 		break;
4254 
4255 	default:
4256 		check = B_TRUE;
4257 		break;
4258 	}
4259 
4260 	/*
4261 	 * If <check> is false, we're sure the link hasn't changed.
4262 	 * If true, however, it's not yet definitive; we have to call
4263 	 * bge_phys_check() to determine whether the link has settled
4264 	 * into a new state yet ... and if it has, then call the link
4265 	 * state change handler.But when the chip is 5700 in Dell 6650
4266 	 * ,even if check is false, the link may have changed.So we
4267 	 * have to call bge_phys_check() to determine the link state.
4268 	 */
4269 	if (check || bgep->chipid.device == DEVICE_ID_5700) {
4270 		check = bge_phys_check(bgep);
4271 		if (check)
4272 			bge_factotum_link_handler(bgep);
4273 	}
4274 
4275 	return (check);
4276 }
4277 
4278 /*
4279  * Factotum routine to check for Tx stall, using the 'watchdog' counter
4280  */
4281 static boolean_t bge_factotum_stall_check(bge_t *bgep);
4282 #pragma	no_inline(bge_factotum_stall_check)
4283 
4284 static boolean_t
4285 bge_factotum_stall_check(bge_t *bgep)
4286 {
4287 	uint32_t dogval;
4288 
4289 	ASSERT(mutex_owned(bgep->genlock));
4290 
4291 	/*
4292 	 * Specific check for Tx stall ...
4293 	 *
4294 	 * The 'watchdog' counter is incremented whenever a packet
4295 	 * is queued, reset to 1 when some (but not all) buffers
4296 	 * are reclaimed, reset to 0 (disabled) when all buffers
4297 	 * are reclaimed, and shifted left here.  If it exceeds the
4298 	 * threshold value, the chip is assumed to have stalled and
4299 	 * is put into the ERROR state.  The factotum will then reset
4300 	 * it on the next pass.
4301 	 *
4302 	 * All of which should ensure that we don't get into a state
4303 	 * where packets are left pending indefinitely!
4304 	 */
4305 	dogval = bge_atomic_shl32(&bgep->watchdog, 1);
4306 	if (dogval < bge_watchdog_count)
4307 		return (B_FALSE);
4308 
4309 #if !defined(BGE_NETCONSOLE)
4310 	BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval));
4311 #endif
4312 	bge_fm_ereport(bgep, DDI_FM_DEVICE_STALL);
4313 	return (B_TRUE);
4314 }
4315 
4316 /*
4317  * The factotum is woken up when there's something to do that we'd rather
4318  * not do from inside a hardware interrupt handler or high-level cyclic.
4319  * Its two main tasks are:
4320  *	reset & restart the chip after an error
4321  *	check the link status whenever necessary
4322  */
4323 uint_t bge_chip_factotum(caddr_t arg);
4324 #pragma	no_inline(bge_chip_factotum)
4325 
4326 uint_t
4327 bge_chip_factotum(caddr_t arg)
4328 {
4329 	bge_t *bgep;
4330 	uint_t result;
4331 	boolean_t error;
4332 	boolean_t linkchg;
4333 	int dma_state;
4334 
4335 	bgep = (void *)arg;
4336 
4337 	BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep));
4338 
4339 	mutex_enter(bgep->softintrlock);
4340 	if (bgep->factotum_flag == 0) {
4341 		mutex_exit(bgep->softintrlock);
4342 		return (DDI_INTR_UNCLAIMED);
4343 	}
4344 	bgep->factotum_flag = 0;
4345 	mutex_exit(bgep->softintrlock);
4346 
4347 	result = DDI_INTR_CLAIMED;
4348 	error = B_FALSE;
4349 	linkchg = B_FALSE;
4350 
4351 	mutex_enter(bgep->genlock);
4352 	switch (bgep->bge_chip_state) {
4353 	default:
4354 		break;
4355 
4356 	case BGE_CHIP_RUNNING:
4357 		linkchg = bge_factotum_link_check(bgep, &dma_state);
4358 		error = bge_factotum_stall_check(bgep);
4359 		if (dma_state != DDI_FM_OK) {
4360 			bgep->bge_dma_error = B_TRUE;
4361 			error = B_TRUE;
4362 		}
4363 		if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
4364 			error = B_TRUE;
4365 		if (error)
4366 			bgep->bge_chip_state = BGE_CHIP_ERROR;
4367 		break;
4368 
4369 	case BGE_CHIP_ERROR:
4370 		error = B_TRUE;
4371 		break;
4372 
4373 	case BGE_CHIP_FAULT:
4374 		/*
4375 		 * Fault detected, time to reset ...
4376 		 */
4377 		if (bge_autorecover) {
4378 			if (!(bgep->progress & PROGRESS_BUFS)) {
4379 				/*
4380 				 * if we can't allocate the ring buffers,
4381 				 * try later
4382 				 */
4383 				if (bge_alloc_bufs(bgep) != DDI_SUCCESS) {
4384 					mutex_exit(bgep->genlock);
4385 					return (result);
4386 				}
4387 				bgep->progress |= PROGRESS_BUFS;
4388 			}
4389 			if (!(bgep->progress & PROGRESS_INTR)) {
4390 				bge_init_rings(bgep);
4391 				bge_intr_enable(bgep);
4392 				bgep->progress |= PROGRESS_INTR;
4393 			}
4394 			if (!(bgep->progress & PROGRESS_KSTATS)) {
4395 				bge_init_kstats(bgep,
4396 				    ddi_get_instance(bgep->devinfo));
4397 				bgep->progress |= PROGRESS_KSTATS;
4398 			}
4399 
4400 			BGE_REPORT((bgep, "automatic recovery activated"));
4401 
4402 			if (bge_restart(bgep, B_FALSE) != DDI_SUCCESS) {
4403 				bgep->bge_chip_state = BGE_CHIP_ERROR;
4404 				error = B_TRUE;
4405 			}
4406 			if (bge_check_acc_handle(bgep, bgep->cfg_handle) !=
4407 			    DDI_FM_OK) {
4408 				bgep->bge_chip_state = BGE_CHIP_ERROR;
4409 				error = B_TRUE;
4410 			}
4411 			if (bge_check_acc_handle(bgep, bgep->io_handle) !=
4412 			    DDI_FM_OK) {
4413 				bgep->bge_chip_state = BGE_CHIP_ERROR;
4414 				error = B_TRUE;
4415 			}
4416 			if (error == B_FALSE) {
4417 #ifdef BGE_IPMI_ASF
4418 				if (bgep->asf_enabled &&
4419 				    bgep->asf_status != ASF_STAT_RUN) {
4420 					bgep->asf_timeout_id = timeout(
4421 					    bge_asf_heartbeat, (void *)bgep,
4422 					    drv_usectohz(
4423 					    BGE_ASF_HEARTBEAT_INTERVAL));
4424 					bgep->asf_status = ASF_STAT_RUN;
4425 				}
4426 #endif
4427 				if (!bgep->manual_reset) {
4428 					ddi_fm_service_impact(bgep->devinfo,
4429 					    DDI_SERVICE_RESTORED);
4430 				}
4431 			}
4432 		}
4433 		break;
4434 	}
4435 
4436 
4437 	/*
4438 	 * If an error is detected, stop the chip now, marking it as
4439 	 * faulty, so that it will be reset next time through ...
4440 	 *
4441 	 * Note that if intr_running is set, then bge_intr() has dropped
4442 	 * genlock to call bge_receive/bge_recycle. Can't stop the chip at
4443 	 * this point so have to wait until the next time the factotum runs.
4444 	 */
4445 	if (error && !bgep->bge_intr_running) {
4446 #ifdef BGE_IPMI_ASF
4447 		if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) {
4448 			/*
4449 			 * We must stop ASF heart beat before bge_chip_stop(),
4450 			 * otherwise some computers (ex. IBM HS20 blade server)
4451 			 * may crash.
4452 			 */
4453 			bge_asf_update_status(bgep);
4454 			bge_asf_stop_timer(bgep);
4455 			bgep->asf_status = ASF_STAT_STOP;
4456 
4457 			bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET);
4458 			(void) bge_check_acc_handle(bgep, bgep->cfg_handle);
4459 		}
4460 #endif
4461 		bge_chip_stop(bgep, B_TRUE);
4462 		(void) bge_check_acc_handle(bgep, bgep->io_handle);
4463 	}
4464 	mutex_exit(bgep->genlock);
4465 
4466 	/*
4467 	 * If the link state changed, tell the world about it.
4468 	 * Note: can't do this while still holding the mutex.
4469 	 */
4470 	if (bgep->link_update_timer == BGE_LINK_UPDATE_TIMEOUT &&
4471 	    bgep->link_state != LINK_STATE_UNKNOWN)
4472 		linkchg = B_TRUE;
4473 	else if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT &&
4474 	    bgep->link_state == LINK_STATE_DOWN)
4475 		linkchg = B_FALSE;
4476 
4477 	if (linkchg) {
4478 		mac_link_update(bgep->mh, bgep->link_state);
4479 		bgep->link_update_timer = BGE_LINK_UPDATE_DONE;
4480 	}
4481 	if (bgep->manual_reset) {
4482 		bgep->manual_reset = B_FALSE;
4483 	}
4484 
4485 	return (result);
4486 }
4487 
4488 /*
4489  * High-level cyclic handler
4490  *
4491  * This routine schedules a (low-level) softint callback to the
4492  * factotum, and prods the chip to update the status block (which
4493  * will cause a hardware interrupt when complete).
4494  */
4495 void bge_chip_cyclic(void *arg);
4496 #pragma	no_inline(bge_chip_cyclic)
4497 
4498 void
4499 bge_chip_cyclic(void *arg)
4500 {
4501 	bge_t *bgep;
4502 
4503 	bgep = arg;
4504 
4505 	switch (bgep->bge_chip_state) {
4506 	default:
4507 		return;
4508 
4509 	case BGE_CHIP_RUNNING:
4510 		bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW);
4511 		if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
4512 			ddi_fm_service_impact(bgep->devinfo,
4513 			    DDI_SERVICE_UNAFFECTED);
4514 
4515 		if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT)
4516 			bgep->link_update_timer++;
4517 
4518 		break;
4519 
4520 	case BGE_CHIP_FAULT:
4521 	case BGE_CHIP_ERROR:
4522 		break;
4523 	}
4524 
4525 	bge_wake_factotum(bgep);
4526 }
4527 
4528 
4529 /*
4530  * ========== Ioctl subfunctions ==========
4531  */
4532 
4533 #undef	BGE_DBG
4534 #define	BGE_DBG		BGE_DBG_PPIO	/* debug flag for this code	*/
4535 
4536 #if	BGE_DEBUGGING || BGE_DO_PPIO
4537 
4538 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd);
4539 #pragma	no_inline(bge_chip_peek_cfg)
4540 
4541 static void
4542 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd)
4543 {
4544 	uint64_t regval;
4545 	uint64_t regno;
4546 
4547 	BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)",
4548 	    (void *)bgep, (void *)ppd));
4549 
4550 	regno = ppd->pp_acc_offset;
4551 
4552 	switch (ppd->pp_acc_size) {
4553 	case 1:
4554 		regval = pci_config_get8(bgep->cfg_handle, regno);
4555 		break;
4556 
4557 	case 2:
4558 		regval = pci_config_get16(bgep->cfg_handle, regno);
4559 		break;
4560 
4561 	case 4:
4562 		regval = pci_config_get32(bgep->cfg_handle, regno);
4563 		break;
4564 
4565 	case 8:
4566 		regval = pci_config_get64(bgep->cfg_handle, regno);
4567 		break;
4568 	}
4569 
4570 	ppd->pp_acc_data = regval;
4571 }
4572 
4573 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd);
4574 #pragma	no_inline(bge_chip_poke_cfg)
4575 
4576 static void
4577 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd)
4578 {
4579 	uint64_t regval;
4580 	uint64_t regno;
4581 
4582 	BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)",
4583 	    (void *)bgep, (void *)ppd));
4584 
4585 	regno = ppd->pp_acc_offset;
4586 	regval = ppd->pp_acc_data;
4587 
4588 	switch (ppd->pp_acc_size) {
4589 	case 1:
4590 		pci_config_put8(bgep->cfg_handle, regno, regval);
4591 		break;
4592 
4593 	case 2:
4594 		pci_config_put16(bgep->cfg_handle, regno, regval);
4595 		break;
4596 
4597 	case 4:
4598 		pci_config_put32(bgep->cfg_handle, regno, regval);
4599 		break;
4600 
4601 	case 8:
4602 		pci_config_put64(bgep->cfg_handle, regno, regval);
4603 		break;
4604 	}
4605 }
4606 
4607 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd);
4608 #pragma	no_inline(bge_chip_peek_reg)
4609 
4610 static void
4611 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd)
4612 {
4613 	uint64_t regval;
4614 	void *regaddr;
4615 
4616 	BGE_TRACE(("bge_chip_peek_reg($%p, $%p)",
4617 	    (void *)bgep, (void *)ppd));
4618 
4619 	regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset);
4620 
4621 	switch (ppd->pp_acc_size) {
4622 	case 1:
4623 		regval = ddi_get8(bgep->io_handle, regaddr);
4624 		break;
4625 
4626 	case 2:
4627 		regval = ddi_get16(bgep->io_handle, regaddr);
4628 		break;
4629 
4630 	case 4:
4631 		regval = ddi_get32(bgep->io_handle, regaddr);
4632 		break;
4633 
4634 	case 8:
4635 		regval = ddi_get64(bgep->io_handle, regaddr);
4636 		break;
4637 	}
4638 
4639 	ppd->pp_acc_data = regval;
4640 }
4641 
4642 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd);
4643 #pragma	no_inline(bge_chip_peek_reg)
4644 
4645 static void
4646 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd)
4647 {
4648 	uint64_t regval;
4649 	void *regaddr;
4650 
4651 	BGE_TRACE(("bge_chip_poke_reg($%p, $%p)",
4652 	    (void *)bgep, (void *)ppd));
4653 
4654 	regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset);
4655 	regval = ppd->pp_acc_data;
4656 
4657 	switch (ppd->pp_acc_size) {
4658 	case 1:
4659 		ddi_put8(bgep->io_handle, regaddr, regval);
4660 		break;
4661 
4662 	case 2:
4663 		ddi_put16(bgep->io_handle, regaddr, regval);
4664 		break;
4665 
4666 	case 4:
4667 		ddi_put32(bgep->io_handle, regaddr, regval);
4668 		break;
4669 
4670 	case 8:
4671 		ddi_put64(bgep->io_handle, regaddr, regval);
4672 		break;
4673 	}
4674 	BGE_PCICHK(bgep);
4675 }
4676 
4677 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd);
4678 #pragma	no_inline(bge_chip_peek_nic)
4679 
4680 static void
4681 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd)
4682 {
4683 	uint64_t regoff;
4684 	uint64_t regval;
4685 	void *regaddr;
4686 
4687 	BGE_TRACE(("bge_chip_peek_nic($%p, $%p)",
4688 	    (void *)bgep, (void *)ppd));
4689 
4690 	regoff = ppd->pp_acc_offset;
4691 	bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK);
4692 	regoff &= MWBAR_GRANULE_MASK;
4693 	regoff += NIC_MEM_WINDOW_OFFSET;
4694 	regaddr = PIO_ADDR(bgep, regoff);
4695 
4696 	switch (ppd->pp_acc_size) {
4697 	case 1:
4698 		regval = ddi_get8(bgep->io_handle, regaddr);
4699 		break;
4700 
4701 	case 2:
4702 		regval = ddi_get16(bgep->io_handle, regaddr);
4703 		break;
4704 
4705 	case 4:
4706 		regval = ddi_get32(bgep->io_handle, regaddr);
4707 		break;
4708 
4709 	case 8:
4710 		regval = ddi_get64(bgep->io_handle, regaddr);
4711 		break;
4712 	}
4713 
4714 	ppd->pp_acc_data = regval;
4715 }
4716 
4717 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd);
4718 #pragma	no_inline(bge_chip_poke_nic)
4719 
4720 static void
4721 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd)
4722 {
4723 	uint64_t regoff;
4724 	uint64_t regval;
4725 	void *regaddr;
4726 
4727 	BGE_TRACE(("bge_chip_poke_nic($%p, $%p)",
4728 	    (void *)bgep, (void *)ppd));
4729 
4730 	regoff = ppd->pp_acc_offset;
4731 	bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK);
4732 	regoff &= MWBAR_GRANULE_MASK;
4733 	regoff += NIC_MEM_WINDOW_OFFSET;
4734 	regaddr = PIO_ADDR(bgep, regoff);
4735 	regval = ppd->pp_acc_data;
4736 
4737 	switch (ppd->pp_acc_size) {
4738 	case 1:
4739 		ddi_put8(bgep->io_handle, regaddr, regval);
4740 		break;
4741 
4742 	case 2:
4743 		ddi_put16(bgep->io_handle, regaddr, regval);
4744 		break;
4745 
4746 	case 4:
4747 		ddi_put32(bgep->io_handle, regaddr, regval);
4748 		break;
4749 
4750 	case 8:
4751 		ddi_put64(bgep->io_handle, regaddr, regval);
4752 		break;
4753 	}
4754 	BGE_PCICHK(bgep);
4755 }
4756 
4757 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd);
4758 #pragma	no_inline(bge_chip_peek_mii)
4759 
4760 static void
4761 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd)
4762 {
4763 	BGE_TRACE(("bge_chip_peek_mii($%p, $%p)",
4764 	    (void *)bgep, (void *)ppd));
4765 
4766 	ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2);
4767 }
4768 
4769 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd);
4770 #pragma	no_inline(bge_chip_poke_mii)
4771 
4772 static void
4773 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd)
4774 {
4775 	BGE_TRACE(("bge_chip_poke_mii($%p, $%p)",
4776 	    (void *)bgep, (void *)ppd));
4777 
4778 	bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data);
4779 }
4780 
4781 #if	BGE_SEE_IO32
4782 
4783 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd);
4784 #pragma	no_inline(bge_chip_peek_seeprom)
4785 
4786 static void
4787 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd)
4788 {
4789 	uint32_t data;
4790 	int err;
4791 
4792 	BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)",
4793 	    (void *)bgep, (void *)ppd));
4794 
4795 	err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data);
4796 	ppd->pp_acc_data = err ? ~0ull : data;
4797 }
4798 
4799 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd);
4800 #pragma	no_inline(bge_chip_poke_seeprom)
4801 
4802 static void
4803 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd)
4804 {
4805 	uint32_t data;
4806 
4807 	BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)",
4808 	    (void *)bgep, (void *)ppd));
4809 
4810 	data = ppd->pp_acc_data;
4811 	(void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data);
4812 }
4813 #endif	/* BGE_SEE_IO32 */
4814 
4815 #if	BGE_FLASH_IO32
4816 
4817 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd);
4818 #pragma	no_inline(bge_chip_peek_flash)
4819 
4820 static void
4821 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd)
4822 {
4823 	uint32_t data;
4824 	int err;
4825 
4826 	BGE_TRACE(("bge_chip_peek_flash($%p, $%p)",
4827 	    (void *)bgep, (void *)ppd));
4828 
4829 	err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data);
4830 	ppd->pp_acc_data = err ? ~0ull : data;
4831 }
4832 
4833 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd);
4834 #pragma	no_inline(bge_chip_poke_flash)
4835 
4836 static void
4837 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd)
4838 {
4839 	uint32_t data;
4840 
4841 	BGE_TRACE(("bge_chip_poke_flash($%p, $%p)",
4842 	    (void *)bgep, (void *)ppd));
4843 
4844 	data = ppd->pp_acc_data;
4845 	(void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE,
4846 	    ppd->pp_acc_offset, &data);
4847 }
4848 #endif	/* BGE_FLASH_IO32 */
4849 
4850 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd);
4851 #pragma	no_inline(bge_chip_peek_mem)
4852 
4853 static void
4854 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd)
4855 {
4856 	uint64_t regval;
4857 	void *vaddr;
4858 
4859 	BGE_TRACE(("bge_chip_peek_bge($%p, $%p)",
4860 	    (void *)bgep, (void *)ppd));
4861 
4862 	vaddr = (void *)(uintptr_t)ppd->pp_acc_offset;
4863 
4864 	switch (ppd->pp_acc_size) {
4865 	case 1:
4866 		regval = *(uint8_t *)vaddr;
4867 		break;
4868 
4869 	case 2:
4870 		regval = *(uint16_t *)vaddr;
4871 		break;
4872 
4873 	case 4:
4874 		regval = *(uint32_t *)vaddr;
4875 		break;
4876 
4877 	case 8:
4878 		regval = *(uint64_t *)vaddr;
4879 		break;
4880 	}
4881 
4882 	BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p",
4883 	    (void *)bgep, (void *)ppd, regval, vaddr));
4884 
4885 	ppd->pp_acc_data = regval;
4886 }
4887 
4888 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd);
4889 #pragma	no_inline(bge_chip_poke_mem)
4890 
4891 static void
4892 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd)
4893 {
4894 	uint64_t regval;
4895 	void *vaddr;
4896 
4897 	BGE_TRACE(("bge_chip_poke_mem($%p, $%p)",
4898 	    (void *)bgep, (void *)ppd));
4899 
4900 	vaddr = (void *)(uintptr_t)ppd->pp_acc_offset;
4901 	regval = ppd->pp_acc_data;
4902 
4903 	BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p",
4904 	    (void *)bgep, (void *)ppd, regval, vaddr));
4905 
4906 	switch (ppd->pp_acc_size) {
4907 	case 1:
4908 		*(uint8_t *)vaddr = (uint8_t)regval;
4909 		break;
4910 
4911 	case 2:
4912 		*(uint16_t *)vaddr = (uint16_t)regval;
4913 		break;
4914 
4915 	case 4:
4916 		*(uint32_t *)vaddr = (uint32_t)regval;
4917 		break;
4918 
4919 	case 8:
4920 		*(uint64_t *)vaddr = (uint64_t)regval;
4921 		break;
4922 	}
4923 }
4924 
4925 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
4926 					struct iocblk *iocp);
4927 #pragma	no_inline(bge_pp_ioctl)
4928 
4929 static enum ioc_reply
4930 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
4931 {
4932 	void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd);
4933 	bge_peekpoke_t *ppd;
4934 	dma_area_t *areap;
4935 	uint64_t sizemask;
4936 	uint64_t mem_va;
4937 	uint64_t maxoff;
4938 	boolean_t peek;
4939 
4940 	switch (cmd) {
4941 	default:
4942 		/* NOTREACHED */
4943 		bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd);
4944 		return (IOC_INVAL);
4945 
4946 	case BGE_PEEK:
4947 		peek = B_TRUE;
4948 		break;
4949 
4950 	case BGE_POKE:
4951 		peek = B_FALSE;
4952 		break;
4953 	}
4954 
4955 	/*
4956 	 * Validate format of ioctl
4957 	 */
4958 	if (iocp->ioc_count != sizeof (bge_peekpoke_t))
4959 		return (IOC_INVAL);
4960 	if (mp->b_cont == NULL)
4961 		return (IOC_INVAL);
4962 	ppd = (void *)mp->b_cont->b_rptr;
4963 
4964 	/*
4965 	 * Validate request parameters
4966 	 */
4967 	switch (ppd->pp_acc_space) {
4968 	default:
4969 		return (IOC_INVAL);
4970 
4971 	case BGE_PP_SPACE_CFG:
4972 		/*
4973 		 * Config space
4974 		 */
4975 		sizemask = 8|4|2|1;
4976 		mem_va = 0;
4977 		maxoff = PCI_CONF_HDR_SIZE;
4978 		ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg;
4979 		break;
4980 
4981 	case BGE_PP_SPACE_REG:
4982 		/*
4983 		 * Memory-mapped I/O space
4984 		 */
4985 		sizemask = 8|4|2|1;
4986 		mem_va = 0;
4987 		maxoff = RIAAR_REGISTER_MAX;
4988 		ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg;
4989 		break;
4990 
4991 	case BGE_PP_SPACE_NIC:
4992 		/*
4993 		 * NIC on-chip memory
4994 		 */
4995 		sizemask = 8|4|2|1;
4996 		mem_va = 0;
4997 		maxoff = MWBAR_ONCHIP_MAX;
4998 		ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic;
4999 		break;
5000 
5001 	case BGE_PP_SPACE_MII:
5002 		/*
5003 		 * PHY's MII registers
5004 		 * NB: all PHY registers are two bytes, but the
5005 		 * addresses increment in ones (word addressing).
5006 		 * So we scale the address here, then undo the
5007 		 * transformation inside the peek/poke functions.
5008 		 */
5009 		ppd->pp_acc_offset *= 2;
5010 		sizemask = 2;
5011 		mem_va = 0;
5012 		maxoff = (MII_MAXREG+1)*2;
5013 		ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii;
5014 		break;
5015 
5016 #if	BGE_SEE_IO32
5017 	case BGE_PP_SPACE_SEEPROM:
5018 		/*
5019 		 * Attached SEEPROM(s), if any.
5020 		 * NB: we use the high-order bits of the 'address' as
5021 		 * a device select to accommodate multiple SEEPROMS,
5022 		 * If each one is the maximum size (64kbytes), this
5023 		 * makes them appear contiguous.  Otherwise, there may
5024 		 * be holes in the mapping.  ENxS doesn't have any
5025 		 * SEEPROMs anyway ...
5026 		 */
5027 		sizemask = 4;
5028 		mem_va = 0;
5029 		maxoff = SEEPROM_DEV_AND_ADDR_MASK;
5030 		ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom;
5031 		break;
5032 #endif	/* BGE_SEE_IO32 */
5033 
5034 #if	BGE_FLASH_IO32
5035 	case BGE_PP_SPACE_FLASH:
5036 		/*
5037 		 * Attached Flash device (if any); a maximum of one device
5038 		 * is currently supported.  But it can be up to 1MB (unlike
5039 		 * the 64k limit on SEEPROMs) so why would you need more ;-)
5040 		 */
5041 		sizemask = 4;
5042 		mem_va = 0;
5043 		maxoff = NVM_FLASH_ADDR_MASK;
5044 		ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash;
5045 		break;
5046 #endif	/* BGE_FLASH_IO32 */
5047 
5048 	case BGE_PP_SPACE_BGE:
5049 		/*
5050 		 * BGE data structure!
5051 		 */
5052 		sizemask = 8|4|2|1;
5053 		mem_va = (uintptr_t)bgep;
5054 		maxoff = sizeof (*bgep);
5055 		ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem;
5056 		break;
5057 
5058 	case BGE_PP_SPACE_STATUS:
5059 	case BGE_PP_SPACE_STATISTICS:
5060 	case BGE_PP_SPACE_TXDESC:
5061 	case BGE_PP_SPACE_TXBUFF:
5062 	case BGE_PP_SPACE_RXDESC:
5063 	case BGE_PP_SPACE_RXBUFF:
5064 		/*
5065 		 * Various DMA_AREAs
5066 		 */
5067 		switch (ppd->pp_acc_space) {
5068 		case BGE_PP_SPACE_TXDESC:
5069 			areap = &bgep->tx_desc;
5070 			break;
5071 		case BGE_PP_SPACE_TXBUFF:
5072 			areap = &bgep->tx_buff[0];
5073 			break;
5074 		case BGE_PP_SPACE_RXDESC:
5075 			areap = &bgep->rx_desc[0];
5076 			break;
5077 		case BGE_PP_SPACE_RXBUFF:
5078 			areap = &bgep->rx_buff[0];
5079 			break;
5080 		case BGE_PP_SPACE_STATUS:
5081 			areap = &bgep->status_block;
5082 			break;
5083 		case BGE_PP_SPACE_STATISTICS:
5084 			if (bgep->chipid.statistic_type == BGE_STAT_BLK)
5085 				areap = &bgep->statistics;
5086 			break;
5087 		}
5088 
5089 		sizemask = 8|4|2|1;
5090 		mem_va = (uintptr_t)areap->mem_va;
5091 		maxoff = areap->alength;
5092 		ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem;
5093 		break;
5094 	}
5095 
5096 	switch (ppd->pp_acc_size) {
5097 	default:
5098 		return (IOC_INVAL);
5099 
5100 	case 8:
5101 	case 4:
5102 	case 2:
5103 	case 1:
5104 		if ((ppd->pp_acc_size & sizemask) == 0)
5105 			return (IOC_INVAL);
5106 		break;
5107 	}
5108 
5109 	if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0)
5110 		return (IOC_INVAL);
5111 
5112 	if (ppd->pp_acc_offset >= maxoff)
5113 		return (IOC_INVAL);
5114 
5115 	if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff)
5116 		return (IOC_INVAL);
5117 
5118 	/*
5119 	 * All OK - go do it!
5120 	 */
5121 	ppd->pp_acc_offset += mem_va;
5122 	(*ppfn)(bgep, ppd);
5123 	return (peek ? IOC_REPLY : IOC_ACK);
5124 }
5125 
5126 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
5127 					struct iocblk *iocp);
5128 #pragma	no_inline(bge_diag_ioctl)
5129 
5130 static enum ioc_reply
5131 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
5132 {
5133 	ASSERT(mutex_owned(bgep->genlock));
5134 
5135 	switch (cmd) {
5136 	default:
5137 		/* NOTREACHED */
5138 		bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd);
5139 		return (IOC_INVAL);
5140 
5141 	case BGE_DIAG:
5142 		/*
5143 		 * Currently a no-op
5144 		 */
5145 		return (IOC_ACK);
5146 
5147 	case BGE_PEEK:
5148 	case BGE_POKE:
5149 		return (bge_pp_ioctl(bgep, cmd, mp, iocp));
5150 
5151 	case BGE_PHY_RESET:
5152 		return (IOC_RESTART_ACK);
5153 
5154 	case BGE_SOFT_RESET:
5155 	case BGE_HARD_RESET:
5156 		/*
5157 		 * Reset and reinitialise the 570x hardware
5158 		 */
5159 		bgep->bge_chip_state = BGE_CHIP_FAULT;
5160 		ddi_trigger_softintr(bgep->factotum_id);
5161 		(void) bge_restart(bgep, cmd == BGE_HARD_RESET);
5162 		return (IOC_ACK);
5163 	}
5164 
5165 	/* NOTREACHED */
5166 }
5167 
5168 #endif	/* BGE_DEBUGGING || BGE_DO_PPIO */
5169 
5170 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
5171 				    struct iocblk *iocp);
5172 #pragma	no_inline(bge_mii_ioctl)
5173 
5174 static enum ioc_reply
5175 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
5176 {
5177 	struct bge_mii_rw *miirwp;
5178 
5179 	/*
5180 	 * Validate format of ioctl
5181 	 */
5182 	if (iocp->ioc_count != sizeof (struct bge_mii_rw))
5183 		return (IOC_INVAL);
5184 	if (mp->b_cont == NULL)
5185 		return (IOC_INVAL);
5186 	miirwp = (void *)mp->b_cont->b_rptr;
5187 
5188 	/*
5189 	 * Validate request parameters ...
5190 	 */
5191 	if (miirwp->mii_reg > MII_MAXREG)
5192 		return (IOC_INVAL);
5193 
5194 	switch (cmd) {
5195 	default:
5196 		/* NOTREACHED */
5197 		bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd);
5198 		return (IOC_INVAL);
5199 
5200 	case BGE_MII_READ:
5201 		miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg);
5202 		return (IOC_REPLY);
5203 
5204 	case BGE_MII_WRITE:
5205 		bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data);
5206 		return (IOC_ACK);
5207 	}
5208 
5209 	/* NOTREACHED */
5210 }
5211 
5212 #if	BGE_SEE_IO32
5213 
5214 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
5215 				    struct iocblk *iocp);
5216 #pragma	no_inline(bge_see_ioctl)
5217 
5218 static enum ioc_reply
5219 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
5220 {
5221 	struct bge_see_rw *seerwp;
5222 
5223 	/*
5224 	 * Validate format of ioctl
5225 	 */
5226 	if (iocp->ioc_count != sizeof (struct bge_see_rw))
5227 		return (IOC_INVAL);
5228 	if (mp->b_cont == NULL)
5229 		return (IOC_INVAL);
5230 	seerwp = (void *)mp->b_cont->b_rptr;
5231 
5232 	/*
5233 	 * Validate request parameters ...
5234 	 */
5235 	if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK)
5236 		return (IOC_INVAL);
5237 
5238 	switch (cmd) {
5239 	default:
5240 		/* NOTREACHED */
5241 		bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd);
5242 		return (IOC_INVAL);
5243 
5244 	case BGE_SEE_READ:
5245 	case BGE_SEE_WRITE:
5246 		iocp->ioc_error = bge_nvmem_rw32(bgep, cmd,
5247 		    seerwp->see_addr, &seerwp->see_data);
5248 		return (IOC_REPLY);
5249 	}
5250 
5251 	/* NOTREACHED */
5252 }
5253 
5254 #endif	/* BGE_SEE_IO32 */
5255 
5256 #if	BGE_FLASH_IO32
5257 
5258 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
5259 				    struct iocblk *iocp);
5260 #pragma	no_inline(bge_flash_ioctl)
5261 
5262 static enum ioc_reply
5263 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
5264 {
5265 	struct bge_flash_rw *flashrwp;
5266 
5267 	/*
5268 	 * Validate format of ioctl
5269 	 */
5270 	if (iocp->ioc_count != sizeof (struct bge_flash_rw))
5271 		return (IOC_INVAL);
5272 	if (mp->b_cont == NULL)
5273 		return (IOC_INVAL);
5274 	flashrwp = (void *)mp->b_cont->b_rptr;
5275 
5276 	/*
5277 	 * Validate request parameters ...
5278 	 */
5279 	if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK)
5280 		return (IOC_INVAL);
5281 
5282 	switch (cmd) {
5283 	default:
5284 		/* NOTREACHED */
5285 		bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd);
5286 		return (IOC_INVAL);
5287 
5288 	case BGE_FLASH_READ:
5289 	case BGE_FLASH_WRITE:
5290 		iocp->ioc_error = bge_nvmem_rw32(bgep, cmd,
5291 		    flashrwp->flash_addr, &flashrwp->flash_data);
5292 		return (IOC_REPLY);
5293 	}
5294 
5295 	/* NOTREACHED */
5296 }
5297 
5298 #endif	/* BGE_FLASH_IO32 */
5299 
5300 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp,
5301 				struct iocblk *iocp);
5302 #pragma	no_inline(bge_chip_ioctl)
5303 
5304 enum ioc_reply
5305 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp)
5306 {
5307 	int cmd;
5308 
5309 	BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)",
5310 	    (void *)bgep, (void *)wq, (void *)mp, (void *)iocp));
5311 
5312 	ASSERT(mutex_owned(bgep->genlock));
5313 
5314 	cmd = iocp->ioc_cmd;
5315 	switch (cmd) {
5316 	default:
5317 		/* NOTREACHED */
5318 		bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd);
5319 		return (IOC_INVAL);
5320 
5321 	case BGE_DIAG:
5322 	case BGE_PEEK:
5323 	case BGE_POKE:
5324 	case BGE_PHY_RESET:
5325 	case BGE_SOFT_RESET:
5326 	case BGE_HARD_RESET:
5327 #if	BGE_DEBUGGING || BGE_DO_PPIO
5328 		return (bge_diag_ioctl(bgep, cmd, mp, iocp));
5329 #else
5330 		return (IOC_INVAL);
5331 #endif	/* BGE_DEBUGGING || BGE_DO_PPIO */
5332 
5333 	case BGE_MII_READ:
5334 	case BGE_MII_WRITE:
5335 		return (bge_mii_ioctl(bgep, cmd, mp, iocp));
5336 
5337 #if	BGE_SEE_IO32
5338 	case BGE_SEE_READ:
5339 	case BGE_SEE_WRITE:
5340 		return (bge_see_ioctl(bgep, cmd, mp, iocp));
5341 #endif	/* BGE_SEE_IO32 */
5342 
5343 #if	BGE_FLASH_IO32
5344 	case BGE_FLASH_READ:
5345 	case BGE_FLASH_WRITE:
5346 		return (bge_flash_ioctl(bgep, cmd, mp, iocp));
5347 #endif	/* BGE_FLASH_IO32 */
5348 	}
5349 
5350 	/* NOTREACHED */
5351 }
5352 
5353 void
5354 bge_chip_blank(void *arg, time_t ticks, uint_t count)
5355 {
5356 	bge_t *bgep = arg;
5357 
5358 	mutex_enter(bgep->genlock);
5359 	bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks);
5360 	bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count);
5361 	if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
5362 		ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED);
5363 	mutex_exit(bgep->genlock);
5364 }
5365 
5366 #ifdef BGE_IPMI_ASF
5367 
5368 uint32_t
5369 bge_nic_read32(bge_t *bgep, bge_regno_t addr)
5370 {
5371 	uint32_t data;
5372 
5373 #ifndef __sparc
5374 	if (!bgep->asf_wordswapped) {
5375 		/* a workaround word swap error */
5376 		if (addr & 4)
5377 			addr = addr - 4;
5378 		else
5379 			addr = addr + 4;
5380 	}
5381 #endif
5382 
5383 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr);
5384 	data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR);
5385 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0);
5386 
5387 	data = LE_32(data);
5388 	return (data);
5389 }
5390 
5391 void
5392 bge_asf_update_status(bge_t *bgep)
5393 {
5394 	uint32_t event;
5395 
5396 	bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE);
5397 	bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4);
5398 	bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX,   3);
5399 
5400 	event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
5401 	bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT);
5402 }
5403 
5404 
5405 /*
5406  * The driver is supposed to notify ASF that the OS is still running
5407  * every three seconds, otherwise the management server may attempt
5408  * to reboot the machine.  If it hasn't actually failed, this is
5409  * not a desirable result.  However, this isn't running as a real-time
5410  * thread, and even if it were, it might not be able to generate the
5411  * heartbeat in a timely manner due to system load.  As it isn't a
5412  * significant strain on the machine, we will set the interval to half
5413  * of the required value.
5414  */
5415 void
5416 bge_asf_heartbeat(void *arg)
5417 {
5418 	bge_t *bgep = (bge_t *)arg;
5419 
5420 	mutex_enter(bgep->genlock);
5421 	bge_asf_update_status((bge_t *)bgep);
5422 	if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
5423 		ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
5424 	if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK)
5425 		ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
5426 	mutex_exit(bgep->genlock);
5427 	((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep,
5428 	    drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL));
5429 }
5430 
5431 
5432 void
5433 bge_asf_stop_timer(bge_t *bgep)
5434 {
5435 	timeout_id_t tmp_id = 0;
5436 
5437 	while ((bgep->asf_timeout_id != 0) &&
5438 	    (tmp_id != bgep->asf_timeout_id)) {
5439 		tmp_id = bgep->asf_timeout_id;
5440 		(void) untimeout(tmp_id);
5441 	}
5442 	bgep->asf_timeout_id = 0;
5443 }
5444 
5445 
5446 
5447 /*
5448  * This function should be placed at the earliest position of bge_attach().
5449  */
5450 void
5451 bge_asf_get_config(bge_t *bgep)
5452 {
5453 	uint32_t nicsig;
5454 	uint32_t niccfg;
5455 
5456 	bgep->asf_enabled = B_FALSE;
5457 	nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR);
5458 	if (nicsig == BGE_NIC_DATA_SIG) {
5459 		niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR);
5460 		if (niccfg & BGE_NIC_CFG_ENABLE_ASF)
5461 			/*
5462 			 * Here, we don't consider BAXTER, because BGE haven't
5463 			 * supported BAXTER (that is 5752). Also, as I know,
5464 			 * BAXTER doesn't support ASF feature.
5465 			 */
5466 			bgep->asf_enabled = B_TRUE;
5467 		else
5468 			bgep->asf_enabled = B_FALSE;
5469 	} else
5470 		bgep->asf_enabled = B_FALSE;
5471 }
5472 
5473 
5474 void
5475 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode)
5476 {
5477 	uint32_t tries;
5478 	uint32_t event;
5479 
5480 	ASSERT(bgep->asf_enabled);
5481 
5482 	/* Issues "pause firmware" command and wait for ACK */
5483 	bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW);
5484 	event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
5485 	bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT);
5486 
5487 	event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
5488 	tries = 0;
5489 	while ((event & RRER_ASF_EVENT) && (tries < 100)) {
5490 		drv_usecwait(1);
5491 		tries ++;
5492 		event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
5493 	}
5494 
5495 	bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX,
5496 	    BGE_MAGIC_NUM_FIRMWARE_INIT_DONE);
5497 
5498 	if (bgep->asf_newhandshake) {
5499 		switch (mode) {
5500 		case BGE_INIT_RESET:
5501 			bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5502 			    BGE_DRV_STATE_START);
5503 			break;
5504 		case BGE_SHUTDOWN_RESET:
5505 			bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5506 			    BGE_DRV_STATE_UNLOAD);
5507 			break;
5508 		case BGE_SUSPEND_RESET:
5509 			bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5510 			    BGE_DRV_STATE_SUSPEND);
5511 			break;
5512 		default:
5513 			break;
5514 		}
5515 	}
5516 }
5517 
5518 
5519 void
5520 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode)
5521 {
5522 	switch (mode) {
5523 	case BGE_INIT_RESET:
5524 		bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5525 		    BGE_DRV_STATE_START);
5526 		break;
5527 	case BGE_SHUTDOWN_RESET:
5528 		bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5529 		    BGE_DRV_STATE_UNLOAD);
5530 		break;
5531 	case BGE_SUSPEND_RESET:
5532 		bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5533 		    BGE_DRV_STATE_SUSPEND);
5534 		break;
5535 	default:
5536 		break;
5537 	}
5538 }
5539 
5540 
5541 void
5542 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode)
5543 {
5544 	switch (mode) {
5545 	case BGE_INIT_RESET:
5546 		bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5547 		    BGE_DRV_STATE_START_DONE);
5548 		break;
5549 	case BGE_SHUTDOWN_RESET:
5550 		bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5551 		    BGE_DRV_STATE_UNLOAD_DONE);
5552 		break;
5553 	default:
5554 		break;
5555 	}
5556 }
5557 
5558 #endif /* BGE_IPMI_ASF */
5559