1 /* 2 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6 /* 7 * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 18 * redistribution must be conditioned upon including a substantially 19 * similar Disclaimer requirement for further binary redistribution. 20 * 3. Neither the names of the above-listed copyright holders nor the names 21 * of any contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * NO WARRANTY 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 28 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 29 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 30 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 33 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 35 * THE POSSIBILITY OF SUCH DAMAGES. 36 * 37 */ 38 39 #pragma ident "%Z%%M% %I% %E% SMI" 40 41 /* 42 * Driver for the Atheros Wireless LAN controller. 43 * 44 * The Atheros driver calls into net80211 module for IEEE80211 protocol 45 * management functionalities. The driver includes a LLD(Low Level Driver) 46 * part to implement H/W related operations. 47 * The following is the high level structure of ath driver. 48 * (The arrows between modules indicate function call direction.) 49 * 50 * 51 * | 52 * | GLD thread 53 * V 54 * ================== ========================================= 55 * | | |[1] | 56 * | | | GLDv3 Callback functions registered | 57 * | Net80211 | ========================= by | 58 * | module | | | driver | 59 * | | V | | 60 * | |======================== | | 61 * | Functions exported by net80211 | | | 62 * | | | | 63 * ========================================== ================= 64 * | | 65 * V | 66 * +----------------------------------+ | 67 * |[2] | | 68 * | Net80211 Callback functions | | 69 * | registered by LLD | | 70 * +----------------------------------+ | 71 * | | 72 * V v 73 * +-----------------------------------------------------------+ 74 * |[3] | 75 * | LLD Internal functions | 76 * | | 77 * +-----------------------------------------------------------+ 78 * ^ 79 * | Software interrupt thread 80 * | 81 * 82 * The short description of each module is as below: 83 * Module 1: GLD callback functions, which are intercepting the calls from 84 * GLD to LLD. 85 * Module 2: Net80211 callback functions registered by LLD, which 86 * calls into LLD for H/W related functions needed by net80211. 87 * Module 3: LLD Internal functions, which are responsible for allocing 88 * descriptor/buffer, handling interrupt and other H/W 89 * operations. 90 * 91 * All functions are running in 3 types of thread: 92 * 1. GLD callbacks threads, such as ioctl, intr, etc. 93 * 2. Clock interruptt thread which is responsible for scan, rate control and 94 * calibration. 95 * 3. Software Interrupt thread originated in LLD. 96 * 97 * The lock strategy is as below: 98 * There have 4 queues for tx, each queue has one asc_txqlock[i] to 99 * prevent conflicts access to queue resource from different thread. 100 * 101 * All the transmit buffers are contained in asc_txbuf which are 102 * protected by asc_txbuflock. 103 * 104 * Each receive buffers are contained in asc_rxbuf which are protected 105 * by asc_rxbuflock. 106 * 107 * In ath struct, asc_genlock is a general lock, protecting most other 108 * operational data in ath_softc struct and HAL accesses. 109 * It is acquired by the interupt handler and most "mode-ctrl" routines. 110 * 111 * Any of the locks can be acquired singly, but where multiple 112 * locks are acquired, they *must* be in the order: 113 * asc_genlock >> asc_txqlock[i] >> asc_txbuflock >> asc_rxbuflock 114 */ 115 116 #include <sys/param.h> 117 #include <sys/types.h> 118 #include <sys/signal.h> 119 #include <sys/stream.h> 120 #include <sys/termio.h> 121 #include <sys/errno.h> 122 #include <sys/file.h> 123 #include <sys/cmn_err.h> 124 #include <sys/stropts.h> 125 #include <sys/strsubr.h> 126 #include <sys/strtty.h> 127 #include <sys/kbio.h> 128 #include <sys/cred.h> 129 #include <sys/stat.h> 130 #include <sys/consdev.h> 131 #include <sys/kmem.h> 132 #include <sys/modctl.h> 133 #include <sys/ddi.h> 134 #include <sys/sunddi.h> 135 #include <sys/pci.h> 136 #include <sys/errno.h> 137 #include <sys/mac.h> 138 #include <sys/dlpi.h> 139 #include <sys/ethernet.h> 140 #include <sys/list.h> 141 #include <sys/byteorder.h> 142 #include <sys/strsun.h> 143 #include <sys/policy.h> 144 #include <inet/common.h> 145 #include <inet/nd.h> 146 #include <inet/mi.h> 147 #include <inet/wifi_ioctl.h> 148 #include <sys/mac_wifi.h> 149 #include "ath_hal.h" 150 #include "ath_impl.h" 151 #include "ath_aux.h" 152 #include "ath_rate.h" 153 154 #define ATH_MAX_RSSI 63 /* max rssi */ 155 156 extern void ath_halfix_init(void); 157 extern void ath_halfix_finit(void); 158 extern int32_t ath_getset(ath_t *asc, mblk_t *mp, uint32_t cmd); 159 160 /* 161 * PIO access attributes for registers 162 */ 163 static ddi_device_acc_attr_t ath_reg_accattr = { 164 DDI_DEVICE_ATTR_V0, 165 DDI_STRUCTURE_LE_ACC, 166 DDI_STRICTORDER_ACC 167 }; 168 169 /* 170 * DMA access attributes for descriptors: NOT to be byte swapped. 171 */ 172 static ddi_device_acc_attr_t ath_desc_accattr = { 173 DDI_DEVICE_ATTR_V0, 174 DDI_STRUCTURE_LE_ACC, 175 DDI_STRICTORDER_ACC 176 }; 177 178 /* 179 * Describes the chip's DMA engine 180 */ 181 static ddi_dma_attr_t ath_dma_attr = { 182 DMA_ATTR_V0, /* version number */ 183 0, /* low address */ 184 0xffffffffU, /* high address */ 185 0x3ffffU, /* counter register max */ 186 1, /* alignment */ 187 0xFFF, /* burst sizes */ 188 1, /* minimum transfer size */ 189 0x3ffffU, /* max transfer size */ 190 0xffffffffU, /* address register max */ 191 1, /* no scatter-gather */ 192 1, /* granularity of device */ 193 0, /* DMA flags */ 194 }; 195 196 static ddi_dma_attr_t ath_desc_dma_attr = { 197 DMA_ATTR_V0, /* version number */ 198 0, /* low address */ 199 0xffffffffU, /* high address */ 200 0xffffffffU, /* counter register max */ 201 0x1000, /* alignment */ 202 0xFFF, /* burst sizes */ 203 1, /* minimum transfer size */ 204 0xffffffffU, /* max transfer size */ 205 0xffffffffU, /* address register max */ 206 1, /* no scatter-gather */ 207 1, /* granularity of device */ 208 0, /* DMA flags */ 209 }; 210 211 static kmutex_t ath_loglock; 212 static void *ath_soft_state_p = NULL; 213 static int ath_dwelltime = 150; /* scan interval, ms */ 214 215 static int ath_m_stat(void *, uint_t, uint64_t *); 216 static int ath_m_start(void *); 217 static void ath_m_stop(void *); 218 static int ath_m_promisc(void *, boolean_t); 219 static int ath_m_multicst(void *, boolean_t, const uint8_t *); 220 static int ath_m_unicst(void *, const uint8_t *); 221 static mblk_t *ath_m_tx(void *, mblk_t *); 222 static void ath_m_ioctl(void *, queue_t *, mblk_t *); 223 static mac_callbacks_t ath_m_callbacks = { 224 MC_IOCTL, 225 ath_m_stat, 226 ath_m_start, 227 ath_m_stop, 228 ath_m_promisc, 229 ath_m_multicst, 230 ath_m_unicst, 231 ath_m_tx, 232 NULL, /* mc_resources; */ 233 ath_m_ioctl, 234 NULL /* mc_getcapab */ 235 }; 236 237 /* 238 * Available debug flags: 239 * ATH_DBG_INIT, ATH_DBG_GLD, ATH_DBG_HAL, ATH_DBG_INT, ATH_DBG_ATTACH, 240 * ATH_DBG_DETACH, ATH_DBG_AUX, ATH_DBG_WIFICFG, ATH_DBG_OSDEP 241 */ 242 uint32_t ath_dbg_flags = 0; 243 244 /* 245 * Exception/warning cases not leading to panic. 246 */ 247 void 248 ath_problem(const int8_t *fmt, ...) 249 { 250 va_list args; 251 252 mutex_enter(&ath_loglock); 253 254 va_start(args, fmt); 255 vcmn_err(CE_WARN, fmt, args); 256 va_end(args); 257 258 mutex_exit(&ath_loglock); 259 } 260 261 /* 262 * Normal log information independent of debug. 263 */ 264 void 265 ath_log(const int8_t *fmt, ...) 266 { 267 va_list args; 268 269 mutex_enter(&ath_loglock); 270 271 va_start(args, fmt); 272 vcmn_err(CE_CONT, fmt, args); 273 va_end(args); 274 275 mutex_exit(&ath_loglock); 276 } 277 278 void 279 ath_dbg(uint32_t dbg_flags, const int8_t *fmt, ...) 280 { 281 va_list args; 282 283 if (dbg_flags & ath_dbg_flags) { 284 mutex_enter(&ath_loglock); 285 va_start(args, fmt); 286 vcmn_err(CE_CONT, fmt, args); 287 va_end(args); 288 mutex_exit(&ath_loglock); 289 } 290 } 291 292 void 293 ath_setup_desc(ath_t *asc, struct ath_buf *bf) 294 { 295 struct ath_desc *ds; 296 297 ds = bf->bf_desc; 298 ds->ds_link = bf->bf_daddr; 299 ds->ds_data = bf->bf_dma.cookie.dmac_address; 300 ds->ds_vdata = bf->bf_dma.mem_va; 301 ATH_HAL_SETUPRXDESC(asc->asc_ah, ds, 302 bf->bf_dma.alength, /* buffer size */ 303 0); 304 305 if (asc->asc_rxlink != NULL) 306 *asc->asc_rxlink = bf->bf_daddr; 307 asc->asc_rxlink = &ds->ds_link; 308 } 309 310 311 /* 312 * Allocate an area of memory and a DMA handle for accessing it 313 */ 314 static int 315 ath_alloc_dma_mem(dev_info_t *devinfo, ddi_dma_attr_t *dma_attr, size_t memsize, 316 ddi_device_acc_attr_t *attr_p, uint_t alloc_flags, 317 uint_t bind_flags, dma_area_t *dma_p) 318 { 319 int err; 320 321 /* 322 * Allocate handle 323 */ 324 err = ddi_dma_alloc_handle(devinfo, dma_attr, 325 DDI_DMA_SLEEP, NULL, &dma_p->dma_hdl); 326 if (err != DDI_SUCCESS) 327 return (DDI_FAILURE); 328 329 /* 330 * Allocate memory 331 */ 332 err = ddi_dma_mem_alloc(dma_p->dma_hdl, memsize, attr_p, 333 alloc_flags, DDI_DMA_SLEEP, NULL, &dma_p->mem_va, 334 &dma_p->alength, &dma_p->acc_hdl); 335 if (err != DDI_SUCCESS) 336 return (DDI_FAILURE); 337 338 /* 339 * Bind the two together 340 */ 341 err = ddi_dma_addr_bind_handle(dma_p->dma_hdl, NULL, 342 dma_p->mem_va, dma_p->alength, bind_flags, 343 DDI_DMA_SLEEP, NULL, &dma_p->cookie, &dma_p->ncookies); 344 if (err != DDI_DMA_MAPPED) 345 return (DDI_FAILURE); 346 347 dma_p->nslots = ~0U; 348 dma_p->size = ~0U; 349 dma_p->token = ~0U; 350 dma_p->offset = 0; 351 return (DDI_SUCCESS); 352 } 353 354 /* 355 * Free one allocated area of DMAable memory 356 */ 357 static void 358 ath_free_dma_mem(dma_area_t *dma_p) 359 { 360 if (dma_p->dma_hdl != NULL) { 361 (void) ddi_dma_unbind_handle(dma_p->dma_hdl); 362 if (dma_p->acc_hdl != NULL) { 363 ddi_dma_mem_free(&dma_p->acc_hdl); 364 dma_p->acc_hdl = NULL; 365 } 366 ddi_dma_free_handle(&dma_p->dma_hdl); 367 dma_p->ncookies = 0; 368 dma_p->dma_hdl = NULL; 369 } 370 } 371 372 373 static int 374 ath_desc_alloc(dev_info_t *devinfo, ath_t *asc) 375 { 376 int i, err; 377 size_t size; 378 struct ath_desc *ds; 379 struct ath_buf *bf; 380 381 size = sizeof (struct ath_desc) * (ATH_TXBUF + ATH_RXBUF); 382 383 err = ath_alloc_dma_mem(devinfo, &ath_desc_dma_attr, size, 384 &ath_desc_accattr, DDI_DMA_CONSISTENT, 385 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, &asc->asc_desc_dma); 386 387 /* virtual address of the first descriptor */ 388 asc->asc_desc = (struct ath_desc *)asc->asc_desc_dma.mem_va; 389 390 ds = asc->asc_desc; 391 ATH_DEBUG((ATH_DBG_INIT, "ath: ath_desc_alloc(): DMA map: " 392 "%p (%d) -> %p\n", 393 asc->asc_desc, asc->asc_desc_dma.alength, 394 asc->asc_desc_dma.cookie.dmac_address)); 395 396 /* allocate data structures to describe TX/RX DMA buffers */ 397 asc->asc_vbuflen = sizeof (struct ath_buf) * (ATH_TXBUF + ATH_RXBUF); 398 bf = (struct ath_buf *)kmem_zalloc(asc->asc_vbuflen, KM_SLEEP); 399 asc->asc_vbufptr = bf; 400 401 /* DMA buffer size for each TX/RX packet */ 402 asc->asc_dmabuf_size = roundup(1000 + sizeof (struct ieee80211_frame) + 403 IEEE80211_MTU + IEEE80211_CRC_LEN + 404 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + 405 IEEE80211_WEP_CRCLEN), asc->asc_cachelsz); 406 407 /* create RX buffer list and allocate DMA memory */ 408 list_create(&asc->asc_rxbuf_list, sizeof (struct ath_buf), 409 offsetof(struct ath_buf, bf_node)); 410 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++) { 411 bf->bf_desc = ds; 412 bf->bf_daddr = asc->asc_desc_dma.cookie.dmac_address + 413 ((uintptr_t)ds - (uintptr_t)asc->asc_desc); 414 list_insert_tail(&asc->asc_rxbuf_list, bf); 415 416 /* alloc DMA memory */ 417 err = ath_alloc_dma_mem(devinfo, &ath_dma_attr, 418 asc->asc_dmabuf_size, &ath_desc_accattr, 419 DDI_DMA_STREAMING, DDI_DMA_READ | DDI_DMA_STREAMING, 420 &bf->bf_dma); 421 if (err != DDI_SUCCESS) 422 return (err); 423 } 424 425 /* create TX buffer list and allocate DMA memory */ 426 list_create(&asc->asc_txbuf_list, sizeof (struct ath_buf), 427 offsetof(struct ath_buf, bf_node)); 428 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++) { 429 bf->bf_desc = ds; 430 bf->bf_daddr = asc->asc_desc_dma.cookie.dmac_address + 431 ((uintptr_t)ds - (uintptr_t)asc->asc_desc); 432 list_insert_tail(&asc->asc_txbuf_list, bf); 433 434 /* alloc DMA memory */ 435 err = ath_alloc_dma_mem(devinfo, &ath_dma_attr, 436 asc->asc_dmabuf_size, &ath_desc_accattr, 437 DDI_DMA_STREAMING, DDI_DMA_STREAMING, &bf->bf_dma); 438 if (err != DDI_SUCCESS) 439 return (err); 440 } 441 442 return (DDI_SUCCESS); 443 } 444 445 static void 446 ath_desc_free(ath_t *asc) 447 { 448 struct ath_buf *bf; 449 450 /* Free TX DMA buffer */ 451 bf = list_head(&asc->asc_txbuf_list); 452 while (bf != NULL) { 453 ath_free_dma_mem(&bf->bf_dma); 454 list_remove(&asc->asc_txbuf_list, bf); 455 bf = list_head(&asc->asc_txbuf_list); 456 } 457 list_destroy(&asc->asc_txbuf_list); 458 459 /* Free RX DMA uffer */ 460 bf = list_head(&asc->asc_rxbuf_list); 461 while (bf != NULL) { 462 ath_free_dma_mem(&bf->bf_dma); 463 list_remove(&asc->asc_rxbuf_list, bf); 464 bf = list_head(&asc->asc_rxbuf_list); 465 } 466 list_destroy(&asc->asc_rxbuf_list); 467 468 /* Free descriptor DMA buffer */ 469 ath_free_dma_mem(&asc->asc_desc_dma); 470 471 kmem_free((void *)asc->asc_vbufptr, asc->asc_vbuflen); 472 asc->asc_vbufptr = NULL; 473 } 474 475 static void 476 ath_printrxbuf(struct ath_buf *bf, int32_t done) 477 { 478 struct ath_desc *ds = bf->bf_desc; 479 480 ATH_DEBUG((ATH_DBG_RECV, "ath: R (%p %p) %08x %08x %08x " 481 "%08x %08x %08x %c\n", 482 ds, bf->bf_daddr, 483 ds->ds_link, ds->ds_data, 484 ds->ds_ctl0, ds->ds_ctl1, 485 ds->ds_hw[0], ds->ds_hw[1], 486 !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!')); 487 } 488 489 static void 490 ath_rx_handler(ath_t *asc) 491 { 492 ieee80211com_t *ic = (ieee80211com_t *)asc; 493 struct ath_buf *bf; 494 struct ath_hal *ah = asc->asc_ah; 495 struct ath_desc *ds; 496 mblk_t *rx_mp; 497 struct ieee80211_frame *wh; 498 int32_t len, loop = 1; 499 uint8_t phyerr; 500 HAL_STATUS status; 501 HAL_NODE_STATS hal_node_stats; 502 struct ieee80211_node *in; 503 504 do { 505 mutex_enter(&asc->asc_rxbuflock); 506 bf = list_head(&asc->asc_rxbuf_list); 507 if (bf == NULL) { 508 ATH_DEBUG((ATH_DBG_RECV, "ath: ath_rx_handler(): " 509 "no buffer\n")); 510 mutex_exit(&asc->asc_rxbuflock); 511 break; 512 } 513 ASSERT(bf->bf_dma.cookie.dmac_address != NULL); 514 ds = bf->bf_desc; 515 if (ds->ds_link == bf->bf_daddr) { 516 /* 517 * Never process the self-linked entry at the end, 518 * this may be met at heavy load. 519 */ 520 mutex_exit(&asc->asc_rxbuflock); 521 break; 522 } 523 524 status = ATH_HAL_RXPROCDESC(ah, ds, 525 bf->bf_daddr, 526 ATH_PA2DESC(asc, ds->ds_link)); 527 if (status == HAL_EINPROGRESS) { 528 mutex_exit(&asc->asc_rxbuflock); 529 break; 530 } 531 list_remove(&asc->asc_rxbuf_list, bf); 532 mutex_exit(&asc->asc_rxbuflock); 533 534 if (ds->ds_rxstat.rs_status != 0) { 535 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC) 536 asc->asc_stats.ast_rx_crcerr++; 537 if (ds->ds_rxstat.rs_status & HAL_RXERR_FIFO) 538 asc->asc_stats.ast_rx_fifoerr++; 539 if (ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT) 540 asc->asc_stats.ast_rx_badcrypt++; 541 if (ds->ds_rxstat.rs_status & HAL_RXERR_PHY) { 542 asc->asc_stats.ast_rx_phyerr++; 543 phyerr = ds->ds_rxstat.rs_phyerr & 0x1f; 544 asc->asc_stats.ast_rx_phy[phyerr]++; 545 } 546 goto rx_next; 547 } 548 len = ds->ds_rxstat.rs_datalen; 549 550 /* less than sizeof(struct ieee80211_frame) */ 551 if (len < 20) { 552 asc->asc_stats.ast_rx_tooshort++; 553 goto rx_next; 554 } 555 556 if ((rx_mp = allocb(asc->asc_dmabuf_size, BPRI_MED)) == NULL) { 557 ath_problem("ath: ath_rx_handler(): " 558 "allocing mblk buffer failed.\n"); 559 return; 560 } 561 562 ATH_DMA_SYNC(bf->bf_dma, DDI_DMA_SYNC_FORCPU); 563 bcopy(bf->bf_dma.mem_va, rx_mp->b_rptr, len); 564 565 rx_mp->b_wptr += len; 566 wh = (struct ieee80211_frame *)rx_mp->b_rptr; 567 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 568 IEEE80211_FC0_TYPE_CTL) { 569 /* 570 * Ignore control frame received in promisc mode. 571 */ 572 freemsg(rx_mp); 573 goto rx_next; 574 } 575 /* Remove the CRC at the end of IEEE80211 frame */ 576 rx_mp->b_wptr -= IEEE80211_CRC_LEN; 577 #ifdef DEBUG 578 ath_printrxbuf(bf, status == HAL_OK); 579 #endif /* DEBUG */ 580 /* 581 * Locate the node for sender, track state, and then 582 * pass the (referenced) node up to the 802.11 layer 583 * for its use. 584 */ 585 in = ieee80211_find_rxnode(ic, wh); 586 587 /* 588 * Send frame up for processing. 589 */ 590 (void) ieee80211_input(ic, rx_mp, in, 591 ds->ds_rxstat.rs_rssi, 592 ds->ds_rxstat.rs_tstamp); 593 594 ieee80211_free_node(in); 595 596 rx_next: 597 mutex_enter(&asc->asc_rxbuflock); 598 list_insert_tail(&asc->asc_rxbuf_list, bf); 599 mutex_exit(&asc->asc_rxbuflock); 600 ath_setup_desc(asc, bf); 601 } while (loop); 602 603 /* rx signal state monitoring */ 604 ATH_HAL_RXMONITOR(ah, &hal_node_stats, &asc->asc_curchan); 605 } 606 607 static void 608 ath_printtxbuf(struct ath_buf *bf, int done) 609 { 610 struct ath_desc *ds = bf->bf_desc; 611 612 ATH_DEBUG((ATH_DBG_SEND, "ath: T(%p %p) %08x %08x %08x %08x %08x" 613 " %08x %08x %08x %c\n", 614 ds, bf->bf_daddr, 615 ds->ds_link, ds->ds_data, 616 ds->ds_ctl0, ds->ds_ctl1, 617 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], 618 !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!')); 619 } 620 621 /* 622 * The input parameter mp has following assumption: 623 * For data packets, GLDv3 mac_wifi plugin allocates and fills the 624 * ieee80211 header. For management packets, net80211 allocates and 625 * fills the ieee80211 header. In both cases, enough spaces in the 626 * header are left for encryption option. 627 */ 628 static int32_t 629 ath_tx_start(ath_t *asc, struct ieee80211_node *in, struct ath_buf *bf, 630 mblk_t *mp) 631 { 632 ieee80211com_t *ic = (ieee80211com_t *)asc; 633 struct ieee80211_frame *wh; 634 struct ath_hal *ah = asc->asc_ah; 635 uint32_t subtype, flags, ctsduration; 636 int32_t keyix, iswep, hdrlen, pktlen, mblen, mbslen, try0; 637 uint8_t rix, cix, txrate, ctsrate; 638 struct ath_desc *ds; 639 struct ath_txq *txq; 640 HAL_PKT_TYPE atype; 641 const HAL_RATE_TABLE *rt; 642 HAL_BOOL shortPreamble; 643 struct ath_node *an; 644 caddr_t dest; 645 646 /* 647 * CRC are added by H/W, not encaped by driver, 648 * but we must count it in pkt length. 649 */ 650 pktlen = IEEE80211_CRC_LEN; 651 652 wh = (struct ieee80211_frame *)mp->b_rptr; 653 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 654 keyix = HAL_TXKEYIX_INVALID; 655 hdrlen = sizeof (struct ieee80211_frame); 656 if (iswep != 0) { 657 const struct ieee80211_cipher *cip; 658 struct ieee80211_key *k; 659 660 /* 661 * Construct the 802.11 header+trailer for an encrypted 662 * frame. The only reason this can fail is because of an 663 * unknown or unsupported cipher/key type. 664 */ 665 k = ieee80211_crypto_encap(ic, mp); 666 if (k == NULL) { 667 ATH_DEBUG((ATH_DBG_AUX, "crypto_encap failed\n")); 668 /* 669 * This can happen when the key is yanked after the 670 * frame was queued. Just discard the frame; the 671 * 802.11 layer counts failures and provides 672 * debugging/diagnostics. 673 */ 674 return (EIO); 675 } 676 cip = k->wk_cipher; 677 /* 678 * Adjust the packet + header lengths for the crypto 679 * additions and calculate the h/w key index. When 680 * a s/w mic is done the frame will have had any mic 681 * added to it prior to entry so m0->m_pkthdr.len above will 682 * account for it. Otherwise we need to add it to the 683 * packet length. 684 */ 685 hdrlen += cip->ic_header; 686 pktlen += cip->ic_trailer; 687 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0) 688 pktlen += cip->ic_miclen; 689 keyix = k->wk_keyix; 690 691 /* packet header may have moved, reset our local pointer */ 692 wh = (struct ieee80211_frame *)mp->b_rptr; 693 } 694 695 dest = bf->bf_dma.mem_va; 696 for (; mp != NULL; mp = mp->b_cont) { 697 mblen = MBLKL(mp); 698 bcopy(mp->b_rptr, dest, mblen); 699 dest += mblen; 700 } 701 mbslen = (uintptr_t)dest - (uintptr_t)bf->bf_dma.mem_va; 702 pktlen += mbslen; 703 704 bf->bf_in = in; 705 706 /* setup descriptors */ 707 ds = bf->bf_desc; 708 rt = asc->asc_currates; 709 ASSERT(rt != NULL); 710 711 /* 712 * The 802.11 layer marks whether or not we should 713 * use short preamble based on the current mode and 714 * negotiated parameters. 715 */ 716 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 717 (in->in_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) { 718 shortPreamble = AH_TRUE; 719 asc->asc_stats.ast_tx_shortpre++; 720 } else { 721 shortPreamble = AH_FALSE; 722 } 723 724 an = ATH_NODE(in); 725 726 /* 727 * Calculate Atheros packet type from IEEE80211 packet header 728 * and setup for rate calculations. 729 */ 730 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 731 case IEEE80211_FC0_TYPE_MGT: 732 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 733 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 734 atype = HAL_PKT_TYPE_BEACON; 735 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 736 atype = HAL_PKT_TYPE_PROBE_RESP; 737 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 738 atype = HAL_PKT_TYPE_ATIM; 739 else 740 atype = HAL_PKT_TYPE_NORMAL; 741 rix = 0; /* lowest rate */ 742 try0 = ATH_TXMAXTRY; 743 if (shortPreamble) 744 txrate = an->an_tx_mgtratesp; 745 else 746 txrate = an->an_tx_mgtrate; 747 /* force all ctl frames to highest queue */ 748 txq = asc->asc_ac2q[WME_AC_VO]; 749 break; 750 case IEEE80211_FC0_TYPE_CTL: 751 atype = HAL_PKT_TYPE_PSPOLL; 752 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 753 rix = 0; /* lowest rate */ 754 try0 = ATH_TXMAXTRY; 755 if (shortPreamble) 756 txrate = an->an_tx_mgtratesp; 757 else 758 txrate = an->an_tx_mgtrate; 759 /* force all ctl frames to highest queue */ 760 txq = asc->asc_ac2q[WME_AC_VO]; 761 break; 762 case IEEE80211_FC0_TYPE_DATA: 763 atype = HAL_PKT_TYPE_NORMAL; 764 rix = an->an_tx_rix0; 765 try0 = an->an_tx_try0; 766 if (shortPreamble) 767 txrate = an->an_tx_rate0sp; 768 else 769 txrate = an->an_tx_rate0; 770 /* Always use background queue */ 771 txq = asc->asc_ac2q[WME_AC_BK]; 772 break; 773 default: 774 /* Unknown 802.11 frame */ 775 asc->asc_stats.ast_tx_invalid++; 776 return (1); 777 } 778 /* 779 * Calculate miscellaneous flags. 780 */ 781 flags = HAL_TXDESC_CLRDMASK; 782 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 783 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 784 asc->asc_stats.ast_tx_noack++; 785 } else if (pktlen > ic->ic_rtsthreshold) { 786 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 787 asc->asc_stats.ast_tx_rts++; 788 } 789 790 /* 791 * Calculate duration. This logically belongs in the 802.11 792 * layer but it lacks sufficient information to calculate it. 793 */ 794 if ((flags & HAL_TXDESC_NOACK) == 0 && 795 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != 796 IEEE80211_FC0_TYPE_CTL) { 797 uint16_t dur; 798 dur = ath_hal_computetxtime(ah, rt, IEEE80211_ACK_SIZE, 799 rix, shortPreamble); 800 /* LINTED E_BAD_PTR_CAST_ALIGN */ 801 *(uint16_t *)wh->i_dur = LE_16(dur); 802 } 803 804 /* 805 * Calculate RTS/CTS rate and duration if needed. 806 */ 807 ctsduration = 0; 808 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { 809 /* 810 * CTS transmit rate is derived from the transmit rate 811 * by looking in the h/w rate table. We must also factor 812 * in whether or not a short preamble is to be used. 813 */ 814 cix = rt->info[rix].controlRate; 815 ctsrate = rt->info[cix].rateCode; 816 if (shortPreamble) 817 ctsrate |= rt->info[cix].shortPreamble; 818 /* 819 * Compute the transmit duration based on the size 820 * of an ACK frame. We call into the HAL to do the 821 * computation since it depends on the characteristics 822 * of the actual PHY being used. 823 */ 824 if (flags & HAL_TXDESC_RTSENA) { /* SIFS + CTS */ 825 ctsduration += ath_hal_computetxtime(ah, 826 rt, IEEE80211_ACK_SIZE, cix, shortPreamble); 827 } 828 /* SIFS + data */ 829 ctsduration += ath_hal_computetxtime(ah, 830 rt, pktlen, rix, shortPreamble); 831 if ((flags & HAL_TXDESC_NOACK) == 0) { /* SIFS + ACK */ 832 ctsduration += ath_hal_computetxtime(ah, 833 rt, IEEE80211_ACK_SIZE, cix, shortPreamble); 834 } 835 } else 836 ctsrate = 0; 837 838 if (++txq->axq_intrcnt >= ATH_TXINTR_PERIOD) { 839 flags |= HAL_TXDESC_INTREQ; 840 txq->axq_intrcnt = 0; 841 } 842 843 /* 844 * Formulate first tx descriptor with tx controls. 845 */ 846 ATH_HAL_SETUPTXDESC(ah, ds, 847 pktlen, /* packet length */ 848 hdrlen, /* header length */ 849 atype, /* Atheros packet type */ 850 MIN(in->in_txpower, 60), /* txpower */ 851 txrate, try0, /* series 0 rate/tries */ 852 keyix, /* key cache index */ 853 an->an_tx_antenna, /* antenna mode */ 854 flags, /* flags */ 855 ctsrate, /* rts/cts rate */ 856 ctsduration); /* rts/cts duration */ 857 bf->bf_flags = flags; 858 859 /* LINTED E_BAD_PTR_CAST_ALIGN */ 860 ATH_DEBUG((ATH_DBG_SEND, "ath: ath_xmit(): to %s totlen=%d " 861 "an->an_tx_rate1sp=%d tx_rate2sp=%d tx_rate3sp=%d " 862 "qnum=%d rix=%d sht=%d dur = %d\n", 863 ieee80211_macaddr_sprintf(wh->i_addr1), mbslen, an->an_tx_rate1sp, 864 an->an_tx_rate2sp, an->an_tx_rate3sp, 865 txq->axq_qnum, rix, shortPreamble, *(uint16_t *)wh->i_dur)); 866 867 /* 868 * Setup the multi-rate retry state only when we're 869 * going to use it. This assumes ath_hal_setuptxdesc 870 * initializes the descriptors (so we don't have to) 871 * when the hardware supports multi-rate retry and 872 * we don't use it. 873 */ 874 if (try0 != ATH_TXMAXTRY) 875 ATH_HAL_SETUPXTXDESC(ah, ds, 876 an->an_tx_rate1sp, 2, /* series 1 */ 877 an->an_tx_rate2sp, 2, /* series 2 */ 878 an->an_tx_rate3sp, 2); /* series 3 */ 879 880 ds->ds_link = 0; 881 ds->ds_data = bf->bf_dma.cookie.dmac_address; 882 ATH_HAL_FILLTXDESC(ah, ds, 883 mbslen, /* segment length */ 884 AH_TRUE, /* first segment */ 885 AH_TRUE, /* last segment */ 886 ds); /* first descriptor */ 887 888 ATH_DMA_SYNC(bf->bf_dma, DDI_DMA_SYNC_FORDEV); 889 890 mutex_enter(&txq->axq_lock); 891 list_insert_tail(&txq->axq_list, bf); 892 if (txq->axq_link == NULL) { 893 ATH_HAL_PUTTXBUF(ah, txq->axq_qnum, bf->bf_daddr); 894 } else { 895 *txq->axq_link = bf->bf_daddr; 896 } 897 txq->axq_link = &ds->ds_link; 898 mutex_exit(&txq->axq_lock); 899 900 ATH_HAL_TXSTART(ah, txq->axq_qnum); 901 902 ic->ic_stats.is_tx_frags++; 903 ic->ic_stats.is_tx_bytes += pktlen; 904 905 return (0); 906 } 907 908 /* 909 * Transmit a management frame. On failure we reclaim the skbuff. 910 * Note that management frames come directly from the 802.11 layer 911 * and do not honor the send queue flow control. Need to investigate 912 * using priority queueing so management frames can bypass data. 913 */ 914 static int 915 ath_xmit(ieee80211com_t *ic, mblk_t *mp, uint8_t type) 916 { 917 ath_t *asc = (ath_t *)ic; 918 struct ath_hal *ah = asc->asc_ah; 919 struct ieee80211_node *in = NULL; 920 struct ath_buf *bf = NULL; 921 struct ieee80211_frame *wh; 922 int error = 0; 923 924 ASSERT(mp->b_next == NULL); 925 926 if (!ATH_IS_RUNNING(asc)) { 927 if ((type & IEEE80211_FC0_TYPE_MASK) != 928 IEEE80211_FC0_TYPE_DATA) { 929 freemsg(mp); 930 } 931 return (ENXIO); 932 } 933 934 /* Grab a TX buffer */ 935 mutex_enter(&asc->asc_txbuflock); 936 bf = list_head(&asc->asc_txbuf_list); 937 if (bf != NULL) 938 list_remove(&asc->asc_txbuf_list, bf); 939 if (list_empty(&asc->asc_txbuf_list)) { 940 ATH_DEBUG((ATH_DBG_SEND, "ath: ath_mgmt_send(): " 941 "stop queue\n")); 942 asc->asc_stats.ast_tx_qstop++; 943 } 944 mutex_exit(&asc->asc_txbuflock); 945 if (bf == NULL) { 946 ATH_DEBUG((ATH_DBG_SEND, "ath: ath_mgmt_send(): discard, " 947 "no xmit buf\n")); 948 ic->ic_stats.is_tx_nobuf++; 949 if ((type & IEEE80211_FC0_TYPE_MASK) == 950 IEEE80211_FC0_TYPE_DATA) { 951 asc->asc_stats.ast_tx_nobuf++; 952 mutex_enter(&asc->asc_resched_lock); 953 asc->asc_resched_needed = B_TRUE; 954 mutex_exit(&asc->asc_resched_lock); 955 } else { 956 asc->asc_stats.ast_tx_nobufmgt++; 957 freemsg(mp); 958 } 959 return (ENOMEM); 960 } 961 962 wh = (struct ieee80211_frame *)mp->b_rptr; 963 964 /* Locate node */ 965 in = ieee80211_find_txnode(ic, wh->i_addr1); 966 if (in == NULL) { 967 error = EIO; 968 goto bad; 969 } 970 971 in->in_inact = 0; 972 switch (type & IEEE80211_FC0_TYPE_MASK) { 973 case IEEE80211_FC0_TYPE_DATA: 974 (void) ieee80211_encap(ic, mp, in); 975 break; 976 default: 977 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 978 IEEE80211_FC0_SUBTYPE_PROBE_RESP) { 979 /* fill time stamp */ 980 uint64_t tsf; 981 uint32_t *tstamp; 982 983 tsf = ATH_HAL_GETTSF64(ah); 984 /* adjust 100us delay to xmit */ 985 tsf += 100; 986 /* LINTED E_BAD_PTR_CAST_ALIGN */ 987 tstamp = (uint32_t *)&wh[1]; 988 tstamp[0] = LE_32(tsf & 0xffffffff); 989 tstamp[1] = LE_32(tsf >> 32); 990 } 991 asc->asc_stats.ast_tx_mgmt++; 992 break; 993 } 994 995 error = ath_tx_start(asc, in, bf, mp); 996 if (error != 0) { 997 bad: 998 ic->ic_stats.is_tx_failed++; 999 if (bf != NULL) { 1000 mutex_enter(&asc->asc_txbuflock); 1001 list_insert_tail(&asc->asc_txbuf_list, bf); 1002 mutex_exit(&asc->asc_txbuflock); 1003 } 1004 } 1005 if (in != NULL) 1006 ieee80211_free_node(in); 1007 if ((type & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_DATA || 1008 error == 0) { 1009 freemsg(mp); 1010 } 1011 1012 return (error); 1013 } 1014 1015 static mblk_t * 1016 ath_m_tx(void *arg, mblk_t *mp) 1017 { 1018 ath_t *asc = arg; 1019 ieee80211com_t *ic = (ieee80211com_t *)asc; 1020 mblk_t *next; 1021 int error = 0; 1022 1023 /* 1024 * No data frames go out unless we're associated; this 1025 * should not happen as the 802.11 layer does not enable 1026 * the xmit queue until we enter the RUN state. 1027 */ 1028 if (ic->ic_state != IEEE80211_S_RUN) { 1029 ATH_DEBUG((ATH_DBG_SEND, "ath: ath_m_tx(): " 1030 "discard, state %u\n", ic->ic_state)); 1031 asc->asc_stats.ast_tx_discard++; 1032 freemsgchain(mp); 1033 return (NULL); 1034 } 1035 1036 while (mp != NULL) { 1037 next = mp->b_next; 1038 mp->b_next = NULL; 1039 error = ath_xmit(ic, mp, IEEE80211_FC0_TYPE_DATA); 1040 if (error != 0) { 1041 mp->b_next = next; 1042 if (error == ENOMEM) { 1043 break; 1044 } else { 1045 freemsgchain(mp); /* CR6501759 issues */ 1046 return (NULL); 1047 } 1048 } 1049 mp = next; 1050 } 1051 1052 return (mp); 1053 1054 } 1055 1056 static int 1057 ath_tx_processq(ath_t *asc, struct ath_txq *txq) 1058 { 1059 ieee80211com_t *ic = (ieee80211com_t *)asc; 1060 struct ath_hal *ah = asc->asc_ah; 1061 struct ath_buf *bf; 1062 struct ath_desc *ds; 1063 struct ieee80211_node *in; 1064 int32_t sr, lr, nacked = 0; 1065 HAL_STATUS status; 1066 struct ath_node *an; 1067 1068 for (;;) { 1069 mutex_enter(&txq->axq_lock); 1070 bf = list_head(&txq->axq_list); 1071 if (bf == NULL) { 1072 txq->axq_link = NULL; 1073 mutex_exit(&txq->axq_lock); 1074 break; 1075 } 1076 ds = bf->bf_desc; /* last decriptor */ 1077 status = ATH_HAL_TXPROCDESC(ah, ds); 1078 #ifdef DEBUG 1079 ath_printtxbuf(bf, status == HAL_OK); 1080 #endif 1081 if (status == HAL_EINPROGRESS) { 1082 mutex_exit(&txq->axq_lock); 1083 break; 1084 } 1085 list_remove(&txq->axq_list, bf); 1086 mutex_exit(&txq->axq_lock); 1087 in = bf->bf_in; 1088 if (in != NULL) { 1089 an = ATH_NODE(in); 1090 /* Successful transmition */ 1091 if (ds->ds_txstat.ts_status == 0) { 1092 an->an_tx_ok++; 1093 an->an_tx_antenna = 1094 ds->ds_txstat.ts_antenna; 1095 if (ds->ds_txstat.ts_rate & 1096 HAL_TXSTAT_ALTRATE) 1097 asc->asc_stats.ast_tx_altrate++; 1098 asc->asc_stats.ast_tx_rssidelta = 1099 ds->ds_txstat.ts_rssi - 1100 asc->asc_stats.ast_tx_rssi; 1101 asc->asc_stats.ast_tx_rssi = 1102 ds->ds_txstat.ts_rssi; 1103 } else { 1104 an->an_tx_err++; 1105 if (ds->ds_txstat.ts_status & 1106 HAL_TXERR_XRETRY) 1107 asc->asc_stats. 1108 ast_tx_xretries++; 1109 if (ds->ds_txstat.ts_status & 1110 HAL_TXERR_FIFO) 1111 asc->asc_stats.ast_tx_fifoerr++; 1112 if (ds->ds_txstat.ts_status & 1113 HAL_TXERR_FILT) 1114 asc->asc_stats. 1115 ast_tx_filtered++; 1116 an->an_tx_antenna = 0; /* invalidate */ 1117 } 1118 sr = ds->ds_txstat.ts_shortretry; 1119 lr = ds->ds_txstat.ts_longretry; 1120 asc->asc_stats.ast_tx_shortretry += sr; 1121 asc->asc_stats.ast_tx_longretry += lr; 1122 /* 1123 * Hand the descriptor to the rate control algorithm. 1124 */ 1125 if ((ds->ds_txstat.ts_status & HAL_TXERR_FILT) == 0 && 1126 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) { 1127 /* 1128 * If frame was ack'd update the last rx time 1129 * used to workaround phantom bmiss interrupts. 1130 */ 1131 if (ds->ds_txstat.ts_status == 0) { 1132 nacked++; 1133 an->an_tx_ok++; 1134 } else { 1135 an->an_tx_err++; 1136 } 1137 an->an_tx_retr += sr + lr; 1138 } 1139 } 1140 bf->bf_in = NULL; 1141 mutex_enter(&asc->asc_txbuflock); 1142 list_insert_tail(&asc->asc_txbuf_list, bf); 1143 mutex_exit(&asc->asc_txbuflock); 1144 /* 1145 * Reschedule stalled outbound packets 1146 */ 1147 mutex_enter(&asc->asc_resched_lock); 1148 if (asc->asc_resched_needed) { 1149 asc->asc_resched_needed = B_FALSE; 1150 mac_tx_update(ic->ic_mach); 1151 } 1152 mutex_exit(&asc->asc_resched_lock); 1153 } 1154 return (nacked); 1155 } 1156 1157 1158 static void 1159 ath_tx_handler(ath_t *asc) 1160 { 1161 int i; 1162 1163 /* 1164 * Process each active queue. 1165 */ 1166 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 1167 if (ATH_TXQ_SETUP(asc, i)) { 1168 (void) ath_tx_processq(asc, &asc->asc_txq[i]); 1169 } 1170 } 1171 } 1172 1173 static struct ieee80211_node * 1174 ath_node_alloc(ieee80211com_t *ic) 1175 { 1176 struct ath_node *an; 1177 ath_t *asc = (ath_t *)ic; 1178 1179 an = kmem_zalloc(sizeof (struct ath_node), KM_SLEEP); 1180 ath_rate_update(asc, &an->an_node, 0); 1181 return (&an->an_node); 1182 } 1183 1184 static void 1185 ath_node_free(struct ieee80211_node *in) 1186 { 1187 ieee80211com_t *ic = in->in_ic; 1188 ath_t *asc = (ath_t *)ic; 1189 struct ath_buf *bf; 1190 struct ath_txq *txq; 1191 int32_t i; 1192 1193 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 1194 if (ATH_TXQ_SETUP(asc, i)) { 1195 txq = &asc->asc_txq[i]; 1196 mutex_enter(&txq->axq_lock); 1197 bf = list_head(&txq->axq_list); 1198 while (bf != NULL) { 1199 if (bf->bf_in == in) { 1200 bf->bf_in = NULL; 1201 } 1202 bf = list_next(&txq->axq_list, bf); 1203 } 1204 mutex_exit(&txq->axq_lock); 1205 } 1206 } 1207 ic->ic_node_cleanup(in); 1208 if (in->in_wpa_ie != NULL) 1209 ieee80211_free(in->in_wpa_ie); 1210 kmem_free(in, sizeof (struct ath_node)); 1211 } 1212 1213 static void 1214 ath_next_scan(void *arg) 1215 { 1216 ieee80211com_t *ic = arg; 1217 ath_t *asc = (ath_t *)ic; 1218 1219 asc->asc_scan_timer = 0; 1220 if (ic->ic_state == IEEE80211_S_SCAN) { 1221 asc->asc_scan_timer = timeout(ath_next_scan, (void *)asc, 1222 drv_usectohz(ath_dwelltime * 1000)); 1223 ieee80211_next_scan(ic); 1224 } 1225 } 1226 1227 static void 1228 ath_stop_scantimer(ath_t *asc) 1229 { 1230 timeout_id_t tmp_id = 0; 1231 1232 while ((asc->asc_scan_timer != 0) && (tmp_id != asc->asc_scan_timer)) { 1233 tmp_id = asc->asc_scan_timer; 1234 (void) untimeout(tmp_id); 1235 } 1236 asc->asc_scan_timer = 0; 1237 } 1238 1239 static int32_t 1240 ath_newstate(ieee80211com_t *ic, enum ieee80211_state nstate, int arg) 1241 { 1242 ath_t *asc = (ath_t *)ic; 1243 struct ath_hal *ah = asc->asc_ah; 1244 struct ieee80211_node *in; 1245 int32_t i, error; 1246 uint8_t *bssid; 1247 uint32_t rfilt; 1248 enum ieee80211_state ostate; 1249 1250 static const HAL_LED_STATE leds[] = { 1251 HAL_LED_INIT, /* IEEE80211_S_INIT */ 1252 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 1253 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 1254 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 1255 HAL_LED_RUN, /* IEEE80211_S_RUN */ 1256 }; 1257 if (!ATH_IS_RUNNING(asc)) 1258 return (0); 1259 1260 ostate = ic->ic_state; 1261 if (nstate != IEEE80211_S_SCAN) 1262 ath_stop_scantimer(asc); 1263 1264 ATH_LOCK(asc); 1265 ATH_HAL_SETLEDSTATE(ah, leds[nstate]); /* set LED */ 1266 1267 if (nstate == IEEE80211_S_INIT) { 1268 asc->asc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 1269 ATH_HAL_INTRSET(ah, asc->asc_imask &~ HAL_INT_GLOBAL); 1270 ATH_UNLOCK(asc); 1271 goto done; 1272 } 1273 in = ic->ic_bss; 1274 error = ath_chan_set(asc, ic->ic_curchan); 1275 if (error != 0) { 1276 if (nstate != IEEE80211_S_SCAN) { 1277 ATH_UNLOCK(asc); 1278 ieee80211_reset_chan(ic); 1279 goto bad; 1280 } 1281 } 1282 1283 rfilt = ath_calcrxfilter(asc); 1284 if (nstate == IEEE80211_S_SCAN) 1285 bssid = ic->ic_macaddr; 1286 else 1287 bssid = in->in_bssid; 1288 ATH_HAL_SETRXFILTER(ah, rfilt); 1289 1290 if (nstate == IEEE80211_S_RUN && ic->ic_opmode != IEEE80211_M_IBSS) 1291 ATH_HAL_SETASSOCID(ah, bssid, in->in_associd); 1292 else 1293 ATH_HAL_SETASSOCID(ah, bssid, 0); 1294 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 1295 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 1296 if (ATH_HAL_KEYISVALID(ah, i)) 1297 ATH_HAL_KEYSETMAC(ah, i, bssid); 1298 } 1299 } 1300 1301 if ((nstate == IEEE80211_S_RUN) && 1302 (ostate != IEEE80211_S_RUN)) { 1303 /* Configure the beacon and sleep timers. */ 1304 ath_beacon_config(asc); 1305 } else { 1306 asc->asc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 1307 ATH_HAL_INTRSET(ah, asc->asc_imask); 1308 } 1309 /* 1310 * Reset the rate control state. 1311 */ 1312 ath_rate_ctl_reset(asc, nstate); 1313 1314 if (nstate == IEEE80211_S_RUN && (ostate != IEEE80211_S_RUN)) { 1315 nvlist_t *attr_list = NULL; 1316 sysevent_id_t eid; 1317 int32_t err = 0; 1318 char *str_name = "ATH"; 1319 char str_value[256] = {0}; 1320 1321 ATH_DEBUG((ATH_DBG_80211, "ath: ath new state(RUN): " 1322 "ic_flags=0x%08x iv=%d" 1323 " bssid=%s capinfo=0x%04x chan=%d\n", 1324 ic->ic_flags, 1325 in->in_intval, 1326 ieee80211_macaddr_sprintf(in->in_bssid), 1327 in->in_capinfo, 1328 ieee80211_chan2ieee(ic, in->in_chan))); 1329 1330 (void) sprintf(str_value, "%s%s%d", "-i ", 1331 ddi_driver_name(asc->asc_dev), 1332 ddi_get_instance(asc->asc_dev)); 1333 if (nvlist_alloc(&attr_list, 1334 NV_UNIQUE_NAME_TYPE, KM_SLEEP) == 0) { 1335 err = nvlist_add_string(attr_list, 1336 str_name, str_value); 1337 if (err != DDI_SUCCESS) 1338 ATH_DEBUG((ATH_DBG_80211, "ath: " 1339 "ath_new_state: error log event\n")); 1340 err = ddi_log_sysevent(asc->asc_dev, 1341 DDI_VENDOR_SUNW, "class", 1342 "subclass", attr_list, 1343 &eid, DDI_NOSLEEP); 1344 if (err != DDI_SUCCESS) 1345 ATH_DEBUG((ATH_DBG_80211, "ath: " 1346 "ath_new_state(): error log event\n")); 1347 nvlist_free(attr_list); 1348 } 1349 } 1350 1351 ATH_UNLOCK(asc); 1352 done: 1353 /* 1354 * Invoke the parent method to complete the work. 1355 */ 1356 error = asc->asc_newstate(ic, nstate, arg); 1357 /* 1358 * Finally, start any timers. 1359 */ 1360 if (nstate == IEEE80211_S_RUN) { 1361 ieee80211_start_watchdog(ic, 1); 1362 } else if ((nstate == IEEE80211_S_SCAN) && (ostate != nstate)) { 1363 /* start ap/neighbor scan timer */ 1364 ASSERT(asc->asc_scan_timer == 0); 1365 asc->asc_scan_timer = timeout(ath_next_scan, (void *)asc, 1366 drv_usectohz(ath_dwelltime * 1000)); 1367 } 1368 bad: 1369 return (error); 1370 } 1371 1372 /* 1373 * Periodically recalibrate the PHY to account 1374 * for temperature/environment changes. 1375 */ 1376 static void 1377 ath_calibrate(ath_t *asc) 1378 { 1379 struct ath_hal *ah = asc->asc_ah; 1380 HAL_BOOL iqcaldone; 1381 1382 asc->asc_stats.ast_per_cal++; 1383 1384 if (ATH_HAL_GETRFGAIN(ah) == HAL_RFGAIN_NEED_CHANGE) { 1385 /* 1386 * Rfgain is out of bounds, reset the chip 1387 * to load new gain values. 1388 */ 1389 ATH_DEBUG((ATH_DBG_HAL, "ath: ath_calibrate(): " 1390 "Need change RFgain\n")); 1391 asc->asc_stats.ast_per_rfgain++; 1392 (void) ath_reset(&asc->asc_isc); 1393 } 1394 if (!ATH_HAL_CALIBRATE(ah, &asc->asc_curchan, &iqcaldone)) { 1395 ATH_DEBUG((ATH_DBG_HAL, "ath: ath_calibrate(): " 1396 "calibration of channel %u failed\n", 1397 asc->asc_curchan.channel)); 1398 asc->asc_stats.ast_per_calfail++; 1399 } 1400 } 1401 1402 static void 1403 ath_watchdog(void *arg) 1404 { 1405 ath_t *asc = arg; 1406 ieee80211com_t *ic = &asc->asc_isc; 1407 int ntimer = 0; 1408 1409 ATH_LOCK(asc); 1410 ic->ic_watchdog_timer = 0; 1411 if (!ATH_IS_RUNNING(asc)) { 1412 ATH_UNLOCK(asc); 1413 return; 1414 } 1415 1416 if (ic->ic_state == IEEE80211_S_RUN) { 1417 /* periodic recalibration */ 1418 ath_calibrate(asc); 1419 1420 /* 1421 * Start the background rate control thread if we 1422 * are not configured to use a fixed xmit rate. 1423 */ 1424 if (ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE) { 1425 asc->asc_stats.ast_rate_calls ++; 1426 if (ic->ic_opmode == IEEE80211_M_STA) 1427 ath_rate_ctl(ic, ic->ic_bss); 1428 else 1429 ieee80211_iterate_nodes(&ic->ic_sta, 1430 ath_rate_cb, asc); 1431 } 1432 1433 ntimer = 1; 1434 } 1435 ATH_UNLOCK(asc); 1436 1437 ieee80211_watchdog(ic); 1438 if (ntimer != 0) 1439 ieee80211_start_watchdog(ic, ntimer); 1440 } 1441 1442 static uint_t 1443 ath_intr(caddr_t arg) 1444 { 1445 /* LINTED E_BAD_PTR_CAST_ALIGN */ 1446 ath_t *asc = (ath_t *)arg; 1447 struct ath_hal *ah = asc->asc_ah; 1448 HAL_INT status; 1449 ieee80211com_t *ic = (ieee80211com_t *)asc; 1450 1451 ATH_LOCK(asc); 1452 1453 if (!ATH_IS_RUNNING(asc)) { 1454 /* 1455 * The hardware is not ready/present, don't touch anything. 1456 * Note this can happen early on if the IRQ is shared. 1457 */ 1458 ATH_UNLOCK(asc); 1459 return (DDI_INTR_UNCLAIMED); 1460 } 1461 1462 if (!ATH_HAL_INTRPEND(ah)) { /* shared irq, not for us */ 1463 ATH_UNLOCK(asc); 1464 return (DDI_INTR_UNCLAIMED); 1465 } 1466 1467 ATH_HAL_GETISR(ah, &status); 1468 status &= asc->asc_imask; 1469 if (status & HAL_INT_FATAL) { 1470 asc->asc_stats.ast_hardware++; 1471 goto reset; 1472 } else if (status & HAL_INT_RXORN) { 1473 asc->asc_stats.ast_rxorn++; 1474 goto reset; 1475 } else { 1476 if (status & HAL_INT_RXEOL) { 1477 asc->asc_stats.ast_rxeol++; 1478 asc->asc_rxlink = NULL; 1479 } 1480 if (status & HAL_INT_TXURN) { 1481 asc->asc_stats.ast_txurn++; 1482 ATH_HAL_UPDATETXTRIGLEVEL(ah, AH_TRUE); 1483 } 1484 1485 if (status & HAL_INT_RX) { 1486 asc->asc_rx_pend = 1; 1487 ddi_trigger_softintr(asc->asc_softint_id); 1488 } 1489 if (status & HAL_INT_TX) { 1490 ath_tx_handler(asc); 1491 } 1492 ATH_UNLOCK(asc); 1493 1494 if (status & HAL_INT_SWBA) { 1495 /* This will occur only in Host-AP or Ad-Hoc mode */ 1496 return (DDI_INTR_CLAIMED); 1497 } 1498 if (status & HAL_INT_BMISS) { 1499 if (ic->ic_state == IEEE80211_S_RUN) { 1500 (void) ieee80211_new_state(ic, 1501 IEEE80211_S_ASSOC, -1); 1502 } 1503 } 1504 } 1505 1506 return (DDI_INTR_CLAIMED); 1507 reset: 1508 (void) ath_reset(ic); 1509 ATH_UNLOCK(asc); 1510 return (DDI_INTR_CLAIMED); 1511 } 1512 1513 static uint_t 1514 ath_softint_handler(caddr_t data) 1515 { 1516 /* LINTED E_BAD_PTR_CAST_ALIGN */ 1517 ath_t *asc = (ath_t *)data; 1518 1519 /* 1520 * Check if the soft interrupt is triggered by another 1521 * driver at the same level. 1522 */ 1523 ATH_LOCK(asc); 1524 if (asc->asc_rx_pend) { /* Soft interrupt for this driver */ 1525 asc->asc_rx_pend = 0; 1526 ATH_UNLOCK(asc); 1527 ath_rx_handler(asc); 1528 return (DDI_INTR_CLAIMED); 1529 } 1530 ATH_UNLOCK(asc); 1531 return (DDI_INTR_UNCLAIMED); 1532 } 1533 1534 /* 1535 * following are gld callback routine 1536 * ath_gld_send, ath_gld_ioctl, ath_gld_gstat 1537 * are listed in other corresponding sections. 1538 * reset the hardware w/o losing operational state. this is 1539 * basically a more efficient way of doing ath_gld_stop, ath_gld_start, 1540 * followed by state transitions to the current 802.11 1541 * operational state. used to recover from errors rx overrun 1542 * and to reset the hardware when rf gain settings must be reset. 1543 */ 1544 1545 static void 1546 ath_stop_locked(ath_t *asc) 1547 { 1548 ieee80211com_t *ic = (ieee80211com_t *)asc; 1549 struct ath_hal *ah = asc->asc_ah; 1550 1551 ATH_LOCK_ASSERT(asc); 1552 if (!asc->asc_isrunning) 1553 return; 1554 1555 /* 1556 * Shutdown the hardware and driver: 1557 * reset 802.11 state machine 1558 * turn off timers 1559 * disable interrupts 1560 * turn off the radio 1561 * clear transmit machinery 1562 * clear receive machinery 1563 * drain and release tx queues 1564 * reclaim beacon resources 1565 * power down hardware 1566 * 1567 * Note that some of this work is not possible if the 1568 * hardware is gone (invalid). 1569 */ 1570 ATH_UNLOCK(asc); 1571 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1572 ieee80211_stop_watchdog(ic); 1573 ATH_LOCK(asc); 1574 ATH_HAL_INTRSET(ah, 0); 1575 ath_draintxq(asc); 1576 if (!asc->asc_invalid) { 1577 ath_stoprecv(asc); 1578 ATH_HAL_PHYDISABLE(ah); 1579 } else { 1580 asc->asc_rxlink = NULL; 1581 } 1582 asc->asc_isrunning = 0; 1583 } 1584 1585 static void 1586 ath_m_stop(void *arg) 1587 { 1588 ath_t *asc = arg; 1589 struct ath_hal *ah = asc->asc_ah; 1590 1591 ATH_LOCK(asc); 1592 ath_stop_locked(asc); 1593 ATH_HAL_SETPOWER(ah, HAL_PM_AWAKE); 1594 asc->asc_invalid = 1; 1595 ATH_UNLOCK(asc); 1596 } 1597 1598 static int 1599 ath_start_locked(ath_t *asc) 1600 { 1601 ieee80211com_t *ic = (ieee80211com_t *)asc; 1602 struct ath_hal *ah = asc->asc_ah; 1603 HAL_STATUS status; 1604 1605 ATH_LOCK_ASSERT(asc); 1606 1607 /* 1608 * The basic interface to setting the hardware in a good 1609 * state is ``reset''. On return the hardware is known to 1610 * be powered up and with interrupts disabled. This must 1611 * be followed by initialization of the appropriate bits 1612 * and then setup of the interrupt mask. 1613 */ 1614 asc->asc_curchan.channel = ic->ic_curchan->ich_freq; 1615 asc->asc_curchan.channelFlags = ath_chan2flags(ic, ic->ic_curchan); 1616 if (!ATH_HAL_RESET(ah, (HAL_OPMODE)ic->ic_opmode, 1617 &asc->asc_curchan, AH_FALSE, &status)) { 1618 ATH_DEBUG((ATH_DBG_HAL, "ath: ath_m_start(): " 1619 "reset hardware failed: '%s' (HAL status %u)\n", 1620 ath_get_hal_status_desc(status), status)); 1621 return (ENOTACTIVE); 1622 } 1623 1624 (void) ath_startrecv(asc); 1625 1626 /* 1627 * Enable interrupts. 1628 */ 1629 asc->asc_imask = HAL_INT_RX | HAL_INT_TX 1630 | HAL_INT_RXEOL | HAL_INT_RXORN 1631 | HAL_INT_FATAL | HAL_INT_GLOBAL; 1632 ATH_HAL_INTRSET(ah, asc->asc_imask); 1633 1634 /* 1635 * The hardware should be ready to go now so it's safe 1636 * to kick the 802.11 state machine as it's likely to 1637 * immediately call back to us to send mgmt frames. 1638 */ 1639 ath_chan_change(asc, ic->ic_curchan); 1640 1641 asc->asc_isrunning = 1; 1642 1643 return (0); 1644 } 1645 1646 int 1647 ath_m_start(void *arg) 1648 { 1649 ath_t *asc = arg; 1650 int err; 1651 1652 ATH_LOCK(asc); 1653 /* 1654 * Stop anything previously setup. This is safe 1655 * whether this is the first time through or not. 1656 */ 1657 ath_stop_locked(asc); 1658 1659 if ((err = ath_start_locked(asc)) != 0) { 1660 ATH_UNLOCK(asc); 1661 return (err); 1662 } 1663 1664 asc->asc_invalid = 0; 1665 ATH_UNLOCK(asc); 1666 1667 return (0); 1668 } 1669 1670 1671 static int 1672 ath_m_unicst(void *arg, const uint8_t *macaddr) 1673 { 1674 ath_t *asc = arg; 1675 struct ath_hal *ah = asc->asc_ah; 1676 1677 ATH_DEBUG((ATH_DBG_GLD, "ath: ath_gld_saddr(): " 1678 "%.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", 1679 macaddr[0], macaddr[1], macaddr[2], 1680 macaddr[3], macaddr[4], macaddr[5])); 1681 1682 ATH_LOCK(asc); 1683 IEEE80211_ADDR_COPY(asc->asc_isc.ic_macaddr, macaddr); 1684 ATH_HAL_SETMAC(ah, asc->asc_isc.ic_macaddr); 1685 1686 (void) ath_reset(&asc->asc_isc); 1687 ATH_UNLOCK(asc); 1688 return (0); 1689 } 1690 1691 static int 1692 ath_m_promisc(void *arg, boolean_t on) 1693 { 1694 ath_t *asc = arg; 1695 struct ath_hal *ah = asc->asc_ah; 1696 uint32_t rfilt; 1697 1698 ATH_LOCK(asc); 1699 rfilt = ATH_HAL_GETRXFILTER(ah); 1700 if (on) 1701 rfilt |= HAL_RX_FILTER_PROM; 1702 else 1703 rfilt &= ~HAL_RX_FILTER_PROM; 1704 asc->asc_promisc = on; 1705 ATH_HAL_SETRXFILTER(ah, rfilt); 1706 ATH_UNLOCK(asc); 1707 1708 return (0); 1709 } 1710 1711 static int 1712 ath_m_multicst(void *arg, boolean_t add, const uint8_t *mca) 1713 { 1714 ath_t *asc = arg; 1715 struct ath_hal *ah = asc->asc_ah; 1716 uint32_t val, index, bit; 1717 uint8_t pos; 1718 uint32_t *mfilt = asc->asc_mcast_hash; 1719 1720 ATH_LOCK(asc); 1721 /* calculate XOR of eight 6bit values */ 1722 val = ATH_LE_READ_4(mca + 0); 1723 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1724 val = ATH_LE_READ_4(mca + 3); 1725 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1726 pos &= 0x3f; 1727 index = pos / 32; 1728 bit = 1 << (pos % 32); 1729 1730 if (add) { /* enable multicast */ 1731 asc->asc_mcast_refs[pos]++; 1732 mfilt[index] |= bit; 1733 } else { /* disable multicast */ 1734 if (--asc->asc_mcast_refs[pos] == 0) 1735 mfilt[index] &= ~bit; 1736 } 1737 ATH_HAL_SETMCASTFILTER(ah, mfilt[0], mfilt[1]); 1738 1739 ATH_UNLOCK(asc); 1740 return (0); 1741 } 1742 1743 static void 1744 ath_m_ioctl(void *arg, queue_t *wq, mblk_t *mp) 1745 { 1746 ath_t *asc = arg; 1747 int32_t err; 1748 1749 err = ieee80211_ioctl(&asc->asc_isc, wq, mp); 1750 ATH_LOCK(asc); 1751 if (err == ENETRESET) { 1752 if (ATH_IS_RUNNING(asc)) { 1753 ATH_UNLOCK(asc); 1754 (void) ath_m_start(asc); 1755 (void) ieee80211_new_state(&asc->asc_isc, 1756 IEEE80211_S_SCAN, -1); 1757 ATH_LOCK(asc); 1758 } 1759 } 1760 ATH_UNLOCK(asc); 1761 } 1762 1763 static int 1764 ath_m_stat(void *arg, uint_t stat, uint64_t *val) 1765 { 1766 ath_t *asc = arg; 1767 ieee80211com_t *ic = (ieee80211com_t *)asc; 1768 struct ieee80211_node *in = ic->ic_bss; 1769 struct ieee80211_rateset *rs = &in->in_rates; 1770 1771 ATH_LOCK(asc); 1772 switch (stat) { 1773 case MAC_STAT_IFSPEED: 1774 *val = (rs->ir_rates[in->in_txrate] & IEEE80211_RATE_VAL) / 2 * 1775 1000000ull; 1776 break; 1777 case MAC_STAT_NOXMTBUF: 1778 *val = asc->asc_stats.ast_tx_nobuf + 1779 asc->asc_stats.ast_tx_nobufmgt; 1780 break; 1781 case MAC_STAT_IERRORS: 1782 *val = asc->asc_stats.ast_rx_tooshort; 1783 break; 1784 case MAC_STAT_RBYTES: 1785 *val = ic->ic_stats.is_rx_bytes; 1786 break; 1787 case MAC_STAT_IPACKETS: 1788 *val = ic->ic_stats.is_rx_frags; 1789 break; 1790 case MAC_STAT_OBYTES: 1791 *val = ic->ic_stats.is_tx_bytes; 1792 break; 1793 case MAC_STAT_OPACKETS: 1794 *val = ic->ic_stats.is_tx_frags; 1795 break; 1796 case MAC_STAT_OERRORS: 1797 case WIFI_STAT_TX_FAILED: 1798 *val = asc->asc_stats.ast_tx_fifoerr + 1799 asc->asc_stats.ast_tx_xretries + 1800 asc->asc_stats.ast_tx_discard; 1801 break; 1802 case WIFI_STAT_TX_RETRANS: 1803 *val = asc->asc_stats.ast_tx_xretries; 1804 break; 1805 case WIFI_STAT_FCS_ERRORS: 1806 *val = asc->asc_stats.ast_rx_crcerr; 1807 break; 1808 case WIFI_STAT_WEP_ERRORS: 1809 *val = asc->asc_stats.ast_rx_badcrypt; 1810 break; 1811 case WIFI_STAT_TX_FRAGS: 1812 case WIFI_STAT_MCAST_TX: 1813 case WIFI_STAT_RTS_SUCCESS: 1814 case WIFI_STAT_RTS_FAILURE: 1815 case WIFI_STAT_ACK_FAILURE: 1816 case WIFI_STAT_RX_FRAGS: 1817 case WIFI_STAT_MCAST_RX: 1818 case WIFI_STAT_RX_DUPS: 1819 ATH_UNLOCK(asc); 1820 return (ieee80211_stat(ic, stat, val)); 1821 default: 1822 ATH_UNLOCK(asc); 1823 return (ENOTSUP); 1824 } 1825 ATH_UNLOCK(asc); 1826 1827 return (0); 1828 } 1829 1830 static int 1831 ath_pci_setup(ath_t *asc) 1832 { 1833 uint16_t command; 1834 1835 /* 1836 * Enable memory mapping and bus mastering 1837 */ 1838 ASSERT(asc != NULL); 1839 command = pci_config_get16(asc->asc_cfg_handle, PCI_CONF_COMM); 1840 command |= PCI_COMM_MAE | PCI_COMM_ME; 1841 pci_config_put16(asc->asc_cfg_handle, PCI_CONF_COMM, command); 1842 command = pci_config_get16(asc->asc_cfg_handle, PCI_CONF_COMM); 1843 if ((command & PCI_COMM_MAE) == 0) { 1844 ath_problem("ath: ath_pci_setup(): " 1845 "failed to enable memory mapping\n"); 1846 return (EIO); 1847 } 1848 if ((command & PCI_COMM_ME) == 0) { 1849 ath_problem("ath: ath_pci_setup(): " 1850 "failed to enable bus mastering\n"); 1851 return (EIO); 1852 } 1853 ATH_DEBUG((ATH_DBG_INIT, "ath: ath_pci_setup(): " 1854 "set command reg to 0x%x \n", command)); 1855 1856 return (0); 1857 } 1858 1859 static int 1860 ath_resume(dev_info_t *devinfo) 1861 { 1862 ath_t *asc; 1863 int ret = DDI_SUCCESS; 1864 1865 asc = ddi_get_soft_state(ath_soft_state_p, ddi_get_instance(devinfo)); 1866 if (asc == NULL) { 1867 ATH_DEBUG((ATH_DBG_SUSPEND, "ath: ath_resume(): " 1868 "failed to get soft state\n")); 1869 return (DDI_FAILURE); 1870 } 1871 1872 ATH_LOCK(asc); 1873 /* 1874 * Set up config space command register(s). Refuse 1875 * to resume on failure. 1876 */ 1877 if (ath_pci_setup(asc) != 0) { 1878 ATH_DEBUG((ATH_DBG_SUSPEND, "ath: ath_resume(): " 1879 "ath_pci_setup() failed\n")); 1880 ATH_UNLOCK(asc); 1881 return (DDI_FAILURE); 1882 } 1883 1884 if (!asc->asc_invalid) 1885 ret = ath_start_locked(asc); 1886 ATH_UNLOCK(asc); 1887 1888 return (ret); 1889 } 1890 1891 static int 1892 ath_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 1893 { 1894 ath_t *asc; 1895 ieee80211com_t *ic; 1896 struct ath_hal *ah; 1897 uint8_t csz; 1898 HAL_STATUS status; 1899 caddr_t regs; 1900 uint32_t i, val; 1901 uint16_t vendor_id, device_id; 1902 const char *athname; 1903 int32_t ath_countrycode = CTRY_DEFAULT; /* country code */ 1904 int32_t err, ath_regdomain = 0; /* regulatory domain */ 1905 char strbuf[32]; 1906 int instance; 1907 wifi_data_t wd = { 0 }; 1908 mac_register_t *macp; 1909 1910 switch (cmd) { 1911 case DDI_ATTACH: 1912 break; 1913 1914 case DDI_RESUME: 1915 return (ath_resume(devinfo)); 1916 1917 default: 1918 return (DDI_FAILURE); 1919 } 1920 1921 instance = ddi_get_instance(devinfo); 1922 if (ddi_soft_state_zalloc(ath_soft_state_p, instance) != DDI_SUCCESS) { 1923 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 1924 "Unable to alloc softstate\n")); 1925 return (DDI_FAILURE); 1926 } 1927 1928 asc = ddi_get_soft_state(ath_soft_state_p, ddi_get_instance(devinfo)); 1929 ic = (ieee80211com_t *)asc; 1930 asc->asc_dev = devinfo; 1931 1932 mutex_init(&asc->asc_genlock, NULL, MUTEX_DRIVER, NULL); 1933 mutex_init(&asc->asc_txbuflock, NULL, MUTEX_DRIVER, NULL); 1934 mutex_init(&asc->asc_rxbuflock, NULL, MUTEX_DRIVER, NULL); 1935 mutex_init(&asc->asc_resched_lock, NULL, MUTEX_DRIVER, NULL); 1936 1937 err = pci_config_setup(devinfo, &asc->asc_cfg_handle); 1938 if (err != DDI_SUCCESS) { 1939 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 1940 "pci_config_setup() failed")); 1941 goto attach_fail0; 1942 } 1943 1944 if (ath_pci_setup(asc) != 0) 1945 goto attach_fail1; 1946 1947 /* 1948 * Cache line size is used to size and align various 1949 * structures used to communicate with the hardware. 1950 */ 1951 csz = pci_config_get8(asc->asc_cfg_handle, PCI_CONF_CACHE_LINESZ); 1952 if (csz == 0) { 1953 /* 1954 * We must have this setup properly for rx buffer 1955 * DMA to work so force a reasonable value here if it 1956 * comes up zero. 1957 */ 1958 csz = ATH_DEF_CACHE_BYTES / sizeof (uint32_t); 1959 pci_config_put8(asc->asc_cfg_handle, PCI_CONF_CACHE_LINESZ, 1960 csz); 1961 } 1962 asc->asc_cachelsz = csz << 2; 1963 vendor_id = pci_config_get16(asc->asc_cfg_handle, PCI_CONF_VENID); 1964 device_id = pci_config_get16(asc->asc_cfg_handle, PCI_CONF_DEVID); 1965 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): vendor 0x%x, " 1966 "device id 0x%x, cache size %d\n", vendor_id, device_id, csz)); 1967 1968 athname = ath_hal_probe(vendor_id, device_id); 1969 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): athname: %s\n", 1970 athname ? athname : "Atheros ???")); 1971 1972 pci_config_put8(asc->asc_cfg_handle, PCI_CONF_LATENCY_TIMER, 0xa8); 1973 val = pci_config_get32(asc->asc_cfg_handle, 0x40); 1974 if ((val & 0x0000ff00) != 0) 1975 pci_config_put32(asc->asc_cfg_handle, 0x40, val & 0xffff00ff); 1976 1977 err = ddi_regs_map_setup(devinfo, 1, 1978 ®s, 0, 0, &ath_reg_accattr, &asc->asc_io_handle); 1979 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 1980 "regs map1 = %x err=%d\n", regs, err)); 1981 if (err != DDI_SUCCESS) { 1982 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 1983 "ddi_regs_map_setup() failed")); 1984 goto attach_fail1; 1985 } 1986 1987 ah = ath_hal_attach(device_id, asc, 0, regs, &status); 1988 if (ah == NULL) { 1989 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 1990 "unable to attach hw: '%s' (HAL status %u)\n", 1991 ath_get_hal_status_desc(status), status)); 1992 goto attach_fail2; 1993 } 1994 ATH_HAL_INTRSET(ah, 0); 1995 asc->asc_ah = ah; 1996 1997 if (ah->ah_abi != HAL_ABI_VERSION) { 1998 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 1999 "HAL ABI mismatch detected (0x%x != 0x%x)\n", 2000 ah->ah_abi, HAL_ABI_VERSION)); 2001 goto attach_fail3; 2002 } 2003 2004 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 2005 "HAL ABI version 0x%x\n", ah->ah_abi)); 2006 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 2007 "HAL mac version %d.%d, phy version %d.%d\n", 2008 ah->ah_macVersion, ah->ah_macRev, 2009 ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf)); 2010 if (ah->ah_analog5GhzRev) 2011 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 2012 "HAL 5ghz radio version %d.%d\n", 2013 ah->ah_analog5GhzRev >> 4, 2014 ah->ah_analog5GhzRev & 0xf)); 2015 if (ah->ah_analog2GhzRev) 2016 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 2017 "HAL 2ghz radio version %d.%d\n", 2018 ah->ah_analog2GhzRev >> 4, 2019 ah->ah_analog2GhzRev & 0xf)); 2020 2021 /* 2022 * Check if the MAC has multi-rate retry support. 2023 * We do this by trying to setup a fake extended 2024 * descriptor. MAC's that don't have support will 2025 * return false w/o doing anything. MAC's that do 2026 * support it will return true w/o doing anything. 2027 */ 2028 asc->asc_mrretry = ATH_HAL_SETUPXTXDESC(ah, NULL, 0, 0, 0, 0, 0, 0); 2029 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 2030 "multi rate retry support=%x\n", 2031 asc->asc_mrretry)); 2032 2033 /* 2034 * Get the hardware key cache size. 2035 */ 2036 asc->asc_keymax = ATH_HAL_KEYCACHESIZE(ah); 2037 if (asc->asc_keymax > sizeof (asc->asc_keymap) * NBBY) { 2038 ATH_DEBUG((ATH_DBG_ATTACH, "ath_attach:" 2039 " Warning, using only %u entries in %u key cache\n", 2040 sizeof (asc->asc_keymap) * NBBY, asc->asc_keymax)); 2041 asc->asc_keymax = sizeof (asc->asc_keymap) * NBBY; 2042 } 2043 /* 2044 * Reset the key cache since some parts do not 2045 * reset the contents on initial power up. 2046 */ 2047 for (i = 0; i < asc->asc_keymax; i++) 2048 ATH_HAL_KEYRESET(ah, i); 2049 2050 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2051 setbit(asc->asc_keymap, i); 2052 setbit(asc->asc_keymap, i+32); 2053 setbit(asc->asc_keymap, i+64); 2054 setbit(asc->asc_keymap, i+32+64); 2055 } 2056 2057 ATH_HAL_GETREGDOMAIN(ah, (uint32_t *)&ath_regdomain); 2058 ATH_HAL_GETCOUNTRYCODE(ah, &ath_countrycode); 2059 /* 2060 * Collect the channel list using the default country 2061 * code and including outdoor channels. The 802.11 layer 2062 * is resposible for filtering this list to a set of 2063 * channels that it considers ok to use. 2064 */ 2065 asc->asc_have11g = 0; 2066 2067 /* enable outdoor use, enable extended channels */ 2068 err = ath_getchannels(asc, ath_countrycode, AH_FALSE, AH_TRUE); 2069 if (err != 0) 2070 goto attach_fail3; 2071 2072 /* 2073 * Setup rate tables for all potential media types. 2074 */ 2075 ath_rate_setup(asc, IEEE80211_MODE_11A); 2076 ath_rate_setup(asc, IEEE80211_MODE_11B); 2077 ath_rate_setup(asc, IEEE80211_MODE_11G); 2078 ath_rate_setup(asc, IEEE80211_MODE_TURBO_A); 2079 2080 /* Setup here so ath_rate_update is happy */ 2081 ath_setcurmode(asc, IEEE80211_MODE_11A); 2082 2083 err = ath_desc_alloc(devinfo, asc); 2084 if (err != DDI_SUCCESS) { 2085 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 2086 "failed to allocate descriptors: %d\n", err)); 2087 goto attach_fail3; 2088 } 2089 2090 /* Setup transmit queues in the HAL */ 2091 if (ath_txq_setup(asc)) 2092 goto attach_fail4; 2093 2094 ATH_HAL_GETMAC(ah, ic->ic_macaddr); 2095 2096 /* 2097 * Initialize pointers to device specific functions which 2098 * will be used by the generic layer. 2099 */ 2100 /* 11g support is identified when we fetch the channel set */ 2101 if (asc->asc_have11g) 2102 ic->ic_caps |= IEEE80211_C_SHPREAMBLE | 2103 IEEE80211_C_SHSLOT; /* short slot time */ 2104 /* 2105 * Query the hal to figure out h/w crypto support. 2106 */ 2107 if (ATH_HAL_CIPHERSUPPORTED(ah, HAL_CIPHER_WEP)) 2108 ic->ic_caps |= IEEE80211_C_WEP; 2109 if (ATH_HAL_CIPHERSUPPORTED(ah, HAL_CIPHER_AES_OCB)) 2110 ic->ic_caps |= IEEE80211_C_AES; 2111 if (ATH_HAL_CIPHERSUPPORTED(ah, HAL_CIPHER_AES_CCM)) { 2112 ATH_DEBUG((ATH_DBG_ATTACH, "Atheros support H/W CCMP\n")); 2113 ic->ic_caps |= IEEE80211_C_AES_CCM; 2114 } 2115 if (ATH_HAL_CIPHERSUPPORTED(ah, HAL_CIPHER_CKIP)) 2116 ic->ic_caps |= IEEE80211_C_CKIP; 2117 if (ATH_HAL_CIPHERSUPPORTED(ah, HAL_CIPHER_TKIP)) { 2118 ATH_DEBUG((ATH_DBG_ATTACH, "Atheros support H/W TKIP\n")); 2119 ic->ic_caps |= IEEE80211_C_TKIP; 2120 /* 2121 * Check if h/w does the MIC and/or whether the 2122 * separate key cache entries are required to 2123 * handle both tx+rx MIC keys. 2124 */ 2125 if (ATH_HAL_CIPHERSUPPORTED(ah, HAL_CIPHER_MIC)) { 2126 ATH_DEBUG((ATH_DBG_ATTACH, "Support H/W TKIP MIC\n")); 2127 ic->ic_caps |= IEEE80211_C_TKIPMIC; 2128 } 2129 if (ATH_HAL_TKIPSPLIT(ah)) 2130 asc->asc_splitmic = 1; 2131 } 2132 ic->ic_caps |= IEEE80211_C_WPA; /* Support WPA/WPA2 */ 2133 2134 asc->asc_hasclrkey = ATH_HAL_CIPHERSUPPORTED(ah, HAL_CIPHER_CLR); 2135 ic->ic_phytype = IEEE80211_T_OFDM; 2136 ic->ic_opmode = IEEE80211_M_STA; 2137 ic->ic_state = IEEE80211_S_INIT; 2138 ic->ic_maxrssi = ATH_MAX_RSSI; 2139 ic->ic_set_shortslot = ath_set_shortslot; 2140 ic->ic_xmit = ath_xmit; 2141 ieee80211_attach(ic); 2142 2143 /* different instance has different WPA door */ 2144 (void) snprintf(ic->ic_wpadoor, MAX_IEEE80211STR, "%s_%s%d", WPA_DOOR, 2145 ddi_driver_name(devinfo), 2146 ddi_get_instance(devinfo)); 2147 2148 /* Override 80211 default routines */ 2149 ic->ic_reset = ath_reset; 2150 asc->asc_newstate = ic->ic_newstate; 2151 ic->ic_newstate = ath_newstate; 2152 ic->ic_watchdog = ath_watchdog; 2153 ic->ic_node_alloc = ath_node_alloc; 2154 ic->ic_node_free = ath_node_free; 2155 ic->ic_crypto.cs_key_alloc = ath_key_alloc; 2156 ic->ic_crypto.cs_key_delete = ath_key_delete; 2157 ic->ic_crypto.cs_key_set = ath_key_set; 2158 ieee80211_media_init(ic); 2159 /* 2160 * initialize default tx key 2161 */ 2162 ic->ic_def_txkey = 0; 2163 2164 asc->asc_rx_pend = 0; 2165 ATH_HAL_INTRSET(ah, 0); 2166 err = ddi_add_softintr(devinfo, DDI_SOFTINT_LOW, 2167 &asc->asc_softint_id, NULL, 0, ath_softint_handler, (caddr_t)asc); 2168 if (err != DDI_SUCCESS) { 2169 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 2170 "ddi_add_softintr() failed\n")); 2171 goto attach_fail5; 2172 } 2173 2174 if (ddi_get_iblock_cookie(devinfo, 0, &asc->asc_iblock) 2175 != DDI_SUCCESS) { 2176 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 2177 "Can not get iblock cookie for INT\n")); 2178 goto attach_fail6; 2179 } 2180 2181 if (ddi_add_intr(devinfo, 0, NULL, NULL, ath_intr, 2182 (caddr_t)asc) != DDI_SUCCESS) { 2183 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 2184 "Can not set intr for ATH driver\n")); 2185 goto attach_fail6; 2186 } 2187 2188 /* 2189 * Provide initial settings for the WiFi plugin; whenever this 2190 * information changes, we need to call mac_plugindata_update() 2191 */ 2192 wd.wd_opmode = ic->ic_opmode; 2193 wd.wd_secalloc = WIFI_SEC_NONE; 2194 IEEE80211_ADDR_COPY(wd.wd_bssid, ic->ic_bss->in_bssid); 2195 2196 if ((macp = mac_alloc(MAC_VERSION)) == NULL) { 2197 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 2198 "MAC version mismatch\n")); 2199 goto attach_fail7; 2200 } 2201 2202 macp->m_type_ident = MAC_PLUGIN_IDENT_WIFI; 2203 macp->m_driver = asc; 2204 macp->m_dip = devinfo; 2205 macp->m_src_addr = ic->ic_macaddr; 2206 macp->m_callbacks = &ath_m_callbacks; 2207 macp->m_min_sdu = 0; 2208 macp->m_max_sdu = IEEE80211_MTU; 2209 macp->m_pdata = &wd; 2210 macp->m_pdata_size = sizeof (wd); 2211 2212 err = mac_register(macp, &ic->ic_mach); 2213 mac_free(macp); 2214 if (err != 0) { 2215 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 2216 "mac_register err %x\n", err)); 2217 goto attach_fail7; 2218 } 2219 2220 /* Create minor node of type DDI_NT_NET_WIFI */ 2221 (void) snprintf(strbuf, sizeof (strbuf), "%s%d", 2222 ATH_NODENAME, instance); 2223 err = ddi_create_minor_node(devinfo, strbuf, S_IFCHR, 2224 instance + 1, DDI_NT_NET_WIFI, 0); 2225 if (err != DDI_SUCCESS) 2226 ATH_DEBUG((ATH_DBG_ATTACH, "WARN: ath: ath_attach(): " 2227 "Create minor node failed - %d\n", err)); 2228 2229 mac_link_update(ic->ic_mach, LINK_STATE_DOWN); 2230 asc->asc_invalid = 1; 2231 asc->asc_isrunning = 0; 2232 asc->asc_promisc = B_FALSE; 2233 bzero(asc->asc_mcast_refs, sizeof (asc->asc_mcast_refs)); 2234 bzero(asc->asc_mcast_hash, sizeof (asc->asc_mcast_hash)); 2235 return (DDI_SUCCESS); 2236 attach_fail7: 2237 ddi_remove_intr(devinfo, 0, asc->asc_iblock); 2238 attach_fail6: 2239 ddi_remove_softintr(asc->asc_softint_id); 2240 attach_fail5: 2241 (void) ieee80211_detach(ic); 2242 attach_fail4: 2243 ath_desc_free(asc); 2244 attach_fail3: 2245 ah->ah_detach(asc->asc_ah); 2246 attach_fail2: 2247 ddi_regs_map_free(&asc->asc_io_handle); 2248 attach_fail1: 2249 pci_config_teardown(&asc->asc_cfg_handle); 2250 attach_fail0: 2251 asc->asc_invalid = 1; 2252 mutex_destroy(&asc->asc_txbuflock); 2253 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 2254 if (ATH_TXQ_SETUP(asc, i)) { 2255 struct ath_txq *txq = &asc->asc_txq[i]; 2256 mutex_destroy(&txq->axq_lock); 2257 } 2258 } 2259 mutex_destroy(&asc->asc_rxbuflock); 2260 mutex_destroy(&asc->asc_genlock); 2261 mutex_destroy(&asc->asc_resched_lock); 2262 ddi_soft_state_free(ath_soft_state_p, instance); 2263 2264 return (DDI_FAILURE); 2265 } 2266 2267 /* 2268 * Suspend transmit/receive for powerdown 2269 */ 2270 static int 2271 ath_suspend(ath_t *asc) 2272 { 2273 ATH_LOCK(asc); 2274 ath_stop_locked(asc); 2275 ATH_UNLOCK(asc); 2276 ATH_DEBUG((ATH_DBG_SUSPEND, "ath: suspended.\n")); 2277 2278 return (DDI_SUCCESS); 2279 } 2280 2281 static int32_t 2282 ath_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 2283 { 2284 ath_t *asc; 2285 2286 asc = ddi_get_soft_state(ath_soft_state_p, ddi_get_instance(devinfo)); 2287 ASSERT(asc != NULL); 2288 2289 switch (cmd) { 2290 case DDI_DETACH: 2291 break; 2292 2293 case DDI_SUSPEND: 2294 return (ath_suspend(asc)); 2295 2296 default: 2297 return (DDI_FAILURE); 2298 } 2299 2300 ath_stop_scantimer(asc); 2301 2302 /* disable interrupts */ 2303 ATH_HAL_INTRSET(asc->asc_ah, 0); 2304 2305 /* 2306 * Unregister from the MAC layer subsystem 2307 */ 2308 if (mac_unregister(asc->asc_isc.ic_mach) != 0) 2309 return (DDI_FAILURE); 2310 2311 /* free intterrupt resources */ 2312 ddi_remove_intr(devinfo, 0, asc->asc_iblock); 2313 ddi_remove_softintr(asc->asc_softint_id); 2314 2315 /* 2316 * NB: the order of these is important: 2317 * o call the 802.11 layer before detaching the hal to 2318 * insure callbacks into the driver to delete global 2319 * key cache entries can be handled 2320 * o reclaim the tx queue data structures after calling 2321 * the 802.11 layer as we'll get called back to reclaim 2322 * node state and potentially want to use them 2323 * o to cleanup the tx queues the hal is called, so detach 2324 * it last 2325 */ 2326 ieee80211_detach(&asc->asc_isc); 2327 ath_desc_free(asc); 2328 ath_txq_cleanup(asc); 2329 asc->asc_ah->ah_detach(asc->asc_ah); 2330 2331 /* free io handle */ 2332 ddi_regs_map_free(&asc->asc_io_handle); 2333 pci_config_teardown(&asc->asc_cfg_handle); 2334 2335 /* destroy locks */ 2336 mutex_destroy(&asc->asc_rxbuflock); 2337 mutex_destroy(&asc->asc_genlock); 2338 mutex_destroy(&asc->asc_resched_lock); 2339 2340 ddi_remove_minor_node(devinfo, NULL); 2341 ddi_soft_state_free(ath_soft_state_p, ddi_get_instance(devinfo)); 2342 2343 return (DDI_SUCCESS); 2344 } 2345 2346 DDI_DEFINE_STREAM_OPS(ath_dev_ops, nulldev, nulldev, ath_attach, ath_detach, 2347 nodev, NULL, D_MP, NULL); 2348 2349 static struct modldrv ath_modldrv = { 2350 &mod_driverops, /* Type of module. This one is a driver */ 2351 "ath driver 1.3.1/HAL 0.9.17.2", /* short description */ 2352 &ath_dev_ops /* driver specific ops */ 2353 }; 2354 2355 static struct modlinkage modlinkage = { 2356 MODREV_1, (void *)&ath_modldrv, NULL 2357 }; 2358 2359 2360 int 2361 _info(struct modinfo *modinfop) 2362 { 2363 return (mod_info(&modlinkage, modinfop)); 2364 } 2365 2366 int 2367 _init(void) 2368 { 2369 int status; 2370 2371 status = ddi_soft_state_init(&ath_soft_state_p, sizeof (ath_t), 1); 2372 if (status != 0) 2373 return (status); 2374 2375 mutex_init(&ath_loglock, NULL, MUTEX_DRIVER, NULL); 2376 ath_halfix_init(); 2377 mac_init_ops(&ath_dev_ops, "ath"); 2378 status = mod_install(&modlinkage); 2379 if (status != 0) { 2380 mac_fini_ops(&ath_dev_ops); 2381 ath_halfix_finit(); 2382 mutex_destroy(&ath_loglock); 2383 ddi_soft_state_fini(&ath_soft_state_p); 2384 } 2385 2386 return (status); 2387 } 2388 2389 int 2390 _fini(void) 2391 { 2392 int status; 2393 2394 status = mod_remove(&modlinkage); 2395 if (status == 0) { 2396 mac_fini_ops(&ath_dev_ops); 2397 ath_halfix_finit(); 2398 mutex_destroy(&ath_loglock); 2399 ddi_soft_state_fini(&ath_soft_state_p); 2400 } 2401 return (status); 2402 } 2403