1 /* 2 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6 /* 7 * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 18 * redistribution must be conditioned upon including a substantially 19 * similar Disclaimer requirement for further binary redistribution. 20 * 3. Neither the names of the above-listed copyright holders nor the names 21 * of any contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * NO WARRANTY 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 28 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 29 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 30 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 33 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 35 * THE POSSIBILITY OF SUCH DAMAGES. 36 * 37 */ 38 39 /* 40 * Driver for the Atheros Wireless LAN controller. 41 * 42 * The Atheros driver calls into net80211 module for IEEE80211 protocol 43 * management functionalities. The driver includes a LLD(Low Level Driver) 44 * part to implement H/W related operations. 45 * The following is the high level structure of ath driver. 46 * (The arrows between modules indicate function call direction.) 47 * 48 * 49 * | 50 * | GLD thread 51 * V 52 * ================== ========================================= 53 * | | |[1] | 54 * | | | GLDv3 Callback functions registered | 55 * | Net80211 | ========================= by | 56 * | module | | | driver | 57 * | | V | | 58 * | |======================== | | 59 * | Functions exported by net80211 | | | 60 * | | | | 61 * ========================================== ================= 62 * | | 63 * V | 64 * +----------------------------------+ | 65 * |[2] | | 66 * | Net80211 Callback functions | | 67 * | registered by LLD | | 68 * +----------------------------------+ | 69 * | | 70 * V v 71 * +-----------------------------------------------------------+ 72 * |[3] | 73 * | LLD Internal functions | 74 * | | 75 * +-----------------------------------------------------------+ 76 * ^ 77 * | Software interrupt thread 78 * | 79 * 80 * The short description of each module is as below: 81 * Module 1: GLD callback functions, which are intercepting the calls from 82 * GLD to LLD. 83 * Module 2: Net80211 callback functions registered by LLD, which 84 * calls into LLD for H/W related functions needed by net80211. 85 * Module 3: LLD Internal functions, which are responsible for allocing 86 * descriptor/buffer, handling interrupt and other H/W 87 * operations. 88 * 89 * All functions are running in 3 types of thread: 90 * 1. GLD callbacks threads, such as ioctl, intr, etc. 91 * 2. Clock interruptt thread which is responsible for scan, rate control and 92 * calibration. 93 * 3. Software Interrupt thread originated in LLD. 94 * 95 * The lock strategy is as below: 96 * There have 4 queues for tx, each queue has one asc_txqlock[i] to 97 * prevent conflicts access to queue resource from different thread. 98 * 99 * All the transmit buffers are contained in asc_txbuf which are 100 * protected by asc_txbuflock. 101 * 102 * Each receive buffers are contained in asc_rxbuf which are protected 103 * by asc_rxbuflock. 104 * 105 * In ath struct, asc_genlock is a general lock, protecting most other 106 * operational data in ath_softc struct and HAL accesses. 107 * It is acquired by the interupt handler and most "mode-ctrl" routines. 108 * 109 * Any of the locks can be acquired singly, but where multiple 110 * locks are acquired, they *must* be in the order: 111 * asc_genlock >> asc_txqlock[i] >> asc_txbuflock >> asc_rxbuflock 112 */ 113 114 #include <sys/param.h> 115 #include <sys/types.h> 116 #include <sys/signal.h> 117 #include <sys/stream.h> 118 #include <sys/termio.h> 119 #include <sys/errno.h> 120 #include <sys/file.h> 121 #include <sys/cmn_err.h> 122 #include <sys/stropts.h> 123 #include <sys/strsubr.h> 124 #include <sys/strtty.h> 125 #include <sys/kbio.h> 126 #include <sys/cred.h> 127 #include <sys/stat.h> 128 #include <sys/consdev.h> 129 #include <sys/kmem.h> 130 #include <sys/modctl.h> 131 #include <sys/ddi.h> 132 #include <sys/sunddi.h> 133 #include <sys/pci.h> 134 #include <sys/errno.h> 135 #include <sys/mac.h> 136 #include <sys/dlpi.h> 137 #include <sys/ethernet.h> 138 #include <sys/list.h> 139 #include <sys/byteorder.h> 140 #include <sys/strsun.h> 141 #include <sys/policy.h> 142 #include <inet/common.h> 143 #include <inet/nd.h> 144 #include <inet/mi.h> 145 #include <inet/wifi_ioctl.h> 146 #include <sys/mac_wifi.h> 147 #include "ath_hal.h" 148 #include "ath_impl.h" 149 #include "ath_aux.h" 150 #include "ath_rate.h" 151 152 #define ATH_MAX_RSSI 63 /* max rssi */ 153 154 extern void ath_halfix_init(void); 155 extern void ath_halfix_finit(void); 156 extern int32_t ath_getset(ath_t *asc, mblk_t *mp, uint32_t cmd); 157 158 /* 159 * PIO access attributes for registers 160 */ 161 static ddi_device_acc_attr_t ath_reg_accattr = { 162 DDI_DEVICE_ATTR_V0, 163 DDI_STRUCTURE_LE_ACC, 164 DDI_STRICTORDER_ACC 165 }; 166 167 /* 168 * DMA access attributes for descriptors: NOT to be byte swapped. 169 */ 170 static ddi_device_acc_attr_t ath_desc_accattr = { 171 DDI_DEVICE_ATTR_V0, 172 DDI_STRUCTURE_LE_ACC, 173 DDI_STRICTORDER_ACC 174 }; 175 176 /* 177 * DMA attributes for rx/tx buffers 178 */ 179 static ddi_dma_attr_t ath_dma_attr = { 180 DMA_ATTR_V0, /* version number */ 181 0, /* low address */ 182 0xffffffffU, /* high address */ 183 0x3ffffU, /* counter register max */ 184 1, /* alignment */ 185 0xFFF, /* burst sizes */ 186 1, /* minimum transfer size */ 187 0x3ffffU, /* max transfer size */ 188 0xffffffffU, /* address register max */ 189 1, /* no scatter-gather */ 190 1, /* granularity of device */ 191 0, /* DMA flags */ 192 }; 193 194 static ddi_dma_attr_t ath_desc_dma_attr = { 195 DMA_ATTR_V0, /* version number */ 196 0, /* low address */ 197 0xffffffffU, /* high address */ 198 0xffffffffU, /* counter register max */ 199 0x1000, /* alignment */ 200 0xFFF, /* burst sizes */ 201 1, /* minimum transfer size */ 202 0xffffffffU, /* max transfer size */ 203 0xffffffffU, /* address register max */ 204 1, /* no scatter-gather */ 205 1, /* granularity of device */ 206 0, /* DMA flags */ 207 }; 208 209 static kmutex_t ath_loglock; 210 static void *ath_soft_state_p = NULL; 211 static int ath_dwelltime = 150; /* scan interval, ms */ 212 213 static int ath_m_stat(void *, uint_t, uint64_t *); 214 static int ath_m_start(void *); 215 static void ath_m_stop(void *); 216 static int ath_m_promisc(void *, boolean_t); 217 static int ath_m_multicst(void *, boolean_t, const uint8_t *); 218 static int ath_m_unicst(void *, const uint8_t *); 219 static mblk_t *ath_m_tx(void *, mblk_t *); 220 static void ath_m_ioctl(void *, queue_t *, mblk_t *); 221 static int ath_m_setprop(void *, const char *, mac_prop_id_t, 222 uint_t, const void *); 223 static int ath_m_getprop(void *, const char *, mac_prop_id_t, 224 uint_t, uint_t, void *, uint_t *); 225 226 static mac_callbacks_t ath_m_callbacks = { 227 MC_IOCTL | MC_SETPROP | MC_GETPROP, 228 ath_m_stat, 229 ath_m_start, 230 ath_m_stop, 231 ath_m_promisc, 232 ath_m_multicst, 233 ath_m_unicst, 234 ath_m_tx, 235 NULL, /* mc_resources; */ 236 ath_m_ioctl, 237 NULL, /* mc_getcapab */ 238 NULL, 239 NULL, 240 ath_m_setprop, 241 ath_m_getprop 242 }; 243 244 /* 245 * Available debug flags: 246 * ATH_DBG_INIT, ATH_DBG_GLD, ATH_DBG_HAL, ATH_DBG_INT, ATH_DBG_ATTACH, 247 * ATH_DBG_DETACH, ATH_DBG_AUX, ATH_DBG_WIFICFG, ATH_DBG_OSDEP 248 */ 249 uint32_t ath_dbg_flags = 0; 250 251 /* 252 * Exception/warning cases not leading to panic. 253 */ 254 void 255 ath_problem(const int8_t *fmt, ...) 256 { 257 va_list args; 258 259 mutex_enter(&ath_loglock); 260 261 va_start(args, fmt); 262 vcmn_err(CE_WARN, fmt, args); 263 va_end(args); 264 265 mutex_exit(&ath_loglock); 266 } 267 268 /* 269 * Normal log information independent of debug. 270 */ 271 void 272 ath_log(const int8_t *fmt, ...) 273 { 274 va_list args; 275 276 mutex_enter(&ath_loglock); 277 278 va_start(args, fmt); 279 vcmn_err(CE_CONT, fmt, args); 280 va_end(args); 281 282 mutex_exit(&ath_loglock); 283 } 284 285 void 286 ath_dbg(uint32_t dbg_flags, const int8_t *fmt, ...) 287 { 288 va_list args; 289 290 if (dbg_flags & ath_dbg_flags) { 291 mutex_enter(&ath_loglock); 292 va_start(args, fmt); 293 vcmn_err(CE_CONT, fmt, args); 294 va_end(args); 295 mutex_exit(&ath_loglock); 296 } 297 } 298 299 void 300 ath_setup_desc(ath_t *asc, struct ath_buf *bf) 301 { 302 struct ath_desc *ds; 303 304 ds = bf->bf_desc; 305 ds->ds_link = bf->bf_daddr; 306 ds->ds_data = bf->bf_dma.cookie.dmac_address; 307 ATH_HAL_SETUPRXDESC(asc->asc_ah, ds, 308 bf->bf_dma.alength, /* buffer size */ 309 0); 310 311 if (asc->asc_rxlink != NULL) 312 *asc->asc_rxlink = bf->bf_daddr; 313 asc->asc_rxlink = &ds->ds_link; 314 } 315 316 317 /* 318 * Allocate an area of memory and a DMA handle for accessing it 319 */ 320 static int 321 ath_alloc_dma_mem(dev_info_t *devinfo, ddi_dma_attr_t *dma_attr, size_t memsize, 322 ddi_device_acc_attr_t *attr_p, uint_t alloc_flags, 323 uint_t bind_flags, dma_area_t *dma_p) 324 { 325 int err; 326 327 /* 328 * Allocate handle 329 */ 330 err = ddi_dma_alloc_handle(devinfo, dma_attr, 331 DDI_DMA_SLEEP, NULL, &dma_p->dma_hdl); 332 if (err != DDI_SUCCESS) 333 return (DDI_FAILURE); 334 335 /* 336 * Allocate memory 337 */ 338 err = ddi_dma_mem_alloc(dma_p->dma_hdl, memsize, attr_p, 339 alloc_flags, DDI_DMA_SLEEP, NULL, &dma_p->mem_va, 340 &dma_p->alength, &dma_p->acc_hdl); 341 if (err != DDI_SUCCESS) 342 return (DDI_FAILURE); 343 344 /* 345 * Bind the two together 346 */ 347 err = ddi_dma_addr_bind_handle(dma_p->dma_hdl, NULL, 348 dma_p->mem_va, dma_p->alength, bind_flags, 349 DDI_DMA_SLEEP, NULL, &dma_p->cookie, &dma_p->ncookies); 350 if (err != DDI_DMA_MAPPED) 351 return (DDI_FAILURE); 352 353 dma_p->nslots = ~0U; 354 dma_p->size = ~0U; 355 dma_p->token = ~0U; 356 dma_p->offset = 0; 357 return (DDI_SUCCESS); 358 } 359 360 /* 361 * Free one allocated area of DMAable memory 362 */ 363 static void 364 ath_free_dma_mem(dma_area_t *dma_p) 365 { 366 if (dma_p->dma_hdl != NULL) { 367 (void) ddi_dma_unbind_handle(dma_p->dma_hdl); 368 if (dma_p->acc_hdl != NULL) { 369 ddi_dma_mem_free(&dma_p->acc_hdl); 370 dma_p->acc_hdl = NULL; 371 } 372 ddi_dma_free_handle(&dma_p->dma_hdl); 373 dma_p->ncookies = 0; 374 dma_p->dma_hdl = NULL; 375 } 376 } 377 378 379 /* 380 * Initialize tx/rx buffer list. Allocate DMA memory for 381 * each buffer. 382 */ 383 static int 384 ath_buflist_setup(dev_info_t *devinfo, ath_t *asc, list_t *bflist, 385 struct ath_buf **pbf, struct ath_desc **pds, int nbuf, uint_t dmabflags) 386 { 387 int i, err; 388 struct ath_buf *bf = *pbf; 389 struct ath_desc *ds = *pds; 390 391 list_create(bflist, sizeof (struct ath_buf), 392 offsetof(struct ath_buf, bf_node)); 393 for (i = 0; i < nbuf; i++, bf++, ds++) { 394 bf->bf_desc = ds; 395 bf->bf_daddr = asc->asc_desc_dma.cookie.dmac_address + 396 ((uintptr_t)ds - (uintptr_t)asc->asc_desc); 397 list_insert_tail(bflist, bf); 398 399 /* alloc DMA memory */ 400 err = ath_alloc_dma_mem(devinfo, &ath_dma_attr, 401 asc->asc_dmabuf_size, &ath_desc_accattr, DDI_DMA_STREAMING, 402 dmabflags, &bf->bf_dma); 403 if (err != DDI_SUCCESS) 404 return (err); 405 } 406 *pbf = bf; 407 *pds = ds; 408 409 return (DDI_SUCCESS); 410 } 411 412 /* 413 * Destroy tx/rx buffer list. Free DMA memory. 414 */ 415 static void 416 ath_buflist_cleanup(list_t *buflist) 417 { 418 struct ath_buf *bf; 419 420 if (!buflist) 421 return; 422 423 bf = list_head(buflist); 424 while (bf != NULL) { 425 if (bf->bf_m != NULL) { 426 freemsg(bf->bf_m); 427 bf->bf_m = NULL; 428 } 429 /* Free DMA buffer */ 430 ath_free_dma_mem(&bf->bf_dma); 431 if (bf->bf_in != NULL) { 432 ieee80211_free_node(bf->bf_in); 433 bf->bf_in = NULL; 434 } 435 list_remove(buflist, bf); 436 bf = list_head(buflist); 437 } 438 list_destroy(buflist); 439 } 440 441 442 static void 443 ath_desc_free(ath_t *asc) 444 { 445 ath_buflist_cleanup(&asc->asc_txbuf_list); 446 ath_buflist_cleanup(&asc->asc_rxbuf_list); 447 448 /* Free descriptor DMA buffer */ 449 ath_free_dma_mem(&asc->asc_desc_dma); 450 451 kmem_free((void *)asc->asc_vbufptr, asc->asc_vbuflen); 452 asc->asc_vbufptr = NULL; 453 } 454 455 static int 456 ath_desc_alloc(dev_info_t *devinfo, ath_t *asc) 457 { 458 int err; 459 size_t size; 460 struct ath_desc *ds; 461 struct ath_buf *bf; 462 463 size = sizeof (struct ath_desc) * (ATH_TXBUF + ATH_RXBUF); 464 465 err = ath_alloc_dma_mem(devinfo, &ath_desc_dma_attr, size, 466 &ath_desc_accattr, DDI_DMA_CONSISTENT, 467 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, &asc->asc_desc_dma); 468 469 /* virtual address of the first descriptor */ 470 asc->asc_desc = (struct ath_desc *)asc->asc_desc_dma.mem_va; 471 472 ds = asc->asc_desc; 473 ATH_DEBUG((ATH_DBG_INIT, "ath: ath_desc_alloc(): DMA map: " 474 "%p (%d) -> %p\n", 475 asc->asc_desc, asc->asc_desc_dma.alength, 476 asc->asc_desc_dma.cookie.dmac_address)); 477 478 /* allocate data structures to describe TX/RX DMA buffers */ 479 asc->asc_vbuflen = sizeof (struct ath_buf) * (ATH_TXBUF + ATH_RXBUF); 480 bf = (struct ath_buf *)kmem_zalloc(asc->asc_vbuflen, KM_SLEEP); 481 asc->asc_vbufptr = bf; 482 483 /* DMA buffer size for each TX/RX packet */ 484 asc->asc_dmabuf_size = roundup(1000 + sizeof (struct ieee80211_frame) + 485 IEEE80211_MTU + IEEE80211_CRC_LEN + 486 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + 487 IEEE80211_WEP_CRCLEN), asc->asc_cachelsz); 488 489 /* create RX buffer list */ 490 err = ath_buflist_setup(devinfo, asc, &asc->asc_rxbuf_list, &bf, &ds, 491 ATH_RXBUF, DDI_DMA_READ | DDI_DMA_STREAMING); 492 if (err != DDI_SUCCESS) { 493 ath_desc_free(asc); 494 return (err); 495 } 496 497 /* create TX buffer list */ 498 err = ath_buflist_setup(devinfo, asc, &asc->asc_txbuf_list, &bf, &ds, 499 ATH_TXBUF, DDI_DMA_STREAMING); 500 if (err != DDI_SUCCESS) { 501 ath_desc_free(asc); 502 return (err); 503 } 504 505 506 return (DDI_SUCCESS); 507 } 508 509 static void 510 ath_printrxbuf(struct ath_buf *bf, int32_t done) 511 { 512 struct ath_desc *ds = bf->bf_desc; 513 const struct ath_rx_status *rs = &bf->bf_status.ds_rxstat; 514 515 ATH_DEBUG((ATH_DBG_RECV, "ath: R (%p %p) %08x %08x %08x " 516 "%08x %08x %08x %c\n", 517 ds, bf->bf_daddr, 518 ds->ds_link, ds->ds_data, 519 ds->ds_ctl0, ds->ds_ctl1, 520 ds->ds_hw[0], ds->ds_hw[1], 521 !done ? ' ' : (rs->rs_status == 0) ? '*' : '!')); 522 } 523 524 static void 525 ath_rx_handler(ath_t *asc) 526 { 527 ieee80211com_t *ic = (ieee80211com_t *)asc; 528 struct ath_buf *bf; 529 struct ath_hal *ah = asc->asc_ah; 530 struct ath_desc *ds; 531 struct ath_rx_status *rs; 532 mblk_t *rx_mp; 533 struct ieee80211_frame *wh; 534 int32_t len, loop = 1; 535 uint8_t phyerr; 536 HAL_STATUS status; 537 HAL_NODE_STATS hal_node_stats; 538 struct ieee80211_node *in; 539 540 do { 541 mutex_enter(&asc->asc_rxbuflock); 542 bf = list_head(&asc->asc_rxbuf_list); 543 if (bf == NULL) { 544 ATH_DEBUG((ATH_DBG_RECV, "ath: ath_rx_handler(): " 545 "no buffer\n")); 546 mutex_exit(&asc->asc_rxbuflock); 547 break; 548 } 549 ASSERT(bf->bf_dma.cookie.dmac_address != NULL); 550 ds = bf->bf_desc; 551 if (ds->ds_link == bf->bf_daddr) { 552 /* 553 * Never process the self-linked entry at the end, 554 * this may be met at heavy load. 555 */ 556 mutex_exit(&asc->asc_rxbuflock); 557 break; 558 } 559 560 rs = &bf->bf_status.ds_rxstat; 561 status = ATH_HAL_RXPROCDESC(ah, ds, 562 bf->bf_daddr, 563 ATH_PA2DESC(asc, ds->ds_link), rs); 564 if (status == HAL_EINPROGRESS) { 565 mutex_exit(&asc->asc_rxbuflock); 566 break; 567 } 568 list_remove(&asc->asc_rxbuf_list, bf); 569 mutex_exit(&asc->asc_rxbuflock); 570 571 if (rs->rs_status != 0) { 572 if (rs->rs_status & HAL_RXERR_CRC) 573 asc->asc_stats.ast_rx_crcerr++; 574 if (rs->rs_status & HAL_RXERR_FIFO) 575 asc->asc_stats.ast_rx_fifoerr++; 576 if (rs->rs_status & HAL_RXERR_DECRYPT) 577 asc->asc_stats.ast_rx_badcrypt++; 578 if (rs->rs_status & HAL_RXERR_PHY) { 579 asc->asc_stats.ast_rx_phyerr++; 580 phyerr = rs->rs_phyerr & 0x1f; 581 asc->asc_stats.ast_rx_phy[phyerr]++; 582 } 583 goto rx_next; 584 } 585 len = rs->rs_datalen; 586 587 /* less than sizeof(struct ieee80211_frame) */ 588 if (len < 20) { 589 asc->asc_stats.ast_rx_tooshort++; 590 goto rx_next; 591 } 592 593 if ((rx_mp = allocb(asc->asc_dmabuf_size, BPRI_MED)) == NULL) { 594 ath_problem("ath: ath_rx_handler(): " 595 "allocing mblk buffer failed.\n"); 596 return; 597 } 598 599 ATH_DMA_SYNC(bf->bf_dma, DDI_DMA_SYNC_FORCPU); 600 bcopy(bf->bf_dma.mem_va, rx_mp->b_rptr, len); 601 602 rx_mp->b_wptr += len; 603 wh = (struct ieee80211_frame *)rx_mp->b_rptr; 604 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 605 IEEE80211_FC0_TYPE_CTL) { 606 /* 607 * Ignore control frame received in promisc mode. 608 */ 609 freemsg(rx_mp); 610 goto rx_next; 611 } 612 /* Remove the CRC at the end of IEEE80211 frame */ 613 rx_mp->b_wptr -= IEEE80211_CRC_LEN; 614 #ifdef DEBUG 615 ath_printrxbuf(bf, status == HAL_OK); 616 #endif /* DEBUG */ 617 /* 618 * Locate the node for sender, track state, and then 619 * pass the (referenced) node up to the 802.11 layer 620 * for its use. 621 */ 622 in = ieee80211_find_rxnode(ic, wh); 623 624 /* 625 * Send frame up for processing. 626 */ 627 (void) ieee80211_input(ic, rx_mp, in, 628 rs->rs_rssi, rs->rs_tstamp); 629 630 ieee80211_free_node(in); 631 632 rx_next: 633 mutex_enter(&asc->asc_rxbuflock); 634 list_insert_tail(&asc->asc_rxbuf_list, bf); 635 mutex_exit(&asc->asc_rxbuflock); 636 ath_setup_desc(asc, bf); 637 } while (loop); 638 639 /* rx signal state monitoring */ 640 ATH_HAL_RXMONITOR(ah, &hal_node_stats, &asc->asc_curchan); 641 } 642 643 static void 644 ath_printtxbuf(struct ath_buf *bf, int done) 645 { 646 struct ath_desc *ds = bf->bf_desc; 647 const struct ath_tx_status *ts = &bf->bf_status.ds_txstat; 648 649 ATH_DEBUG((ATH_DBG_SEND, "ath: T(%p %p) %08x %08x %08x %08x %08x" 650 " %08x %08x %08x %c\n", 651 ds, bf->bf_daddr, 652 ds->ds_link, ds->ds_data, 653 ds->ds_ctl0, ds->ds_ctl1, 654 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], 655 !done ? ' ' : (ts->ts_status == 0) ? '*' : '!')); 656 } 657 658 /* 659 * The input parameter mp has following assumption: 660 * For data packets, GLDv3 mac_wifi plugin allocates and fills the 661 * ieee80211 header. For management packets, net80211 allocates and 662 * fills the ieee80211 header. In both cases, enough spaces in the 663 * header are left for encryption option. 664 */ 665 static int32_t 666 ath_tx_start(ath_t *asc, struct ieee80211_node *in, struct ath_buf *bf, 667 mblk_t *mp) 668 { 669 ieee80211com_t *ic = (ieee80211com_t *)asc; 670 struct ieee80211_frame *wh; 671 struct ath_hal *ah = asc->asc_ah; 672 uint32_t subtype, flags, ctsduration; 673 int32_t keyix, iswep, hdrlen, pktlen, mblen, mbslen, try0; 674 uint8_t rix, cix, txrate, ctsrate; 675 struct ath_desc *ds; 676 struct ath_txq *txq; 677 HAL_PKT_TYPE atype; 678 const HAL_RATE_TABLE *rt; 679 HAL_BOOL shortPreamble; 680 struct ath_node *an; 681 caddr_t dest; 682 683 /* 684 * CRC are added by H/W, not encaped by driver, 685 * but we must count it in pkt length. 686 */ 687 pktlen = IEEE80211_CRC_LEN; 688 689 wh = (struct ieee80211_frame *)mp->b_rptr; 690 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 691 keyix = HAL_TXKEYIX_INVALID; 692 hdrlen = sizeof (struct ieee80211_frame); 693 if (iswep != 0) { 694 const struct ieee80211_cipher *cip; 695 struct ieee80211_key *k; 696 697 /* 698 * Construct the 802.11 header+trailer for an encrypted 699 * frame. The only reason this can fail is because of an 700 * unknown or unsupported cipher/key type. 701 */ 702 k = ieee80211_crypto_encap(ic, mp); 703 if (k == NULL) { 704 ATH_DEBUG((ATH_DBG_AUX, "crypto_encap failed\n")); 705 /* 706 * This can happen when the key is yanked after the 707 * frame was queued. Just discard the frame; the 708 * 802.11 layer counts failures and provides 709 * debugging/diagnostics. 710 */ 711 return (EIO); 712 } 713 cip = k->wk_cipher; 714 /* 715 * Adjust the packet + header lengths for the crypto 716 * additions and calculate the h/w key index. When 717 * a s/w mic is done the frame will have had any mic 718 * added to it prior to entry so m0->m_pkthdr.len above will 719 * account for it. Otherwise we need to add it to the 720 * packet length. 721 */ 722 hdrlen += cip->ic_header; 723 pktlen += cip->ic_trailer; 724 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0) 725 pktlen += cip->ic_miclen; 726 keyix = k->wk_keyix; 727 728 /* packet header may have moved, reset our local pointer */ 729 wh = (struct ieee80211_frame *)mp->b_rptr; 730 } 731 732 dest = bf->bf_dma.mem_va; 733 for (; mp != NULL; mp = mp->b_cont) { 734 mblen = MBLKL(mp); 735 bcopy(mp->b_rptr, dest, mblen); 736 dest += mblen; 737 } 738 mbslen = (uintptr_t)dest - (uintptr_t)bf->bf_dma.mem_va; 739 pktlen += mbslen; 740 741 bf->bf_in = in; 742 743 /* setup descriptors */ 744 ds = bf->bf_desc; 745 rt = asc->asc_currates; 746 ASSERT(rt != NULL); 747 748 /* 749 * The 802.11 layer marks whether or not we should 750 * use short preamble based on the current mode and 751 * negotiated parameters. 752 */ 753 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 754 (in->in_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) { 755 shortPreamble = AH_TRUE; 756 asc->asc_stats.ast_tx_shortpre++; 757 } else { 758 shortPreamble = AH_FALSE; 759 } 760 761 an = ATH_NODE(in); 762 763 /* 764 * Calculate Atheros packet type from IEEE80211 packet header 765 * and setup for rate calculations. 766 */ 767 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 768 case IEEE80211_FC0_TYPE_MGT: 769 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 770 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 771 atype = HAL_PKT_TYPE_BEACON; 772 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 773 atype = HAL_PKT_TYPE_PROBE_RESP; 774 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 775 atype = HAL_PKT_TYPE_ATIM; 776 else 777 atype = HAL_PKT_TYPE_NORMAL; 778 rix = 0; /* lowest rate */ 779 try0 = ATH_TXMAXTRY; 780 if (shortPreamble) 781 txrate = an->an_tx_mgtratesp; 782 else 783 txrate = an->an_tx_mgtrate; 784 /* force all ctl frames to highest queue */ 785 txq = asc->asc_ac2q[WME_AC_VO]; 786 break; 787 case IEEE80211_FC0_TYPE_CTL: 788 atype = HAL_PKT_TYPE_PSPOLL; 789 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 790 rix = 0; /* lowest rate */ 791 try0 = ATH_TXMAXTRY; 792 if (shortPreamble) 793 txrate = an->an_tx_mgtratesp; 794 else 795 txrate = an->an_tx_mgtrate; 796 /* force all ctl frames to highest queue */ 797 txq = asc->asc_ac2q[WME_AC_VO]; 798 break; 799 case IEEE80211_FC0_TYPE_DATA: 800 atype = HAL_PKT_TYPE_NORMAL; 801 rix = an->an_tx_rix0; 802 try0 = an->an_tx_try0; 803 if (shortPreamble) 804 txrate = an->an_tx_rate0sp; 805 else 806 txrate = an->an_tx_rate0; 807 /* Always use background queue */ 808 txq = asc->asc_ac2q[WME_AC_BK]; 809 break; 810 default: 811 /* Unknown 802.11 frame */ 812 asc->asc_stats.ast_tx_invalid++; 813 return (1); 814 } 815 /* 816 * Calculate miscellaneous flags. 817 */ 818 flags = HAL_TXDESC_CLRDMASK; 819 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 820 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 821 asc->asc_stats.ast_tx_noack++; 822 } else if (pktlen > ic->ic_rtsthreshold) { 823 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 824 asc->asc_stats.ast_tx_rts++; 825 } 826 827 /* 828 * Calculate duration. This logically belongs in the 802.11 829 * layer but it lacks sufficient information to calculate it. 830 */ 831 if ((flags & HAL_TXDESC_NOACK) == 0 && 832 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != 833 IEEE80211_FC0_TYPE_CTL) { 834 uint16_t dur; 835 dur = ath_hal_computetxtime(ah, rt, IEEE80211_ACK_SIZE, 836 rix, shortPreamble); 837 /* LINTED E_BAD_PTR_CAST_ALIGN */ 838 *(uint16_t *)wh->i_dur = LE_16(dur); 839 } 840 841 /* 842 * Calculate RTS/CTS rate and duration if needed. 843 */ 844 ctsduration = 0; 845 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { 846 /* 847 * CTS transmit rate is derived from the transmit rate 848 * by looking in the h/w rate table. We must also factor 849 * in whether or not a short preamble is to be used. 850 */ 851 cix = rt->info[rix].controlRate; 852 ctsrate = rt->info[cix].rateCode; 853 if (shortPreamble) 854 ctsrate |= rt->info[cix].shortPreamble; 855 /* 856 * Compute the transmit duration based on the size 857 * of an ACK frame. We call into the HAL to do the 858 * computation since it depends on the characteristics 859 * of the actual PHY being used. 860 */ 861 if (flags & HAL_TXDESC_RTSENA) { /* SIFS + CTS */ 862 ctsduration += ath_hal_computetxtime(ah, 863 rt, IEEE80211_ACK_SIZE, cix, shortPreamble); 864 } 865 /* SIFS + data */ 866 ctsduration += ath_hal_computetxtime(ah, 867 rt, pktlen, rix, shortPreamble); 868 if ((flags & HAL_TXDESC_NOACK) == 0) { /* SIFS + ACK */ 869 ctsduration += ath_hal_computetxtime(ah, 870 rt, IEEE80211_ACK_SIZE, cix, shortPreamble); 871 } 872 } else 873 ctsrate = 0; 874 875 if (++txq->axq_intrcnt >= ATH_TXINTR_PERIOD) { 876 flags |= HAL_TXDESC_INTREQ; 877 txq->axq_intrcnt = 0; 878 } 879 880 /* 881 * Formulate first tx descriptor with tx controls. 882 */ 883 ATH_HAL_SETUPTXDESC(ah, ds, 884 pktlen, /* packet length */ 885 hdrlen, /* header length */ 886 atype, /* Atheros packet type */ 887 MIN(in->in_txpower, 60), /* txpower */ 888 txrate, try0, /* series 0 rate/tries */ 889 keyix, /* key cache index */ 890 an->an_tx_antenna, /* antenna mode */ 891 flags, /* flags */ 892 ctsrate, /* rts/cts rate */ 893 ctsduration); /* rts/cts duration */ 894 bf->bf_flags = flags; 895 896 /* LINTED E_BAD_PTR_CAST_ALIGN */ 897 ATH_DEBUG((ATH_DBG_SEND, "ath: ath_xmit(): to %s totlen=%d " 898 "an->an_tx_rate1sp=%d tx_rate2sp=%d tx_rate3sp=%d " 899 "qnum=%d rix=%d sht=%d dur = %d\n", 900 ieee80211_macaddr_sprintf(wh->i_addr1), mbslen, an->an_tx_rate1sp, 901 an->an_tx_rate2sp, an->an_tx_rate3sp, 902 txq->axq_qnum, rix, shortPreamble, *(uint16_t *)wh->i_dur)); 903 904 /* 905 * Setup the multi-rate retry state only when we're 906 * going to use it. This assumes ath_hal_setuptxdesc 907 * initializes the descriptors (so we don't have to) 908 * when the hardware supports multi-rate retry and 909 * we don't use it. 910 */ 911 if (try0 != ATH_TXMAXTRY) 912 ATH_HAL_SETUPXTXDESC(ah, ds, 913 an->an_tx_rate1sp, 2, /* series 1 */ 914 an->an_tx_rate2sp, 2, /* series 2 */ 915 an->an_tx_rate3sp, 2); /* series 3 */ 916 917 ds->ds_link = 0; 918 ds->ds_data = bf->bf_dma.cookie.dmac_address; 919 ATH_HAL_FILLTXDESC(ah, ds, 920 mbslen, /* segment length */ 921 AH_TRUE, /* first segment */ 922 AH_TRUE, /* last segment */ 923 ds); /* first descriptor */ 924 925 ATH_DMA_SYNC(bf->bf_dma, DDI_DMA_SYNC_FORDEV); 926 927 mutex_enter(&txq->axq_lock); 928 list_insert_tail(&txq->axq_list, bf); 929 if (txq->axq_link == NULL) { 930 ATH_HAL_PUTTXBUF(ah, txq->axq_qnum, bf->bf_daddr); 931 } else { 932 *txq->axq_link = bf->bf_daddr; 933 } 934 txq->axq_link = &ds->ds_link; 935 mutex_exit(&txq->axq_lock); 936 937 ATH_HAL_TXSTART(ah, txq->axq_qnum); 938 939 ic->ic_stats.is_tx_frags++; 940 ic->ic_stats.is_tx_bytes += pktlen; 941 942 return (0); 943 } 944 945 /* 946 * Transmit a management frame. On failure we reclaim the skbuff. 947 * Note that management frames come directly from the 802.11 layer 948 * and do not honor the send queue flow control. Need to investigate 949 * using priority queueing so management frames can bypass data. 950 */ 951 static int 952 ath_xmit(ieee80211com_t *ic, mblk_t *mp, uint8_t type) 953 { 954 ath_t *asc = (ath_t *)ic; 955 struct ath_hal *ah = asc->asc_ah; 956 struct ieee80211_node *in = NULL; 957 struct ath_buf *bf = NULL; 958 struct ieee80211_frame *wh; 959 int error = 0; 960 961 ASSERT(mp->b_next == NULL); 962 963 if (!ATH_IS_RUNNING(asc)) { 964 if ((type & IEEE80211_FC0_TYPE_MASK) != 965 IEEE80211_FC0_TYPE_DATA) { 966 freemsg(mp); 967 } 968 return (ENXIO); 969 } 970 971 /* Grab a TX buffer */ 972 mutex_enter(&asc->asc_txbuflock); 973 bf = list_head(&asc->asc_txbuf_list); 974 if (bf != NULL) 975 list_remove(&asc->asc_txbuf_list, bf); 976 if (list_empty(&asc->asc_txbuf_list)) { 977 ATH_DEBUG((ATH_DBG_SEND, "ath: ath_mgmt_send(): " 978 "stop queue\n")); 979 asc->asc_stats.ast_tx_qstop++; 980 } 981 mutex_exit(&asc->asc_txbuflock); 982 if (bf == NULL) { 983 ATH_DEBUG((ATH_DBG_SEND, "ath: ath_mgmt_send(): discard, " 984 "no xmit buf\n")); 985 ic->ic_stats.is_tx_nobuf++; 986 if ((type & IEEE80211_FC0_TYPE_MASK) == 987 IEEE80211_FC0_TYPE_DATA) { 988 asc->asc_stats.ast_tx_nobuf++; 989 mutex_enter(&asc->asc_resched_lock); 990 asc->asc_resched_needed = B_TRUE; 991 mutex_exit(&asc->asc_resched_lock); 992 } else { 993 asc->asc_stats.ast_tx_nobufmgt++; 994 freemsg(mp); 995 } 996 return (ENOMEM); 997 } 998 999 wh = (struct ieee80211_frame *)mp->b_rptr; 1000 1001 /* Locate node */ 1002 in = ieee80211_find_txnode(ic, wh->i_addr1); 1003 if (in == NULL) { 1004 error = EIO; 1005 goto bad; 1006 } 1007 1008 in->in_inact = 0; 1009 switch (type & IEEE80211_FC0_TYPE_MASK) { 1010 case IEEE80211_FC0_TYPE_DATA: 1011 (void) ieee80211_encap(ic, mp, in); 1012 break; 1013 default: 1014 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1015 IEEE80211_FC0_SUBTYPE_PROBE_RESP) { 1016 /* fill time stamp */ 1017 uint64_t tsf; 1018 uint32_t *tstamp; 1019 1020 tsf = ATH_HAL_GETTSF64(ah); 1021 /* adjust 100us delay to xmit */ 1022 tsf += 100; 1023 /* LINTED E_BAD_PTR_CAST_ALIGN */ 1024 tstamp = (uint32_t *)&wh[1]; 1025 tstamp[0] = LE_32(tsf & 0xffffffff); 1026 tstamp[1] = LE_32(tsf >> 32); 1027 } 1028 asc->asc_stats.ast_tx_mgmt++; 1029 break; 1030 } 1031 1032 error = ath_tx_start(asc, in, bf, mp); 1033 if (error != 0) { 1034 bad: 1035 ic->ic_stats.is_tx_failed++; 1036 if (bf != NULL) { 1037 mutex_enter(&asc->asc_txbuflock); 1038 list_insert_tail(&asc->asc_txbuf_list, bf); 1039 mutex_exit(&asc->asc_txbuflock); 1040 } 1041 } 1042 if (in != NULL) 1043 ieee80211_free_node(in); 1044 if ((type & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_DATA || 1045 error == 0) { 1046 freemsg(mp); 1047 } 1048 1049 return (error); 1050 } 1051 1052 static mblk_t * 1053 ath_m_tx(void *arg, mblk_t *mp) 1054 { 1055 ath_t *asc = arg; 1056 ieee80211com_t *ic = (ieee80211com_t *)asc; 1057 mblk_t *next; 1058 int error = 0; 1059 1060 /* 1061 * No data frames go out unless we're associated; this 1062 * should not happen as the 802.11 layer does not enable 1063 * the xmit queue until we enter the RUN state. 1064 */ 1065 if (ic->ic_state != IEEE80211_S_RUN) { 1066 ATH_DEBUG((ATH_DBG_SEND, "ath: ath_m_tx(): " 1067 "discard, state %u\n", ic->ic_state)); 1068 asc->asc_stats.ast_tx_discard++; 1069 freemsgchain(mp); 1070 return (NULL); 1071 } 1072 1073 while (mp != NULL) { 1074 next = mp->b_next; 1075 mp->b_next = NULL; 1076 error = ath_xmit(ic, mp, IEEE80211_FC0_TYPE_DATA); 1077 if (error != 0) { 1078 mp->b_next = next; 1079 if (error == ENOMEM) { 1080 break; 1081 } else { 1082 freemsgchain(mp); /* CR6501759 issues */ 1083 return (NULL); 1084 } 1085 } 1086 mp = next; 1087 } 1088 1089 return (mp); 1090 } 1091 1092 static int 1093 ath_tx_processq(ath_t *asc, struct ath_txq *txq) 1094 { 1095 ieee80211com_t *ic = (ieee80211com_t *)asc; 1096 struct ath_hal *ah = asc->asc_ah; 1097 struct ath_buf *bf; 1098 struct ath_desc *ds; 1099 struct ieee80211_node *in; 1100 int32_t sr, lr, nacked = 0; 1101 struct ath_tx_status *ts; 1102 HAL_STATUS status; 1103 struct ath_node *an; 1104 1105 for (;;) { 1106 mutex_enter(&txq->axq_lock); 1107 bf = list_head(&txq->axq_list); 1108 if (bf == NULL) { 1109 txq->axq_link = NULL; 1110 mutex_exit(&txq->axq_lock); 1111 break; 1112 } 1113 ds = bf->bf_desc; /* last decriptor */ 1114 ts = &bf->bf_status.ds_txstat; 1115 status = ATH_HAL_TXPROCDESC(ah, ds, ts); 1116 #ifdef DEBUG 1117 ath_printtxbuf(bf, status == HAL_OK); 1118 #endif 1119 if (status == HAL_EINPROGRESS) { 1120 mutex_exit(&txq->axq_lock); 1121 break; 1122 } 1123 list_remove(&txq->axq_list, bf); 1124 mutex_exit(&txq->axq_lock); 1125 in = bf->bf_in; 1126 if (in != NULL) { 1127 an = ATH_NODE(in); 1128 /* Successful transmition */ 1129 if (ts->ts_status == 0) { 1130 an->an_tx_ok++; 1131 an->an_tx_antenna = ts->ts_antenna; 1132 if (ts->ts_rate & HAL_TXSTAT_ALTRATE) 1133 asc->asc_stats.ast_tx_altrate++; 1134 asc->asc_stats.ast_tx_rssidelta = 1135 ts->ts_rssi - asc->asc_stats.ast_tx_rssi; 1136 asc->asc_stats.ast_tx_rssi = ts->ts_rssi; 1137 } else { 1138 an->an_tx_err++; 1139 if (ts->ts_status & HAL_TXERR_XRETRY) 1140 asc->asc_stats.ast_tx_xretries++; 1141 if (ts->ts_status & HAL_TXERR_FIFO) 1142 asc->asc_stats.ast_tx_fifoerr++; 1143 if (ts->ts_status & HAL_TXERR_FILT) 1144 asc->asc_stats.ast_tx_filtered++; 1145 an->an_tx_antenna = 0; /* invalidate */ 1146 } 1147 sr = ts->ts_shortretry; 1148 lr = ts->ts_longretry; 1149 asc->asc_stats.ast_tx_shortretry += sr; 1150 asc->asc_stats.ast_tx_longretry += lr; 1151 /* 1152 * Hand the descriptor to the rate control algorithm. 1153 */ 1154 if ((ts->ts_status & HAL_TXERR_FILT) == 0 && 1155 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) { 1156 /* 1157 * If frame was ack'd update the last rx time 1158 * used to workaround phantom bmiss interrupts. 1159 */ 1160 if (ts->ts_status == 0) { 1161 nacked++; 1162 an->an_tx_ok++; 1163 } else { 1164 an->an_tx_err++; 1165 } 1166 an->an_tx_retr += sr + lr; 1167 } 1168 } 1169 bf->bf_in = NULL; 1170 mutex_enter(&asc->asc_txbuflock); 1171 list_insert_tail(&asc->asc_txbuf_list, bf); 1172 mutex_exit(&asc->asc_txbuflock); 1173 /* 1174 * Reschedule stalled outbound packets 1175 */ 1176 mutex_enter(&asc->asc_resched_lock); 1177 if (asc->asc_resched_needed) { 1178 asc->asc_resched_needed = B_FALSE; 1179 mac_tx_update(ic->ic_mach); 1180 } 1181 mutex_exit(&asc->asc_resched_lock); 1182 } 1183 return (nacked); 1184 } 1185 1186 1187 static void 1188 ath_tx_handler(ath_t *asc) 1189 { 1190 int i; 1191 1192 /* 1193 * Process each active queue. 1194 */ 1195 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 1196 if (ATH_TXQ_SETUP(asc, i)) { 1197 (void) ath_tx_processq(asc, &asc->asc_txq[i]); 1198 } 1199 } 1200 } 1201 1202 static struct ieee80211_node * 1203 ath_node_alloc(ieee80211com_t *ic) 1204 { 1205 struct ath_node *an; 1206 ath_t *asc = (ath_t *)ic; 1207 1208 an = kmem_zalloc(sizeof (struct ath_node), KM_SLEEP); 1209 ath_rate_update(asc, &an->an_node, 0); 1210 return (&an->an_node); 1211 } 1212 1213 static void 1214 ath_node_free(struct ieee80211_node *in) 1215 { 1216 ieee80211com_t *ic = in->in_ic; 1217 ath_t *asc = (ath_t *)ic; 1218 struct ath_buf *bf; 1219 struct ath_txq *txq; 1220 int32_t i; 1221 1222 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 1223 if (ATH_TXQ_SETUP(asc, i)) { 1224 txq = &asc->asc_txq[i]; 1225 mutex_enter(&txq->axq_lock); 1226 bf = list_head(&txq->axq_list); 1227 while (bf != NULL) { 1228 if (bf->bf_in == in) { 1229 bf->bf_in = NULL; 1230 } 1231 bf = list_next(&txq->axq_list, bf); 1232 } 1233 mutex_exit(&txq->axq_lock); 1234 } 1235 } 1236 ic->ic_node_cleanup(in); 1237 if (in->in_wpa_ie != NULL) 1238 ieee80211_free(in->in_wpa_ie); 1239 kmem_free(in, sizeof (struct ath_node)); 1240 } 1241 1242 static void 1243 ath_next_scan(void *arg) 1244 { 1245 ieee80211com_t *ic = arg; 1246 ath_t *asc = (ath_t *)ic; 1247 1248 asc->asc_scan_timer = 0; 1249 if (ic->ic_state == IEEE80211_S_SCAN) { 1250 asc->asc_scan_timer = timeout(ath_next_scan, (void *)asc, 1251 drv_usectohz(ath_dwelltime * 1000)); 1252 ieee80211_next_scan(ic); 1253 } 1254 } 1255 1256 static void 1257 ath_stop_scantimer(ath_t *asc) 1258 { 1259 timeout_id_t tmp_id = 0; 1260 1261 while ((asc->asc_scan_timer != 0) && (tmp_id != asc->asc_scan_timer)) { 1262 tmp_id = asc->asc_scan_timer; 1263 (void) untimeout(tmp_id); 1264 } 1265 asc->asc_scan_timer = 0; 1266 } 1267 1268 static int32_t 1269 ath_newstate(ieee80211com_t *ic, enum ieee80211_state nstate, int arg) 1270 { 1271 ath_t *asc = (ath_t *)ic; 1272 struct ath_hal *ah = asc->asc_ah; 1273 struct ieee80211_node *in; 1274 int32_t i, error; 1275 uint8_t *bssid; 1276 uint32_t rfilt; 1277 enum ieee80211_state ostate; 1278 1279 static const HAL_LED_STATE leds[] = { 1280 HAL_LED_INIT, /* IEEE80211_S_INIT */ 1281 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 1282 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 1283 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 1284 HAL_LED_RUN, /* IEEE80211_S_RUN */ 1285 }; 1286 if (!ATH_IS_RUNNING(asc)) 1287 return (0); 1288 1289 ostate = ic->ic_state; 1290 if (nstate != IEEE80211_S_SCAN) 1291 ath_stop_scantimer(asc); 1292 1293 ATH_LOCK(asc); 1294 ATH_HAL_SETLEDSTATE(ah, leds[nstate]); /* set LED */ 1295 1296 if (nstate == IEEE80211_S_INIT) { 1297 asc->asc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 1298 /* 1299 * Disable interrupts. 1300 */ 1301 ATH_HAL_INTRSET(ah, asc->asc_imask &~ HAL_INT_GLOBAL); 1302 ATH_UNLOCK(asc); 1303 goto done; 1304 } 1305 in = ic->ic_bss; 1306 error = ath_chan_set(asc, ic->ic_curchan); 1307 if (error != 0) { 1308 if (nstate != IEEE80211_S_SCAN) { 1309 ATH_UNLOCK(asc); 1310 ieee80211_reset_chan(ic); 1311 goto bad; 1312 } 1313 } 1314 1315 rfilt = ath_calcrxfilter(asc); 1316 1317 if (nstate == IEEE80211_S_SCAN) 1318 bssid = ic->ic_macaddr; 1319 else 1320 bssid = in->in_bssid; 1321 ATH_HAL_SETRXFILTER(ah, rfilt); 1322 1323 if (nstate == IEEE80211_S_RUN && ic->ic_opmode != IEEE80211_M_IBSS) 1324 ATH_HAL_SETASSOCID(ah, bssid, in->in_associd); 1325 else 1326 ATH_HAL_SETASSOCID(ah, bssid, 0); 1327 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 1328 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 1329 if (ATH_HAL_KEYISVALID(ah, i)) 1330 ATH_HAL_KEYSETMAC(ah, i, bssid); 1331 } 1332 } 1333 1334 if ((nstate == IEEE80211_S_RUN) && 1335 (ostate != IEEE80211_S_RUN)) { 1336 /* Configure the beacon and sleep timers. */ 1337 ath_beacon_config(asc); 1338 } else { 1339 asc->asc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 1340 ATH_HAL_INTRSET(ah, asc->asc_imask); 1341 } 1342 /* 1343 * Reset the rate control state. 1344 */ 1345 ath_rate_ctl_reset(asc, nstate); 1346 1347 ATH_UNLOCK(asc); 1348 done: 1349 /* 1350 * Invoke the parent method to complete the work. 1351 */ 1352 error = asc->asc_newstate(ic, nstate, arg); 1353 /* 1354 * Finally, start any timers. 1355 */ 1356 if (nstate == IEEE80211_S_RUN) { 1357 ieee80211_start_watchdog(ic, 1); 1358 } else if ((nstate == IEEE80211_S_SCAN) && (ostate != nstate)) { 1359 /* start ap/neighbor scan timer */ 1360 ASSERT(asc->asc_scan_timer == 0); 1361 asc->asc_scan_timer = timeout(ath_next_scan, (void *)asc, 1362 drv_usectohz(ath_dwelltime * 1000)); 1363 } 1364 bad: 1365 return (error); 1366 } 1367 1368 /* 1369 * Periodically recalibrate the PHY to account 1370 * for temperature/environment changes. 1371 */ 1372 static void 1373 ath_calibrate(ath_t *asc) 1374 { 1375 struct ath_hal *ah = asc->asc_ah; 1376 HAL_BOOL iqcaldone; 1377 1378 asc->asc_stats.ast_per_cal++; 1379 1380 if (ATH_HAL_GETRFGAIN(ah) == HAL_RFGAIN_NEED_CHANGE) { 1381 /* 1382 * Rfgain is out of bounds, reset the chip 1383 * to load new gain values. 1384 */ 1385 ATH_DEBUG((ATH_DBG_HAL, "ath: ath_calibrate(): " 1386 "Need change RFgain\n")); 1387 asc->asc_stats.ast_per_rfgain++; 1388 (void) ath_reset(&asc->asc_isc); 1389 } 1390 if (!ATH_HAL_CALIBRATE(ah, &asc->asc_curchan, &iqcaldone)) { 1391 ATH_DEBUG((ATH_DBG_HAL, "ath: ath_calibrate(): " 1392 "calibration of channel %u failed\n", 1393 asc->asc_curchan.channel)); 1394 asc->asc_stats.ast_per_calfail++; 1395 } 1396 } 1397 1398 static void 1399 ath_watchdog(void *arg) 1400 { 1401 ath_t *asc = arg; 1402 ieee80211com_t *ic = &asc->asc_isc; 1403 int ntimer = 0; 1404 1405 ATH_LOCK(asc); 1406 ic->ic_watchdog_timer = 0; 1407 if (!ATH_IS_RUNNING(asc)) { 1408 ATH_UNLOCK(asc); 1409 return; 1410 } 1411 1412 if (ic->ic_state == IEEE80211_S_RUN) { 1413 /* periodic recalibration */ 1414 ath_calibrate(asc); 1415 1416 /* 1417 * Start the background rate control thread if we 1418 * are not configured to use a fixed xmit rate. 1419 */ 1420 if (ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE) { 1421 asc->asc_stats.ast_rate_calls ++; 1422 if (ic->ic_opmode == IEEE80211_M_STA) 1423 ath_rate_ctl(ic, ic->ic_bss); 1424 else 1425 ieee80211_iterate_nodes(&ic->ic_sta, 1426 ath_rate_ctl, asc); 1427 } 1428 1429 ntimer = 1; 1430 } 1431 ATH_UNLOCK(asc); 1432 1433 ieee80211_watchdog(ic); 1434 if (ntimer != 0) 1435 ieee80211_start_watchdog(ic, ntimer); 1436 } 1437 1438 static void 1439 ath_tx_proc(void *arg) 1440 { 1441 ath_t *asc = arg; 1442 ath_tx_handler(asc); 1443 } 1444 1445 1446 static uint_t 1447 ath_intr(caddr_t arg) 1448 { 1449 /* LINTED E_BAD_PTR_CAST_ALIGN */ 1450 ath_t *asc = (ath_t *)arg; 1451 struct ath_hal *ah = asc->asc_ah; 1452 HAL_INT status; 1453 ieee80211com_t *ic = (ieee80211com_t *)asc; 1454 1455 ATH_LOCK(asc); 1456 1457 if (!ATH_IS_RUNNING(asc)) { 1458 /* 1459 * The hardware is not ready/present, don't touch anything. 1460 * Note this can happen early on if the IRQ is shared. 1461 */ 1462 ATH_UNLOCK(asc); 1463 return (DDI_INTR_UNCLAIMED); 1464 } 1465 1466 if (!ATH_HAL_INTRPEND(ah)) { /* shared irq, not for us */ 1467 ATH_UNLOCK(asc); 1468 return (DDI_INTR_UNCLAIMED); 1469 } 1470 1471 ATH_HAL_GETISR(ah, &status); 1472 status &= asc->asc_imask; 1473 if (status & HAL_INT_FATAL) { 1474 asc->asc_stats.ast_hardware++; 1475 goto reset; 1476 } else if (status & HAL_INT_RXORN) { 1477 asc->asc_stats.ast_rxorn++; 1478 goto reset; 1479 } else { 1480 if (status & HAL_INT_RXEOL) { 1481 asc->asc_stats.ast_rxeol++; 1482 asc->asc_rxlink = NULL; 1483 } 1484 if (status & HAL_INT_TXURN) { 1485 asc->asc_stats.ast_txurn++; 1486 ATH_HAL_UPDATETXTRIGLEVEL(ah, AH_TRUE); 1487 } 1488 1489 if (status & HAL_INT_RX) { 1490 asc->asc_rx_pend = 1; 1491 ddi_trigger_softintr(asc->asc_softint_id); 1492 } 1493 if (status & HAL_INT_TX) { 1494 if (ddi_taskq_dispatch(asc->asc_tq, ath_tx_proc, 1495 asc, DDI_NOSLEEP) != DDI_SUCCESS) { 1496 ath_problem("ath: ath_intr(): " 1497 "No memory available for tx taskq\n"); 1498 } 1499 } 1500 ATH_UNLOCK(asc); 1501 1502 if (status & HAL_INT_SWBA) { 1503 /* This will occur only in Host-AP or Ad-Hoc mode */ 1504 return (DDI_INTR_CLAIMED); 1505 } 1506 1507 if (status & HAL_INT_BMISS) { 1508 if (ic->ic_state == IEEE80211_S_RUN) { 1509 (void) ieee80211_new_state(ic, 1510 IEEE80211_S_ASSOC, -1); 1511 } 1512 } 1513 1514 } 1515 1516 return (DDI_INTR_CLAIMED); 1517 reset: 1518 (void) ath_reset(ic); 1519 ATH_UNLOCK(asc); 1520 return (DDI_INTR_CLAIMED); 1521 } 1522 1523 static uint_t 1524 ath_softint_handler(caddr_t data) 1525 { 1526 /* LINTED E_BAD_PTR_CAST_ALIGN */ 1527 ath_t *asc = (ath_t *)data; 1528 1529 /* 1530 * Check if the soft interrupt is triggered by another 1531 * driver at the same level. 1532 */ 1533 ATH_LOCK(asc); 1534 if (asc->asc_rx_pend) { /* Soft interrupt for this driver */ 1535 asc->asc_rx_pend = 0; 1536 ATH_UNLOCK(asc); 1537 ath_rx_handler(asc); 1538 return (DDI_INTR_CLAIMED); 1539 } 1540 ATH_UNLOCK(asc); 1541 return (DDI_INTR_UNCLAIMED); 1542 } 1543 1544 /* 1545 * following are gld callback routine 1546 * ath_gld_send, ath_gld_ioctl, ath_gld_gstat 1547 * are listed in other corresponding sections. 1548 * reset the hardware w/o losing operational state. this is 1549 * basically a more efficient way of doing ath_gld_stop, ath_gld_start, 1550 * followed by state transitions to the current 802.11 1551 * operational state. used to recover from errors rx overrun 1552 * and to reset the hardware when rf gain settings must be reset. 1553 */ 1554 1555 static void 1556 ath_stop_locked(ath_t *asc) 1557 { 1558 ieee80211com_t *ic = (ieee80211com_t *)asc; 1559 struct ath_hal *ah = asc->asc_ah; 1560 1561 ATH_LOCK_ASSERT(asc); 1562 if (!asc->asc_isrunning) 1563 return; 1564 1565 /* 1566 * Shutdown the hardware and driver: 1567 * reset 802.11 state machine 1568 * turn off timers 1569 * disable interrupts 1570 * turn off the radio 1571 * clear transmit machinery 1572 * clear receive machinery 1573 * drain and release tx queues 1574 * reclaim beacon resources 1575 * power down hardware 1576 * 1577 * Note that some of this work is not possible if the 1578 * hardware is gone (invalid). 1579 */ 1580 ATH_UNLOCK(asc); 1581 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1582 ieee80211_stop_watchdog(ic); 1583 ATH_LOCK(asc); 1584 ATH_HAL_INTRSET(ah, 0); 1585 ath_draintxq(asc); 1586 if (!asc->asc_invalid) { 1587 ath_stoprecv(asc); 1588 ATH_HAL_PHYDISABLE(ah); 1589 } else { 1590 asc->asc_rxlink = NULL; 1591 } 1592 asc->asc_isrunning = 0; 1593 } 1594 1595 static void 1596 ath_m_stop(void *arg) 1597 { 1598 ath_t *asc = arg; 1599 struct ath_hal *ah = asc->asc_ah; 1600 1601 ATH_LOCK(asc); 1602 ath_stop_locked(asc); 1603 ATH_HAL_SETPOWER(ah, HAL_PM_AWAKE); 1604 asc->asc_invalid = 1; 1605 ATH_UNLOCK(asc); 1606 } 1607 1608 static int 1609 ath_start_locked(ath_t *asc) 1610 { 1611 ieee80211com_t *ic = (ieee80211com_t *)asc; 1612 struct ath_hal *ah = asc->asc_ah; 1613 HAL_STATUS status; 1614 1615 ATH_LOCK_ASSERT(asc); 1616 1617 /* 1618 * The basic interface to setting the hardware in a good 1619 * state is ``reset''. On return the hardware is known to 1620 * be powered up and with interrupts disabled. This must 1621 * be followed by initialization of the appropriate bits 1622 * and then setup of the interrupt mask. 1623 */ 1624 asc->asc_curchan.channel = ic->ic_curchan->ich_freq; 1625 asc->asc_curchan.channelFlags = ath_chan2flags(ic, ic->ic_curchan); 1626 if (!ATH_HAL_RESET(ah, (HAL_OPMODE)ic->ic_opmode, 1627 &asc->asc_curchan, AH_FALSE, &status)) { 1628 ATH_DEBUG((ATH_DBG_HAL, "ath: ath_m_start(): " 1629 "reset hardware failed: '%s' (HAL status %u)\n", 1630 ath_get_hal_status_desc(status), status)); 1631 return (ENOTACTIVE); 1632 } 1633 1634 (void) ath_startrecv(asc); 1635 1636 /* 1637 * Enable interrupts. 1638 */ 1639 asc->asc_imask = HAL_INT_RX | HAL_INT_TX 1640 | HAL_INT_RXEOL | HAL_INT_RXORN 1641 | HAL_INT_FATAL | HAL_INT_GLOBAL; 1642 ATH_HAL_INTRSET(ah, asc->asc_imask); 1643 1644 /* 1645 * The hardware should be ready to go now so it's safe 1646 * to kick the 802.11 state machine as it's likely to 1647 * immediately call back to us to send mgmt frames. 1648 */ 1649 ath_chan_change(asc, ic->ic_curchan); 1650 1651 asc->asc_isrunning = 1; 1652 1653 return (0); 1654 } 1655 1656 int 1657 ath_m_start(void *arg) 1658 { 1659 ath_t *asc = arg; 1660 int err; 1661 1662 ATH_LOCK(asc); 1663 /* 1664 * Stop anything previously setup. This is safe 1665 * whether this is the first time through or not. 1666 */ 1667 ath_stop_locked(asc); 1668 1669 if ((err = ath_start_locked(asc)) != 0) { 1670 ATH_UNLOCK(asc); 1671 return (err); 1672 } 1673 1674 asc->asc_invalid = 0; 1675 ATH_UNLOCK(asc); 1676 1677 return (0); 1678 } 1679 1680 1681 static int 1682 ath_m_unicst(void *arg, const uint8_t *macaddr) 1683 { 1684 ath_t *asc = arg; 1685 struct ath_hal *ah = asc->asc_ah; 1686 1687 ATH_DEBUG((ATH_DBG_GLD, "ath: ath_gld_saddr(): " 1688 "%.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", 1689 macaddr[0], macaddr[1], macaddr[2], 1690 macaddr[3], macaddr[4], macaddr[5])); 1691 1692 ATH_LOCK(asc); 1693 IEEE80211_ADDR_COPY(asc->asc_isc.ic_macaddr, macaddr); 1694 ATH_HAL_SETMAC(ah, asc->asc_isc.ic_macaddr); 1695 1696 (void) ath_reset(&asc->asc_isc); 1697 ATH_UNLOCK(asc); 1698 return (0); 1699 } 1700 1701 static int 1702 ath_m_promisc(void *arg, boolean_t on) 1703 { 1704 ath_t *asc = arg; 1705 struct ath_hal *ah = asc->asc_ah; 1706 uint32_t rfilt; 1707 1708 ATH_LOCK(asc); 1709 rfilt = ATH_HAL_GETRXFILTER(ah); 1710 if (on) 1711 rfilt |= HAL_RX_FILTER_PROM; 1712 else 1713 rfilt &= ~HAL_RX_FILTER_PROM; 1714 asc->asc_promisc = on; 1715 ATH_HAL_SETRXFILTER(ah, rfilt); 1716 ATH_UNLOCK(asc); 1717 1718 return (0); 1719 } 1720 1721 static int 1722 ath_m_multicst(void *arg, boolean_t add, const uint8_t *mca) 1723 { 1724 ath_t *asc = arg; 1725 struct ath_hal *ah = asc->asc_ah; 1726 uint32_t val, index, bit; 1727 uint8_t pos; 1728 uint32_t *mfilt = asc->asc_mcast_hash; 1729 1730 ATH_LOCK(asc); 1731 1732 /* calculate XOR of eight 6bit values */ 1733 val = ATH_LE_READ_4(mca + 0); 1734 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1735 val = ATH_LE_READ_4(mca + 3); 1736 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1737 pos &= 0x3f; 1738 index = pos / 32; 1739 bit = 1 << (pos % 32); 1740 1741 if (add) { /* enable multicast */ 1742 asc->asc_mcast_refs[pos]++; 1743 mfilt[index] |= bit; 1744 } else { /* disable multicast */ 1745 if (--asc->asc_mcast_refs[pos] == 0) 1746 mfilt[index] &= ~bit; 1747 } 1748 ATH_HAL_SETMCASTFILTER(ah, mfilt[0], mfilt[1]); 1749 1750 ATH_UNLOCK(asc); 1751 return (0); 1752 } 1753 /* 1754 * callback functions for /get/set properties 1755 */ 1756 static int 1757 ath_m_setprop(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num, 1758 uint_t wldp_length, const void *wldp_buf) 1759 { 1760 ath_t *asc = arg; 1761 int err; 1762 1763 err = ieee80211_setprop(&asc->asc_isc, pr_name, wldp_pr_num, 1764 wldp_length, wldp_buf); 1765 1766 ATH_LOCK(asc); 1767 1768 if (err == ENETRESET) { 1769 if (ATH_IS_RUNNING(asc)) { 1770 ATH_UNLOCK(asc); 1771 (void) ath_m_start(asc); 1772 (void) ieee80211_new_state(&asc->asc_isc, 1773 IEEE80211_S_SCAN, -1); 1774 ATH_LOCK(asc); 1775 } 1776 err = 0; 1777 } 1778 1779 ATH_UNLOCK(asc); 1780 1781 return (err); 1782 } 1783 /* ARGSUSED */ 1784 static int 1785 ath_m_getprop(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num, 1786 uint_t pr_flags, uint_t wldp_length, void *wldp_buf, uint_t *perm) 1787 { 1788 ath_t *asc = arg; 1789 int err = 0; 1790 1791 err = ieee80211_getprop(&asc->asc_isc, pr_name, wldp_pr_num, 1792 pr_flags, wldp_length, wldp_buf, perm); 1793 1794 return (err); 1795 } 1796 1797 static void 1798 ath_m_ioctl(void *arg, queue_t *wq, mblk_t *mp) 1799 { 1800 ath_t *asc = arg; 1801 int32_t err; 1802 1803 err = ieee80211_ioctl(&asc->asc_isc, wq, mp); 1804 ATH_LOCK(asc); 1805 if (err == ENETRESET) { 1806 if (ATH_IS_RUNNING(asc)) { 1807 ATH_UNLOCK(asc); 1808 (void) ath_m_start(asc); 1809 (void) ieee80211_new_state(&asc->asc_isc, 1810 IEEE80211_S_SCAN, -1); 1811 ATH_LOCK(asc); 1812 } 1813 } 1814 ATH_UNLOCK(asc); 1815 } 1816 1817 static int 1818 ath_m_stat(void *arg, uint_t stat, uint64_t *val) 1819 { 1820 ath_t *asc = arg; 1821 ieee80211com_t *ic = (ieee80211com_t *)asc; 1822 struct ieee80211_node *in = ic->ic_bss; 1823 struct ieee80211_rateset *rs = &in->in_rates; 1824 1825 ATH_LOCK(asc); 1826 switch (stat) { 1827 case MAC_STAT_IFSPEED: 1828 *val = (rs->ir_rates[in->in_txrate] & IEEE80211_RATE_VAL) / 2 * 1829 1000000ull; 1830 break; 1831 case MAC_STAT_NOXMTBUF: 1832 *val = asc->asc_stats.ast_tx_nobuf + 1833 asc->asc_stats.ast_tx_nobufmgt; 1834 break; 1835 case MAC_STAT_IERRORS: 1836 *val = asc->asc_stats.ast_rx_tooshort; 1837 break; 1838 case MAC_STAT_RBYTES: 1839 *val = ic->ic_stats.is_rx_bytes; 1840 break; 1841 case MAC_STAT_IPACKETS: 1842 *val = ic->ic_stats.is_rx_frags; 1843 break; 1844 case MAC_STAT_OBYTES: 1845 *val = ic->ic_stats.is_tx_bytes; 1846 break; 1847 case MAC_STAT_OPACKETS: 1848 *val = ic->ic_stats.is_tx_frags; 1849 break; 1850 case MAC_STAT_OERRORS: 1851 case WIFI_STAT_TX_FAILED: 1852 *val = asc->asc_stats.ast_tx_fifoerr + 1853 asc->asc_stats.ast_tx_xretries + 1854 asc->asc_stats.ast_tx_discard; 1855 break; 1856 case WIFI_STAT_TX_RETRANS: 1857 *val = asc->asc_stats.ast_tx_xretries; 1858 break; 1859 case WIFI_STAT_FCS_ERRORS: 1860 *val = asc->asc_stats.ast_rx_crcerr; 1861 break; 1862 case WIFI_STAT_WEP_ERRORS: 1863 *val = asc->asc_stats.ast_rx_badcrypt; 1864 break; 1865 case WIFI_STAT_TX_FRAGS: 1866 case WIFI_STAT_MCAST_TX: 1867 case WIFI_STAT_RTS_SUCCESS: 1868 case WIFI_STAT_RTS_FAILURE: 1869 case WIFI_STAT_ACK_FAILURE: 1870 case WIFI_STAT_RX_FRAGS: 1871 case WIFI_STAT_MCAST_RX: 1872 case WIFI_STAT_RX_DUPS: 1873 ATH_UNLOCK(asc); 1874 return (ieee80211_stat(ic, stat, val)); 1875 default: 1876 ATH_UNLOCK(asc); 1877 return (ENOTSUP); 1878 } 1879 ATH_UNLOCK(asc); 1880 1881 return (0); 1882 } 1883 1884 static int 1885 ath_pci_setup(ath_t *asc) 1886 { 1887 uint16_t command; 1888 1889 /* 1890 * Enable memory mapping and bus mastering 1891 */ 1892 ASSERT(asc != NULL); 1893 command = pci_config_get16(asc->asc_cfg_handle, PCI_CONF_COMM); 1894 command |= PCI_COMM_MAE | PCI_COMM_ME; 1895 pci_config_put16(asc->asc_cfg_handle, PCI_CONF_COMM, command); 1896 command = pci_config_get16(asc->asc_cfg_handle, PCI_CONF_COMM); 1897 if ((command & PCI_COMM_MAE) == 0) { 1898 ath_problem("ath: ath_pci_setup(): " 1899 "failed to enable memory mapping\n"); 1900 return (EIO); 1901 } 1902 if ((command & PCI_COMM_ME) == 0) { 1903 ath_problem("ath: ath_pci_setup(): " 1904 "failed to enable bus mastering\n"); 1905 return (EIO); 1906 } 1907 ATH_DEBUG((ATH_DBG_INIT, "ath: ath_pci_setup(): " 1908 "set command reg to 0x%x \n", command)); 1909 1910 return (0); 1911 } 1912 1913 static int 1914 ath_resume(dev_info_t *devinfo) 1915 { 1916 ath_t *asc; 1917 int ret = DDI_SUCCESS; 1918 1919 asc = ddi_get_soft_state(ath_soft_state_p, ddi_get_instance(devinfo)); 1920 if (asc == NULL) { 1921 ATH_DEBUG((ATH_DBG_SUSPEND, "ath: ath_resume(): " 1922 "failed to get soft state\n")); 1923 return (DDI_FAILURE); 1924 } 1925 1926 ATH_LOCK(asc); 1927 /* 1928 * Set up config space command register(s). Refuse 1929 * to resume on failure. 1930 */ 1931 if (ath_pci_setup(asc) != 0) { 1932 ATH_DEBUG((ATH_DBG_SUSPEND, "ath: ath_resume(): " 1933 "ath_pci_setup() failed\n")); 1934 ATH_UNLOCK(asc); 1935 return (DDI_FAILURE); 1936 } 1937 1938 if (!asc->asc_invalid) 1939 ret = ath_start_locked(asc); 1940 ATH_UNLOCK(asc); 1941 1942 return (ret); 1943 } 1944 1945 static int 1946 ath_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 1947 { 1948 ath_t *asc; 1949 ieee80211com_t *ic; 1950 struct ath_hal *ah; 1951 uint8_t csz; 1952 HAL_STATUS status; 1953 caddr_t regs; 1954 uint32_t i, val; 1955 uint16_t vendor_id, device_id; 1956 const char *athname; 1957 int32_t ath_countrycode = CTRY_DEFAULT; /* country code */ 1958 int32_t err, ath_regdomain = 0; /* regulatory domain */ 1959 char strbuf[32]; 1960 int instance; 1961 wifi_data_t wd = { 0 }; 1962 mac_register_t *macp; 1963 1964 switch (cmd) { 1965 case DDI_ATTACH: 1966 break; 1967 1968 case DDI_RESUME: 1969 return (ath_resume(devinfo)); 1970 1971 default: 1972 return (DDI_FAILURE); 1973 } 1974 1975 instance = ddi_get_instance(devinfo); 1976 if (ddi_soft_state_zalloc(ath_soft_state_p, instance) != DDI_SUCCESS) { 1977 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 1978 "Unable to alloc softstate\n")); 1979 return (DDI_FAILURE); 1980 } 1981 1982 asc = ddi_get_soft_state(ath_soft_state_p, ddi_get_instance(devinfo)); 1983 ic = (ieee80211com_t *)asc; 1984 asc->asc_dev = devinfo; 1985 1986 mutex_init(&asc->asc_genlock, NULL, MUTEX_DRIVER, NULL); 1987 mutex_init(&asc->asc_txbuflock, NULL, MUTEX_DRIVER, NULL); 1988 mutex_init(&asc->asc_rxbuflock, NULL, MUTEX_DRIVER, NULL); 1989 mutex_init(&asc->asc_resched_lock, NULL, MUTEX_DRIVER, NULL); 1990 1991 err = pci_config_setup(devinfo, &asc->asc_cfg_handle); 1992 if (err != DDI_SUCCESS) { 1993 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 1994 "pci_config_setup() failed")); 1995 goto attach_fail0; 1996 } 1997 1998 if (ath_pci_setup(asc) != 0) 1999 goto attach_fail1; 2000 2001 /* 2002 * Cache line size is used to size and align various 2003 * structures used to communicate with the hardware. 2004 */ 2005 csz = pci_config_get8(asc->asc_cfg_handle, PCI_CONF_CACHE_LINESZ); 2006 if (csz == 0) { 2007 /* 2008 * We must have this setup properly for rx buffer 2009 * DMA to work so force a reasonable value here if it 2010 * comes up zero. 2011 */ 2012 csz = ATH_DEF_CACHE_BYTES / sizeof (uint32_t); 2013 pci_config_put8(asc->asc_cfg_handle, PCI_CONF_CACHE_LINESZ, 2014 csz); 2015 } 2016 asc->asc_cachelsz = csz << 2; 2017 vendor_id = pci_config_get16(asc->asc_cfg_handle, PCI_CONF_VENID); 2018 device_id = pci_config_get16(asc->asc_cfg_handle, PCI_CONF_DEVID); 2019 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): vendor 0x%x, " 2020 "device id 0x%x, cache size %d\n", vendor_id, device_id, csz)); 2021 2022 athname = ath_hal_probe(vendor_id, device_id); 2023 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): athname: %s\n", 2024 athname ? athname : "Atheros ???")); 2025 2026 pci_config_put8(asc->asc_cfg_handle, PCI_CONF_LATENCY_TIMER, 0xa8); 2027 val = pci_config_get32(asc->asc_cfg_handle, 0x40); 2028 if ((val & 0x0000ff00) != 0) 2029 pci_config_put32(asc->asc_cfg_handle, 0x40, val & 0xffff00ff); 2030 2031 err = ddi_regs_map_setup(devinfo, 1, 2032 ®s, 0, 0, &ath_reg_accattr, &asc->asc_io_handle); 2033 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 2034 "regs map1 = %x err=%d\n", regs, err)); 2035 if (err != DDI_SUCCESS) { 2036 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 2037 "ddi_regs_map_setup() failed")); 2038 goto attach_fail1; 2039 } 2040 2041 ah = ath_hal_attach(device_id, asc, 0, regs, &status); 2042 if (ah == NULL) { 2043 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 2044 "unable to attach hw: '%s' (HAL status %u)\n", 2045 ath_get_hal_status_desc(status), status)); 2046 goto attach_fail2; 2047 } 2048 ATH_DEBUG((ATH_DBG_ATTACH, "mac %d.%d phy %d.%d", 2049 ah->ah_macVersion, ah->ah_macRev, 2050 ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf)); 2051 ATH_HAL_INTRSET(ah, 0); 2052 asc->asc_ah = ah; 2053 2054 if (ah->ah_abi != HAL_ABI_VERSION) { 2055 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 2056 "HAL ABI mismatch detected (0x%x != 0x%x)\n", 2057 ah->ah_abi, HAL_ABI_VERSION)); 2058 goto attach_fail3; 2059 } 2060 2061 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 2062 "HAL ABI version 0x%x\n", ah->ah_abi)); 2063 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 2064 "HAL mac version %d.%d, phy version %d.%d\n", 2065 ah->ah_macVersion, ah->ah_macRev, 2066 ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf)); 2067 if (ah->ah_analog5GhzRev) 2068 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 2069 "HAL 5ghz radio version %d.%d\n", 2070 ah->ah_analog5GhzRev >> 4, 2071 ah->ah_analog5GhzRev & 0xf)); 2072 if (ah->ah_analog2GhzRev) 2073 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 2074 "HAL 2ghz radio version %d.%d\n", 2075 ah->ah_analog2GhzRev >> 4, 2076 ah->ah_analog2GhzRev & 0xf)); 2077 2078 /* 2079 * Check if the MAC has multi-rate retry support. 2080 * We do this by trying to setup a fake extended 2081 * descriptor. MAC's that don't have support will 2082 * return false w/o doing anything. MAC's that do 2083 * support it will return true w/o doing anything. 2084 */ 2085 asc->asc_mrretry = ATH_HAL_SETUPXTXDESC(ah, NULL, 0, 0, 0, 0, 0, 0); 2086 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 2087 "multi rate retry support=%x\n", 2088 asc->asc_mrretry)); 2089 2090 /* 2091 * Get the hardware key cache size. 2092 */ 2093 asc->asc_keymax = ATH_HAL_KEYCACHESIZE(ah); 2094 if (asc->asc_keymax > sizeof (asc->asc_keymap) * NBBY) { 2095 ATH_DEBUG((ATH_DBG_ATTACH, "ath_attach:" 2096 " Warning, using only %u entries in %u key cache\n", 2097 sizeof (asc->asc_keymap) * NBBY, asc->asc_keymax)); 2098 asc->asc_keymax = sizeof (asc->asc_keymap) * NBBY; 2099 } 2100 /* 2101 * Reset the key cache since some parts do not 2102 * reset the contents on initial power up. 2103 */ 2104 for (i = 0; i < asc->asc_keymax; i++) 2105 ATH_HAL_KEYRESET(ah, i); 2106 2107 ATH_HAL_GETREGDOMAIN(ah, (uint32_t *)&ath_regdomain); 2108 ATH_HAL_GETCOUNTRYCODE(ah, &ath_countrycode); 2109 /* 2110 * Collect the channel list using the default country 2111 * code and including outdoor channels. The 802.11 layer 2112 * is resposible for filtering this list to a set of 2113 * channels that it considers ok to use. 2114 */ 2115 asc->asc_have11g = 0; 2116 2117 /* enable outdoor use, enable extended channels */ 2118 err = ath_getchannels(asc, ath_countrycode, AH_FALSE, AH_TRUE); 2119 if (err != 0) 2120 goto attach_fail3; 2121 2122 /* 2123 * Setup rate tables for all potential media types. 2124 */ 2125 ath_rate_setup(asc, IEEE80211_MODE_11A); 2126 ath_rate_setup(asc, IEEE80211_MODE_11B); 2127 ath_rate_setup(asc, IEEE80211_MODE_11G); 2128 ath_rate_setup(asc, IEEE80211_MODE_TURBO_A); 2129 2130 /* Setup here so ath_rate_update is happy */ 2131 ath_setcurmode(asc, IEEE80211_MODE_11A); 2132 2133 err = ath_desc_alloc(devinfo, asc); 2134 if (err != DDI_SUCCESS) { 2135 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 2136 "failed to allocate descriptors: %d\n", err)); 2137 goto attach_fail3; 2138 } 2139 2140 if ((asc->asc_tq = ddi_taskq_create(devinfo, "ath_taskq", 1, 2141 TASKQ_DEFAULTPRI, 0)) == NULL) { 2142 goto attach_fail4; 2143 } 2144 /* Setup transmit queues in the HAL */ 2145 if (ath_txq_setup(asc)) 2146 goto attach_fail4; 2147 2148 ATH_HAL_GETMAC(ah, ic->ic_macaddr); 2149 2150 /* 2151 * Initialize pointers to device specific functions which 2152 * will be used by the generic layer. 2153 */ 2154 /* 11g support is identified when we fetch the channel set */ 2155 if (asc->asc_have11g) 2156 ic->ic_caps |= IEEE80211_C_SHPREAMBLE | 2157 IEEE80211_C_SHSLOT; /* short slot time */ 2158 /* 2159 * Query the hal to figure out h/w crypto support. 2160 */ 2161 if (ATH_HAL_CIPHERSUPPORTED(ah, HAL_CIPHER_WEP)) 2162 ic->ic_caps |= IEEE80211_C_WEP; 2163 if (ATH_HAL_CIPHERSUPPORTED(ah, HAL_CIPHER_AES_OCB)) 2164 ic->ic_caps |= IEEE80211_C_AES; 2165 if (ATH_HAL_CIPHERSUPPORTED(ah, HAL_CIPHER_AES_CCM)) { 2166 ATH_DEBUG((ATH_DBG_ATTACH, "Atheros support H/W CCMP\n")); 2167 ic->ic_caps |= IEEE80211_C_AES_CCM; 2168 } 2169 if (ATH_HAL_CIPHERSUPPORTED(ah, HAL_CIPHER_CKIP)) 2170 ic->ic_caps |= IEEE80211_C_CKIP; 2171 if (ATH_HAL_CIPHERSUPPORTED(ah, HAL_CIPHER_TKIP)) { 2172 ATH_DEBUG((ATH_DBG_ATTACH, "Atheros support H/W TKIP\n")); 2173 ic->ic_caps |= IEEE80211_C_TKIP; 2174 /* 2175 * Check if h/w does the MIC and/or whether the 2176 * separate key cache entries are required to 2177 * handle both tx+rx MIC keys. 2178 */ 2179 if (ATH_HAL_CIPHERSUPPORTED(ah, HAL_CIPHER_MIC)) { 2180 ATH_DEBUG((ATH_DBG_ATTACH, "Support H/W TKIP MIC\n")); 2181 ic->ic_caps |= IEEE80211_C_TKIPMIC; 2182 } 2183 2184 /* 2185 * If the h/w supports storing tx+rx MIC keys 2186 * in one cache slot automatically enable use. 2187 */ 2188 if (ATH_HAL_HASTKIPSPLIT(ah) || 2189 !ATH_HAL_SETTKIPSPLIT(ah, AH_FALSE)) { 2190 asc->asc_splitmic = 1; 2191 } 2192 } 2193 ic->ic_caps |= IEEE80211_C_WPA; /* Support WPA/WPA2 */ 2194 2195 asc->asc_hasclrkey = ATH_HAL_CIPHERSUPPORTED(ah, HAL_CIPHER_CLR); 2196 /* 2197 * Mark key cache slots associated with global keys 2198 * as in use. If we knew TKIP was not to be used we 2199 * could leave the +32, +64, and +32+64 slots free. 2200 */ 2201 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2202 setbit(asc->asc_keymap, i); 2203 setbit(asc->asc_keymap, i+64); 2204 if (asc->asc_splitmic) { 2205 setbit(asc->asc_keymap, i+32); 2206 setbit(asc->asc_keymap, i+32+64); 2207 } 2208 } 2209 2210 ic->ic_phytype = IEEE80211_T_OFDM; 2211 ic->ic_opmode = IEEE80211_M_STA; 2212 ic->ic_state = IEEE80211_S_INIT; 2213 ic->ic_maxrssi = ATH_MAX_RSSI; 2214 ic->ic_set_shortslot = ath_set_shortslot; 2215 ic->ic_xmit = ath_xmit; 2216 ieee80211_attach(ic); 2217 2218 /* different instance has different WPA door */ 2219 (void) snprintf(ic->ic_wpadoor, MAX_IEEE80211STR, "%s_%s%d", WPA_DOOR, 2220 ddi_driver_name(devinfo), 2221 ddi_get_instance(devinfo)); 2222 2223 /* Override 80211 default routines */ 2224 ic->ic_reset = ath_reset; 2225 asc->asc_newstate = ic->ic_newstate; 2226 ic->ic_newstate = ath_newstate; 2227 ic->ic_watchdog = ath_watchdog; 2228 ic->ic_node_alloc = ath_node_alloc; 2229 ic->ic_node_free = ath_node_free; 2230 ic->ic_crypto.cs_key_alloc = ath_key_alloc; 2231 ic->ic_crypto.cs_key_delete = ath_key_delete; 2232 ic->ic_crypto.cs_key_set = ath_key_set; 2233 ieee80211_media_init(ic); 2234 /* 2235 * initialize default tx key 2236 */ 2237 ic->ic_def_txkey = 0; 2238 2239 asc->asc_rx_pend = 0; 2240 ATH_HAL_INTRSET(ah, 0); 2241 err = ddi_add_softintr(devinfo, DDI_SOFTINT_LOW, 2242 &asc->asc_softint_id, NULL, 0, ath_softint_handler, (caddr_t)asc); 2243 if (err != DDI_SUCCESS) { 2244 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 2245 "ddi_add_softintr() failed\n")); 2246 goto attach_fail5; 2247 } 2248 2249 if (ddi_get_iblock_cookie(devinfo, 0, &asc->asc_iblock) 2250 != DDI_SUCCESS) { 2251 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 2252 "Can not get iblock cookie for INT\n")); 2253 goto attach_fail6; 2254 } 2255 2256 if (ddi_add_intr(devinfo, 0, NULL, NULL, ath_intr, 2257 (caddr_t)asc) != DDI_SUCCESS) { 2258 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 2259 "Can not set intr for ATH driver\n")); 2260 goto attach_fail6; 2261 } 2262 2263 /* 2264 * Provide initial settings for the WiFi plugin; whenever this 2265 * information changes, we need to call mac_plugindata_update() 2266 */ 2267 wd.wd_opmode = ic->ic_opmode; 2268 wd.wd_secalloc = WIFI_SEC_NONE; 2269 IEEE80211_ADDR_COPY(wd.wd_bssid, ic->ic_bss->in_bssid); 2270 2271 if ((macp = mac_alloc(MAC_VERSION)) == NULL) { 2272 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 2273 "MAC version mismatch\n")); 2274 goto attach_fail7; 2275 } 2276 2277 macp->m_type_ident = MAC_PLUGIN_IDENT_WIFI; 2278 macp->m_driver = asc; 2279 macp->m_dip = devinfo; 2280 macp->m_src_addr = ic->ic_macaddr; 2281 macp->m_callbacks = &ath_m_callbacks; 2282 macp->m_min_sdu = 0; 2283 macp->m_max_sdu = IEEE80211_MTU; 2284 macp->m_pdata = &wd; 2285 macp->m_pdata_size = sizeof (wd); 2286 2287 err = mac_register(macp, &ic->ic_mach); 2288 mac_free(macp); 2289 if (err != 0) { 2290 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 2291 "mac_register err %x\n", err)); 2292 goto attach_fail7; 2293 } 2294 2295 /* Create minor node of type DDI_NT_NET_WIFI */ 2296 (void) snprintf(strbuf, sizeof (strbuf), "%s%d", 2297 ATH_NODENAME, instance); 2298 err = ddi_create_minor_node(devinfo, strbuf, S_IFCHR, 2299 instance + 1, DDI_NT_NET_WIFI, 0); 2300 if (err != DDI_SUCCESS) 2301 ATH_DEBUG((ATH_DBG_ATTACH, "WARN: ath: ath_attach(): " 2302 "Create minor node failed - %d\n", err)); 2303 2304 mac_link_update(ic->ic_mach, LINK_STATE_DOWN); 2305 asc->asc_invalid = 1; 2306 asc->asc_isrunning = 0; 2307 asc->asc_promisc = B_FALSE; 2308 bzero(asc->asc_mcast_refs, sizeof (asc->asc_mcast_refs)); 2309 bzero(asc->asc_mcast_hash, sizeof (asc->asc_mcast_hash)); 2310 return (DDI_SUCCESS); 2311 attach_fail7: 2312 ddi_remove_intr(devinfo, 0, asc->asc_iblock); 2313 attach_fail6: 2314 ddi_remove_softintr(asc->asc_softint_id); 2315 attach_fail5: 2316 (void) ieee80211_detach(ic); 2317 attach_fail4: 2318 ath_desc_free(asc); 2319 if (asc->asc_tq) 2320 ddi_taskq_destroy(asc->asc_tq); 2321 attach_fail3: 2322 ah->ah_detach(asc->asc_ah); 2323 attach_fail2: 2324 ddi_regs_map_free(&asc->asc_io_handle); 2325 attach_fail1: 2326 pci_config_teardown(&asc->asc_cfg_handle); 2327 attach_fail0: 2328 asc->asc_invalid = 1; 2329 mutex_destroy(&asc->asc_txbuflock); 2330 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 2331 if (ATH_TXQ_SETUP(asc, i)) { 2332 struct ath_txq *txq = &asc->asc_txq[i]; 2333 mutex_destroy(&txq->axq_lock); 2334 } 2335 } 2336 mutex_destroy(&asc->asc_rxbuflock); 2337 mutex_destroy(&asc->asc_genlock); 2338 mutex_destroy(&asc->asc_resched_lock); 2339 ddi_soft_state_free(ath_soft_state_p, instance); 2340 2341 return (DDI_FAILURE); 2342 } 2343 2344 /* 2345 * Suspend transmit/receive for powerdown 2346 */ 2347 static int 2348 ath_suspend(ath_t *asc) 2349 { 2350 ATH_LOCK(asc); 2351 ath_stop_locked(asc); 2352 ATH_UNLOCK(asc); 2353 ATH_DEBUG((ATH_DBG_SUSPEND, "ath: suspended.\n")); 2354 2355 return (DDI_SUCCESS); 2356 } 2357 2358 static int32_t 2359 ath_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 2360 { 2361 ath_t *asc; 2362 2363 asc = ddi_get_soft_state(ath_soft_state_p, ddi_get_instance(devinfo)); 2364 ASSERT(asc != NULL); 2365 2366 switch (cmd) { 2367 case DDI_DETACH: 2368 break; 2369 2370 case DDI_SUSPEND: 2371 return (ath_suspend(asc)); 2372 2373 default: 2374 return (DDI_FAILURE); 2375 } 2376 2377 if (mac_disable(asc->asc_isc.ic_mach) != 0) 2378 return (DDI_FAILURE); 2379 2380 ath_stop_scantimer(asc); 2381 2382 /* disable interrupts */ 2383 ATH_HAL_INTRSET(asc->asc_ah, 0); 2384 2385 /* 2386 * Unregister from the MAC layer subsystem 2387 */ 2388 (void) mac_unregister(asc->asc_isc.ic_mach); 2389 2390 /* free intterrupt resources */ 2391 ddi_remove_intr(devinfo, 0, asc->asc_iblock); 2392 ddi_remove_softintr(asc->asc_softint_id); 2393 2394 /* 2395 * NB: the order of these is important: 2396 * o call the 802.11 layer before detaching the hal to 2397 * insure callbacks into the driver to delete global 2398 * key cache entries can be handled 2399 * o reclaim the tx queue data structures after calling 2400 * the 802.11 layer as we'll get called back to reclaim 2401 * node state and potentially want to use them 2402 * o to cleanup the tx queues the hal is called, so detach 2403 * it last 2404 */ 2405 ieee80211_detach(&asc->asc_isc); 2406 ath_desc_free(asc); 2407 ddi_taskq_destroy(asc->asc_tq); 2408 ath_txq_cleanup(asc); 2409 asc->asc_ah->ah_detach(asc->asc_ah); 2410 2411 /* free io handle */ 2412 ddi_regs_map_free(&asc->asc_io_handle); 2413 pci_config_teardown(&asc->asc_cfg_handle); 2414 2415 /* destroy locks */ 2416 mutex_destroy(&asc->asc_rxbuflock); 2417 mutex_destroy(&asc->asc_genlock); 2418 mutex_destroy(&asc->asc_resched_lock); 2419 2420 ddi_remove_minor_node(devinfo, NULL); 2421 ddi_soft_state_free(ath_soft_state_p, ddi_get_instance(devinfo)); 2422 2423 return (DDI_SUCCESS); 2424 } 2425 2426 /* 2427 * quiesce(9E) entry point. 2428 * 2429 * This function is called when the system is single-threaded at high 2430 * PIL with preemption disabled. Therefore, this function must not be 2431 * blocked. 2432 * 2433 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 2434 * DDI_FAILURE indicates an error condition and should almost never happen. 2435 */ 2436 static int32_t 2437 ath_quiesce(dev_info_t *devinfo) 2438 { 2439 ath_t *asc; 2440 struct ath_hal *ah; 2441 int i; 2442 2443 asc = ddi_get_soft_state(ath_soft_state_p, ddi_get_instance(devinfo)); 2444 2445 if (asc == NULL || (ah = asc->asc_ah) == NULL) 2446 return (DDI_FAILURE); 2447 2448 /* 2449 * Disable interrupts 2450 */ 2451 ATH_HAL_INTRSET(ah, 0); 2452 2453 /* 2454 * Disable TX HW 2455 */ 2456 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 2457 if (ATH_TXQ_SETUP(asc, i)) { 2458 ATH_HAL_STOPTXDMA(ah, asc->asc_txq[i].axq_qnum); 2459 } 2460 } 2461 2462 /* 2463 * Disable RX HW 2464 */ 2465 ATH_HAL_STOPPCURECV(ah); 2466 ATH_HAL_SETRXFILTER(ah, 0); 2467 ATH_HAL_STOPDMARECV(ah); 2468 drv_usecwait(3000); 2469 2470 /* 2471 * Power down HW 2472 */ 2473 ATH_HAL_PHYDISABLE(ah); 2474 2475 return (DDI_SUCCESS); 2476 } 2477 2478 DDI_DEFINE_STREAM_OPS(ath_dev_ops, nulldev, nulldev, ath_attach, ath_detach, 2479 nodev, NULL, D_MP, NULL, ath_quiesce); 2480 2481 static struct modldrv ath_modldrv = { 2482 &mod_driverops, /* Type of module. This one is a driver */ 2483 "ath driver 1.4/HAL 0.10.5.6", /* short description */ 2484 &ath_dev_ops /* driver specific ops */ 2485 }; 2486 2487 static struct modlinkage modlinkage = { 2488 MODREV_1, (void *)&ath_modldrv, NULL 2489 }; 2490 2491 2492 int 2493 _info(struct modinfo *modinfop) 2494 { 2495 return (mod_info(&modlinkage, modinfop)); 2496 } 2497 2498 int 2499 _init(void) 2500 { 2501 int status; 2502 2503 status = ddi_soft_state_init(&ath_soft_state_p, sizeof (ath_t), 1); 2504 if (status != 0) 2505 return (status); 2506 2507 mutex_init(&ath_loglock, NULL, MUTEX_DRIVER, NULL); 2508 ath_halfix_init(); 2509 mac_init_ops(&ath_dev_ops, "ath"); 2510 status = mod_install(&modlinkage); 2511 if (status != 0) { 2512 mac_fini_ops(&ath_dev_ops); 2513 ath_halfix_finit(); 2514 mutex_destroy(&ath_loglock); 2515 ddi_soft_state_fini(&ath_soft_state_p); 2516 } 2517 2518 return (status); 2519 } 2520 2521 int 2522 _fini(void) 2523 { 2524 int status; 2525 2526 status = mod_remove(&modlinkage); 2527 if (status == 0) { 2528 mac_fini_ops(&ath_dev_ops); 2529 ath_halfix_finit(); 2530 mutex_destroy(&ath_loglock); 2531 ddi_soft_state_fini(&ath_soft_state_p); 2532 } 2533 return (status); 2534 } 2535