1 /* 2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting, Atheros 3 * Communications, Inc. All rights reserved. 4 * 5 * Use is subject to license terms. 6 * 7 * Redistribution and use in source and binary forms are permitted 8 * provided that the following conditions are met: 9 * 1. The materials contained herein are unmodified and are used 10 * unmodified. 11 * 2. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following NO 13 * ''WARRANTY'' disclaimer below (''Disclaimer''), without 14 * modification. 15 * 3. Redistributions in binary form must reproduce at minimum a 16 * disclaimer similar to the Disclaimer below and any redistribution 17 * must be conditioned upon including a substantially similar 18 * Disclaimer requirement for further binary redistribution. 19 * 4. Neither the names of the above-listed copyright holders nor the 20 * names of any contributors may be used to endorse or promote 21 * product derived from this software without specific prior written 22 * permission. 23 * 24 * NO WARRANTY 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, 28 * MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 * IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE 30 * FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 32 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 33 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 34 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 35 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGES. 37 * 38 */ 39 40 #ifndef _ATH_HAL_H 41 #define _ATH_HAL_H 42 43 #pragma ident "%Z%%M% %I% %E% SMI" 44 45 /* 46 * ath_hal.h is released by Atheros and used to describe the Atheros 47 * Hardware Access Layer(HAL) interface. All kinds of data structures, 48 * constant definition, APIs declaration are defined here.Clients of 49 * the HAL call ath_hal_attach() to obtain a reference to an ath_hal 50 * structure for use with the device. Hardware-related operations that 51 * follow must call back into the HAL through interface, supplying the 52 * reference as the first parameter. 53 */ 54 55 #ifdef __cplusplus 56 extern "C" { 57 #endif 58 59 /* HAL version of this release */ 60 #define HAL_ABI_VERSION 0x04112900 /* YYMMDDnn */ 61 62 /* HAL data type definition */ 63 typedef void * HAL_SOFTC; 64 typedef int HAL_BUS_TAG; 65 typedef void * HAL_BUS_HANDLE; 66 typedef uint32_t HAL_BUS_ADDR; 67 typedef uint16_t HAL_CTRY_CODE; /* country code */ 68 typedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */ 69 70 #define HAL_NUM_TX_QUEUES 10 /* max number of tx queues */ 71 72 #define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */ 73 #define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */ 74 #define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */ 75 76 #define CHANNEL_RAD_INT 0x0001 /* Radar interference detected on channel */ 77 #define CHANNEL_CW_INT 0x0002 /* CW interference detected on channel */ 78 #define CHANNEL_BUSY 0x0004 /* Busy, occupied or overlap with adjoin chan */ 79 #define CHANNEL_TURBO 0x0010 /* Turbo Channel */ 80 #define CHANNEL_CCK 0x0020 /* CCK channel */ 81 #define CHANNEL_OFDM 0x0040 /* OFDM channel */ 82 #define CHANNEL_2GHZ 0x0080 /* 2 GHz spectrum channel. */ 83 #define CHANNEL_5GHZ 0x0100 /* 5 GHz spectrum channel */ 84 #define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed in the channel */ 85 #define CHANNEL_DYN 0x0400 /* dynamic CCK-OFDM channel */ 86 #define CHANNEL_XR 0x0800 /* XR channel */ 87 #define CHANNEL_AR 0x8000 /* Software use: radar detected */ 88 89 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) 90 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) 91 #define CHANNEL_PUREG (CHANNEL_2GHZ|CHANNEL_OFDM) 92 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) 93 #define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO) 94 #define CHANNEL_108G (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO) 95 #define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR) 96 #define CHANNEL_ALL \ 97 (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_5GHZ|CHANNEL_2GHZ|CHANNEL_TURBO) 98 #define CHANNEL_ALL_NOTURBO (CHANNEL_ALL &~ CHANNEL_TURBO) 99 100 #define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */ 101 102 /* flags passed to tx descriptor setup methods */ 103 #define HAL_TXDESC_CLRDMASK 0x0001 /* clear destination filter mask */ 104 #define HAL_TXDESC_NOACK 0x0002 /* don't wait for ACK */ 105 #define HAL_TXDESC_RTSENA 0x0004 /* enable RTS */ 106 #define HAL_TXDESC_CTSENA 0x0008 /* enable CTS */ 107 #define HAL_TXDESC_INTREQ 0x0010 /* enable per-descriptor interrupt */ 108 #define HAL_TXDESC_VEOL 0x0020 /* mark virtual EOL */ 109 110 /* flags passed to rx descriptor setup methods */ 111 #define HAL_RXDESC_INTREQ 0x0020 /* enable per-descriptor interrupt */ 112 113 /* tx error flags */ 114 #define HAL_TXERR_XRETRY 0x01 /* excessive retries */ 115 #define HAL_TXERR_FILT 0x02 /* blocked by tx filtering */ 116 #define HAL_TXERR_FIFO 0x04 /* fifo underrun */ 117 #define HAL_TXSTAT_ALTRATE 0x80 /* alternate xmit rate used */ 118 119 /* rx error flags */ 120 #define HAL_RXERR_CRC 0x01 /* CRC error on frame */ 121 #define HAL_RXERR_PHY 0x02 /* PHY error, rs_phyerr is valid */ 122 #define HAL_RXERR_FIFO 0x04 /* fifo overrun */ 123 #define HAL_RXERR_DECRYPT 0x08 /* non-Michael decrypt error */ 124 #define HAL_RXERR_MIC 0x10 /* Michael MIC decrypt error */ 125 126 /* value found in rs_keyix to mark invalid entries */ 127 #define HAL_RXKEYIX_INVALID ((uint8_t)-1) 128 129 /* value used to specify no encryption key for xmit */ 130 #define HAL_TXKEYIX_INVALID ((uint32_t)-1) 131 132 /* 133 * Status codes that may be returned by the HAL. Note that 134 * interfaces that return a status code set it only when an 135 * error occurs--i.e. you cannot check it for success. 136 */ 137 typedef enum { 138 HAL_OK = 0, /* No error */ 139 HAL_ENXIO = 1, /* No hardware present */ 140 HAL_ENOMEM = 2, /* Memory allocation failed */ 141 HAL_EIO = 3, /* Hardware didn't respond as expected */ 142 HAL_EEMAGIC = 4, /* EEPROM magic number invalid */ 143 HAL_EEVERSION = 5, /* EEPROM version invalid */ 144 HAL_EELOCKED = 6, /* EEPROM unreadable */ 145 HAL_EEBADSUM = 7, /* EEPROM checksum invalid */ 146 HAL_EEREAD = 8, /* EEPROM read problem */ 147 HAL_EEBADMAC = 9, /* EEPROM mac address invalid */ 148 HAL_EESIZE = 10, /* EEPROM size not supported */ 149 HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */ 150 HAL_EINVAL = 12, /* Invalid parameter to function */ 151 HAL_ENOTSUPP = 13, /* Hardware revision not supported */ 152 HAL_ESELFTEST = 14, /* Hardware self-test failed */ 153 HAL_EINPROGRESS = 15 /* Operation incomplete */ 154 } HAL_STATUS; 155 156 typedef enum { 157 AH_FALSE = 0, /* NB: lots of code assumes false is zero */ 158 AH_TRUE = 1 159 } HAL_BOOL; 160 161 typedef enum { 162 HAL_CAP_REG_DMN = 0, /* current regulatory domain */ 163 HAL_CAP_CIPHER = 1, /* hardware supports cipher */ 164 HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */ 165 HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */ 166 HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */ 167 HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */ 168 HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */ 169 HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */ 170 HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */ 171 HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll */ 172 /* support */ 173 HAL_CAP_DIAG = 11, /* hardware diagnostic support */ 174 HAL_CAP_COMPRESSION = 12, /* hardware supports compression */ 175 HAL_CAP_BURST = 13, /* hardware supports packet bursting */ 176 HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */ 177 HAL_CAP_TXPOW = 15, /* global tx power limit */ 178 HAL_CAP_TPC = 16 /* per-packet tx power control */ 179 } HAL_CAPABILITY_TYPE; 180 181 /* 182 * "States" for setting the LED. These correspond to 183 * the possible 802.11 operational states and there may 184 * be a many-to-one mapping between these states and the 185 * actual hardware states for the LED's (i.e. the hardware 186 * may have fewer states). 187 */ 188 typedef enum { 189 HAL_LED_INIT = 0, 190 HAL_LED_SCAN = 1, 191 HAL_LED_AUTH = 2, 192 HAL_LED_ASSOC = 3, 193 HAL_LED_RUN = 4 194 } HAL_LED_STATE; 195 196 /* 197 * Transmit queue types/numbers. These are used to tag 198 * each transmit queue in the hardware and to identify a set 199 * of transmit queues for operations such as start/stop dma. 200 */ 201 typedef enum { 202 HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */ 203 HAL_TX_QUEUE_DATA = 1, /* data xmit q's */ 204 HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */ 205 HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */ 206 HAL_TX_QUEUE_PSPOLL = 4 /* power-save poll xmit q */ 207 } HAL_TX_QUEUE; 208 209 210 /* 211 * Transmit queue subtype. These map directly to 212 * WME Access Categories (except for UPSD). Refer 213 * to Table 5 of the WME spec. 214 */ 215 typedef enum { 216 HAL_WME_AC_BK = 0, /* background access category */ 217 HAL_WME_AC_BE = 1, /* best effort access category */ 218 HAL_WME_AC_VI = 2, /* video access category */ 219 HAL_WME_AC_VO = 3, /* voice access category */ 220 HAL_WME_UPSD = 4 /* uplink power save */ 221 } HAL_TX_QUEUE_SUBTYPE; 222 223 /* 224 * Transmit queue flags that control various 225 * operational parameters. 226 */ 227 typedef enum { 228 TXQ_FLAG_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */ 229 TXQ_FLAG_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */ 230 TXQ_FLAG_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */ 231 TXQ_FLAG_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */ 232 TXQ_FLAG_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */ 233 TXQ_FLAG_BACKOFF_DISABLE = 0x0010, /* disable Post Backoff */ 234 TXQ_FLAG_COMPRESSION_ENABLE = 0x0020, /* compression enabled */ 235 /* enable ready time expiry policy */ 236 TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040, 237 /* enable backoff while sending fragment burst */ 238 TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080 239 } HAL_TX_QUEUE_FLAGS; 240 241 typedef struct { 242 uint32_t tqi_ver; /* hal TXQ version */ 243 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */ 244 HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */ 245 uint32_t tqi_priority; /* (not used) */ 246 uint32_t tqi_aifs; /* AIFS shift */ 247 int32_t tqi_cwmin; /* cwMin shift */ 248 int32_t tqi_cwmax; /* cwMax shift */ 249 uint16_t tqi_shretry; /* rts retry limit */ 250 uint16_t tqi_lgretry; /* long retry limit(not used) */ 251 uint32_t tqi_cbrPeriod; 252 uint32_t tqi_cbrOverflowLimit; 253 uint32_t tqi_burstTime; 254 uint32_t tqi_readyTime; 255 } HAL_TXQ_INFO; 256 257 /* token to use for aifs, cwmin, cwmax */ 258 #define HAL_TXQ_USEDEFAULT ((uint32_t)-1) 259 260 /* 261 * Transmit packet types. This belongs in ah_desc.h, but 262 * is here so we can give a proper type to various parameters 263 * (and not require everyone include the file). 264 * 265 * NB: These values are intentionally assigned for 266 * direct use when setting up h/w descriptors. 267 */ 268 typedef enum { 269 HAL_PKT_TYPE_NORMAL = 0, 270 HAL_PKT_TYPE_ATIM = 1, 271 HAL_PKT_TYPE_PSPOLL = 2, 272 HAL_PKT_TYPE_BEACON = 3, 273 HAL_PKT_TYPE_PROBE_RESP = 4 274 } HAL_PKT_TYPE; 275 276 /* Rx Filter Frame Types */ 277 typedef enum { 278 HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */ 279 HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */ 280 HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */ 281 HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */ 282 HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */ 283 HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */ 284 HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */ 285 HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */ 286 HAL_RX_FILTER_PHYRADAR = 0x00000200 /* Allow phy radar errors */ 287 } HAL_RX_FILTER; 288 289 typedef enum { 290 HAL_PM_UNDEFINED = 0, 291 HAL_PM_AUTO = 1, 292 HAL_PM_AWAKE = 2, 293 HAL_PM_FULL_SLEEP = 3, 294 HAL_PM_NETWORK_SLEEP = 4 295 } HAL_POWER_MODE; 296 297 /* 298 * NOTE WELL: 299 * These are mapped to take advantage of the common locations for many of 300 * the bits on all of the currently supported MAC chips. This is to make 301 * the ISR as efficient as possible, while still abstracting HW differences. 302 * When new hardware breaks this commonality this enumerated type, as well 303 * as the HAL functions using it, must be modified. All values are directly 304 * mapped unless commented otherwise. 305 */ 306 typedef enum { 307 HAL_INT_RX = 0x00000001, /* Non-common mapping */ 308 HAL_INT_RXDESC = 0x00000002, 309 HAL_INT_RXNOFRM = 0x00000008, 310 HAL_INT_RXEOL = 0x00000010, 311 HAL_INT_RXORN = 0x00000020, 312 HAL_INT_TX = 0x00000040, /* Non-common mapping */ 313 HAL_INT_TXDESC = 0x00000080, 314 HAL_INT_TXURN = 0x00000800, 315 HAL_INT_MIB = 0x00001000, 316 HAL_INT_RXPHY = 0x00004000, 317 HAL_INT_RXKCM = 0x00008000, 318 HAL_INT_SWBA = 0x00010000, 319 HAL_INT_BMISS = 0x00040000, 320 HAL_INT_BNR = 0x00100000, /* Non-common mapping */ 321 HAL_INT_GPIO = 0x01000000, 322 HAL_INT_FATAL = 0x40000000, /* Non-common mapping */ 323 HAL_INT_GLOBAL = INT_MIN, /* Set/clear IER */ 324 325 /* Interrupt bits that map directly to ISR/IMR bits */ 326 HAL_INT_COMMON = HAL_INT_RXNOFRM 327 | HAL_INT_RXDESC 328 | HAL_INT_RXEOL 329 | HAL_INT_RXORN 330 | HAL_INT_TXURN 331 | HAL_INT_TXDESC 332 | HAL_INT_MIB 333 | HAL_INT_RXPHY 334 | HAL_INT_RXKCM 335 | HAL_INT_SWBA 336 | HAL_INT_BMISS 337 | HAL_INT_GPIO, 338 HAL_INT_NOCARD = -1 /* To signal the card was removed */ 339 } HAL_INT; 340 341 typedef enum { 342 HAL_RFGAIN_INACTIVE = 0, 343 HAL_RFGAIN_READ_REQUESTED = 1, 344 HAL_RFGAIN_NEED_CHANGE = 2 345 } HAL_RFGAIN; 346 347 typedef enum { 348 HAL_PHYERR_UNDERRUN = 0, /* Transmit underrun */ 349 HAL_PHYERR_TIMING = 1, /* Timing error */ 350 HAL_PHYERR_PARITY = 2, /* Illegal parity */ 351 HAL_PHYERR_RATE = 3, /* Illegal rate */ 352 HAL_PHYERR_LENGTH = 4, /* Illegal length */ 353 HAL_PHYERR_RADAR = 5, /* Radar detect */ 354 HAL_PHYERR_SERVICE = 6, /* Illegal service */ 355 HAL_PHYERR_TOR = 7, /* Transmit override receive */ 356 /* NB: these are specific to the 5212 */ 357 HAL_PHYERR_OFDM_TIMING = 17, /* */ 358 HAL_PHYERR_OFDM_SIGNAL_PARITY = 18, /* */ 359 HAL_PHYERR_OFDM_RATE_ILLEGAL = 19, /* */ 360 HAL_PHYERR_OFDM_LENGTH_ILLEGAL = 20, /* */ 361 HAL_PHYERR_OFDM_POWER_DROP = 21, /* */ 362 HAL_PHYERR_OFDM_SERVICE = 22, /* */ 363 HAL_PHYERR_OFDM_RESTART = 23, /* */ 364 HAL_PHYERR_CCK_TIMING = 25, /* */ 365 HAL_PHYERR_CCK_HEADER_CRC = 26, /* */ 366 HAL_PHYERR_CCK_RATE_ILLEGAL = 27, /* */ 367 HAL_PHYERR_CCK_SERVICE = 30, /* */ 368 HAL_PHYERR_CCK_RESTART = 31 /* */ 369 }HAL_PHYERR; 370 371 /* 372 * Channels are specified by frequency. 373 */ 374 typedef struct { 375 uint16_t channel; /* setting in Mhz */ 376 uint16_t channelFlags; /* see below */ 377 } HAL_CHANNEL; 378 379 380 typedef struct { 381 uint32_t ackrcv_bad; 382 uint32_t rts_bad; 383 uint32_t rts_good; 384 uint32_t fcs_bad; 385 uint32_t beacons; 386 } HAL_MIB_STATS; 387 388 389 enum { 390 CTRY_DEBUG = 0x1ff, /* debug country code */ 391 CTRY_DEFAULT = 0 /* default country code */ 392 }; 393 394 enum { 395 HAL_MODE_11A = 0x001, 396 HAL_MODE_TURBO = 0x002, 397 HAL_MODE_11B = 0x004, 398 HAL_MODE_PUREG = 0x008, 399 HAL_MODE_11G = 0x008, 400 HAL_MODE_108G = 0x020, 401 HAL_MODE_ALL = 0xfff 402 }; 403 404 typedef struct { 405 int rateCount; /* NB: for proper padding */ 406 uint8_t rateCodeToIndex[32]; /* back mapping */ 407 struct { 408 uint8_t valid; /* valid for rate control use */ 409 uint8_t phy; /* CCK/OFDM/XR */ 410 uint16_t rateKbps; /* transfer rate in kbs */ 411 uint8_t rateCode; /* rate for h/w descriptors */ 412 /* mask for enabling short preamble in CCK rate code */ 413 uint8_t shortPreamble; 414 /* value for supported rates info element of MLME */ 415 uint8_t dot11Rate; 416 /* index of next lower basic rate; used for dur. calcs */ 417 uint8_t controlRate; 418 uint16_t lpAckDuration; /* long preamble ACK duration */ 419 uint16_t spAckDuration; /* short preamble ACK duration */ 420 } info[32]; 421 } HAL_RATE_TABLE; 422 423 typedef struct { 424 uint32_t rs_count; /* number of valid entries */ 425 uint8_t rs_rates[32]; /* rates */ 426 } HAL_RATE_SET; 427 428 typedef enum { 429 HAL_ANT_VARIABLE = 0, /* variable by programming */ 430 HAL_ANT_FIXED_A = 1, /* fixed to 11a frequencies */ 431 HAL_ANT_FIXED_B = 2 /* fixed to 11b frequencies */ 432 } HAL_ANT_SETTING; 433 434 typedef enum { 435 HAL_M_STA = 1, /* infrastructure station */ 436 HAL_M_IBSS = 0, /* IBSS (adhoc) station */ 437 HAL_M_HOSTAP = 6, /* Software Access Point */ 438 HAL_M_MONITOR = 8 /* Monitor mode */ 439 } HAL_OPMODE; 440 441 typedef struct { 442 uint8_t kv_type; /* one of HAL_CIPHER */ 443 uint8_t kv_pad; 444 uint16_t kv_len; /* length in bits */ 445 uint8_t kv_val[16]; /* enough for 128-bit keys */ 446 uint8_t kv_mic[8]; /* TKIP MIC key */ 447 } HAL_KEYVAL; 448 449 typedef enum { 450 HAL_CIPHER_WEP = 0, 451 HAL_CIPHER_AES_OCB = 1, 452 HAL_CIPHER_AES_CCM = 2, 453 HAL_CIPHER_CKIP = 3, 454 HAL_CIPHER_TKIP = 4, 455 HAL_CIPHER_CLR = 5, /* no encryption */ 456 457 HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */ 458 } HAL_CIPHER; 459 460 enum { 461 HAL_SLOT_TIME_9 = 9, 462 HAL_SLOT_TIME_20 = 20 463 }; 464 465 /* 466 * Per-station beacon timer state. Note that the specified 467 * beacon interval (given in TU's) can also include flags 468 * to force a TSF reset and to enable the beacon xmit logic. 469 * If bs_cfpmaxduration is non-zero the hardware is setup to 470 * coexist with a PCF-capable AP. 471 */ 472 typedef struct { 473 uint32_t bs_nexttbtt; /* next beacon in TU */ 474 uint32_t bs_nextdtim; /* next DTIM in TU */ 475 uint32_t bs_intval; /* beacon interval+flags */ 476 uint32_t bs_dtimperiod; 477 uint16_t bs_cfpperiod; /* CFP period in TU */ 478 uint16_t bs_cfpmaxduration; /* max CFP duration in TU */ 479 uint32_t bs_cfpnext; /* next CFP in TU */ 480 uint16_t bs_timoffset; /* byte offset to TIM bitmap */ 481 uint16_t bs_bmissthreshold; /* beacon miss threshold */ 482 uint32_t bs_sleepduration; /* max sleep duration */ 483 } HAL_BEACON_STATE; 484 485 /* 486 * Per-node statistics maintained by the driver for use in 487 * optimizing signal quality and other operational aspects. 488 */ 489 typedef struct { 490 uint32_t ns_avgbrssi; /* average beacon rssi */ 491 uint32_t ns_avgrssi; /* average data rssi */ 492 uint32_t ns_avgtxrssi; /* average tx rssi */ 493 } HAL_NODE_STATS; 494 495 /* 496 * Transmit descriptor status. This structure is filled 497 * in only after the tx descriptor process method finds a 498 * ``done'' descriptor; at which point it returns something 499 * other than HAL_EINPROGRESS. 500 * 501 * Note that ts_antenna may not be valid for all h/w. It 502 * should be used only if non-zero. 503 */ 504 struct ath_tx_status { 505 uint16_t ts_seqnum; /* h/w assigned sequence number */ 506 uint16_t ts_tstamp; /* h/w assigned timestamp */ 507 uint8_t ts_status; /* frame status, 0 => xmit ok */ 508 uint8_t ts_rate; /* h/w transmit rate index */ 509 int8_t ts_rssi; /* tx ack RSSI */ 510 uint8_t ts_shortretry; /* # short retries */ 511 uint8_t ts_longretry; /* # long retries */ 512 uint8_t ts_virtcol; /* virtual collision count */ 513 uint8_t ts_antenna; /* antenna information */ 514 }; 515 516 517 /* 518 * Receive descriptor status. This structure is filled 519 * in only after the rx descriptor process method finds a 520 * ``done'' descriptor; at which point it returns something 521 * other than HAL_EINPROGRESS. 522 * 523 * If rx_status is zero, then the frame was received ok; 524 * otherwise the error information is indicated and rs_phyerr 525 * contains a phy error code if HAL_RXERR_PHY is set. In general 526 * the frame contents is undefined when an error occurred thought 527 * for some errors (e.g. a decryption error), it may be meaningful. 528 * 529 * Note that the receive timestamp is expanded using the TSF to 530 * a full 16 bits (regardless of what the h/w provides directly). 531 * 532 * rx_rssi is in units of dbm above the noise floor. This value 533 * is measured during the preamble and PLCP; i.e. with the initial 534 * 4us of detection. The noise floor is typically a consistent 535 * -96dBm absolute power in a 20MHz channel. 536 */ 537 struct ath_rx_status { 538 uint16_t rs_datalen; /* rx frame length */ 539 uint16_t rs_tstamp; /* h/w assigned timestamp */ 540 uint8_t rs_status; /* rx status, 0 => recv ok */ 541 uint8_t rs_phyerr; /* phy error code */ 542 int8_t rs_rssi; /* rx frame RSSI */ 543 uint8_t rs_keyix; /* key cache index */ 544 uint8_t rs_rate; /* h/w receive rate index */ 545 uint8_t rs_antenna; /* antenna information */ 546 uint8_t rs_more; /* see HAL_RXERR_XXX definition */ 547 }; 548 549 /* 550 * Definitions for the software frame/packet descriptors used by 551 * the Atheros HAL. This definition obscures hardware-specific 552 * details from the driver. Drivers are expected to fillin the 553 * portions of a descriptor that are not opaque then use HAL calls 554 * to complete the work. Status for completed frames is returned 555 * in a device-independent format. 556 */ 557 #pragma pack(1) 558 struct ath_desc { 559 /* 560 * The following definitions are passed directly 561 * the hardware and managed by the HAL. Drivers 562 * should not touch those elements marked opaque. 563 */ 564 uint32_t ds_link; /* phys address of next descriptor */ 565 uint32_t ds_data; /* phys address of data buffer */ 566 uint32_t ds_ctl0; /* opaque DMA control 0 */ 567 uint32_t ds_ctl1; /* opaque DMA control 1 */ 568 uint32_t ds_hw[4]; /* opaque h/w region */ 569 /* 570 * The remaining definitions are managed by software; 571 * these are valid only after the rx/tx process descriptor 572 * methods return a non-EINPROGRESS code. 573 */ 574 union { 575 struct ath_tx_status tx; /* xmit status */ 576 struct ath_rx_status rx; /* recv status */ 577 } ds_us; 578 }; 579 #pragma pack() 580 581 #define ds_txstat ds_us.tx 582 #define ds_rxstat ds_us.rx 583 584 /* 585 * Hardware Access Layer (HAL) API. 586 * 587 * Clients of the HAL call ath_hal_attach to obtain a reference to an 588 * ath_hal structure for use with the device. Hardware-related operations 589 * that follow must call back into the HAL through interface, supplying 590 * the reference as the first parameter. Note that before using the 591 * reference returned by ath_hal_attach the caller should verify the 592 * ABI version number. 593 */ 594 struct ath_hal { 595 uint32_t ah_magic; /* consistency check magic number */ 596 uint32_t ah_abi; /* HAL ABI version */ 597 uint16_t ah_devid; /* PCI device ID */ 598 uint16_t ah_subvendorid; /* PCI subvendor ID */ 599 HAL_SOFTC ah_sc; /* back pointer to driver/os state */ 600 HAL_BUS_TAG ah_st; /* params for register r+w */ 601 HAL_BUS_HANDLE ah_sh; 602 HAL_CTRY_CODE ah_countryCode; 603 604 uint32_t ah_macVersion; /* MAC version id */ 605 uint16_t ah_macRev; /* MAC revision */ 606 uint16_t ah_phyRev; /* PHY revision */ 607 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 608 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 609 610 const HAL_RATE_TABLE *(*ah_getRateTable)(struct ath_hal *, 611 uint32_t mode); 612 void (*ah_detach) (struct ath_hal *); 613 614 /* Reset functions */ 615 HAL_BOOL (*ah_reset) (struct ath_hal *, HAL_OPMODE, 616 HAL_CHANNEL *, HAL_BOOL bChannelChange, 617 HAL_STATUS *status); 618 HAL_BOOL (*ah_phyDisable) (struct ath_hal *); 619 void (*ah_setPCUConfig) (struct ath_hal *); 620 HAL_BOOL (*ah_perCalibration) (struct ath_hal *, HAL_CHANNEL *); 621 HAL_BOOL (*ah_setTxPowerLimit)(struct ath_hal *, uint32_t); 622 623 /* Transmit functions */ 624 HAL_BOOL (*ah_updateTxTrigLevel) (struct ath_hal *, 625 HAL_BOOL incTrigLevel); 626 int (*ah_setupTxQueue) (struct ath_hal *, HAL_TX_QUEUE, 627 const HAL_TXQ_INFO *qInfo); 628 HAL_BOOL (*ah_setTxQueueProps) (struct ath_hal *, int q, 629 const HAL_TXQ_INFO *qInfo); 630 HAL_BOOL (*ah_getTxQueueProps)(struct ath_hal *, int q, 631 HAL_TXQ_INFO *qInfo); 632 HAL_BOOL (*ah_releaseTxQueue) (struct ath_hal *ah, uint32_t q); 633 HAL_BOOL (*ah_resetTxQueue) (struct ath_hal *ah, uint32_t q); 634 uint32_t (*ah_getTxDP) (struct ath_hal *, uint32_t); 635 HAL_BOOL (*ah_setTxDP) (struct ath_hal *, uint32_t, uint32_t txdp); 636 uint32_t (*ah_numTxPending)(struct ath_hal *, uint32_t q); 637 HAL_BOOL (*ah_startTxDma) (struct ath_hal *, uint32_t); 638 HAL_BOOL (*ah_stopTxDma) (struct ath_hal *, uint32_t); 639 HAL_BOOL (*ah_updateCTSForBursting)(struct ath_hal *, 640 struct ath_desc *, struct ath_desc *, 641 struct ath_desc *, struct ath_desc *, 642 uint32_t, uint32_t); 643 HAL_BOOL (*ah_setupTxDesc) (struct ath_hal *, struct ath_desc *, 644 uint32_t pktLen, uint32_t hdrLen, 645 HAL_PKT_TYPE type, uint32_t txPower, 646 uint32_t txRate0, uint32_t txTries0, 647 uint32_t keyIx, uint32_t antMode, 648 uint32_t flags, uint32_t rtsctsRate, 649 uint32_t rtsctsDuration); 650 HAL_BOOL (*ah_setupXTxDesc) (struct ath_hal *, struct ath_desc *, 651 uint32_t txRate1, uint32_t txTries1, 652 uint32_t txRate2, uint32_t txTries2, 653 uint32_t txRate3, uint32_t txTries3); 654 HAL_BOOL (*ah_fillTxDesc) (struct ath_hal *, struct ath_desc *, 655 uint32_t segLen, HAL_BOOL firstSeg, 656 HAL_BOOL lastSeg, const struct ath_desc *); 657 HAL_STATUS (*ah_procTxDesc) (struct ath_hal *, struct ath_desc *); 658 void (*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *); 659 660 /* Receive Functions */ 661 uint32_t (*ah_getRxDP) (struct ath_hal *); 662 void (*ah_setRxDP) (struct ath_hal *, uint32_t rxdp); 663 void (*ah_enableReceive) (struct ath_hal *); 664 HAL_BOOL (*ah_stopDmaReceive) (struct ath_hal *); 665 void (*ah_startPcuReceive) (struct ath_hal *); 666 void (*ah_stopPcuReceive) (struct ath_hal *); 667 void (*ah_setMulticastFilter) (struct ath_hal *, 668 uint32_t filter0, uint32_t filter1); 669 HAL_BOOL (*ah_setMulticastFilterIndex) (struct ath_hal *, 670 uint32_t index); 671 HAL_BOOL (*ah_clrMulticastFilterIndex) (struct ath_hal *, 672 uint32_t index); 673 uint32_t (*ah_getRxFilter) (struct ath_hal *); 674 void (*ah_setRxFilter) (struct ath_hal *, uint32_t); 675 HAL_BOOL (*ah_setupRxDesc) (struct ath_hal *, struct ath_desc *, 676 uint32_t size, uint32_t flags); 677 HAL_STATUS (*ah_procRxDesc) (struct ath_hal *, struct ath_desc *, 678 uint32_t phyAddr, struct ath_desc *next); 679 void (*ah_rxMonitor) (struct ath_hal *, 680 const HAL_NODE_STATS *); 681 void (*ah_procMibEvent) (struct ath_hal *, 682 const HAL_NODE_STATS *); 683 684 /* Misc Functions */ 685 HAL_STATUS (*ah_getCapability) (struct ath_hal *, 686 HAL_CAPABILITY_TYPE, uint32_t capability, 687 uint32_t *result); 688 HAL_BOOL (*ah_setCapability) (struct ath_hal *, 689 HAL_CAPABILITY_TYPE, uint32_t capability, 690 uint32_t setting, HAL_STATUS *); 691 HAL_BOOL (*ah_getDiagState) (struct ath_hal *, int request, 692 const void *args, uint32_t argsize, 693 void **result, uint32_t *resultsize); 694 void (*ah_getMacAddress) (struct ath_hal *, uint8_t *); 695 HAL_BOOL (*ah_setMacAddress) (struct ath_hal *, const uint8_t *); 696 HAL_BOOL (*ah_setRegulatoryDomain) (struct ath_hal *, 697 uint16_t, HAL_STATUS *); 698 void (*ah_setLedState) (struct ath_hal *, HAL_LED_STATE); 699 void (*ah_writeAssocid) (struct ath_hal *, 700 const uint8_t *bssid, uint16_t assocId); 701 HAL_BOOL (*ah_gpioCfgOutput) (struct ath_hal *, uint32_t gpio); 702 HAL_BOOL (*ah_gpioCfgInput) (struct ath_hal *, uint32_t gpio); 703 uint32_t (*ah_gpioGet) (struct ath_hal *, uint32_t gpio); 704 HAL_BOOL (*ah_gpioSet) (struct ath_hal *, 705 uint32_t gpio, uint32_t val); 706 void (*ah_gpioSetIntr) (struct ath_hal *, uint32_t, uint32_t); 707 uint32_t (*ah_getTsf32) (struct ath_hal *); 708 uint64_t (*ah_getTsf64) (struct ath_hal *); 709 void (*ah_resetTsf) (struct ath_hal *); 710 HAL_BOOL (*ah_detectCardPresent) (struct ath_hal *); 711 void (*ah_updateMibCounters) (struct ath_hal *, HAL_MIB_STATS *); 712 HAL_RFGAIN (*ah_getRfGain) (struct ath_hal *); 713 uint32_t (*ah_getDefAntenna) (struct ath_hal *); 714 void (*ah_setDefAntenna) (struct ath_hal *, uint32_t); 715 HAL_BOOL (*ah_setSlotTime) (struct ath_hal *, uint32_t); 716 uint32_t (*ah_getSlotTime) (struct ath_hal *); 717 HAL_BOOL (*ah_setAckTimeout) (struct ath_hal *, uint32_t); 718 uint32_t (*ah_getAckTimeout) (struct ath_hal *); 719 HAL_BOOL (*ah_setCTSTimeout) (struct ath_hal *, uint32_t); 720 uint32_t (*ah_getCTSTimeout) (struct ath_hal *); 721 722 /* Key Cache Functions */ 723 uint32_t (*ah_getKeyCacheSize) (struct ath_hal *); 724 HAL_BOOL (*ah_resetKeyCacheEntry) (struct ath_hal *, uint16_t); 725 HAL_BOOL (*ah_isKeyCacheEntryValid) (struct ath_hal *, uint16_t); 726 HAL_BOOL (*ah_setKeyCacheEntry) (struct ath_hal *, 727 uint16_t, const HAL_KEYVAL *, 728 const uint8_t *, int); 729 HAL_BOOL (*ah_setKeyCacheEntryMac) (struct ath_hal *, 730 uint16_t, const uint8_t *); 731 732 /* Power Management Functions */ 733 HAL_BOOL (*ah_setPowerMode) (struct ath_hal *, 734 HAL_POWER_MODE mode, int setChip, 735 uint16_t sleepDuration); 736 HAL_POWER_MODE (*ah_getPowerMode) (struct ath_hal *); 737 HAL_BOOL (*ah_initPSPoll) (struct ath_hal *); 738 HAL_BOOL (*ah_enablePSPoll) (struct ath_hal *, 739 uint8_t *, uint16_t); 740 HAL_BOOL (*ah_disablePSPoll) (struct ath_hal *); 741 742 /* Beacon Management Functions */ 743 void (*ah_beaconInit) (struct ath_hal *, 744 uint32_t nexttbtt, uint32_t intval); 745 void (*ah_setStationBeaconTimers) (struct ath_hal *, 746 const HAL_BEACON_STATE *); 747 void (*ah_resetStationBeaconTimers) (struct ath_hal *); 748 HAL_BOOL (*ah_waitForBeaconDone) (struct ath_hal *, 749 HAL_BUS_ADDR); 750 751 /* Interrupt functions */ 752 HAL_BOOL (*ah_isInterruptPending) (struct ath_hal *); 753 HAL_BOOL (*ah_getPendingInterrupts) (struct ath_hal *, HAL_INT *); 754 HAL_INT (*ah_getInterrupts) (struct ath_hal *); 755 HAL_INT (*ah_setInterrupts) (struct ath_hal *, HAL_INT); 756 }; 757 758 /* 759 * Check the PCI vendor ID and device ID against Atheros' values 760 * and return a printable description for any Atheros hardware. 761 * AH_NULL is returned if the ID's do not describe Atheros hardware. 762 */ 763 extern const char *ath_hal_probe(uint16_t vendorid, uint16_t devid); 764 765 /* 766 * Attach the HAL for use with the specified device. The device is 767 * defined by the PCI device ID. The caller provides an opaque pointer 768 * to an upper-layer data structure (HAL_SOFTC) that is stored in the 769 * HAL state block for later use. Hardware register accesses are done 770 * using the specified bus tag and handle. On successful return a 771 * reference to a state block is returned that must be supplied in all 772 * subsequent HAL calls. Storage associated with this reference is 773 * dynamically allocated and must be freed by calling the ah_detach 774 * method when the client is done. If the attach operation fails a 775 * null (AH_NULL) reference will be returned and a status code will 776 * be returned if the status parameter is non-zero. 777 */ 778 extern struct ath_hal *ath_hal_attach(uint16_t devid, HAL_SOFTC, 779 HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS *status); 780 781 /* 782 * Return a list of channels available for use with the hardware. 783 * The list is based on what the hardware is capable of, the specified 784 * country code, the modeSelect mask, and whether or not outdoor 785 * channels are to be permitted. 786 * 787 * The channel list is returned in the supplied array. maxchans 788 * defines the maximum size of this array. nchans contains the actual 789 * number of channels returned. If a problem occurred or there were 790 * no channels that met the criteria then AH_FALSE is returned. 791 */ 792 extern HAL_BOOL ath_hal_init_channels(struct ath_hal *, 793 HAL_CHANNEL *chans, uint32_t maxchans, uint32_t *nchans, 794 HAL_CTRY_CODE cc, uint16_t modeSelect, 795 HAL_BOOL enableOutdoor, HAL_BOOL enableExtendedChannels); 796 797 /* 798 * Return bit mask of wireless modes supported by the hardware. 799 */ 800 extern uint32_t ath_hal_getwirelessmodes(struct ath_hal *, HAL_CTRY_CODE); 801 802 /* 803 * Return rate table for specified mode (11a, 11b, 11g, etc). 804 */ 805 extern const HAL_RATE_TABLE * ath_hal_getratetable(struct ath_hal *, 806 uint32_t mode); 807 808 /* 809 * Calculate the transmit duration of a frame. 810 */ 811 extern uint16_t ath_hal_computetxtime(struct ath_hal *, 812 const HAL_RATE_TABLE *rates, uint32_t frameLen, 813 uint16_t rateix, HAL_BOOL shortPreamble); 814 815 /* 816 * Convert between IEEE channel number and channel frequency 817 * using the specified channel flags; e.g. CHANNEL_2GHZ. 818 */ 819 extern uint32_t ath_hal_mhz2ieee(uint32_t mhz, uint32_t flags); 820 extern uint32_t ath_hal_ieee2mhz(uint32_t ieee, uint32_t flags); 821 822 /* 823 * Return a version string for the HAL release. 824 */ 825 extern char ath_hal_version[]; 826 827 /* 828 * Return a NULL-terminated array of build/configuration options. 829 */ 830 extern const char *ath_hal_buildopts[]; 831 832 /* 833 * Macros to encapsulated HAL functions. 834 */ 835 #define ATH_HAL_RESET(_ah, _opmode, _chan, _outdoor, _pstatus) \ 836 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 837 #define ATH_HAL_GETCAPABILITY(_ah, _cap, _param, _result) \ 838 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 839 #define ATH_HAL_GETREGDOMAIN(_ah, _prd) \ 840 ATH_HAL_GETCAPABILITY(_ah, HAL_CAP_REG_DMN, 0, (_prd)) 841 #define ATH_HAL_GETCOUNTRYCODE(_ah, _pcc) \ 842 (*(_pcc) = (_ah)->ah_countryCode) 843 #define ATH_HAL_GETRATETABLE(_ah, _mode) \ 844 ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 845 #define ATH_HAL_GETMAC(_ah, _mac) \ 846 ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 847 #define ATH_HAL_SETMAC(_ah, _mac) \ 848 ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 849 #define ATH_HAL_INTRSET(_ah, _mask) \ 850 ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 851 #define ATH_HAL_INTRGET(_ah) \ 852 ((*(_ah)->ah_getInterrupts)((_ah))) 853 #define ATH_HAL_INTRPEND(_ah) \ 854 ((*(_ah)->ah_isInterruptPending)((_ah))) 855 #define ATH_HAL_GETISR(_ah, _pmask) \ 856 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 857 #define ATH_HAL_UPDATETXTRIGLEVEL(_ah, _inc) \ 858 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 859 #define ATH_HAL_SETPOWER(_ah, _mode, _sleepduration) \ 860 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE, (_sleepduration))) 861 #define ATH_HAL_KEYRESET(_ah, _ix) \ 862 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 863 #define ATH_HAL_KEYSET(_ah, _ix, _pk) \ 864 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), NULL, AH_FALSE)) 865 #define ATH_HAL_KEYISVALID(_ah, _ix) \ 866 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 867 #define ATH_HAL_KEYSETMAC(_ah, _ix, _mac) \ 868 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 869 #define ATH_HAL_KEYCACHESIZE(_ah) \ 870 ((*(_ah)->ah_getKeyCacheSize)((_ah))) 871 #define ATH_HAL_GETRXFILTER(_ah) \ 872 ((*(_ah)->ah_getRxFilter)((_ah))) 873 #define ATH_HAL_SETRXFILTER(_ah, _filter) \ 874 ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 875 #define ATH_HAL_SETMCASTFILTER(_ah, _mfilt0, _mfilt1) \ 876 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 877 #define ATH_HAL_WAITFORBEACON(_ah, _bf) \ 878 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 879 #define ATH_HAL_PUTRXBUF(_ah, _bufaddr) \ 880 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr))) 881 #define ATH_HAL_GETTSF32(_ah) \ 882 ((*(_ah)->ah_getTsf32)((_ah))) 883 #define ATH_HAL_GETTSF64(_ah) \ 884 ((*(_ah)->ah_getTsf64)((_ah))) 885 #define ATH_HAL_RESETTSF(_ah) \ 886 ((*(_ah)->ah_resetTsf)((_ah))) 887 #define ATH_HAL_RXENA(_ah) \ 888 ((*(_ah)->ah_enableReceive)((_ah))) 889 #define ATH_HAL_PUTTXBUF(_ah, _q, _bufaddr) \ 890 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 891 #define ATH_HAL_GETTXBUF(_ah, _q) \ 892 ((*(_ah)->ah_getTxDP)((_ah), (_q))) 893 #define ATH_HAL_GETRXBUF(_ah) \ 894 ((*(_ah)->ah_getRxDP)((_ah))) 895 #define ATH_HAL_TXSTART(_ah, _q) \ 896 ((*(_ah)->ah_startTxDma)((_ah), (_q))) 897 #define ATH_HAL_SETCHANNEL(_ah, _chan) \ 898 ((*(_ah)->ah_setChannel)((_ah), (_chan))) 899 #define ATH_HAL_CALIBRATE(_ah, _chan) \ 900 ((*(_ah)->ah_perCalibration)((_ah), (_chan))) 901 #define ATH_HAL_SETLEDSTATE(_ah, _state) \ 902 ((*(_ah)->ah_setLedState)((_ah), (_state))) 903 #define ATH_HAL_BEACONINIT(_ah, _nextb, _bperiod) \ 904 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 905 #define ATH_HAL_BEACONRESET(_ah) \ 906 ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 907 #define ATH_HAL_BEACONTIMERS(_ah, _beacon_state) \ 908 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_beacon_state))) 909 #define ATH_HAL_SETASSOCID(_ah, _bss, _associd) \ 910 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 911 #define ATH_HAL_SETOPMODE(_ah) \ 912 ((*(_ah)->ah_setPCUConfig)((_ah))) 913 #define ATH_HAL_STOPTXDMA(_ah, _qnum) \ 914 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 915 #define ATH_HAL_STOPPCURECV(_ah) \ 916 ((*(_ah)->ah_stopPcuReceive)((_ah))) 917 #define ATH_HAL_STARTPCURECV(_ah) \ 918 ((*(_ah)->ah_startPcuReceive)((_ah))) 919 #define ATH_HAL_STOPDMARECV(_ah) \ 920 ((*(_ah)->ah_stopDmaReceive)((_ah))) 921 #define ATH_HAL_DUMPSTATE(_ah) \ 922 ((*(_ah)->ah_dumpState)((_ah))) 923 #define ATH_HAL_DUMPEEPROM(_ah) \ 924 ((*(_ah)->ah_dumpEeprom)((_ah))) 925 #define ATH_HAL_DUMPRFGAIN(_ah) \ 926 ((*(_ah)->ah_dumpRfGain)((_ah))) 927 #define ATH_HAL_DUMPANI(_ah) \ 928 ((*(_ah)->ah_dumpAni)((_ah))) 929 #define ATH_HAL_SETUPTXQUEUE(_ah, _type, _irq) \ 930 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 931 #define ATH_HAL_RESETTXQUEUE(_ah, _q) \ 932 ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 933 #define ATH_HAL_RELEASETXQUEUE(_ah, _q) \ 934 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 935 #define ATH_HAL_HASVEOL \ 936 ((*(_ah)->ah_hasVEOL)((_ah))) 937 #define ATH_HAL_GETRFGAIN(_ah) \ 938 ((*(_ah)->ah_getRfGain)((_ah))) 939 #define ATH_HAL_RXMONITOR(_ah, _arg) \ 940 ((*(_ah)->ah_rxMonitor)((_ah), (_arg))) 941 #define ATH_HAL_SETUPBEACONDESC(_ah, _ds, _opmode, _flen, _hlen, \ 942 _rate, _antmode) \ 943 ((*(_ah)->ah_setupBeaconDesc)((_ah), (_ds), (_opmode), \ 944 (_flen), (_hlen), (_rate), (_antmode))) 945 #define ATH_HAL_SETUPRXDESC(_ah, _ds, _size, _intreq) \ 946 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 947 #define ATH_HAL_RXPROCDESC(_ah, _ds, _dspa, _dsnext) \ 948 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext))) 949 #define ATH_HAL_SETUPTXDESC(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 950 _txr0, _txtr0, _keyix, _ant, _flags, \ 951 _rtsrate, _rtsdura) \ 952 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 953 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 954 (_flags), (_rtsrate), (_rtsdura))) 955 #define ATH_HAL_SETUPXTXDESC(_ah, _ds, \ 956 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 957 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 958 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 959 #define ATH_HAL_FILLTXDESC(_ah, _ds, _l, _first, _last, _ath_desc) \ 960 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), \ 961 (_ath_desc))) 962 #define ATH_HAL_TXPROCDESC(_ah, _ds) \ 963 ((*(_ah)->ah_procTxDesc)((_ah), (_ds))) 964 #define ATH_HAL_CIPHERSUPPORTED(_ah, _cipher) \ 965 (ATH_HAL_GETCAPABILITY(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 966 #define ATH_HAL_TKIPSPLIT(_ah) \ 967 (ATH_HAL_GETCAPABILITY(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 968 969 #ifdef __cplusplus 970 } 971 #endif 972 973 #endif /* _ATH_HAL_H */ 974