1 /* 2 * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting, Atheros 3 * Communications, Inc. All rights reserved. 4 * 5 * Use is subject to license terms. 6 * 7 * Redistribution and use in source and binary forms are permitted 8 * provided that the following conditions are met: 9 * 1. The materials contained herein are unmodified and are used 10 * unmodified. 11 * 2. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following NO 13 * ''WARRANTY'' disclaimer below (''Disclaimer''), without 14 * modification. 15 * 3. Redistributions in binary form must reproduce at minimum a 16 * disclaimer similar to the Disclaimer below and any redistribution 17 * must be conditioned upon including a substantially similar 18 * Disclaimer requirement for further binary redistribution. 19 * 4. Neither the names of the above-listed copyright holders nor the 20 * names of any contributors may be used to endorse or promote 21 * product derived from this software without specific prior written 22 * permission. 23 * 24 * NO WARRANTY 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, 28 * MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 * IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE 30 * FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 32 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 33 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 34 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 35 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGES. 37 * 38 */ 39 40 #ifndef _ATH_HAL_H 41 #define _ATH_HAL_H 42 43 #pragma ident "%Z%%M% %I% %E% SMI" 44 45 /* 46 * ath_hal.h is released by Atheros and used to describe the Atheros 47 * Hardware Access Layer(HAL) interface. All kinds of data structures, 48 * constant definition, APIs declaration are defined here.Clients of 49 * the HAL call ath_hal_attach() to obtain a reference to an ath_hal 50 * structure for use with the device. Hardware-related operations that 51 * follow must call back into the HAL through interface, supplying the 52 * reference as the first parameter. 53 */ 54 55 #ifdef __cplusplus 56 extern "C" { 57 #endif 58 59 /* HAL version of this release */ 60 #define HAL_ABI_VERSION 0x06052200 /* YYMMDDnn */ 61 62 /* HAL data type definition */ 63 typedef void * HAL_SOFTC; /* pointer to driver/OS state */ 64 typedef void * HAL_BUS_TAG; /* opaque bus i/o id tag */ 65 typedef void * HAL_BUS_HANDLE; /* opaque bus i/o handle */ 66 typedef uint32_t HAL_BUS_ADDR; 67 typedef uint16_t HAL_CTRY_CODE; /* country code */ 68 typedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */ 69 70 #define HAL_NUM_TX_QUEUES 10 /* max number of tx queues */ 71 72 #define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */ 73 #define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */ 74 #define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */ 75 76 #define CHANNEL_RAD_INT 0x0001 /* Radar interference detected on channel */ 77 #define CHANNEL_CW_INT 0x0002 /* CW interference detected on channel */ 78 #define CHANNEL_BUSY 0x0004 /* Busy, occupied or overlap with adjoin chan */ 79 #define CHANNEL_TURBO 0x0010 /* Turbo Channel */ 80 #define CHANNEL_CCK 0x0020 /* CCK channel */ 81 #define CHANNEL_OFDM 0x0040 /* OFDM channel */ 82 #define CHANNEL_2GHZ 0x0080 /* 2 GHz spectrum channel. */ 83 #define CHANNEL_5GHZ 0x0100 /* 5 GHz spectrum channel */ 84 #define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed in the channel */ 85 #define CHANNEL_DYN 0x0400 /* dynamic CCK-OFDM channel */ 86 #define CHANNEL_XR 0x0800 /* XR channel */ 87 #define CHANNEL_STURBO 0x2000 /* Static turbo, no 11a-only usage */ 88 #define CHANNEL_HALF 0x4000 /* Half rate channel */ 89 #define CHANNEL_QUARTER 0x8000 /* Quarter rate channel */ 90 91 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) 92 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) 93 #define CHANNEL_PUREG (CHANNEL_2GHZ|CHANNEL_OFDM) 94 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) 95 #define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO) 96 #define CHANNEL_ST (CHANNEL_T|CHANNEL_STURBO) 97 #define CHANNEL_108G (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO) 98 #define CHANNEL_108A CHANNEL_T 99 #define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR) 100 #define CHANNEL_ALL \ 101 (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_5GHZ|CHANNEL_2GHZ|CHANNEL_TURBO) 102 #define CHANNEL_ALL_NOTURBO (CHANNEL_ALL &~ CHANNEL_TURBO) 103 104 #define CHANNEL_COMPAT (CHANNEL_ALL_NOTURBO | CHANNEL_PASSIVE) 105 106 /* privFlags */ 107 /* 108 * Software use: channel interference used for AR as well as RADAR 109 * interference detection 110 */ 111 #define CHANNEL_INTERFERENCE 0x01 112 #define CHANNEL_DFS 0x02 /* DFS required on channel */ 113 #define CHANNEL_4MS_LIMIT 0x04 /* 4msec packet limit on this channel */ 114 #define CHANNEL_DFS_CLEAR 0x08 /* if channel has been checked DFS */ 115 116 #define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */ 117 118 /* flags passed to tx descriptor setup methods */ 119 #define HAL_TXDESC_CLRDMASK 0x0001 /* clear destination filter mask */ 120 #define HAL_TXDESC_NOACK 0x0002 /* don't wait for ACK */ 121 #define HAL_TXDESC_RTSENA 0x0004 /* enable RTS */ 122 #define HAL_TXDESC_CTSENA 0x0008 /* enable CTS */ 123 #define HAL_TXDESC_INTREQ 0x0010 /* enable per-descriptor interrupt */ 124 #define HAL_TXDESC_VEOL 0x0020 /* mark virtual EOL */ 125 /* NB: this only affects frame, not any RTS/CTS */ 126 #define HAL_TXDESC_DURENA 0x0040 /* enable h/w write of duration field */ 127 128 /* flags passed to rx descriptor setup methods */ 129 #define HAL_RXDESC_INTREQ 0x0020 /* enable per-descriptor interrupt */ 130 131 /* tx error flags */ 132 #define HAL_TXERR_XRETRY 0x01 /* excessive retries */ 133 #define HAL_TXERR_FILT 0x02 /* blocked by tx filtering */ 134 #define HAL_TXERR_FIFO 0x04 /* fifo underrun */ 135 #define HAL_TXSTAT_ALTRATE 0x80 /* alternate xmit rate used */ 136 137 /* rx error flags */ 138 #define HAL_RXERR_CRC 0x01 /* CRC error on frame */ 139 #define HAL_RXERR_PHY 0x02 /* PHY error, rs_phyerr is valid */ 140 #define HAL_RXERR_FIFO 0x04 /* fifo overrun */ 141 #define HAL_RXERR_DECRYPT 0x08 /* non-Michael decrypt error */ 142 #define HAL_RXERR_MIC 0x10 /* Michael MIC decrypt error */ 143 144 /* value found in rs_keyix to mark invalid entries */ 145 #define HAL_RXKEYIX_INVALID ((uint8_t)-1) 146 147 /* value used to specify no encryption key for xmit */ 148 #define HAL_TXKEYIX_INVALID ((uint32_t)-1) 149 150 /* compression definitions */ 151 #define HAL_COMP_BUF_MAX_SIZE 9216 /* 9k */ 152 #define HAL_COMP_BUF_ALIGN_SIZE 512 153 #define HAL_DECOMP_MASK_SIZE 128 154 155 #define HAL_ANTENNA_MIN_MODE 0 156 #define HAL_ANTENNA_FIXED_A 1 157 #define HAL_ANTENNA_FIXED_B 2 158 #define HAL_ANTENNA_MAX_MODE 3 159 160 /* 161 * Status codes that may be returned by the HAL. Note that 162 * interfaces that return a status code set it only when an 163 * error occurs--i.e. you cannot check it for success. 164 */ 165 typedef enum { 166 HAL_OK = 0, /* No error */ 167 HAL_ENXIO = 1, /* No hardware present */ 168 HAL_ENOMEM = 2, /* Memory allocation failed */ 169 HAL_EIO = 3, /* Hardware didn't respond as expected */ 170 HAL_EEMAGIC = 4, /* EEPROM magic number invalid */ 171 HAL_EEVERSION = 5, /* EEPROM version invalid */ 172 HAL_EELOCKED = 6, /* EEPROM unreadable */ 173 HAL_EEBADSUM = 7, /* EEPROM checksum invalid */ 174 HAL_EEREAD = 8, /* EEPROM read problem */ 175 HAL_EEBADMAC = 9, /* EEPROM mac address invalid */ 176 HAL_EESIZE = 10, /* EEPROM size not supported */ 177 HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */ 178 HAL_EINVAL = 12, /* Invalid parameter to function */ 179 HAL_ENOTSUPP = 13, /* Hardware revision not supported */ 180 HAL_ESELFTEST = 14, /* Hardware self-test failed */ 181 HAL_EINPROGRESS = 15 /* Operation incomplete */ 182 } HAL_STATUS; 183 184 typedef enum { 185 AH_FALSE = 0, /* NB: lots of code assumes false is zero */ 186 AH_TRUE = 1 187 } HAL_BOOL; 188 189 typedef enum { 190 HAL_CAP_REG_DMN = 0, /* current regulatory domain */ 191 HAL_CAP_CIPHER = 1, /* hardware supports cipher */ 192 HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */ 193 HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */ 194 HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */ 195 HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */ 196 HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */ 197 HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */ 198 HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */ 199 HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll */ 200 /* support */ 201 HAL_CAP_DIAG = 11, /* hardware diagnostic support */ 202 HAL_CAP_COMPRESSION = 12, /* hardware supports compression */ 203 HAL_CAP_BURST = 13, /* hardware supports packet bursting */ 204 HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */ 205 HAL_CAP_TXPOW = 15, /* global tx power limit */ 206 HAL_CAP_TPC = 16, /* per-packet tx power control */ 207 HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */ 208 HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */ 209 HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */ 210 HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */ 211 HAL_CAP_XR = 21, /* hardware has XR support */ 212 /* hardware can support TKIP MIC when WMM is turned on */ 213 HAL_CAP_WME_TKIPMIC = 22, 214 /* hardware can support half rate channels */ 215 HAL_CAP_CHAN_HALFRATE = 23, 216 /* hardware can support quarter rate channels */ 217 HAL_CAP_CHAN_QUARTERRATE = 24, 218 HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */ 219 HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */ 220 HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */ 221 HAL_CAP_11D = 28, /* 11d beacon support for changing cc */ 222 HAL_CAP_INTMIT = 29 /* interference mitigation */ 223 } HAL_CAPABILITY_TYPE; 224 225 /* 226 * "States" for setting the LED. These correspond to 227 * the possible 802.11 operational states and there may 228 * be a many-to-one mapping between these states and the 229 * actual hardware states for the LED's (i.e. the hardware 230 * may have fewer states). 231 */ 232 typedef enum { 233 HAL_LED_INIT = 0, 234 HAL_LED_SCAN = 1, 235 HAL_LED_AUTH = 2, 236 HAL_LED_ASSOC = 3, 237 HAL_LED_RUN = 4 238 } HAL_LED_STATE; 239 240 /* 241 * Transmit queue types/numbers. These are used to tag 242 * each transmit queue in the hardware and to identify a set 243 * of transmit queues for operations such as start/stop dma. 244 */ 245 typedef enum { 246 HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */ 247 HAL_TX_QUEUE_DATA = 1, /* data xmit q's */ 248 HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */ 249 HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */ 250 HAL_TX_QUEUE_UAPSD = 4 /* u-apsd power save xmit q */ 251 } HAL_TX_QUEUE; 252 253 254 /* 255 * Transmit queue subtype. These map directly to 256 * WME Access Categories (except for UPSD). Refer 257 * to Table 5 of the WME spec. 258 */ 259 typedef enum { 260 HAL_WME_AC_BK = 0, /* background access category */ 261 HAL_WME_AC_BE = 1, /* best effort access category */ 262 HAL_WME_AC_VI = 2, /* video access category */ 263 HAL_WME_AC_VO = 3, /* voice access category */ 264 HAL_WME_UPSD = 4, /* uplink power save */ 265 HAL_XR_DATA = 5 /* entended range data */ 266 } HAL_TX_QUEUE_SUBTYPE; 267 268 /* 269 * Transmit queue flags that control various 270 * operational parameters. 271 */ 272 typedef enum { 273 /* 274 * Per queue interrupt enables. When set the associated 275 * interrupt may be delivered for packets sent through 276 * the queue. Without these enabled no interrupts will 277 * be delivered for transmits through the queue. 278 * 279 * When 0x0001 is set, both TXQ_TXOKINT and TXQ_TXERRINT 280 * will be enabled. 281 */ 282 HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */ 283 HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */ 284 HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */ 285 HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */ 286 HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */ 287 /* 288 * Enable hardware compression for packets sent through 289 * the queue. The compression buffer must be setup and 290 * packets must have a key entry marked in the tx descriptor. 291 */ 292 HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */ 293 /* 294 * Disable queue when veol is hit or ready time expires. 295 * By default the queue is disabled only on reaching the 296 * physical end of queue (i.e. a null link ptr in the 297 * descriptor chain). 298 */ 299 HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020, 300 /* 301 * Schedule frames on delivery of a DBA (DMA Beacon Alert) 302 * event. Frames will be transmitted only when this timer 303 * fires, e.g to transmit a beacon in ap or adhoc modes. 304 */ 305 HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */ 306 /* 307 * Each transmit queue has a counter that is incremented 308 * each time the queue is enabled and decremented when 309 * the list of frames to transmit is traversed (or when 310 * the ready time for the queue expires). This counter 311 * must be non-zero for frames to be scheduled for 312 * transmission. The following controls disable bumping 313 * this counter under certain conditions. Typically this 314 * is used to gate frames based on the contents of another 315 * queue (e.g. CAB traffic may only follow a beacon frame). 316 * These are meaningful only when frames are scheduled 317 * with a non-ASAP policy (e.g. DBA-gated). 318 */ 319 HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */ 320 HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */ 321 322 /* 323 * Fragment burst backoff policy. Normally no backoff 324 * is done after a successful transmission, the next fragment 325 * is sent at SIFS. If this flag is set backoff is done 326 * after each fragment, regardless whether it was ack'd or 327 * not, after the backoff count reaches zero a normal channel 328 * access procedure is done before the next transmit (i.e. 329 * wait AIFS instead of SIFS). 330 */ 331 HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000, 332 /* 333 * Disable post-tx backoff following each frame. 334 */ 335 HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */ 336 /* 337 * DCU arbiter lockout control. This controls how 338 * lower priority tx queues are handled with respect 339 * to a specific queue when multiple queues have frames 340 * to send. No lockout means lower priority queues arbitrate 341 * concurrently with this queue. Intra-frame lockout 342 * means lower priority queues are locked out until the 343 * current frame transmits (e.g. including backoffs and bursting). 344 * Global lockout means nothing lower can arbitrary so 345 * long as there is traffic activity on this queue (frames, 346 * backoff, etc). 347 */ 348 HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */ 349 HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */ 350 351 HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */ 352 HAL_TXQ_SEQNUM_INC_DIS = 0x00100000 /* disable seqnum increment */ 353 } HAL_TX_QUEUE_FLAGS; 354 355 typedef struct { 356 uint32_t tqi_ver; /* hal TXQ version */ 357 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */ 358 HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */ 359 uint32_t tqi_priority; /* (not used) */ 360 uint32_t tqi_aifs; /* AIFS shift */ 361 int32_t tqi_cwmin; /* cwMin shift */ 362 int32_t tqi_cwmax; /* cwMax shift */ 363 uint16_t tqi_shretry; /* rts retry limit */ 364 uint16_t tqi_lgretry; /* long retry limit(not used) */ 365 uint32_t tqi_cbrPeriod; 366 uint32_t tqi_cbrOverflowLimit; 367 uint32_t tqi_burstTime; 368 uint32_t tqi_readyTime; 369 uint32_t tqi_compBuf; /* compress buffer phys addr */ 370 } HAL_TXQ_INFO; 371 372 #define HAL_TQI_NONVAL 0xffff 373 374 /* token to use for aifs, cwmin, cwmax */ 375 #define HAL_TXQ_USEDEFAULT ((uint32_t)-1) 376 377 /* 378 * Transmit packet types. This belongs in ah_desc.h, but 379 * is here so we can give a proper type to various parameters 380 * (and not require everyone include the file). 381 * 382 * NB: These values are intentionally assigned for 383 * direct use when setting up h/w descriptors. 384 */ 385 typedef enum { 386 HAL_PKT_TYPE_NORMAL = 0, 387 HAL_PKT_TYPE_ATIM = 1, 388 HAL_PKT_TYPE_PSPOLL = 2, 389 HAL_PKT_TYPE_BEACON = 3, 390 HAL_PKT_TYPE_PROBE_RESP = 4, 391 HAL_PKT_TYPE_CHIRP = 5, 392 HAL_PKT_TYPE_GRP_POLL = 6 393 } HAL_PKT_TYPE; 394 395 /* Rx Filter Frame Types */ 396 typedef enum { 397 HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */ 398 HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */ 399 HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */ 400 HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */ 401 HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */ 402 HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */ 403 HAL_RX_FILTER_XRPOLL = 0x00000040, /* Allow XR poll frmae */ 404 HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */ 405 HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */ 406 HAL_RX_FILTER_PHYRADAR = 0x00000200 /* Allow phy radar errors */ 407 } HAL_RX_FILTER; 408 409 typedef enum { 410 HAL_PM_AWAKE = 0, 411 HAL_PM_FULL_SLEEP = 1, 412 HAL_PM_NETWORK_SLEEP = 2, 413 HAL_PM_UNDEFINED = 3 414 } HAL_POWER_MODE; 415 416 /* 417 * NOTE WELL: 418 * These are mapped to take advantage of the common locations for many of 419 * the bits on all of the currently supported MAC chips. This is to make 420 * the ISR as efficient as possible, while still abstracting HW differences. 421 * When new hardware breaks this commonality this enumerated type, as well 422 * as the HAL functions using it, must be modified. All values are directly 423 * mapped unless commented otherwise. 424 */ 425 typedef enum { 426 HAL_INT_RX = 0x00000001, /* Non-common mapping */ 427 HAL_INT_RXDESC = 0x00000002, 428 HAL_INT_RXNOFRM = 0x00000008, 429 HAL_INT_RXEOL = 0x00000010, 430 HAL_INT_RXORN = 0x00000020, 431 HAL_INT_TX = 0x00000040, /* Non-common mapping */ 432 HAL_INT_TXDESC = 0x00000080, 433 HAL_INT_TXURN = 0x00000800, 434 HAL_INT_MIB = 0x00001000, 435 HAL_INT_RXPHY = 0x00004000, 436 HAL_INT_RXKCM = 0x00008000, 437 HAL_INT_SWBA = 0x00010000, 438 HAL_INT_BMISS = 0x00040000, 439 HAL_INT_BNR = 0x00100000, /* Non-common mapping */ 440 HAL_INT_TIM = 0x00200000, /* Non-common mapping */ 441 HAL_INT_DTIM = 0x00400000, /* Non-common mapping */ 442 HAL_INT_DTIMSYNC = 0x00800000, /* Non-common mapping */ 443 HAL_INT_GPIO = 0x01000000, 444 HAL_INT_CABEND = 0x02000000, /* Non-common mapping */ 445 HAL_INT_FATAL = 0x40000000, /* Non-common mapping */ 446 HAL_INT_GLOBAL = INT_MIN, /* Set/clear IER */ 447 HAL_INT_BMISC = HAL_INT_TIM 448 | HAL_INT_DTIM 449 | HAL_INT_DTIMSYNC 450 | HAL_INT_CABEND, 451 452 /* Interrupt bits that map directly to ISR/IMR bits */ 453 HAL_INT_COMMON = HAL_INT_RXNOFRM 454 | HAL_INT_RXDESC 455 | HAL_INT_RXEOL 456 | HAL_INT_RXORN 457 | HAL_INT_TXURN 458 | HAL_INT_TXDESC 459 | HAL_INT_MIB 460 | HAL_INT_RXPHY 461 | HAL_INT_RXKCM 462 | HAL_INT_SWBA 463 | HAL_INT_BMISS 464 | HAL_INT_GPIO, 465 HAL_INT_NOCARD = -1 /* To signal the card was removed */ 466 } HAL_INT; 467 468 typedef enum { 469 HAL_RFGAIN_INACTIVE = 0, 470 HAL_RFGAIN_READ_REQUESTED = 1, 471 HAL_RFGAIN_NEED_CHANGE = 2 472 } HAL_RFGAIN; 473 474 typedef enum { 475 HAL_PHYERR_UNDERRUN = 0, /* Transmit underrun */ 476 HAL_PHYERR_TIMING = 1, /* Timing error */ 477 HAL_PHYERR_PARITY = 2, /* Illegal parity */ 478 HAL_PHYERR_RATE = 3, /* Illegal rate */ 479 HAL_PHYERR_LENGTH = 4, /* Illegal length */ 480 HAL_PHYERR_RADAR = 5, /* Radar detect */ 481 HAL_PHYERR_SERVICE = 6, /* Illegal service */ 482 HAL_PHYERR_TOR = 7, /* Transmit override receive */ 483 /* NB: these are specific to the 5212 */ 484 HAL_PHYERR_OFDM_TIMING = 17, /* */ 485 HAL_PHYERR_OFDM_SIGNAL_PARITY = 18, /* */ 486 HAL_PHYERR_OFDM_RATE_ILLEGAL = 19, /* */ 487 HAL_PHYERR_OFDM_LENGTH_ILLEGAL = 20, /* */ 488 HAL_PHYERR_OFDM_POWER_DROP = 21, /* */ 489 HAL_PHYERR_OFDM_SERVICE = 22, /* */ 490 HAL_PHYERR_OFDM_RESTART = 23, /* */ 491 HAL_PHYERR_CCK_TIMING = 25, /* */ 492 HAL_PHYERR_CCK_HEADER_CRC = 26, /* */ 493 HAL_PHYERR_CCK_RATE_ILLEGAL = 27, /* */ 494 HAL_PHYERR_CCK_SERVICE = 30, /* */ 495 HAL_PHYERR_CCK_RESTART = 31 /* */ 496 }HAL_PHYERR; 497 498 /* 499 * Channels are specified by frequency. 500 */ 501 typedef struct { 502 uint16_t channel; /* setting in Mhz */ 503 uint16_t channelFlags; /* see below */ 504 uint8_t privFlags; 505 int8_t maxRegTxPower; /* max regulatory tx power in dBm */ 506 int8_t maxTxPower; /* max true tx power in 0.5 dBm */ 507 int8_t minTxPower; /* min true tx power in 0.5 dBm */ 508 } HAL_CHANNEL; 509 510 511 typedef struct { 512 uint32_t ackrcv_bad; 513 uint32_t rts_bad; 514 uint32_t rts_good; 515 uint32_t fcs_bad; 516 uint32_t beacons; 517 } HAL_MIB_STATS; 518 519 520 enum { 521 CTRY_DEBUG = 0x1ff, /* debug country code */ 522 CTRY_DEFAULT = 0 /* default country code */ 523 }; 524 525 enum { 526 HAL_MODE_11A = 0x001, /* 11a channels */ 527 HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */ 528 HAL_MODE_11B = 0x004, /* 11b channels */ 529 HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */ 530 HAL_MODE_11G = 0x008, /* XXX historical */ 531 HAL_MODE_108G = 0x020, /* 11g+Turbo channels */ 532 HAL_MODE_108A = 0x040, /* 11a+Turbo channels */ 533 HAL_MODE_XR = 0x100, /* XR channels */ 534 HAL_MODE_11A_HALF_RATE = 0x200, /* 11A half rate channels */ 535 HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11A quarter rate channels */ 536 HAL_MODE_ALL = 0xfff 537 }; 538 539 typedef struct { 540 int rateCount; /* NB: for proper padding */ 541 uint8_t rateCodeToIndex[32]; /* back mapping */ 542 struct { 543 uint8_t valid; /* valid for rate control use */ 544 uint8_t phy; /* CCK/OFDM/XR */ 545 uint16_t rateKbps; /* transfer rate in kbs */ 546 uint8_t rateCode; /* rate for h/w descriptors */ 547 /* mask for enabling short preamble in CCK rate code */ 548 uint8_t shortPreamble; 549 /* value for supported rates info element of MLME */ 550 uint8_t dot11Rate; 551 /* index of next lower basic rate; used for dur. calcs */ 552 uint8_t controlRate; 553 uint16_t lpAckDuration; /* long preamble ACK duration */ 554 uint16_t spAckDuration; /* short preamble ACK duration */ 555 } info[32]; 556 } HAL_RATE_TABLE; 557 558 typedef struct { 559 uint32_t rs_count; /* number of valid entries */ 560 uint8_t rs_rates[32]; /* rates */ 561 } HAL_RATE_SET; 562 563 /* 564 * Antenna switch control. By default antenna selection 565 * enables multiple (2) antenna use. To force use of the 566 * A or B antenna only specify a fixed setting. Fixing 567 * the antenna will also disable any diversity support. 568 */ 569 typedef enum { 570 HAL_ANT_VARIABLE = 0, /* variable by programming */ 571 HAL_ANT_FIXED_A = 1, /* fixed antenna A */ 572 HAL_ANT_FIXED_B = 2 /* fixed antenna B */ 573 } HAL_ANT_SETTING; 574 575 typedef enum { 576 HAL_M_STA = 1, /* infrastructure station */ 577 HAL_M_IBSS = 0, /* IBSS (adhoc) station */ 578 HAL_M_HOSTAP = 6, /* Software Access Point */ 579 HAL_M_MONITOR = 8 /* Monitor mode */ 580 } HAL_OPMODE; 581 582 typedef struct { 583 uint8_t kv_type; /* one of HAL_CIPHER */ 584 uint8_t kv_pad; 585 uint16_t kv_len; /* length in bits */ 586 uint8_t kv_val[16]; /* enough for 128-bit keys */ 587 uint8_t kv_mic[8]; /* TKIP MIC key */ 588 } HAL_KEYVAL; 589 590 typedef enum { 591 HAL_CIPHER_WEP = 0, 592 HAL_CIPHER_AES_OCB = 1, 593 HAL_CIPHER_AES_CCM = 2, 594 HAL_CIPHER_CKIP = 3, 595 HAL_CIPHER_TKIP = 4, 596 HAL_CIPHER_CLR = 5, /* no encryption */ 597 598 HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */ 599 } HAL_CIPHER; 600 601 enum { 602 HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */ 603 HAL_SLOT_TIME_9 = 9, 604 HAL_SLOT_TIME_20 = 20 605 }; 606 607 /* 608 * Per-station beacon timer state. Note that the specified 609 * beacon interval (given in TU's) can also include flags 610 * to force a TSF reset and to enable the beacon xmit logic. 611 * If bs_cfpmaxduration is non-zero the hardware is setup to 612 * coexist with a PCF-capable AP. 613 */ 614 typedef struct { 615 uint32_t bs_nexttbtt; /* next beacon in TU */ 616 uint32_t bs_nextdtim; /* next DTIM in TU */ 617 uint32_t bs_intval; /* beacon interval+flags */ 618 uint32_t bs_dtimperiod; 619 uint16_t bs_cfpperiod; /* CFP period in TU */ 620 uint16_t bs_cfpmaxduration; /* max CFP duration in TU */ 621 uint32_t bs_cfpnext; /* next CFP in TU */ 622 uint16_t bs_timoffset; /* byte offset to TIM bitmap */ 623 uint16_t bs_bmissthreshold; /* beacon miss threshold */ 624 uint32_t bs_sleepduration; /* max sleep duration */ 625 } HAL_BEACON_STATE; 626 627 /* 628 * Like HAL_BEACON_STATE but for non-station mode setup. 629 * NB: see above flag definitions 630 */ 631 typedef struct { 632 uint32_t bt_intval; /* beacon interval+flags */ 633 uint32_t bt_nexttbtt; /* next beacon in TU */ 634 uint32_t bt_nextatim; /* next ATIM in TU */ 635 uint32_t bt_nextdba; /* next DBA in 1/8th TU */ 636 uint32_t bt_nextswba; /* next SWBA in 1/8th TU */ 637 } HAL_BEACON_TIMERS; 638 639 /* 640 * Per-node statistics maintained by the driver for use in 641 * optimizing signal quality and other operational aspects. 642 */ 643 typedef struct { 644 uint32_t ns_avgbrssi; /* average beacon rssi */ 645 uint32_t ns_avgrssi; /* average data rssi */ 646 uint32_t ns_avgtxrssi; /* average tx rssi */ 647 } HAL_NODE_STATS; 648 649 /* 650 * Transmit descriptor status. This structure is filled 651 * in only after the tx descriptor process method finds a 652 * ``done'' descriptor; at which point it returns something 653 * other than HAL_EINPROGRESS. 654 * 655 * Note that ts_antenna may not be valid for all h/w. It 656 * should be used only if non-zero. 657 */ 658 struct ath_tx_status { 659 uint16_t ts_seqnum; /* h/w assigned sequence number */ 660 uint16_t ts_tstamp; /* h/w assigned timestamp */ 661 uint8_t ts_status; /* frame status, 0 => xmit ok */ 662 uint8_t ts_rate; /* h/w transmit rate index */ 663 int8_t ts_rssi; /* tx ack RSSI */ 664 uint8_t ts_shortretry; /* # short retries */ 665 uint8_t ts_longretry; /* # long retries */ 666 uint8_t ts_virtcol; /* virtual collision count */ 667 uint8_t ts_antenna; /* antenna information */ 668 }; 669 670 671 /* 672 * Receive descriptor status. This structure is filled 673 * in only after the rx descriptor process method finds a 674 * ``done'' descriptor; at which point it returns something 675 * other than HAL_EINPROGRESS. 676 * 677 * If rx_status is zero, then the frame was received ok; 678 * otherwise the error information is indicated and rs_phyerr 679 * contains a phy error code if HAL_RXERR_PHY is set. In general 680 * the frame contents is undefined when an error occurred thought 681 * for some errors (e.g. a decryption error), it may be meaningful. 682 * 683 * Note that the receive timestamp is expanded using the TSF to 684 * a full 16 bits (regardless of what the h/w provides directly). 685 * 686 * rx_rssi is in units of dbm above the noise floor. This value 687 * is measured during the preamble and PLCP; i.e. with the initial 688 * 4us of detection. The noise floor is typically a consistent 689 * -96dBm absolute power in a 20MHz channel. 690 */ 691 struct ath_rx_status { 692 uint16_t rs_datalen; /* rx frame length */ 693 uint16_t rs_tstamp; /* h/w assigned timestamp */ 694 uint8_t rs_status; /* rx status, 0 => recv ok */ 695 uint8_t rs_phyerr; /* phy error code */ 696 int8_t rs_rssi; /* rx frame RSSI */ 697 uint8_t rs_keyix; /* key cache index */ 698 uint8_t rs_rate; /* h/w receive rate index */ 699 uint8_t rs_antenna; /* antenna information */ 700 uint8_t rs_more; /* see HAL_RXERR_XXX definition */ 701 }; 702 703 /* 704 * Definitions for the software frame/packet descriptors used by 705 * the Atheros HAL. This definition obscures hardware-specific 706 * details from the driver. Drivers are expected to fillin the 707 * portions of a descriptor that are not opaque then use HAL calls 708 * to complete the work. Status for completed frames is returned 709 * in a device-independent format. 710 */ 711 #pragma pack(1) 712 struct ath_desc { 713 /* 714 * The following definitions are passed directly 715 * the hardware and managed by the HAL. Drivers 716 * should not touch those elements marked opaque. 717 */ 718 uint32_t ds_link; /* phys address of next descriptor */ 719 uint32_t ds_data; /* phys address of data buffer */ 720 uint32_t ds_ctl0; /* opaque DMA control 0 */ 721 uint32_t ds_ctl1; /* opaque DMA control 1 */ 722 uint32_t ds_hw[4]; /* opaque h/w region */ 723 /* 724 * The remaining definitions are managed by software; 725 * these are valid only after the rx/tx process descriptor 726 * methods return a non-EINPROGRESS code. 727 */ 728 union { 729 struct ath_tx_status tx; /* xmit status */ 730 struct ath_rx_status rx; /* recv status */ 731 } ds_us; 732 void *ds_vdata; /* virtual addr of data buffer */ 733 }; 734 #pragma pack() 735 736 #define ds_txstat ds_us.tx 737 #define ds_rxstat ds_us.rx 738 739 /* 740 * Hardware Access Layer (HAL) API. 741 * 742 * Clients of the HAL call ath_hal_attach to obtain a reference to an 743 * ath_hal structure for use with the device. Hardware-related operations 744 * that follow must call back into the HAL through interface, supplying 745 * the reference as the first parameter. Note that before using the 746 * reference returned by ath_hal_attach the caller should verify the 747 * ABI version number. 748 */ 749 struct ath_hal { 750 uint32_t ah_magic; /* consistency check magic number */ 751 uint32_t ah_abi; /* HAL ABI version */ 752 uint16_t ah_devid; /* PCI device ID */ 753 uint16_t ah_subvendorid; /* PCI subvendor ID */ 754 HAL_SOFTC ah_sc; /* back pointer to driver/os state */ 755 HAL_BUS_TAG ah_st; /* params for register r+w */ 756 HAL_BUS_HANDLE ah_sh; 757 HAL_CTRY_CODE ah_countryCode; 758 759 uint32_t ah_macVersion; /* MAC version id */ 760 uint16_t ah_macRev; /* MAC revision */ 761 uint16_t ah_phyRev; /* PHY revision */ 762 /* NB: when only one radio is present the rev is in 5Ghz */ 763 uint16_t ah_analog5GhzRev; /* 5GHz radio revision */ 764 uint16_t ah_analog2GhzRev; /* 2GHz radio revision */ 765 /* decomp mask array */ 766 uint8_t ah_decompMask[HAL_DECOMP_MASK_SIZE]; 767 768 const HAL_RATE_TABLE *(*ah_getRateTable)(struct ath_hal *, 769 uint32_t mode); 770 void (*ah_detach) (struct ath_hal *); 771 772 /* Reset functions */ 773 HAL_BOOL (*ah_reset) (struct ath_hal *, HAL_OPMODE, 774 HAL_CHANNEL *, HAL_BOOL bChannelChange, 775 HAL_STATUS *status); 776 HAL_BOOL (*ah_phyDisable) (struct ath_hal *); 777 HAL_BOOL (*ah_disable) (struct ath_hal *); 778 void (*ah_setPCUConfig) (struct ath_hal *); 779 HAL_BOOL (*ah_perCalibration) (struct ath_hal *, HAL_CHANNEL *, 780 HAL_BOOL *); 781 HAL_BOOL (*ah_setTxPowerLimit)(struct ath_hal *, uint32_t); 782 783 void (*ah_arEnable)(struct ath_hal *); 784 void (*ah_arDisable)(struct ath_hal *); 785 void (*ah_arReset)(struct ath_hal *); 786 HAL_BOOL (*ah_radarHaveEvent)(struct ath_hal *); 787 HAL_BOOL (*ah_processDfs)(struct ath_hal *, HAL_CHANNEL *); 788 uint32_t (*ah_dfsNolCheck)(struct ath_hal *, HAL_CHANNEL *, uint32_t); 789 HAL_BOOL (*ah_radarWait)(struct ath_hal *, HAL_CHANNEL *); 790 791 /* Transmit functions */ 792 HAL_BOOL (*ah_updateTxTrigLevel) (struct ath_hal *, 793 HAL_BOOL incTrigLevel); 794 int (*ah_setupTxQueue) (struct ath_hal *, HAL_TX_QUEUE, 795 const HAL_TXQ_INFO *qInfo); 796 HAL_BOOL (*ah_setTxQueueProps) (struct ath_hal *, int q, 797 const HAL_TXQ_INFO *qInfo); 798 HAL_BOOL (*ah_getTxQueueProps)(struct ath_hal *, int q, 799 HAL_TXQ_INFO *qInfo); 800 HAL_BOOL (*ah_releaseTxQueue) (struct ath_hal *ah, uint32_t q); 801 HAL_BOOL (*ah_resetTxQueue) (struct ath_hal *ah, uint32_t q); 802 uint32_t (*ah_getTxDP) (struct ath_hal *, uint32_t); 803 HAL_BOOL (*ah_setTxDP) (struct ath_hal *, uint32_t, uint32_t txdp); 804 uint32_t (*ah_numTxPending)(struct ath_hal *, uint32_t q); 805 HAL_BOOL (*ah_startTxDma) (struct ath_hal *, uint32_t); 806 HAL_BOOL (*ah_stopTxDma) (struct ath_hal *, uint32_t); 807 HAL_BOOL (*ah_setupTxDesc) (struct ath_hal *, struct ath_desc *, 808 uint32_t pktLen, uint32_t hdrLen, 809 HAL_PKT_TYPE type, uint32_t txPower, 810 uint32_t txRate0, uint32_t txTries0, 811 uint32_t keyIx, uint32_t antMode, 812 uint32_t flags, uint32_t rtsctsRate, 813 uint32_t rtsctsDuration, 814 uint32_t compicvLen, uint32_t compivLen, 815 uint32_t comp); 816 HAL_BOOL (*ah_setupXTxDesc) (struct ath_hal *, struct ath_desc *, 817 uint32_t txRate1, uint32_t txTries1, 818 uint32_t txRate2, uint32_t txTries2, 819 uint32_t txRate3, uint32_t txTries3); 820 HAL_BOOL (*ah_fillTxDesc) (struct ath_hal *, struct ath_desc *, 821 uint32_t segLen, HAL_BOOL firstSeg, 822 HAL_BOOL lastSeg, const struct ath_desc *); 823 HAL_STATUS (*ah_procTxDesc) (struct ath_hal *, struct ath_desc *); 824 void (*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *); 825 void (*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc *); 826 827 /* Receive Functions */ 828 uint32_t (*ah_getRxDP) (struct ath_hal *); 829 void (*ah_setRxDP) (struct ath_hal *, uint32_t rxdp); 830 void (*ah_enableReceive) (struct ath_hal *); 831 HAL_BOOL (*ah_stopDmaReceive) (struct ath_hal *); 832 void (*ah_startPcuReceive) (struct ath_hal *); 833 void (*ah_stopPcuReceive) (struct ath_hal *); 834 void (*ah_setMulticastFilter) (struct ath_hal *, 835 uint32_t filter0, uint32_t filter1); 836 HAL_BOOL (*ah_setMulticastFilterIndex) (struct ath_hal *, 837 uint32_t index); 838 HAL_BOOL (*ah_clrMulticastFilterIndex) (struct ath_hal *, 839 uint32_t index); 840 uint32_t (*ah_getRxFilter) (struct ath_hal *); 841 void (*ah_setRxFilter) (struct ath_hal *, uint32_t); 842 HAL_BOOL (*ah_setupRxDesc) (struct ath_hal *, struct ath_desc *, 843 uint32_t size, uint32_t flags); 844 HAL_STATUS (*ah_procRxDesc) (struct ath_hal *, struct ath_desc *, 845 uint32_t phyAddr, struct ath_desc *next, 846 uint64_t tsf); 847 void (*ah_rxMonitor) (struct ath_hal *, 848 const HAL_NODE_STATS *, HAL_CHANNEL *); 849 void (*ah_procMibEvent) (struct ath_hal *, 850 const HAL_NODE_STATS *); 851 852 /* Misc Functions */ 853 HAL_STATUS (*ah_getCapability) (struct ath_hal *, 854 HAL_CAPABILITY_TYPE, uint32_t capability, 855 uint32_t *result); 856 HAL_BOOL (*ah_setCapability) (struct ath_hal *, 857 HAL_CAPABILITY_TYPE, uint32_t capability, 858 uint32_t setting, HAL_STATUS *); 859 HAL_BOOL (*ah_getDiagState) (struct ath_hal *, int request, 860 const void *args, uint32_t argsize, 861 void **result, uint32_t *resultsize); 862 void (*ah_getMacAddress) (struct ath_hal *, uint8_t *); 863 HAL_BOOL (*ah_setMacAddress) (struct ath_hal *, const uint8_t *); 864 void (*ah_getBssIdMask)(struct ath_hal *, uint8_t *); 865 HAL_BOOL (*ah_setBssIdMask)(struct ath_hal *, const uint8_t *); 866 HAL_BOOL (*ah_setRegulatoryDomain) (struct ath_hal *, 867 uint16_t, HAL_STATUS *); 868 void (*ah_setLedState) (struct ath_hal *, HAL_LED_STATE); 869 void (*ah_writeAssocid) (struct ath_hal *, 870 const uint8_t *bssid, uint16_t assocId); 871 HAL_BOOL (*ah_gpioCfgOutput) (struct ath_hal *, uint32_t gpio); 872 HAL_BOOL (*ah_gpioCfgInput) (struct ath_hal *, uint32_t gpio); 873 uint32_t (*ah_gpioGet) (struct ath_hal *, uint32_t gpio); 874 HAL_BOOL (*ah_gpioSet) (struct ath_hal *, 875 uint32_t gpio, uint32_t val); 876 void (*ah_gpioSetIntr) (struct ath_hal *, uint32_t, uint32_t); 877 uint32_t (*ah_getTsf32) (struct ath_hal *); 878 uint64_t (*ah_getTsf64) (struct ath_hal *); 879 void (*ah_resetTsf) (struct ath_hal *); 880 HAL_BOOL (*ah_detectCardPresent) (struct ath_hal *); 881 void (*ah_updateMibCounters) (struct ath_hal *, HAL_MIB_STATS *); 882 HAL_RFGAIN (*ah_getRfGain) (struct ath_hal *); 883 uint32_t (*ah_getDefAntenna) (struct ath_hal *); 884 void (*ah_setDefAntenna) (struct ath_hal *, uint32_t); 885 HAL_ANT_SETTING (*ah_getAntennaSwitch) (struct ath_hal *); 886 HAL_BOOL (*ah_setAntennaSwitch) (struct ath_hal *, HAL_ANT_SETTING); 887 HAL_BOOL (*ah_setSlotTime) (struct ath_hal *, uint32_t); 888 uint32_t (*ah_getSlotTime) (struct ath_hal *); 889 HAL_BOOL (*ah_setAckTimeout) (struct ath_hal *, uint32_t); 890 uint32_t (*ah_getAckTimeout) (struct ath_hal *); 891 HAL_BOOL (*ah_setAckCTSRate) (struct ath_hal *, uint32_t); 892 uint32_t (*ah_getAckCTSRate) (struct ath_hal *); 893 HAL_BOOL (*ah_setCTSTimeout) (struct ath_hal *, uint32_t); 894 uint32_t (*ah_getCTSTimeout) (struct ath_hal *); 895 HAL_BOOL (*ah_setDecompMask)(struct ath_hal *, uint16_t, int); 896 void (*ah_setCoverageClass)(struct ath_hal *, uint8_t, int); 897 /* Key Cache Functions */ 898 uint32_t (*ah_getKeyCacheSize) (struct ath_hal *); 899 HAL_BOOL (*ah_resetKeyCacheEntry) (struct ath_hal *, uint16_t); 900 HAL_BOOL (*ah_isKeyCacheEntryValid) (struct ath_hal *, uint16_t); 901 HAL_BOOL (*ah_setKeyCacheEntry) (struct ath_hal *, 902 uint16_t, const HAL_KEYVAL *, 903 const uint8_t *, int); 904 HAL_BOOL (*ah_setKeyCacheEntryMac) (struct ath_hal *, 905 uint16_t, const uint8_t *); 906 907 /* Power Management Functions */ 908 HAL_BOOL (*ah_setPowerMode) (struct ath_hal *, 909 HAL_POWER_MODE mode, int setChip); 910 HAL_POWER_MODE (*ah_getPowerMode) (struct ath_hal *); 911 int16_t (*ah_getChanNoise)(struct ath_hal *, HAL_CHANNEL *); 912 913 /* Beacon Management Functions */ 914 void (*ah_setBeaconTimers) (struct ath_hal *, 915 const HAL_BEACON_TIMERS *); 916 /* NB: deprecated, use ah_setBeaconTimers instead */ 917 void (*ah_beaconInit) (struct ath_hal *, 918 uint32_t nexttbtt, uint32_t intval); 919 void (*ah_setStationBeaconTimers) (struct ath_hal *, 920 const HAL_BEACON_STATE *); 921 void (*ah_resetStationBeaconTimers) (struct ath_hal *); 922 923 /* Interrupt functions */ 924 HAL_BOOL (*ah_isInterruptPending) (struct ath_hal *); 925 HAL_BOOL (*ah_getPendingInterrupts) (struct ath_hal *, HAL_INT *); 926 HAL_INT (*ah_getInterrupts) (struct ath_hal *); 927 HAL_INT (*ah_setInterrupts) (struct ath_hal *, HAL_INT); 928 }; 929 930 /* 931 * Check the PCI vendor ID and device ID against Atheros' values 932 * and return a printable description for any Atheros hardware. 933 * AH_NULL is returned if the ID's do not describe Atheros hardware. 934 */ 935 extern const char *ath_hal_probe(uint16_t vendorid, uint16_t devid); 936 937 /* 938 * Attach the HAL for use with the specified device. The device is 939 * defined by the PCI device ID. The caller provides an opaque pointer 940 * to an upper-layer data structure (HAL_SOFTC) that is stored in the 941 * HAL state block for later use. Hardware register accesses are done 942 * using the specified bus tag and handle. On successful return a 943 * reference to a state block is returned that must be supplied in all 944 * subsequent HAL calls. Storage associated with this reference is 945 * dynamically allocated and must be freed by calling the ah_detach 946 * method when the client is done. If the attach operation fails a 947 * null (AH_NULL) reference will be returned and a status code will 948 * be returned if the status parameter is non-zero. 949 */ 950 extern struct ath_hal *ath_hal_attach(uint16_t devid, HAL_SOFTC, 951 HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS *status); 952 953 /* 954 * Set the Vendor ID for Vendor SKU's which can modify the 955 * channel properties returned by ath_hal_init_channels. 956 * Return AH_TRUE if set succeeds 957 */ 958 extern HAL_BOOL ath_hal_setvendor(struct ath_hal *, uint32_t); 959 960 /* 961 * Return a list of channels available for use with the hardware. 962 * The list is based on what the hardware is capable of, the specified 963 * country code, the modeSelect mask, and whether or not outdoor 964 * channels are to be permitted. 965 * 966 * The channel list is returned in the supplied array. maxchans 967 * defines the maximum size of this array. nchans contains the actual 968 * number of channels returned. If a problem occurred or there were 969 * no channels that met the criteria then AH_FALSE is returned. 970 */ 971 extern HAL_BOOL ath_hal_init_channels(struct ath_hal *, 972 HAL_CHANNEL *chans, uint32_t maxchans, uint32_t *nchans, 973 uint8_t *regclassids, uint32_t maxregids, uint32_t *nregids, 974 HAL_CTRY_CODE cc, uint16_t modeSelect, 975 HAL_BOOL enableOutdoor, HAL_BOOL enableExtendedChannels); 976 977 /* 978 * Calibrate noise floor data following a channel scan or similar. 979 * This must be called prior retrieving noise floor data. 980 */ 981 extern void ath_hal_process_noisefloor(struct ath_hal *ah); 982 983 /* 984 * Return bit mask of wireless modes supported by the hardware. 985 */ 986 extern uint32_t ath_hal_getwirelessmodes(struct ath_hal *, HAL_CTRY_CODE); 987 988 /* 989 * Return rate table for specified mode (11a, 11b, 11g, etc). 990 */ 991 extern const HAL_RATE_TABLE * ath_hal_getratetable(struct ath_hal *, 992 uint32_t mode); 993 994 /* 995 * Calculate the transmit duration of a frame. 996 */ 997 extern uint16_t ath_hal_computetxtime(struct ath_hal *, 998 const HAL_RATE_TABLE *rates, uint32_t frameLen, 999 uint16_t rateix, HAL_BOOL shortPreamble); 1000 1001 /* 1002 * Return if device is public safety. 1003 */ 1004 extern HAL_BOOL ath_hal_ispublicsafetysku(struct ath_hal *); 1005 1006 /* 1007 * Convert between IEEE channel number and channel frequency 1008 * using the specified channel flags; e.g. CHANNEL_2GHZ. 1009 */ 1010 extern int ath_hal_mhz2ieee(struct ath_hal *, uint32_t mhz, uint32_t flags); 1011 1012 /* 1013 * Return a version string for the HAL release. 1014 */ 1015 extern char ath_hal_version[]; 1016 1017 /* 1018 * Return a NULL-terminated array of build/configuration options. 1019 */ 1020 extern const char *ath_hal_buildopts[]; 1021 1022 /* 1023 * Macros to encapsulated HAL functions. 1024 */ 1025 #define ATH_HAL_RESET(_ah, _opmode, _chan, _outdoor, _pstatus) \ 1026 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 1027 #define ATH_HAL_PHYDISABLE(_ah) \ 1028 ((*(_ah)->ah_phyDisable)((_ah))) 1029 #define ATH_HAL_GETCAPABILITY(_ah, _cap, _param, _result) \ 1030 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 1031 #define ATH_HAL_SETCAPABILITY(_ah, _type, _cap, _param, _status) \ 1032 ((*ah_setCapability)((_ah), (_type), (_cap), (_param), (_status))) 1033 #define ATH_HAL_GETREGDOMAIN(_ah, _prd) \ 1034 ATH_HAL_GETCAPABILITY(_ah, HAL_CAP_REG_DMN, 0, (_prd)) 1035 #define ATH_HAL_GETCOUNTRYCODE(_ah, _pcc) \ 1036 (*(_pcc) = (_ah)->ah_countryCode) 1037 #define ATH_HAL_GETRATETABLE(_ah, _mode) \ 1038 ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 1039 #define ATH_HAL_GETMAC(_ah, _mac) \ 1040 ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 1041 #define ATH_HAL_SETMAC(_ah, _mac) \ 1042 ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 1043 #define ATH_HAL_INTRSET(_ah, _mask) \ 1044 ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 1045 #define ATH_HAL_INTRGET(_ah) \ 1046 ((*(_ah)->ah_getInterrupts)((_ah))) 1047 #define ATH_HAL_INTRPEND(_ah) \ 1048 ((*(_ah)->ah_isInterruptPending)((_ah))) 1049 #define ATH_HAL_GETISR(_ah, _pmask) \ 1050 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 1051 #define ATH_HAL_UPDATETXTRIGLEVEL(_ah, _inc) \ 1052 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 1053 #define ATH_HAL_SETPOWER(_ah, _mode) \ 1054 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 1055 #define ATH_HAL_KEYRESET(_ah, _ix) \ 1056 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 1057 #define ATH_HAL_KEYSET(_ah, _ix, _pk, _mac) \ 1058 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 1059 #define ATH_HAL_KEYISVALID(_ah, _ix) \ 1060 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 1061 #define ATH_HAL_KEYSETMAC(_ah, _ix, _mac) \ 1062 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 1063 #define ATH_HAL_KEYCACHESIZE(_ah) \ 1064 ((*(_ah)->ah_getKeyCacheSize)((_ah))) 1065 #define ATH_HAL_GETRXFILTER(_ah) \ 1066 ((*(_ah)->ah_getRxFilter)((_ah))) 1067 #define ATH_HAL_SETRXFILTER(_ah, _filter) \ 1068 ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 1069 #define ATH_HAL_SETMCASTFILTER(_ah, _mfilt0, _mfilt1) \ 1070 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 1071 #define ATH_HAL_WAITFORBEACON(_ah, _bf) \ 1072 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 1073 #define ATH_HAL_PUTRXBUF(_ah, _bufaddr) \ 1074 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr))) 1075 #define ATH_HAL_GETTSF32(_ah) \ 1076 ((*(_ah)->ah_getTsf32)((_ah))) 1077 #define ATH_HAL_GETTSF64(_ah) \ 1078 ((*(_ah)->ah_getTsf64)((_ah))) 1079 #define ATH_HAL_RESETTSF(_ah) \ 1080 ((*(_ah)->ah_resetTsf)((_ah))) 1081 #define ATH_HAL_RXENA(_ah) \ 1082 ((*(_ah)->ah_enableReceive)((_ah))) 1083 #define ATH_HAL_PUTTXBUF(_ah, _q, _bufaddr) \ 1084 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 1085 #define ATH_HAL_GETTXBUF(_ah, _q) \ 1086 ((*(_ah)->ah_getTxDP)((_ah), (_q))) 1087 #define ATH_HAL_GETRXBUF(_ah) \ 1088 ((*(_ah)->ah_getRxDP)((_ah))) 1089 #define ATH_HAL_TXSTART(_ah, _q) \ 1090 ((*(_ah)->ah_startTxDma)((_ah), (_q))) 1091 #define ATH_HAL_SETCHANNEL(_ah, _chan) \ 1092 ((*(_ah)->ah_setChannel)((_ah), (_chan))) 1093 #define ATH_HAL_CALIBRATE(_ah, _chan, _iqcal) \ 1094 ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 1095 #define ATH_HAL_SETLEDSTATE(_ah, _state) \ 1096 ((*(_ah)->ah_setLedState)((_ah), (_state))) 1097 #define ATH_HAL_BEACONINIT(_ah, _nextb, _bperiod) \ 1098 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 1099 #define ATH_HAL_BEACONRESET(_ah) \ 1100 ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 1101 #define ATH_HAL_BEACONTIMERS(_ah, _beacon_state) \ 1102 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_beacon_state))) 1103 #define ATH_HAL_SETASSOCID(_ah, _bss, _associd) \ 1104 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 1105 #define ATH_HAL_SETOPMODE(_ah) \ 1106 ((*(_ah)->ah_setPCUConfig)((_ah))) 1107 #define ATH_HAL_STOPTXDMA(_ah, _qnum) \ 1108 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 1109 #define ATH_HAL_STOPPCURECV(_ah) \ 1110 ((*(_ah)->ah_stopPcuReceive)((_ah))) 1111 #define ATH_HAL_STARTPCURECV(_ah) \ 1112 ((*(_ah)->ah_startPcuReceive)((_ah))) 1113 #define ATH_HAL_STOPDMARECV(_ah) \ 1114 ((*(_ah)->ah_stopDmaReceive)((_ah))) 1115 #define ATH_HAL_DUMPSTATE(_ah) \ 1116 ((*(_ah)->ah_dumpState)((_ah))) 1117 #define ATH_HAL_DUMPEEPROM(_ah) \ 1118 ((*(_ah)->ah_dumpEeprom)((_ah))) 1119 #define ATH_HAL_DUMPRFGAIN(_ah) \ 1120 ((*(_ah)->ah_dumpRfGain)((_ah))) 1121 #define ATH_HAL_DUMPANI(_ah) \ 1122 ((*(_ah)->ah_dumpAni)((_ah))) 1123 #define ATH_HAL_SETUPTXQUEUE(_ah, _type, _irq) \ 1124 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 1125 #define ATH_HAL_RESETTXQUEUE(_ah, _q) \ 1126 ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 1127 #define ATH_HAL_RELEASETXQUEUE(_ah, _q) \ 1128 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 1129 #define ATH_HAL_HASVEOL \ 1130 ((*(_ah)->ah_hasVEOL)((_ah))) 1131 #define ATH_HAL_GETRFGAIN(_ah) \ 1132 ((*(_ah)->ah_getRfGain)((_ah))) 1133 #define ATH_HAL_RXMONITOR(_ah, _arg, _chan) \ 1134 ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 1135 #define ATH_HAL_SETSLOTTIME(_ah, _us) \ 1136 ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 1137 #define ATH_HAL_SETUPBEACONDESC(_ah, _ds, _opmode, _flen, _hlen, \ 1138 _rate, _antmode) \ 1139 ((*(_ah)->ah_setupBeaconDesc)((_ah), (_ds), (_opmode), \ 1140 (_flen), (_hlen), (_rate), (_antmode))) 1141 #define ATH_HAL_SETUPRXDESC(_ah, _ds, _size, _intreq) \ 1142 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 1143 #define ATH_HAL_RXPROCDESC(_ah, _ds, _dspa, _dsnext) \ 1144 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0)) 1145 #define ATH_HAL_SETUPTXDESC(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 1146 _txr0, _txtr0, _keyix, _ant, _flags, \ 1147 _rtsrate, _rtsdura) \ 1148 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 1149 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 1150 (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 1151 #define ATH_HAL_SETUPXTXDESC(_ah, _ds, \ 1152 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 1153 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 1154 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 1155 #define ATH_HAL_FILLTXDESC(_ah, _ds, _l, _first, _last, _ath_desc) \ 1156 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), \ 1157 (_ath_desc))) 1158 #define ATH_HAL_TXPROCDESC(_ah, _ds) \ 1159 ((*(_ah)->ah_procTxDesc)((_ah), (_ds))) 1160 #define ATH_HAL_CIPHERSUPPORTED(_ah, _cipher) \ 1161 (ATH_HAL_GETCAPABILITY(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 1162 #define ATH_HAL_TKIPSPLIT(_ah) \ 1163 (ATH_HAL_GETCAPABILITY(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 1164 #define ATH_HAL_HASRFSILENT(ah) \ 1165 (ATH_HAL_GETCAPABILITY(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 1166 #define ATH_HAL_GETRFKILL(_ah) \ 1167 (ATH_HAL_GETCAPABILITY(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 1168 #define ATH_HAL_SETRFKILL(_ah, _onoff) \ 1169 (ATH_HAL_SETCAPABILITY(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL)) 1170 #define ATH_HAL_GETRFSILENT(_ah, _prfsilent) \ 1171 (ATH_HAL_GETCAPABILITY(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 1172 #define ATH_HAL_SETRFSILENT(_ah, _rfsilent) \ 1173 (ATH_HAL_SETCAPABILITY(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL)) 1174 1175 #if HAL_ABI_VERSION < 0x05120700 1176 #define ATH_HAL_PROCESS_NOISEFLOOR(_ah) 1177 #define ATH_HAL_GETCHANNOISE(_ah, _c) (-96) 1178 #define HAL_CAP_TPC_ACK 100 1179 #define HAL_CAP_TPC_CTS 101 1180 #else 1181 #define ATH_HAL_GETCHANNOISE(_ah, _c) \ 1182 ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 1183 #endif 1184 1185 #if HAL_ABI_VERSION < 0x05122200 1186 #define HAL_TXQ_TXOKINT_ENABLE TXQ_FLAG_TXOKINT_ENABLE 1187 #define HAL_TXQ_TXERRINT_ENABLE TXQ_FLAG_TXERRINT_ENABLE 1188 #define HAL_TXQ_TXDESCINT_ENABLE TXQ_FLAG_TXDESCINT_ENABLE 1189 #define HAL_TXQ_TXEOLINT_ENABLE TXQ_FLAG_TXEOLINT_ENABLE 1190 #define HAL_TXQ_TXURNINT_ENABLE TXQ_FLAG_TXURNINT_ENABLE 1191 #endif 1192 1193 #ifdef __cplusplus 1194 } 1195 #endif 1196 1197 #endif /* _ATH_HAL_H */ 1198