1 /* 2 * Solaris driver for ethernet cards based on the ADMtek Centaur 3 * 4 * Copyright (c) 2007 by Garrett D'Amore <garrett@damore.org>. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of the author nor the names of any co-contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS ``AS IS'' 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /* 32 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 33 * Use is subject to license terms. 34 */ 35 36 37 #include <sys/varargs.h> 38 #include <sys/types.h> 39 #include <sys/modctl.h> 40 #include <sys/conf.h> 41 #include <sys/devops.h> 42 #include <sys/stream.h> 43 #include <sys/strsun.h> 44 #include <sys/cmn_err.h> 45 #include <sys/ethernet.h> 46 #include <sys/kmem.h> 47 #include <sys/time.h> 48 #include <sys/crc32.h> 49 #include <sys/miiregs.h> 50 #include <sys/mac.h> 51 #include <sys/mac_ether.h> 52 #include <sys/ddi.h> 53 #include <sys/sunddi.h> 54 #include <sys/vlan.h> 55 56 #include "afe.h" 57 #include "afeimpl.h" 58 59 /* 60 * Driver globals. 61 */ 62 63 /* patchable debug flag ... must not be static! */ 64 #ifdef DEBUG 65 unsigned afe_debug = DWARN; 66 #endif 67 68 /* table of supported devices */ 69 static afe_card_t afe_cards[] = { 70 71 /* 72 * ADMtek Centaur and Comet 73 */ 74 { 0x1317, 0x0981, "ADMtek AL981", MODEL_COMET }, 75 { 0x1317, 0x0985, "ADMtek AN983", MODEL_CENTAUR }, 76 { 0x1317, 0x1985, "ADMtek AN985", MODEL_CENTAUR }, 77 { 0x1317, 0x9511, "ADMtek ADM9511", MODEL_CENTAUR }, 78 { 0x1317, 0x9513, "ADMtek ADM9513", MODEL_CENTAUR }, 79 /* 80 * Accton just relabels other companies' controllers 81 */ 82 { 0x1113, 0x1216, "Accton EN5251", MODEL_CENTAUR }, 83 /* 84 * Models listed here. 85 */ 86 { 0x10b7, 0x9300, "3Com 3CSOHO100B-TX", MODEL_CENTAUR }, 87 { 0x1113, 0xec02, "SMC SMC1244TX", MODEL_CENTAUR }, 88 { 0x10b8, 0x1255, "SMC SMC1255TX", MODEL_CENTAUR }, 89 { 0x111a, 0x1020, "Siemens SpeedStream PCI 10/100", MODEL_CENTAUR }, 90 { 0x1113, 0x1207, "Accton EN1207F", MODEL_CENTAUR }, 91 { 0x1113, 0x2242, "Accton EN2242", MODEL_CENTAUR }, 92 { 0x1113, 0x2220, "Accton EN2220", MODEL_CENTAUR }, 93 { 0x1113, 0x9216, "3M VOL-N100VF+TX", MODEL_CENTAUR }, 94 { 0x1317, 0x0574, "Linksys LNE100TX", MODEL_CENTAUR }, 95 { 0x1317, 0x0570, "Linksys NC100", MODEL_CENTAUR }, 96 { 0x1385, 0x511a, "Netgear FA511", MODEL_CENTAUR }, 97 { 0x13d1, 0xab02, "AboCom FE2500", MODEL_CENTAUR }, 98 { 0x13d1, 0xab03, "AboCom PCM200", MODEL_CENTAUR }, 99 { 0x13d1, 0xab08, "AboCom FE2500MX", MODEL_CENTAUR }, 100 { 0x1414, 0x0001, "Microsoft MN-120", MODEL_CENTAUR }, 101 { 0x16ec, 0x00ed, "U.S. Robotics USR997900", MODEL_CENTAUR }, 102 { 0x1734, 0x100c, "Fujitsu-Siemens D1961", MODEL_CENTAUR }, 103 { 0x1737, 0xab08, "Linksys PCMPC200", MODEL_CENTAUR }, 104 { 0x1737, 0xab09, "Linksys PCM200", MODEL_CENTAUR }, 105 { 0x17b3, 0xab08, "Hawking PN672TX", MODEL_CENTAUR }, 106 }; 107 108 #define ETHERVLANMTU (ETHERMAX + 4) 109 110 /* 111 * Function prototypes 112 */ 113 static int afe_attach(dev_info_t *, ddi_attach_cmd_t); 114 static int afe_detach(dev_info_t *, ddi_detach_cmd_t); 115 static int afe_resume(dev_info_t *); 116 static int afe_quiesce(dev_info_t *); 117 static int afe_m_unicst(void *, const uint8_t *); 118 static int afe_m_multicst(void *, boolean_t, const uint8_t *); 119 static int afe_m_promisc(void *, boolean_t); 120 static mblk_t *afe_m_tx(void *, mblk_t *); 121 static int afe_m_stat(void *, uint_t, uint64_t *); 122 static int afe_m_start(void *); 123 static void afe_m_stop(void *); 124 static int afe_m_getprop(void *, const char *, mac_prop_id_t, uint_t, 125 uint_t, void *, uint_t *); 126 static int afe_m_setprop(void *, const char *, mac_prop_id_t, uint_t, 127 const void *); 128 static unsigned afe_intr(caddr_t); 129 static void afe_startmac(afe_t *); 130 static void afe_stopmac(afe_t *); 131 static void afe_resetrings(afe_t *); 132 static boolean_t afe_initialize(afe_t *); 133 static void afe_startall(afe_t *); 134 static void afe_stopall(afe_t *); 135 static void afe_resetall(afe_t *); 136 static afe_txbuf_t *afe_alloctxbuf(afe_t *); 137 static void afe_destroytxbuf(afe_txbuf_t *); 138 static afe_rxbuf_t *afe_allocrxbuf(afe_t *); 139 static void afe_destroyrxbuf(afe_rxbuf_t *); 140 static boolean_t afe_send(afe_t *, mblk_t *); 141 static int afe_allocrxring(afe_t *); 142 static void afe_freerxring(afe_t *); 143 static int afe_alloctxring(afe_t *); 144 static void afe_freetxring(afe_t *); 145 static void afe_error(dev_info_t *, char *, ...); 146 static void afe_setrxfilt(afe_t *); 147 static uint8_t afe_sromwidth(afe_t *); 148 static uint16_t afe_readsromword(afe_t *, unsigned); 149 static void afe_readsrom(afe_t *, unsigned, unsigned, char *); 150 static void afe_getfactaddr(afe_t *, uchar_t *); 151 static uint8_t afe_miireadbit(afe_t *); 152 static void afe_miiwritebit(afe_t *, uint8_t); 153 static void afe_miitristate(afe_t *); 154 static uint16_t afe_miiread(afe_t *, int, int); 155 static void afe_miiwrite(afe_t *, int, int, uint16_t); 156 static uint16_t afe_miireadgeneral(afe_t *, int, int); 157 static void afe_miiwritegeneral(afe_t *, int, int, uint16_t); 158 static uint16_t afe_miireadcomet(afe_t *, int, int); 159 static void afe_miiwritecomet(afe_t *, int, int, uint16_t); 160 static int afe_getmiibit(afe_t *, uint16_t, uint16_t); 161 static void afe_startphy(afe_t *); 162 static void afe_stopphy(afe_t *); 163 static void afe_reportlink(afe_t *); 164 static void afe_checklink(afe_t *); 165 static void afe_checklinkcomet(afe_t *); 166 static void afe_checklinkcentaur(afe_t *); 167 static void afe_checklinkmii(afe_t *); 168 static void afe_disableinterrupts(afe_t *); 169 static void afe_enableinterrupts(afe_t *); 170 static void afe_reclaim(afe_t *); 171 static mblk_t *afe_receive(afe_t *); 172 173 #ifdef DEBUG 174 static void afe_dprintf(afe_t *, const char *, int, char *, ...); 175 #endif 176 177 #define KIOIP KSTAT_INTR_PTR(afep->afe_intrstat) 178 179 static mac_callbacks_t afe_m_callbacks = { 180 MC_SETPROP | MC_GETPROP, 181 afe_m_stat, 182 afe_m_start, 183 afe_m_stop, 184 afe_m_promisc, 185 afe_m_multicst, 186 afe_m_unicst, 187 afe_m_tx, 188 NULL, /* mc_ioctl */ 189 NULL, /* mc_getcapab */ 190 NULL, /* mc_open */ 191 NULL, /* mc_close */ 192 afe_m_setprop, 193 afe_m_getprop, 194 }; 195 196 197 /* 198 * Stream information 199 */ 200 DDI_DEFINE_STREAM_OPS(afe_devops, nulldev, nulldev, afe_attach, afe_detach, 201 nodev, NULL, D_MP, NULL, afe_quiesce); 202 203 /* 204 * Module linkage information. 205 */ 206 207 static struct modldrv afe_modldrv = { 208 &mod_driverops, /* drv_modops */ 209 "ADMtek Fast Ethernet", /* drv_linkinfo */ 210 &afe_devops /* drv_dev_ops */ 211 }; 212 213 static struct modlinkage afe_modlinkage = { 214 MODREV_1, /* ml_rev */ 215 { &afe_modldrv, NULL } /* ml_linkage */ 216 }; 217 218 /* 219 * Device attributes. 220 */ 221 static ddi_device_acc_attr_t afe_devattr = { 222 DDI_DEVICE_ATTR_V0, 223 DDI_STRUCTURE_LE_ACC, 224 DDI_STRICTORDER_ACC 225 }; 226 227 static ddi_device_acc_attr_t afe_bufattr = { 228 DDI_DEVICE_ATTR_V0, 229 DDI_NEVERSWAP_ACC, 230 DDI_STRICTORDER_ACC 231 }; 232 233 static ddi_dma_attr_t afe_dma_attr = { 234 DMA_ATTR_V0, /* dma_attr_version */ 235 0, /* dma_attr_addr_lo */ 236 0xFFFFFFFFU, /* dma_attr_addr_hi */ 237 0x7FFFFFFFU, /* dma_attr_count_max */ 238 4, /* dma_attr_align */ 239 0x3F, /* dma_attr_burstsizes */ 240 1, /* dma_attr_minxfer */ 241 0xFFFFFFFFU, /* dma_attr_maxxfer */ 242 0xFFFFFFFFU, /* dma_attr_seg */ 243 1, /* dma_attr_sgllen */ 244 1, /* dma_attr_granular */ 245 0 /* dma_attr_flags */ 246 }; 247 248 /* 249 * Tx buffers can be arbitrarily aligned. Additionally, they can 250 * cross a page boundary, so we use the two buffer addresses of the 251 * chip to provide a two-entry scatter-gather list. 252 */ 253 static ddi_dma_attr_t afe_dma_txattr = { 254 DMA_ATTR_V0, /* dma_attr_version */ 255 0, /* dma_attr_addr_lo */ 256 0xFFFFFFFFU, /* dma_attr_addr_hi */ 257 0x7FFFFFFFU, /* dma_attr_count_max */ 258 1, /* dma_attr_align */ 259 0x3F, /* dma_attr_burstsizes */ 260 1, /* dma_attr_minxfer */ 261 0xFFFFFFFFU, /* dma_attr_maxxfer */ 262 0xFFFFFFFFU, /* dma_attr_seg */ 263 2, /* dma_attr_sgllen */ 264 1, /* dma_attr_granular */ 265 0 /* dma_attr_flags */ 266 }; 267 268 /* 269 * Ethernet addresses. 270 */ 271 static uchar_t afe_broadcast[ETHERADDRL] = { 272 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 273 }; 274 275 /* 276 * DDI entry points. 277 */ 278 int 279 _init(void) 280 { 281 int rv; 282 mac_init_ops(&afe_devops, "afe"); 283 if ((rv = mod_install(&afe_modlinkage)) != DDI_SUCCESS) { 284 mac_fini_ops(&afe_devops); 285 } 286 return (rv); 287 } 288 289 int 290 _fini(void) 291 { 292 int rv; 293 if ((rv = mod_remove(&afe_modlinkage)) == DDI_SUCCESS) { 294 mac_fini_ops(&afe_devops); 295 } 296 return (rv); 297 } 298 299 int 300 _info(struct modinfo *modinfop) 301 { 302 return (mod_info(&afe_modlinkage, modinfop)); 303 } 304 305 int 306 afe_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 307 { 308 afe_t *afep; 309 mac_register_t *macp; 310 int inst = ddi_get_instance(dip); 311 ddi_acc_handle_t pci; 312 uint16_t venid; 313 uint16_t devid; 314 uint16_t svid; 315 uint16_t ssid; 316 uint16_t cachesize; 317 afe_card_t *cardp; 318 int i; 319 320 switch (cmd) { 321 case DDI_RESUME: 322 return (afe_resume(dip)); 323 324 case DDI_ATTACH: 325 break; 326 327 default: 328 return (DDI_FAILURE); 329 } 330 331 /* this card is a bus master, reject any slave-only slot */ 332 if (ddi_slaveonly(dip) == DDI_SUCCESS) { 333 afe_error(dip, "slot does not support PCI bus-master"); 334 return (DDI_FAILURE); 335 } 336 /* PCI devices shouldn't generate hilevel interrupts */ 337 if (ddi_intr_hilevel(dip, 0) != 0) { 338 afe_error(dip, "hilevel interrupts not supported"); 339 return (DDI_FAILURE); 340 } 341 if (pci_config_setup(dip, &pci) != DDI_SUCCESS) { 342 afe_error(dip, "unable to setup PCI config handle"); 343 return (DDI_FAILURE); 344 } 345 346 venid = pci_config_get16(pci, PCI_VID); 347 devid = pci_config_get16(pci, PCI_DID); 348 svid = pci_config_get16(pci, PCI_SVID); 349 ssid = pci_config_get16(pci, PCI_SSID); 350 351 /* 352 * Note: ADMtek boards seem to misprogram themselves with bogus 353 * timings, which do not seem to work properly on SPARC. We 354 * reprogram them zero (but only if they appear to be broken), 355 * which seems to at least work. Its unclear that this is a 356 * legal or wise practice to me, but it certainly works better 357 * than the original values. (I would love to hear 358 * suggestions for better values, or a better strategy.) 359 */ 360 if ((pci_config_get8(pci, PCI_MINGNT) == 0xff) && 361 (pci_config_get8(pci, PCI_MAXLAT) == 0xff)) { 362 pci_config_put8(pci, PCI_MINGNT, 0); 363 pci_config_put8(pci, PCI_MAXLAT, 0); 364 } 365 366 /* 367 * the last entry in the card table matches every possible 368 * card, so the for-loop always terminates properly. 369 */ 370 cardp = NULL; 371 for (i = 0; i < (sizeof (afe_cards) / sizeof (afe_card_t)); i++) { 372 if ((venid == afe_cards[i].card_venid) && 373 (devid == afe_cards[i].card_devid)) { 374 cardp = &afe_cards[i]; 375 } 376 if ((svid == afe_cards[i].card_venid) && 377 (ssid == afe_cards[i].card_devid)) { 378 cardp = &afe_cards[i]; 379 break; 380 } 381 } 382 383 if (cardp == NULL) { 384 pci_config_teardown(&pci); 385 afe_error(dip, "Unable to identify PCI card"); 386 return (DDI_FAILURE); 387 } 388 389 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 390 cardp->card_cardname) != DDI_PROP_SUCCESS) { 391 pci_config_teardown(&pci); 392 afe_error(dip, "Unable to create model property"); 393 return (DDI_FAILURE); 394 } 395 396 /* 397 * Grab the PCI cachesize -- we use this to program the 398 * cache-optimization bus access bits. 399 */ 400 cachesize = pci_config_get8(pci, PCI_CLS); 401 402 /* this cannot fail */ 403 afep = kmem_zalloc(sizeof (afe_t), KM_SLEEP); 404 ddi_set_driver_private(dip, afep); 405 406 /* get the interrupt block cookie */ 407 if (ddi_get_iblock_cookie(dip, 0, &afep->afe_icookie) != DDI_SUCCESS) { 408 afe_error(dip, "ddi_get_iblock_cookie failed"); 409 pci_config_teardown(&pci); 410 kmem_free(afep, sizeof (afe_t)); 411 return (DDI_FAILURE); 412 } 413 414 afep->afe_dip = dip; 415 afep->afe_cardp = cardp; 416 afep->afe_phyaddr = -1; 417 afep->afe_cachesize = cachesize; 418 419 /* default properties */ 420 afep->afe_adv_aneg = !!ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0, 421 "adv_autoneg_cap", 1); 422 afep->afe_adv_100T4 = !!ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0, 423 "adv_100T4_cap", 1); 424 afep->afe_adv_100fdx = !!ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0, 425 "adv_100fdx_cap", 1); 426 afep->afe_adv_100hdx = !!ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0, 427 "adv_100hdx_cap", 1); 428 afep->afe_adv_10fdx = !!ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0, 429 "adv_10fdx_cap", 1); 430 afep->afe_adv_10hdx = !!ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0, 431 "adv_10hdx_cap", 1); 432 433 afep->afe_forcefiber = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0, 434 "fiber", 0); 435 436 DBG(DPCI, "PCI vendor id = %x", venid); 437 DBG(DPCI, "PCI device id = %x", devid); 438 DBG(DPCI, "PCI cachesize = %d", cachesize); 439 DBG(DPCI, "PCI COMM = %x", pci_config_get8(pci, PCI_CMD)); 440 DBG(DPCI, "PCI STAT = %x", pci_config_get8(pci, PCI_STAT)); 441 442 mutex_init(&afep->afe_xmtlock, NULL, MUTEX_DRIVER, afep->afe_icookie); 443 mutex_init(&afep->afe_intrlock, NULL, MUTEX_DRIVER, afep->afe_icookie); 444 445 /* 446 * Enable bus master, IO space, and memory space accesses. 447 */ 448 pci_config_put16(pci, PCI_CMD, 449 pci_config_get16(pci, PCI_CMD) | PCI_CMD_BME | PCI_CMD_MAE); 450 451 /* we're done with this now, drop it */ 452 pci_config_teardown(&pci); 453 454 /* 455 * Initialize interrupt kstat. This should not normally fail, since 456 * we don't use a persistent stat. We do it this way to avoid having 457 * to test for it at run time on the hot path. 458 */ 459 afep->afe_intrstat = kstat_create("afe", inst, "intr", "controller", 460 KSTAT_TYPE_INTR, 1, 0); 461 if (afep->afe_intrstat == NULL) { 462 afe_error(dip, "kstat_create failed"); 463 goto failed; 464 } 465 kstat_install(afep->afe_intrstat); 466 467 /* 468 * Map in the device registers. 469 */ 470 if (ddi_regs_map_setup(dip, 1, (caddr_t *)&afep->afe_regs, 471 0, 0, &afe_devattr, &afep->afe_regshandle)) { 472 afe_error(dip, "ddi_regs_map_setup failed"); 473 goto failed; 474 } 475 476 /* 477 * Allocate DMA resources (descriptor rings and buffers). 478 */ 479 if ((afe_allocrxring(afep) != DDI_SUCCESS) || 480 (afe_alloctxring(afep) != DDI_SUCCESS)) { 481 afe_error(dip, "unable to allocate DMA resources"); 482 goto failed; 483 } 484 485 /* Initialize the chip. */ 486 mutex_enter(&afep->afe_intrlock); 487 mutex_enter(&afep->afe_xmtlock); 488 if (!afe_initialize(afep)) { 489 mutex_exit(&afep->afe_xmtlock); 490 mutex_exit(&afep->afe_intrlock); 491 goto failed; 492 } 493 mutex_exit(&afep->afe_xmtlock); 494 mutex_exit(&afep->afe_intrlock); 495 496 /* Determine the number of address bits to our EEPROM. */ 497 afep->afe_sromwidth = afe_sromwidth(afep); 498 499 /* 500 * Get the factory ethernet address. This becomes the current 501 * ethernet address (it can be overridden later via ifconfig). 502 */ 503 afe_getfactaddr(afep, afep->afe_curraddr); 504 afep->afe_promisc = B_FALSE; 505 506 /* make sure we add configure the initial filter */ 507 (void) afe_m_unicst(afep, afep->afe_curraddr); 508 (void) afe_m_multicst(afep, B_TRUE, afe_broadcast); 509 510 /* 511 * Establish interrupt handler. 512 */ 513 if (ddi_add_intr(dip, 0, NULL, NULL, afe_intr, (caddr_t)afep) != 514 DDI_SUCCESS) { 515 afe_error(dip, "unable to add interrupt"); 516 goto failed; 517 } 518 519 /* TODO: do the power management stuff */ 520 521 if ((macp = mac_alloc(MAC_VERSION)) == NULL) { 522 afe_error(dip, "mac_alloc failed"); 523 goto failed; 524 } 525 526 macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 527 macp->m_driver = afep; 528 macp->m_dip = dip; 529 macp->m_src_addr = afep->afe_curraddr; 530 macp->m_callbacks = &afe_m_callbacks; 531 macp->m_min_sdu = 0; 532 macp->m_max_sdu = ETHERMTU; 533 macp->m_margin = VLAN_TAGSZ; 534 535 if (mac_register(macp, &afep->afe_mh) == DDI_SUCCESS) { 536 mac_free(macp); 537 return (DDI_SUCCESS); 538 } 539 540 /* failed to register with MAC */ 541 mac_free(macp); 542 failed: 543 if (afep->afe_icookie != NULL) { 544 ddi_remove_intr(dip, 0, afep->afe_icookie); 545 } 546 if (afep->afe_intrstat) { 547 kstat_delete(afep->afe_intrstat); 548 } 549 mutex_destroy(&afep->afe_intrlock); 550 mutex_destroy(&afep->afe_xmtlock); 551 552 afe_freerxring(afep); 553 afe_freetxring(afep); 554 555 if (afep->afe_regshandle != NULL) { 556 ddi_regs_map_free(&afep->afe_regshandle); 557 } 558 kmem_free(afep, sizeof (afe_t)); 559 return (DDI_FAILURE); 560 } 561 562 int 563 afe_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 564 { 565 afe_t *afep; 566 567 afep = ddi_get_driver_private(dip); 568 if (afep == NULL) { 569 afe_error(dip, "no soft state in detach!"); 570 return (DDI_FAILURE); 571 } 572 573 switch (cmd) { 574 case DDI_DETACH: 575 576 if (mac_unregister(afep->afe_mh) != 0) { 577 return (DDI_FAILURE); 578 } 579 580 /* make sure hardware is quiesced */ 581 mutex_enter(&afep->afe_intrlock); 582 mutex_enter(&afep->afe_xmtlock); 583 afep->afe_flags &= ~AFE_RUNNING; 584 afe_stopall(afep); 585 mutex_exit(&afep->afe_xmtlock); 586 mutex_exit(&afep->afe_intrlock); 587 588 /* clean up and shut down device */ 589 ddi_remove_intr(dip, 0, afep->afe_icookie); 590 591 /* clean up kstats */ 592 kstat_delete(afep->afe_intrstat); 593 594 ddi_prop_remove_all(dip); 595 596 /* free up any left over buffers or DMA resources */ 597 afe_freerxring(afep); 598 afe_freetxring(afep); 599 600 ddi_regs_map_free(&afep->afe_regshandle); 601 mutex_destroy(&afep->afe_intrlock); 602 mutex_destroy(&afep->afe_xmtlock); 603 604 kmem_free(afep, sizeof (afe_t)); 605 return (DDI_SUCCESS); 606 607 case DDI_SUSPEND: 608 /* quiesce the hardware */ 609 mutex_enter(&afep->afe_intrlock); 610 mutex_enter(&afep->afe_xmtlock); 611 afep->afe_flags |= AFE_SUSPENDED; 612 afe_stopall(afep); 613 mutex_exit(&afep->afe_xmtlock); 614 mutex_exit(&afep->afe_intrlock); 615 return (DDI_SUCCESS); 616 default: 617 return (DDI_FAILURE); 618 } 619 } 620 621 int 622 afe_resume(dev_info_t *dip) 623 { 624 afe_t *afep; 625 626 if ((afep = ddi_get_driver_private(dip)) == NULL) { 627 return (DDI_FAILURE); 628 } 629 630 mutex_enter(&afep->afe_intrlock); 631 mutex_enter(&afep->afe_xmtlock); 632 633 afep->afe_flags &= ~AFE_SUSPENDED; 634 635 /* re-initialize chip */ 636 if (!afe_initialize(afep)) { 637 afe_error(afep->afe_dip, "unable to resume chip!"); 638 afep->afe_flags |= AFE_SUSPENDED; 639 mutex_exit(&afep->afe_intrlock); 640 mutex_exit(&afep->afe_xmtlock); 641 return (DDI_SUCCESS); 642 } 643 644 /* start the chip */ 645 if (afep->afe_flags & AFE_RUNNING) { 646 afe_startall(afep); 647 } 648 649 /* drop locks */ 650 mutex_exit(&afep->afe_xmtlock); 651 mutex_exit(&afep->afe_intrlock); 652 653 return (DDI_SUCCESS); 654 } 655 656 int 657 afe_quiesce(dev_info_t *dip) 658 { 659 afe_t *afep; 660 661 if ((afep = ddi_get_driver_private(dip)) == NULL) { 662 return (DDI_FAILURE); 663 } 664 665 SETBIT(afep, CSR_PAR, PAR_RESET); 666 /* 667 * At 66 MHz it is 16 nsec per access or more (always more) 668 * So we need 3,333 times to retry for 50 usec. We just 669 * round up to 5000 times. Unless the hardware is horked, 670 * it will always terminate *well* before that anyway. 671 */ 672 for (int i = 0; i < 5000; i++) { 673 if ((GETCSR(afep, CSR_PAR) & PAR_RESET) == 0) { 674 return (DDI_SUCCESS); 675 } 676 } 677 678 /* hardware didn't quiesce - force a full reboot (PCI reset) */ 679 return (DDI_FAILURE); 680 } 681 682 void 683 afe_setrxfilt(afe_t *afep) 684 { 685 unsigned rxen, pa0, pa1; 686 687 if (afep->afe_flags & AFE_SUSPENDED) { 688 /* don't touch a suspended interface */ 689 return; 690 } 691 692 rxen = GETCSR(afep, CSR_NAR) & NAR_RX_ENABLE; 693 694 /* stop receiver */ 695 if (rxen) { 696 afe_stopmac(afep); 697 } 698 699 /* program promiscuous mode */ 700 if (afep->afe_promisc) 701 SETBIT(afep, CSR_NAR, NAR_RX_PROMISC); 702 else 703 CLRBIT(afep, CSR_NAR, NAR_RX_PROMISC); 704 705 /* program mac address */ 706 pa0 = (afep->afe_curraddr[3] << 24) | (afep->afe_curraddr[2] << 16) | 707 (afep->afe_curraddr[1] << 8) | afep->afe_curraddr[0]; 708 pa1 = (afep->afe_curraddr[5] << 8) | afep->afe_curraddr[4]; 709 710 DBG(DMACID, "programming PAR0 with %x", pa0); 711 DBG(DMACID, "programming PAR1 with %x", pa1); 712 PUTCSR(afep, CSR_PAR0, pa0); 713 PUTCSR(afep, CSR_PAR1, pa1); 714 if (rxen) { 715 SETBIT(afep, CSR_NAR, rxen); 716 } 717 718 DBG(DMACID, "programming MAR0 = %x", afep->afe_mctab[0]); 719 DBG(DMACID, "programming MAR1 = %x", afep->afe_mctab[1]); 720 721 /* program multicast filter */ 722 if (AFE_MODEL(afep) == MODEL_COMET) { 723 if (afep->afe_mctab[0] || afep->afe_mctab[1]) { 724 SETBIT(afep, CSR_NAR, NAR_RX_MULTI); 725 } else { 726 CLRBIT(afep, CSR_NAR, NAR_RX_MULTI); 727 } 728 } else { 729 CLRBIT(afep, CSR_NAR, NAR_RX_MULTI); 730 PUTCSR(afep, CSR_MAR0, afep->afe_mctab[0]); 731 PUTCSR(afep, CSR_MAR1, afep->afe_mctab[1]); 732 } 733 734 /* restart receiver */ 735 if (rxen) { 736 afe_startmac(afep); 737 } 738 } 739 740 int 741 afe_m_multicst(void *arg, boolean_t add, const uint8_t *macaddr) 742 { 743 afe_t *afep = arg; 744 int index; 745 uint32_t crc; 746 uint32_t bit; 747 uint32_t newval, oldval; 748 749 CRC32(crc, macaddr, ETHERADDRL, -1U, crc32_table); 750 crc %= AFE_MCHASH; 751 752 /* bit within a 32-bit word */ 753 index = crc / 32; 754 bit = (1 << (crc % 32)); 755 756 mutex_enter(&afep->afe_intrlock); 757 mutex_enter(&afep->afe_xmtlock); 758 newval = oldval = afep->afe_mctab[index]; 759 760 if (add) { 761 afep->afe_mccount[crc]++; 762 if (afep->afe_mccount[crc] == 1) 763 newval |= bit; 764 } else { 765 afep->afe_mccount[crc]--; 766 if (afep->afe_mccount[crc] == 0) 767 newval &= ~bit; 768 } 769 if (newval != oldval) { 770 afep->afe_mctab[index] = newval; 771 afe_setrxfilt(afep); 772 } 773 774 mutex_exit(&afep->afe_xmtlock); 775 mutex_exit(&afep->afe_intrlock); 776 777 return (0); 778 } 779 780 int 781 afe_m_promisc(void *arg, boolean_t on) 782 { 783 afe_t *afep = arg; 784 785 /* exclusive access to the card while we reprogram it */ 786 mutex_enter(&afep->afe_intrlock); 787 mutex_enter(&afep->afe_xmtlock); 788 /* save current promiscuous mode state for replay in resume */ 789 afep->afe_promisc = on; 790 791 afe_setrxfilt(afep); 792 mutex_exit(&afep->afe_xmtlock); 793 mutex_exit(&afep->afe_intrlock); 794 795 return (0); 796 } 797 798 int 799 afe_m_unicst(void *arg, const uint8_t *macaddr) 800 { 801 afe_t *afep = arg; 802 803 /* exclusive access to the card while we reprogram it */ 804 mutex_enter(&afep->afe_intrlock); 805 mutex_enter(&afep->afe_xmtlock); 806 807 bcopy(macaddr, afep->afe_curraddr, ETHERADDRL); 808 afe_setrxfilt(afep); 809 810 mutex_exit(&afep->afe_xmtlock); 811 mutex_exit(&afep->afe_intrlock); 812 813 return (0); 814 } 815 816 mblk_t * 817 afe_m_tx(void *arg, mblk_t *mp) 818 { 819 afe_t *afep = arg; 820 mblk_t *nmp; 821 822 mutex_enter(&afep->afe_xmtlock); 823 824 if (afep->afe_flags & AFE_SUSPENDED) { 825 while ((nmp = mp) != NULL) { 826 afep->afe_carrier_errors++; 827 mp = mp->b_next; 828 freemsg(nmp); 829 } 830 mutex_exit(&afep->afe_xmtlock); 831 return (NULL); 832 } 833 834 while (mp != NULL) { 835 nmp = mp->b_next; 836 mp->b_next = NULL; 837 838 if (!afe_send(afep, mp)) { 839 mp->b_next = nmp; 840 break; 841 } 842 mp = nmp; 843 } 844 mutex_exit(&afep->afe_xmtlock); 845 846 return (mp); 847 } 848 849 /* 850 * Hardware management. 851 */ 852 static boolean_t 853 afe_initialize(afe_t *afep) 854 { 855 int i; 856 unsigned val; 857 uint32_t par, nar; 858 859 ASSERT(mutex_owned(&afep->afe_intrlock)); 860 ASSERT(mutex_owned(&afep->afe_xmtlock)); 861 862 DBG(DCHATTY, "resetting!"); 863 SETBIT(afep, CSR_PAR, PAR_RESET); 864 for (i = 1; i < 10; i++) { 865 drv_usecwait(5); 866 val = GETCSR(afep, CSR_PAR); 867 if (!(val & PAR_RESET)) { 868 break; 869 } 870 } 871 if (i == 10) { 872 afe_error(afep->afe_dip, "timed out waiting for reset!"); 873 return (B_FALSE); 874 } 875 876 /* 877 * Updated Centaur data sheets show that the Comet and Centaur are 878 * alike here (contrary to earlier versions of the data sheet). 879 */ 880 /* XXX:? chip problems */ 881 /* par = PAR_MRLE | PAR_MRME | PAR_MWIE; */ 882 par = 0; 883 switch (afep->afe_cachesize) { 884 case 8: 885 par |= PAR_CALIGN_8 | PAR_BURST_8; 886 break; 887 case 16: 888 par |= PAR_CALIGN_16 | PAR_BURST_16; 889 break; 890 case 32: 891 par |= PAR_CALIGN_32 | PAR_BURST_32; 892 break; 893 default: 894 par |= PAR_BURST_32; 895 par &= ~(PAR_MWIE | PAR_MRLE | PAR_MRME); 896 break; 897 898 } 899 900 PUTCSR(afep, CSR_PAR, par); 901 902 /* enable transmit underrun auto-recovery */ 903 SETBIT(afep, CSR_CR, CR_TXURAUTOR); 904 905 afe_resetrings(afep); 906 907 /* clear the lost packet counter (cleared on read) */ 908 (void) GETCSR(afep, CSR_LPC); 909 910 nar = GETCSR(afep, CSR_NAR); 911 nar &= ~NAR_TR; /* clear tx threshold */ 912 nar |= NAR_SF; /* store-and-forward */ 913 nar |= NAR_HBD; /* disable SQE test */ 914 PUTCSR(afep, CSR_NAR, nar); 915 916 afe_setrxfilt(afep); 917 918 return (B_TRUE); 919 } 920 921 /* 922 * Serial EEPROM access - inspired by the FreeBSD implementation. 923 */ 924 925 uint8_t 926 afe_sromwidth(afe_t *afep) 927 { 928 int i; 929 uint32_t eeread; 930 uint8_t addrlen = 8; 931 932 eeread = SPR_SROM_READ | SPR_SROM_SEL | SPR_SROM_CHIP; 933 934 PUTCSR(afep, CSR_SPR, eeread & ~SPR_SROM_CHIP); 935 drv_usecwait(1); 936 PUTCSR(afep, CSR_SPR, eeread); 937 938 /* command bits first */ 939 for (i = 4; i != 0; i >>= 1) { 940 unsigned val = (SROM_READCMD & i) ? SPR_SROM_DIN : 0; 941 942 PUTCSR(afep, CSR_SPR, eeread | val); 943 drv_usecwait(1); 944 PUTCSR(afep, CSR_SPR, eeread | val | SPR_SROM_CLOCK); 945 drv_usecwait(1); 946 } 947 948 PUTCSR(afep, CSR_SPR, eeread); 949 950 for (addrlen = 1; addrlen <= 12; addrlen++) { 951 PUTCSR(afep, CSR_SPR, eeread | SPR_SROM_CLOCK); 952 drv_usecwait(1); 953 if (!(GETCSR(afep, CSR_SPR) & SPR_SROM_DOUT)) { 954 PUTCSR(afep, CSR_SPR, eeread); 955 drv_usecwait(1); 956 break; 957 } 958 PUTCSR(afep, CSR_SPR, eeread); 959 drv_usecwait(1); 960 } 961 962 /* turn off accesses to the EEPROM */ 963 PUTCSR(afep, CSR_SPR, eeread &~ SPR_SROM_CHIP); 964 965 DBG(DSROM, "detected srom width = %d bits", addrlen); 966 967 return ((addrlen < 4 || addrlen > 12) ? 6 : addrlen); 968 } 969 970 /* 971 * The words in EEPROM are stored in little endian order. We 972 * shift bits out in big endian order, though. This requires 973 * a byte swap on some platforms. 974 */ 975 uint16_t 976 afe_readsromword(afe_t *afep, unsigned romaddr) 977 { 978 int i; 979 uint16_t word = 0; 980 uint16_t retval; 981 int eeread; 982 uint8_t addrlen; 983 int readcmd; 984 uchar_t *ptr; 985 986 eeread = SPR_SROM_READ | SPR_SROM_SEL | SPR_SROM_CHIP; 987 addrlen = afep->afe_sromwidth; 988 readcmd = (SROM_READCMD << addrlen) | romaddr; 989 990 if (romaddr >= (1 << addrlen)) { 991 /* too big to fit! */ 992 return (0); 993 } 994 995 PUTCSR(afep, CSR_SPR, eeread & ~SPR_SROM_CHIP); 996 PUTCSR(afep, CSR_SPR, eeread); 997 998 /* command and address bits */ 999 for (i = 4 + addrlen; i >= 0; i--) { 1000 short val = (readcmd & (1 << i)) ? SPR_SROM_DIN : 0; 1001 1002 PUTCSR(afep, CSR_SPR, eeread | val); 1003 drv_usecwait(1); 1004 PUTCSR(afep, CSR_SPR, eeread | val | SPR_SROM_CLOCK); 1005 drv_usecwait(1); 1006 } 1007 1008 PUTCSR(afep, CSR_SPR, eeread); 1009 1010 for (i = 0; i < 16; i++) { 1011 PUTCSR(afep, CSR_SPR, eeread | SPR_SROM_CLOCK); 1012 drv_usecwait(1); 1013 word <<= 1; 1014 if (GETCSR(afep, CSR_SPR) & SPR_SROM_DOUT) { 1015 word |= 1; 1016 } 1017 PUTCSR(afep, CSR_SPR, eeread); 1018 drv_usecwait(1); 1019 } 1020 1021 /* turn off accesses to the EEPROM */ 1022 PUTCSR(afep, CSR_SPR, eeread &~ SPR_SROM_CHIP); 1023 1024 /* 1025 * Fix up the endianness thing. Note that the values 1026 * are stored in little endian format on the SROM. 1027 */ 1028 ptr = (uchar_t *)&word; 1029 retval = (ptr[1] << 8) | ptr[0]; 1030 return (retval); 1031 } 1032 1033 void 1034 afe_readsrom(afe_t *afep, unsigned romaddr, unsigned len, char *dest) 1035 { 1036 int i; 1037 uint16_t word; 1038 uint16_t *ptr = (uint16_t *)((void *)dest); 1039 for (i = 0; i < len; i++) { 1040 word = afe_readsromword(afep, romaddr + i); 1041 *ptr = word; 1042 ptr++; 1043 } 1044 } 1045 1046 void 1047 afe_getfactaddr(afe_t *afep, uchar_t *eaddr) 1048 { 1049 afe_readsrom(afep, SROM_ENADDR, ETHERADDRL / 2, (char *)eaddr); 1050 1051 DBG(DMACID, 1052 "factory ethernet address = %02x:%02x:%02x:%02x:%02x:%02x", 1053 eaddr[0], eaddr[1], eaddr[2], eaddr[3], eaddr[4], eaddr[5]); 1054 } 1055 1056 /* 1057 * MII management. 1058 */ 1059 void 1060 afe_startphy(afe_t *afep) 1061 { 1062 unsigned phyaddr; 1063 unsigned bmcr; 1064 unsigned bmsr; 1065 unsigned anar; 1066 unsigned phyidr1; 1067 unsigned phyidr2; 1068 unsigned nosqe = 0; 1069 int retries; 1070 int fiber; 1071 int cnt; 1072 1073 /* ADMtek devices just use the PHY at address 1 */ 1074 afep->afe_phyaddr = phyaddr = 1; 1075 1076 phyidr1 = afe_miiread(afep, phyaddr, MII_PHYIDH); 1077 phyidr2 = afe_miiread(afep, phyaddr, MII_PHYIDL); 1078 if ((phyidr1 == 0x0022) && 1079 ((phyidr2 & 0xfff0) == 0x5410)) { 1080 nosqe = 1; 1081 /* only 983B has fiber support */ 1082 afep->afe_flags |= AFE_HASFIBER; 1083 } 1084 afep->afe_phyid = (phyidr1 << 16) | phyidr2; 1085 1086 DBG(DPHY, "phy at %d: %x,%x", phyaddr, phyidr1, phyidr2); 1087 DBG(DPHY, "bmsr = %x", afe_miiread(afep, 1088 afep->afe_phyaddr, MII_STATUS)); 1089 DBG(DPHY, "anar = %x", afe_miiread(afep, 1090 afep->afe_phyaddr, MII_AN_ADVERT)); 1091 DBG(DPHY, "anlpar = %x", afe_miiread(afep, 1092 afep->afe_phyaddr, MII_AN_LPABLE)); 1093 DBG(DPHY, "aner = %x", afe_miiread(afep, 1094 afep->afe_phyaddr, MII_AN_EXPANSION)); 1095 1096 DBG(DPHY, "resetting phy"); 1097 1098 /* we reset the phy block */ 1099 afe_miiwrite(afep, phyaddr, MII_CONTROL, MII_CONTROL_RESET); 1100 /* 1101 * wait for it to complete -- 500usec is still to short to 1102 * bother getting the system clock involved. 1103 */ 1104 drv_usecwait(500); 1105 for (retries = 0; retries < 10; retries++) { 1106 if (afe_miiread(afep, phyaddr, MII_CONTROL) & 1107 MII_CONTROL_RESET) { 1108 drv_usecwait(500); 1109 continue; 1110 } 1111 break; 1112 } 1113 if (retries == 100) { 1114 afe_error(afep->afe_dip, "timeout waiting on phy to reset"); 1115 return; 1116 } 1117 1118 DBG(DPHY, "phy reset complete"); 1119 1120 bmsr = afe_miiread(afep, phyaddr, MII_STATUS); 1121 anar = afe_miiread(afep, phyaddr, MII_AN_ADVERT); 1122 1123 anar &= ~(MII_ABILITY_100BASE_T4 | 1124 MII_ABILITY_100BASE_TX_FD | MII_ABILITY_100BASE_TX | 1125 MII_ABILITY_10BASE_T_FD | MII_ABILITY_10BASE_T); 1126 1127 fiber = 0; 1128 1129 /* if fiber is being forced, and device supports fiber... */ 1130 if (afep->afe_flags & AFE_HASFIBER) { 1131 1132 uint16_t mcr; 1133 1134 DBG(DPHY, "device supports 100BaseFX"); 1135 mcr = afe_miiread(afep, phyaddr, PHY_MCR); 1136 switch (afep->afe_forcefiber) { 1137 case 0: 1138 /* UTP Port */ 1139 DBG(DPHY, "forcing twpair"); 1140 mcr &= ~MCR_FIBER; 1141 fiber = 0; 1142 break; 1143 case 1: 1144 /* Fiber Port */ 1145 DBG(DPHY, "forcing 100BaseFX"); 1146 mcr |= MCR_FIBER; 1147 bmcr = (MII_CONTROL_100MB | MII_CONTROL_FDUPLEX); 1148 fiber = 1; 1149 break; 1150 default: 1151 DBG(DPHY, "checking for 100BaseFX link"); 1152 /* fiber is 100 Mb FDX */ 1153 afe_miiwrite(afep, phyaddr, MII_CONTROL, 1154 MII_CONTROL_100MB | MII_CONTROL_FDUPLEX); 1155 drv_usecwait(50); 1156 1157 mcr = afe_miiread(afep, phyaddr, PHY_MCR); 1158 mcr |= MCR_FIBER; 1159 afe_miiwrite(afep, phyaddr, PHY_MCR, mcr); 1160 drv_usecwait(500); 1161 1162 /* if fiber is active, use it */ 1163 if ((afe_miiread(afep, phyaddr, MII_STATUS) & 1164 MII_STATUS_LINKUP)) { 1165 bmcr = MII_CONTROL_100MB | MII_CONTROL_FDUPLEX; 1166 fiber = 1; 1167 } else { 1168 mcr &= ~MCR_FIBER; 1169 fiber = 0; 1170 } 1171 break; 1172 } 1173 afe_miiwrite(afep, phyaddr, PHY_MCR, mcr); 1174 drv_usecwait(500); 1175 } 1176 1177 if (fiber) { 1178 /* fiber only supports 100FDX(?) */ 1179 bmsr &= ~(MII_STATUS_100_BASE_T4 | 1180 MII_STATUS_100_BASEX | MII_STATUS_10_FD | MII_STATUS_10); 1181 bmsr |= MII_STATUS_100_BASEX_FD; 1182 } 1183 1184 /* assume full support for everything to start */ 1185 afep->afe_cap_aneg = afep->afe_cap_100T4 = 1186 afep->afe_cap_100fdx = afep->afe_cap_100hdx = 1187 afep->afe_cap_10fdx = afep->afe_cap_10hdx = 1; 1188 1189 /* disable modes not supported in hardware */ 1190 if (!(bmsr & MII_STATUS_100_BASEX_FD)) { 1191 afep->afe_adv_100fdx = 0; 1192 afep->afe_cap_100fdx = 0; 1193 } 1194 if (!(bmsr & MII_STATUS_100_BASE_T4)) { 1195 afep->afe_adv_100T4 = 0; 1196 afep->afe_cap_100T4 = 0; 1197 } 1198 if (!(bmsr & MII_STATUS_100_BASEX)) { 1199 afep->afe_adv_100hdx = 0; 1200 afep->afe_cap_100hdx = 0; 1201 } 1202 if (!(bmsr & MII_STATUS_10_FD)) { 1203 afep->afe_adv_10fdx = 0; 1204 afep->afe_cap_10fdx = 0; 1205 } 1206 if (!(bmsr & MII_STATUS_10)) { 1207 afep->afe_adv_10hdx = 0; 1208 afep->afe_cap_10hdx = 0; 1209 } 1210 if (!(bmsr & MII_STATUS_CANAUTONEG)) { 1211 afep->afe_adv_aneg = 0; 1212 afep->afe_cap_aneg = 0; 1213 } 1214 1215 cnt = 0; 1216 if (afep->afe_adv_100fdx) { 1217 anar |= MII_ABILITY_100BASE_TX_FD; 1218 cnt++; 1219 } 1220 if (afep->afe_adv_100T4) { 1221 anar |= MII_ABILITY_100BASE_T4; 1222 cnt++; 1223 } 1224 if (afep->afe_adv_100hdx) { 1225 anar |= MII_ABILITY_100BASE_TX; 1226 cnt++; 1227 } 1228 if (afep->afe_adv_10fdx) { 1229 anar |= MII_ABILITY_10BASE_T_FD; 1230 cnt++; 1231 } 1232 if (afep->afe_adv_10hdx) { 1233 anar |= MII_ABILITY_10BASE_T; 1234 cnt++; 1235 } 1236 1237 /* 1238 * Make certain at least one valid link mode is selected. 1239 */ 1240 if (!cnt) { 1241 afe_error(afep->afe_dip, "No valid link mode selected."); 1242 afe_error(afep->afe_dip, "Powering down PHY."); 1243 afe_stopphy(afep); 1244 afep->afe_linkup = LINK_STATE_DOWN; 1245 if (afep->afe_flags & AFE_RUNNING) 1246 afe_reportlink(afep); 1247 return; 1248 } 1249 1250 if (fiber) { 1251 bmcr = MII_CONTROL_100MB | MII_CONTROL_FDUPLEX; 1252 } else if ((afep->afe_adv_aneg) && (bmsr & MII_STATUS_CANAUTONEG)) { 1253 DBG(DPHY, "using autoneg mode"); 1254 bmcr = (MII_CONTROL_ANE | MII_CONTROL_RSAN); 1255 } else { 1256 DBG(DPHY, "using forced mode"); 1257 if (afep->afe_adv_100fdx) { 1258 bmcr = (MII_CONTROL_100MB | MII_CONTROL_FDUPLEX); 1259 } else if (afep->afe_adv_100hdx) { 1260 bmcr = MII_CONTROL_100MB; 1261 } else if (afep->afe_adv_10fdx) { 1262 bmcr = MII_CONTROL_FDUPLEX; 1263 } else { 1264 /* 10HDX */ 1265 bmcr = 0; 1266 } 1267 } 1268 1269 DBG(DPHY, "programming anar to 0x%x", anar); 1270 afe_miiwrite(afep, phyaddr, MII_AN_ADVERT, anar); 1271 DBG(DPHY, "programming bmcr to 0x%x", bmcr); 1272 afe_miiwrite(afep, phyaddr, MII_CONTROL, bmcr); 1273 1274 if (nosqe) { 1275 uint16_t pilr; 1276 /* 1277 * work around for errata 983B_0416 -- duplex light flashes 1278 * in 10 HDX. we just disable SQE testing on the device. 1279 */ 1280 pilr = afe_miiread(afep, phyaddr, PHY_PILR); 1281 pilr |= PILR_NOSQE; 1282 afe_miiwrite(afep, phyaddr, PHY_PILR, pilr); 1283 } 1284 1285 /* 1286 * schedule a query of the link status 1287 */ 1288 PUTCSR(afep, CSR_TIMER, TIMER_LOOP | 1289 (AFE_LINKTIMER * 1000 / TIMER_USEC)); 1290 } 1291 1292 void 1293 afe_stopphy(afe_t *afep) 1294 { 1295 /* stop the phy timer */ 1296 PUTCSR(afep, CSR_TIMER, 0); 1297 1298 /* 1299 * phy in isolate & powerdown mode... 1300 */ 1301 afe_miiwrite(afep, afep->afe_phyaddr, MII_CONTROL, 1302 MII_CONTROL_PWRDN | MII_CONTROL_ISOLATE); 1303 1304 /* 1305 * mark the link state unknown 1306 */ 1307 if (!afep->afe_resetting) { 1308 afep->afe_linkup = LINK_STATE_UNKNOWN; 1309 afep->afe_ifspeed = 0; 1310 afep->afe_duplex = LINK_DUPLEX_UNKNOWN; 1311 if (afep->afe_flags & AFE_RUNNING) 1312 afe_reportlink(afep); 1313 } 1314 } 1315 1316 void 1317 afe_reportlink(afe_t *afep) 1318 { 1319 int changed = 0; 1320 1321 if (afep->afe_ifspeed != afep->afe_lastifspeed) { 1322 afep->afe_lastifspeed = afep->afe_ifspeed; 1323 changed++; 1324 } 1325 if (afep->afe_duplex != afep->afe_lastduplex) { 1326 afep->afe_lastduplex = afep->afe_duplex; 1327 changed++; 1328 } 1329 if (changed) 1330 mac_link_update(afep->afe_mh, afep->afe_linkup); 1331 } 1332 1333 void 1334 afe_checklink(afe_t *afep) 1335 { 1336 if ((afep->afe_flags & AFE_RUNNING) == 0) 1337 return; 1338 1339 if ((afep->afe_txstall_time != 0) && 1340 (gethrtime() > afep->afe_txstall_time) && 1341 (afep->afe_txavail != AFE_TXRING)) { 1342 afep->afe_txstall_time = 0; 1343 afe_error(afep->afe_dip, "TX stall detected!"); 1344 afe_resetall(afep); 1345 return; 1346 } 1347 1348 switch (AFE_MODEL(afep)) { 1349 case MODEL_COMET: 1350 afe_checklinkcomet(afep); 1351 break; 1352 case MODEL_CENTAUR: 1353 afe_checklinkcentaur(afep); 1354 break; 1355 } 1356 } 1357 1358 void 1359 afe_checklinkcomet(afe_t *afep) 1360 { 1361 uint16_t xciis; 1362 int reinit = 0; 1363 1364 xciis = GETCSR16(afep, CSR_XCIIS); 1365 if (xciis & XCIIS_PDF) { 1366 afe_error(afep->afe_dip, "Parallel detection fault detected!"); 1367 } 1368 if (xciis & XCIIS_RF) { 1369 afe_error(afep->afe_dip, "Remote fault detected."); 1370 } 1371 if (xciis & XCIIS_LFAIL) { 1372 if (afep->afe_linkup == LINK_STATE_UP) { 1373 reinit++; 1374 } 1375 afep->afe_ifspeed = 0; 1376 afep->afe_linkup = LINK_STATE_DOWN; 1377 afep->afe_duplex = LINK_DUPLEX_UNKNOWN; 1378 afe_reportlink(afep); 1379 if (reinit) { 1380 afe_startphy(afep); 1381 } 1382 return; 1383 } 1384 1385 afep->afe_linkup = LINK_STATE_UP; 1386 afep->afe_ifspeed = (xciis & XCIIS_SPEED) ? 100000000 : 10000000; 1387 if (xciis & XCIIS_DUPLEX) { 1388 afep->afe_duplex = LINK_DUPLEX_FULL; 1389 } else { 1390 afep->afe_duplex = LINK_DUPLEX_HALF; 1391 } 1392 1393 afe_reportlink(afep); 1394 } 1395 1396 void 1397 afe_checklinkcentaur(afe_t *afep) 1398 { 1399 unsigned opmode; 1400 int reinit = 0; 1401 1402 opmode = GETCSR(afep, CSR_OPM); 1403 if ((opmode & OPM_MODE) == OPM_MACONLY) { 1404 DBG(DPHY, "Centaur running in MAC-only mode"); 1405 afe_checklinkmii(afep); 1406 return; 1407 } 1408 DBG(DPHY, "Centaur running in single chip mode"); 1409 if ((opmode & OPM_LINK) == 0) { 1410 if (afep->afe_linkup == LINK_STATE_UP) { 1411 reinit++; 1412 } 1413 afep->afe_ifspeed = 0; 1414 afep->afe_duplex = LINK_DUPLEX_UNKNOWN; 1415 afep->afe_linkup = LINK_STATE_DOWN; 1416 afe_reportlink(afep); 1417 if (reinit) { 1418 afe_startphy(afep); 1419 } 1420 return; 1421 } 1422 1423 afep->afe_linkup = LINK_STATE_UP; 1424 afep->afe_ifspeed = (opmode & OPM_SPEED) ? 100000000 : 10000000; 1425 if (opmode & OPM_DUPLEX) { 1426 afep->afe_duplex = LINK_DUPLEX_FULL; 1427 } else { 1428 afep->afe_duplex = LINK_DUPLEX_HALF; 1429 } 1430 afe_reportlink(afep); 1431 } 1432 1433 void 1434 afe_checklinkmii(afe_t *afep) 1435 { 1436 /* read MII state registers */ 1437 uint16_t bmsr; 1438 uint16_t bmcr; 1439 uint16_t anar; 1440 uint16_t anlpar; 1441 int reinit = 0; 1442 1443 /* read this twice, to clear latched link state */ 1444 bmsr = afe_miiread(afep, afep->afe_phyaddr, MII_STATUS); 1445 bmsr = afe_miiread(afep, afep->afe_phyaddr, MII_STATUS); 1446 bmcr = afe_miiread(afep, afep->afe_phyaddr, MII_CONTROL); 1447 anar = afe_miiread(afep, afep->afe_phyaddr, MII_AN_ADVERT); 1448 anlpar = afe_miiread(afep, afep->afe_phyaddr, MII_AN_LPABLE); 1449 1450 if (bmsr & MII_STATUS_REMFAULT) { 1451 afe_error(afep->afe_dip, "Remote fault detected."); 1452 } 1453 if (bmsr & MII_STATUS_JABBERING) { 1454 afe_error(afep->afe_dip, "Jabber condition detected."); 1455 } 1456 if ((bmsr & MII_STATUS_LINKUP) == 0) { 1457 /* no link */ 1458 if (afep->afe_linkup == LINK_STATE_UP) { 1459 reinit = 1; 1460 } 1461 afep->afe_ifspeed = 0; 1462 afep->afe_duplex = LINK_DUPLEX_UNKNOWN; 1463 afep->afe_linkup = LINK_STATE_DOWN; 1464 afe_reportlink(afep); 1465 if (reinit) { 1466 afe_startphy(afep); 1467 } 1468 return; 1469 } 1470 1471 DBG(DCHATTY, "link up!"); 1472 afep->afe_linkup = LINK_STATE_UP; 1473 1474 if (!(bmcr & MII_CONTROL_ANE)) { 1475 /* forced mode */ 1476 if (bmcr & MII_CONTROL_100MB) { 1477 afep->afe_ifspeed = 100000000; 1478 } else { 1479 afep->afe_ifspeed = 10000000; 1480 } 1481 if (bmcr & MII_CONTROL_FDUPLEX) { 1482 afep->afe_duplex = LINK_DUPLEX_FULL; 1483 } else { 1484 afep->afe_duplex = LINK_DUPLEX_HALF; 1485 } 1486 } else if ((!(bmsr & MII_STATUS_CANAUTONEG)) || 1487 (!(bmsr & MII_STATUS_ANDONE))) { 1488 afep->afe_ifspeed = 0; 1489 afep->afe_duplex = LINK_DUPLEX_UNKNOWN; 1490 } else if (anar & anlpar & MII_ABILITY_100BASE_TX_FD) { 1491 afep->afe_ifspeed = 100000000; 1492 afep->afe_duplex = LINK_DUPLEX_FULL; 1493 } else if (anar & anlpar & MII_ABILITY_100BASE_T4) { 1494 afep->afe_ifspeed = 100000000; 1495 afep->afe_duplex = LINK_DUPLEX_HALF; 1496 } else if (anar & anlpar & MII_ABILITY_100BASE_TX) { 1497 afep->afe_ifspeed = 100000000; 1498 afep->afe_duplex = LINK_DUPLEX_HALF; 1499 } else if (anar & anlpar & MII_ABILITY_10BASE_T_FD) { 1500 afep->afe_ifspeed = 10000000; 1501 afep->afe_duplex = LINK_DUPLEX_FULL; 1502 } else if (anar & anlpar & MII_ABILITY_10BASE_T) { 1503 afep->afe_ifspeed = 10000000; 1504 afep->afe_duplex = LINK_DUPLEX_HALF; 1505 } else { 1506 afep->afe_ifspeed = 0; 1507 afep->afe_duplex = LINK_DUPLEX_UNKNOWN; 1508 } 1509 1510 afe_reportlink(afep); 1511 } 1512 1513 void 1514 afe_miitristate(afe_t *afep) 1515 { 1516 uint32_t val = SPR_SROM_WRITE | SPR_MII_CTRL; 1517 1518 PUTCSR(afep, CSR_SPR, val); 1519 drv_usecwait(1); 1520 PUTCSR(afep, CSR_SPR, val | SPR_MII_CLOCK); 1521 drv_usecwait(1); 1522 } 1523 1524 void 1525 afe_miiwritebit(afe_t *afep, uint8_t bit) 1526 { 1527 uint32_t val = bit ? SPR_MII_DOUT : 0; 1528 1529 PUTCSR(afep, CSR_SPR, val); 1530 drv_usecwait(1); 1531 PUTCSR(afep, CSR_SPR, val | SPR_MII_CLOCK); 1532 drv_usecwait(1); 1533 } 1534 1535 uint8_t 1536 afe_miireadbit(afe_t *afep) 1537 { 1538 uint32_t val = SPR_MII_CTRL | SPR_SROM_READ; 1539 uint8_t bit; 1540 1541 PUTCSR(afep, CSR_SPR, val); 1542 drv_usecwait(1); 1543 bit = (GETCSR(afep, CSR_SPR) & SPR_MII_DIN) ? 1 : 0; 1544 PUTCSR(afep, CSR_SPR, val | SPR_MII_CLOCK); 1545 drv_usecwait(1); 1546 return (bit); 1547 } 1548 1549 uint16_t 1550 afe_miiread(afe_t *afep, int phy, int reg) 1551 { 1552 /* 1553 * ADMtek bugs ignore address decode bits -- they only 1554 * support PHY at 1. 1555 */ 1556 if (phy != 1) { 1557 return (0xffff); 1558 } 1559 switch (AFE_MODEL(afep)) { 1560 case MODEL_COMET: 1561 return (afe_miireadcomet(afep, phy, reg)); 1562 case MODEL_CENTAUR: 1563 return (afe_miireadgeneral(afep, phy, reg)); 1564 } 1565 return (0xffff); 1566 } 1567 1568 uint16_t 1569 afe_miireadgeneral(afe_t *afep, int phy, int reg) 1570 { 1571 uint16_t value = 0; 1572 int i; 1573 1574 /* send the 32 bit preamble */ 1575 for (i = 0; i < 32; i++) { 1576 afe_miiwritebit(afep, 1); 1577 } 1578 1579 /* send the start code - 01b */ 1580 afe_miiwritebit(afep, 0); 1581 afe_miiwritebit(afep, 1); 1582 1583 /* send the opcode for read, - 10b */ 1584 afe_miiwritebit(afep, 1); 1585 afe_miiwritebit(afep, 0); 1586 1587 /* next we send the 5 bit phy address */ 1588 for (i = 0x10; i > 0; i >>= 1) { 1589 afe_miiwritebit(afep, (phy & i) ? 1 : 0); 1590 } 1591 1592 /* the 5 bit register address goes next */ 1593 for (i = 0x10; i > 0; i >>= 1) { 1594 afe_miiwritebit(afep, (reg & i) ? 1 : 0); 1595 } 1596 1597 /* turnaround - tristate followed by logic 0 */ 1598 afe_miitristate(afep); 1599 afe_miiwritebit(afep, 0); 1600 1601 /* read the 16 bit register value */ 1602 for (i = 0x8000; i > 0; i >>= 1) { 1603 value <<= 1; 1604 value |= afe_miireadbit(afep); 1605 } 1606 afe_miitristate(afep); 1607 return (value); 1608 } 1609 1610 uint16_t 1611 afe_miireadcomet(afe_t *afep, int phy, int reg) 1612 { 1613 if (phy != 1) { 1614 return (0xffff); 1615 } 1616 switch (reg) { 1617 case MII_CONTROL: 1618 reg = CSR_BMCR; 1619 break; 1620 case MII_STATUS: 1621 reg = CSR_BMSR; 1622 break; 1623 case MII_PHYIDH: 1624 reg = CSR_PHYIDR1; 1625 break; 1626 case MII_PHYIDL: 1627 reg = CSR_PHYIDR2; 1628 break; 1629 case MII_AN_ADVERT: 1630 reg = CSR_ANAR; 1631 break; 1632 case MII_AN_LPABLE: 1633 reg = CSR_ANLPAR; 1634 break; 1635 case MII_AN_EXPANSION: 1636 reg = CSR_ANER; 1637 break; 1638 default: 1639 return (0); 1640 } 1641 return (GETCSR16(afep, reg) & 0xFFFF); 1642 } 1643 1644 void 1645 afe_miiwrite(afe_t *afep, int phy, int reg, uint16_t val) 1646 { 1647 /* 1648 * ADMtek bugs ignore address decode bits -- they only 1649 * support PHY at 1. 1650 */ 1651 if (phy != 1) { 1652 return; 1653 } 1654 switch (AFE_MODEL(afep)) { 1655 case MODEL_COMET: 1656 afe_miiwritecomet(afep, phy, reg, val); 1657 break; 1658 case MODEL_CENTAUR: 1659 afe_miiwritegeneral(afep, phy, reg, val); 1660 break; 1661 } 1662 } 1663 1664 void 1665 afe_miiwritegeneral(afe_t *afep, int phy, int reg, uint16_t val) 1666 { 1667 int i; 1668 1669 /* send the 32 bit preamble */ 1670 for (i = 0; i < 32; i++) { 1671 afe_miiwritebit(afep, 1); 1672 } 1673 1674 /* send the start code - 01b */ 1675 afe_miiwritebit(afep, 0); 1676 afe_miiwritebit(afep, 1); 1677 1678 /* send the opcode for write, - 01b */ 1679 afe_miiwritebit(afep, 0); 1680 afe_miiwritebit(afep, 1); 1681 1682 /* next we send the 5 bit phy address */ 1683 for (i = 0x10; i > 0; i >>= 1) { 1684 afe_miiwritebit(afep, (phy & i) ? 1 : 0); 1685 } 1686 1687 /* the 5 bit register address goes next */ 1688 for (i = 0x10; i > 0; i >>= 1) { 1689 afe_miiwritebit(afep, (reg & i) ? 1 : 0); 1690 } 1691 1692 /* turnaround - tristate followed by logic 0 */ 1693 afe_miitristate(afep); 1694 afe_miiwritebit(afep, 0); 1695 1696 /* now write out our data (16 bits) */ 1697 for (i = 0x8000; i > 0; i >>= 1) { 1698 afe_miiwritebit(afep, (val & i) ? 1 : 0); 1699 } 1700 1701 /* idle mode */ 1702 afe_miitristate(afep); 1703 } 1704 1705 void 1706 afe_miiwritecomet(afe_t *afep, int phy, int reg, uint16_t val) 1707 { 1708 if (phy != 1) { 1709 return; 1710 } 1711 switch (reg) { 1712 case MII_CONTROL: 1713 reg = CSR_BMCR; 1714 break; 1715 case MII_STATUS: 1716 reg = CSR_BMSR; 1717 break; 1718 case MII_PHYIDH: 1719 reg = CSR_PHYIDR1; 1720 break; 1721 case MII_PHYIDL: 1722 reg = CSR_PHYIDR2; 1723 break; 1724 case MII_AN_ADVERT: 1725 reg = CSR_ANAR; 1726 break; 1727 case MII_AN_LPABLE: 1728 reg = CSR_ANLPAR; 1729 break; 1730 case MII_AN_EXPANSION: 1731 reg = CSR_ANER; 1732 break; 1733 default: 1734 return; 1735 } 1736 PUTCSR16(afep, reg, val); 1737 } 1738 1739 int 1740 afe_m_start(void *arg) 1741 { 1742 afe_t *afep = arg; 1743 1744 /* grab exclusive access to the card */ 1745 mutex_enter(&afep->afe_intrlock); 1746 mutex_enter(&afep->afe_xmtlock); 1747 1748 afe_startall(afep); 1749 afep->afe_flags |= AFE_RUNNING; 1750 1751 mutex_exit(&afep->afe_xmtlock); 1752 mutex_exit(&afep->afe_intrlock); 1753 return (0); 1754 } 1755 1756 void 1757 afe_m_stop(void *arg) 1758 { 1759 afe_t *afep = arg; 1760 1761 /* exclusive access to the hardware! */ 1762 mutex_enter(&afep->afe_intrlock); 1763 mutex_enter(&afep->afe_xmtlock); 1764 1765 afe_stopall(afep); 1766 afep->afe_flags &= ~AFE_RUNNING; 1767 1768 mutex_exit(&afep->afe_xmtlock); 1769 mutex_exit(&afep->afe_intrlock); 1770 } 1771 1772 void 1773 afe_startmac(afe_t *afep) 1774 { 1775 /* verify exclusive access to the card */ 1776 ASSERT(mutex_owned(&afep->afe_intrlock)); 1777 ASSERT(mutex_owned(&afep->afe_xmtlock)); 1778 1779 /* start the card */ 1780 SETBIT(afep, CSR_NAR, NAR_TX_ENABLE | NAR_RX_ENABLE); 1781 1782 if (afep->afe_txavail != AFE_TXRING) 1783 PUTCSR(afep, CSR_TDR, 0); 1784 1785 /* tell the mac that we are ready to go! */ 1786 if (afep->afe_flags & AFE_RUNNING) 1787 mac_tx_update(afep->afe_mh); 1788 } 1789 1790 void 1791 afe_stopmac(afe_t *afep) 1792 { 1793 int i; 1794 1795 /* exclusive access to the hardware! */ 1796 ASSERT(mutex_owned(&afep->afe_intrlock)); 1797 ASSERT(mutex_owned(&afep->afe_xmtlock)); 1798 1799 CLRBIT(afep, CSR_NAR, NAR_TX_ENABLE | NAR_RX_ENABLE); 1800 1801 /* 1802 * A 1518 byte frame at 10Mbps takes about 1.2 msec to drain. 1803 * We just add up to the nearest msec (2), which should be 1804 * plenty to complete. 1805 * 1806 * Note that some chips never seem to indicate the transition to 1807 * the stopped state properly. Experience shows that we can safely 1808 * proceed anyway, after waiting the requisite timeout. 1809 */ 1810 for (i = 2000; i != 0; i -= 10) { 1811 if ((GETCSR(afep, CSR_SR) & (SR_TX_STATE | SR_RX_STATE)) == 0) 1812 break; 1813 drv_usecwait(10); 1814 } 1815 1816 /* prevent an interrupt */ 1817 PUTCSR(afep, CSR_SR2, INT_RXSTOPPED | INT_TXSTOPPED); 1818 } 1819 1820 void 1821 afe_resetrings(afe_t *afep) 1822 { 1823 int i; 1824 1825 /* now we need to reset the pointers... */ 1826 PUTCSR(afep, CSR_RDB, 0); 1827 PUTCSR(afep, CSR_TDB, 0); 1828 1829 /* reset the descriptor ring pointers */ 1830 afep->afe_rxhead = 0; 1831 afep->afe_txreclaim = 0; 1832 afep->afe_txsend = 0; 1833 afep->afe_txavail = AFE_TXRING; 1834 1835 /* set up transmit descriptor ring */ 1836 for (i = 0; i < AFE_TXRING; i++) { 1837 afe_desc_t *tmdp = &afep->afe_txdescp[i]; 1838 unsigned control = 0; 1839 if (i == (AFE_TXRING - 1)) { 1840 control |= TXCTL_ENDRING; 1841 } 1842 PUTTXDESC(afep, tmdp->desc_status, 0); 1843 PUTTXDESC(afep, tmdp->desc_control, control); 1844 PUTTXDESC(afep, tmdp->desc_buffer1, 0); 1845 PUTTXDESC(afep, tmdp->desc_buffer2, 0); 1846 SYNCTXDESC(afep, i, DDI_DMA_SYNC_FORDEV); 1847 } 1848 PUTCSR(afep, CSR_TDB, afep->afe_txdesc_paddr); 1849 1850 /* make the receive buffers available */ 1851 for (i = 0; i < AFE_RXRING; i++) { 1852 afe_rxbuf_t *rxb = afep->afe_rxbufs[i]; 1853 afe_desc_t *rmdp = &afep->afe_rxdescp[i]; 1854 unsigned control; 1855 1856 control = AFE_BUFSZ & RXCTL_BUFLEN1; 1857 if (i == (AFE_RXRING - 1)) { 1858 control |= RXCTL_ENDRING; 1859 } 1860 PUTRXDESC(afep, rmdp->desc_buffer1, rxb->rxb_paddr); 1861 PUTRXDESC(afep, rmdp->desc_buffer2, 0); 1862 PUTRXDESC(afep, rmdp->desc_control, control); 1863 PUTRXDESC(afep, rmdp->desc_status, RXSTAT_OWN); 1864 SYNCRXDESC(afep, i, DDI_DMA_SYNC_FORDEV); 1865 } 1866 PUTCSR(afep, CSR_RDB, afep->afe_rxdesc_paddr); 1867 } 1868 1869 void 1870 afe_stopall(afe_t *afep) 1871 { 1872 afe_disableinterrupts(afep); 1873 1874 afe_stopmac(afep); 1875 1876 /* stop the phy */ 1877 afe_stopphy(afep); 1878 } 1879 1880 void 1881 afe_startall(afe_t *afep) 1882 { 1883 ASSERT(mutex_owned(&afep->afe_intrlock)); 1884 ASSERT(mutex_owned(&afep->afe_xmtlock)); 1885 1886 /* make sure interrupts are disabled to begin */ 1887 afe_disableinterrupts(afep); 1888 1889 /* initialize the chip */ 1890 (void) afe_initialize(afep); 1891 1892 /* now we can enable interrupts */ 1893 afe_enableinterrupts(afep); 1894 1895 /* start up the phy */ 1896 afe_startphy(afep); 1897 1898 /* start up the mac */ 1899 afe_startmac(afep); 1900 } 1901 1902 void 1903 afe_resetall(afe_t *afep) 1904 { 1905 afep->afe_resetting = B_TRUE; 1906 afe_stopall(afep); 1907 afep->afe_resetting = B_FALSE; 1908 afe_startall(afep); 1909 } 1910 1911 afe_txbuf_t * 1912 afe_alloctxbuf(afe_t *afep) 1913 { 1914 ddi_dma_cookie_t dmac; 1915 unsigned ncookies; 1916 afe_txbuf_t *txb; 1917 size_t len; 1918 1919 txb = kmem_zalloc(sizeof (*txb), KM_SLEEP); 1920 1921 if (ddi_dma_alloc_handle(afep->afe_dip, &afe_dma_txattr, 1922 DDI_DMA_SLEEP, NULL, &txb->txb_dmah) != DDI_SUCCESS) { 1923 return (NULL); 1924 } 1925 1926 if (ddi_dma_mem_alloc(txb->txb_dmah, AFE_BUFSZ, &afe_bufattr, 1927 DDI_DMA_STREAMING, DDI_DMA_SLEEP, NULL, &txb->txb_buf, &len, 1928 &txb->txb_acch) != DDI_SUCCESS) { 1929 return (NULL); 1930 } 1931 if (ddi_dma_addr_bind_handle(txb->txb_dmah, NULL, txb->txb_buf, 1932 len, DDI_DMA_WRITE | DDI_DMA_STREAMING, DDI_DMA_SLEEP, NULL, 1933 &dmac, &ncookies) != DDI_DMA_MAPPED) { 1934 return (NULL); 1935 } 1936 txb->txb_paddr = dmac.dmac_address; 1937 1938 return (txb); 1939 } 1940 1941 void 1942 afe_destroytxbuf(afe_txbuf_t *txb) 1943 { 1944 if (txb != NULL) { 1945 if (txb->txb_paddr) 1946 (void) ddi_dma_unbind_handle(txb->txb_dmah); 1947 if (txb->txb_acch) 1948 ddi_dma_mem_free(&txb->txb_acch); 1949 if (txb->txb_dmah) 1950 ddi_dma_free_handle(&txb->txb_dmah); 1951 kmem_free(txb, sizeof (*txb)); 1952 } 1953 } 1954 1955 afe_rxbuf_t * 1956 afe_allocrxbuf(afe_t *afep) 1957 { 1958 afe_rxbuf_t *rxb; 1959 size_t len; 1960 unsigned ccnt; 1961 ddi_dma_cookie_t dmac; 1962 1963 rxb = kmem_zalloc(sizeof (*rxb), KM_SLEEP); 1964 1965 if (ddi_dma_alloc_handle(afep->afe_dip, &afe_dma_attr, 1966 DDI_DMA_SLEEP, NULL, &rxb->rxb_dmah) != DDI_SUCCESS) { 1967 kmem_free(rxb, sizeof (*rxb)); 1968 return (NULL); 1969 } 1970 if (ddi_dma_mem_alloc(rxb->rxb_dmah, AFE_BUFSZ, &afe_bufattr, 1971 DDI_DMA_STREAMING, DDI_DMA_SLEEP, NULL, &rxb->rxb_buf, &len, 1972 &rxb->rxb_acch) != DDI_SUCCESS) { 1973 ddi_dma_free_handle(&rxb->rxb_dmah); 1974 kmem_free(rxb, sizeof (*rxb)); 1975 return (NULL); 1976 } 1977 if (ddi_dma_addr_bind_handle(rxb->rxb_dmah, NULL, rxb->rxb_buf, len, 1978 DDI_DMA_READ | DDI_DMA_STREAMING, DDI_DMA_SLEEP, NULL, &dmac, 1979 &ccnt) != DDI_DMA_MAPPED) { 1980 ddi_dma_mem_free(&rxb->rxb_acch); 1981 ddi_dma_free_handle(&rxb->rxb_dmah); 1982 kmem_free(rxb, sizeof (*rxb)); 1983 return (NULL); 1984 } 1985 rxb->rxb_paddr = dmac.dmac_address; 1986 1987 return (rxb); 1988 } 1989 1990 void 1991 afe_destroyrxbuf(afe_rxbuf_t *rxb) 1992 { 1993 if (rxb) { 1994 (void) ddi_dma_unbind_handle(rxb->rxb_dmah); 1995 ddi_dma_mem_free(&rxb->rxb_acch); 1996 ddi_dma_free_handle(&rxb->rxb_dmah); 1997 kmem_free(rxb, sizeof (*rxb)); 1998 } 1999 } 2000 2001 /* 2002 * Allocate receive resources. 2003 */ 2004 int 2005 afe_allocrxring(afe_t *afep) 2006 { 2007 int rval; 2008 int i; 2009 size_t size; 2010 size_t len; 2011 ddi_dma_cookie_t dmac; 2012 unsigned ncookies; 2013 caddr_t kaddr; 2014 2015 size = AFE_RXRING * sizeof (afe_desc_t); 2016 2017 rval = ddi_dma_alloc_handle(afep->afe_dip, &afe_dma_attr, 2018 DDI_DMA_SLEEP, NULL, &afep->afe_rxdesc_dmah); 2019 if (rval != DDI_SUCCESS) { 2020 afe_error(afep->afe_dip, 2021 "unable to allocate DMA handle for rx descriptors"); 2022 return (DDI_FAILURE); 2023 } 2024 2025 rval = ddi_dma_mem_alloc(afep->afe_rxdesc_dmah, size, &afe_devattr, 2026 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, &kaddr, &len, 2027 &afep->afe_rxdesc_acch); 2028 if (rval != DDI_SUCCESS) { 2029 afe_error(afep->afe_dip, 2030 "unable to allocate DMA memory for rx descriptors"); 2031 return (DDI_FAILURE); 2032 } 2033 2034 rval = ddi_dma_addr_bind_handle(afep->afe_rxdesc_dmah, NULL, kaddr, 2035 size, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, 2036 &dmac, &ncookies); 2037 if (rval != DDI_DMA_MAPPED) { 2038 afe_error(afep->afe_dip, 2039 "unable to bind DMA for rx descriptors"); 2040 return (DDI_FAILURE); 2041 } 2042 2043 /* because of afe_dma_attr */ 2044 ASSERT(ncookies == 1); 2045 2046 /* we take the 32-bit physical address out of the cookie */ 2047 afep->afe_rxdesc_paddr = dmac.dmac_address; 2048 afep->afe_rxdescp = (void *)kaddr; 2049 2050 /* allocate buffer pointers (not the buffers themselves, yet) */ 2051 afep->afe_rxbufs = kmem_zalloc(AFE_RXRING * sizeof (afe_rxbuf_t *), 2052 KM_SLEEP); 2053 2054 /* now allocate rx buffers */ 2055 for (i = 0; i < AFE_RXRING; i++) { 2056 afe_rxbuf_t *rxb = afe_allocrxbuf(afep); 2057 if (rxb == NULL) 2058 return (DDI_FAILURE); 2059 afep->afe_rxbufs[i] = rxb; 2060 } 2061 2062 return (DDI_SUCCESS); 2063 } 2064 2065 /* 2066 * Allocate transmit resources. 2067 */ 2068 int 2069 afe_alloctxring(afe_t *afep) 2070 { 2071 int rval; 2072 int i; 2073 size_t size; 2074 size_t len; 2075 ddi_dma_cookie_t dmac; 2076 unsigned ncookies; 2077 caddr_t kaddr; 2078 2079 size = AFE_TXRING * sizeof (afe_desc_t); 2080 2081 rval = ddi_dma_alloc_handle(afep->afe_dip, &afe_dma_attr, 2082 DDI_DMA_SLEEP, NULL, &afep->afe_txdesc_dmah); 2083 if (rval != DDI_SUCCESS) { 2084 afe_error(afep->afe_dip, 2085 "unable to allocate DMA handle for tx descriptors"); 2086 return (DDI_FAILURE); 2087 } 2088 2089 rval = ddi_dma_mem_alloc(afep->afe_txdesc_dmah, size, &afe_devattr, 2090 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, &kaddr, &len, 2091 &afep->afe_txdesc_acch); 2092 if (rval != DDI_SUCCESS) { 2093 afe_error(afep->afe_dip, 2094 "unable to allocate DMA memory for tx descriptors"); 2095 return (DDI_FAILURE); 2096 } 2097 2098 rval = ddi_dma_addr_bind_handle(afep->afe_txdesc_dmah, NULL, kaddr, 2099 size, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, 2100 &dmac, &ncookies); 2101 if (rval != DDI_DMA_MAPPED) { 2102 afe_error(afep->afe_dip, 2103 "unable to bind DMA for tx descriptors"); 2104 return (DDI_FAILURE); 2105 } 2106 2107 /* because of afe_dma_attr */ 2108 ASSERT(ncookies == 1); 2109 2110 /* we take the 32-bit physical address out of the cookie */ 2111 afep->afe_txdesc_paddr = dmac.dmac_address; 2112 afep->afe_txdescp = (void *)kaddr; 2113 2114 /* allocate buffer pointers (not the buffers themselves, yet) */ 2115 afep->afe_txbufs = kmem_zalloc(AFE_TXRING * sizeof (afe_txbuf_t *), 2116 KM_SLEEP); 2117 2118 /* now allocate tx buffers */ 2119 for (i = 0; i < AFE_TXRING; i++) { 2120 afe_txbuf_t *txb = afe_alloctxbuf(afep); 2121 if (txb == NULL) 2122 return (DDI_FAILURE); 2123 afep->afe_txbufs[i] = txb; 2124 } 2125 2126 return (DDI_SUCCESS); 2127 } 2128 2129 void 2130 afe_freerxring(afe_t *afep) 2131 { 2132 int i; 2133 2134 for (i = 0; i < AFE_RXRING; i++) { 2135 afe_destroyrxbuf(afep->afe_rxbufs[i]); 2136 } 2137 2138 if (afep->afe_rxbufs) { 2139 kmem_free(afep->afe_rxbufs, 2140 AFE_RXRING * sizeof (afe_rxbuf_t *)); 2141 } 2142 2143 if (afep->afe_rxdesc_paddr) 2144 (void) ddi_dma_unbind_handle(afep->afe_rxdesc_dmah); 2145 if (afep->afe_rxdesc_acch) 2146 ddi_dma_mem_free(&afep->afe_rxdesc_acch); 2147 if (afep->afe_rxdesc_dmah) 2148 ddi_dma_free_handle(&afep->afe_rxdesc_dmah); 2149 } 2150 2151 void 2152 afe_freetxring(afe_t *afep) 2153 { 2154 int i; 2155 2156 for (i = 0; i < AFE_TXRING; i++) { 2157 afe_destroytxbuf(afep->afe_txbufs[i]); 2158 } 2159 2160 if (afep->afe_txbufs) { 2161 kmem_free(afep->afe_txbufs, 2162 AFE_TXRING * sizeof (afe_txbuf_t *)); 2163 } 2164 if (afep->afe_txdesc_paddr) 2165 (void) ddi_dma_unbind_handle(afep->afe_txdesc_dmah); 2166 if (afep->afe_txdesc_acch) 2167 ddi_dma_mem_free(&afep->afe_txdesc_acch); 2168 if (afep->afe_txdesc_dmah) 2169 ddi_dma_free_handle(&afep->afe_txdesc_dmah); 2170 } 2171 2172 /* 2173 * Interrupt service routine. 2174 */ 2175 unsigned 2176 afe_intr(caddr_t arg) 2177 { 2178 afe_t *afep = (void *)arg; 2179 uint32_t status; 2180 mblk_t *mp = NULL; 2181 2182 mutex_enter(&afep->afe_intrlock); 2183 2184 if (afep->afe_flags & AFE_SUSPENDED) { 2185 /* we cannot receive interrupts! */ 2186 mutex_exit(&afep->afe_intrlock); 2187 return (DDI_INTR_UNCLAIMED); 2188 } 2189 2190 /* check interrupt status bits, did we interrupt? */ 2191 status = GETCSR(afep, CSR_SR2) & INT_ALL; 2192 2193 if (status == 0) { 2194 KIOIP->intrs[KSTAT_INTR_SPURIOUS]++; 2195 mutex_exit(&afep->afe_intrlock); 2196 return (DDI_INTR_UNCLAIMED); 2197 } 2198 /* ack the interrupt */ 2199 PUTCSR(afep, CSR_SR2, status); 2200 KIOIP->intrs[KSTAT_INTR_HARD]++; 2201 2202 if (!(afep->afe_flags & AFE_RUNNING)) { 2203 /* not running, don't touch anything */ 2204 mutex_exit(&afep->afe_intrlock); 2205 return (DDI_INTR_CLAIMED); 2206 } 2207 2208 if (status & (INT_RXOK|INT_RXNOBUF)) { 2209 /* receive packets */ 2210 mp = afe_receive(afep); 2211 if (status & INT_RXNOBUF) 2212 PUTCSR(afep, CSR_RDR, 0); /* wake up chip */ 2213 } 2214 2215 if (status & INT_TXOK) { 2216 /* transmit completed */ 2217 mutex_enter(&afep->afe_xmtlock); 2218 afe_reclaim(afep); 2219 mutex_exit(&afep->afe_xmtlock); 2220 } 2221 2222 if (status & (INT_LINKCHG|INT_TIMER)) { 2223 mutex_enter(&afep->afe_xmtlock); 2224 afe_checklink(afep); 2225 mutex_exit(&afep->afe_xmtlock); 2226 } 2227 2228 if (status & (INT_RXSTOPPED|INT_TXSTOPPED| 2229 INT_RXJABBER|INT_TXJABBER|INT_TXUNDERFLOW)) { 2230 2231 if (status & (INT_RXJABBER | INT_TXJABBER)) { 2232 afep->afe_jabber++; 2233 } 2234 DBG(DWARN, "resetting mac, status %x", status); 2235 mutex_enter(&afep->afe_xmtlock); 2236 afe_resetall(afep); 2237 mutex_exit(&afep->afe_xmtlock); 2238 } 2239 2240 if (status & INT_BUSERR) { 2241 switch (GETCSR(afep, CSR_SR) & SR_BERR_TYPE) { 2242 case SR_BERR_PARITY: 2243 afe_error(afep->afe_dip, "PCI parity error"); 2244 break; 2245 case SR_BERR_TARGET_ABORT: 2246 afe_error(afep->afe_dip, "PCI target abort"); 2247 break; 2248 case SR_BERR_MASTER_ABORT: 2249 afe_error(afep->afe_dip, "PCI master abort"); 2250 break; 2251 default: 2252 afe_error(afep->afe_dip, "Unknown PCI error"); 2253 break; 2254 } 2255 2256 /* reset the chip in an attempt to fix things */ 2257 mutex_enter(&afep->afe_xmtlock); 2258 afe_resetall(afep); 2259 mutex_exit(&afep->afe_xmtlock); 2260 } 2261 2262 mutex_exit(&afep->afe_intrlock); 2263 2264 /* 2265 * Send up packets. We do this outside of the intrlock. 2266 */ 2267 if (mp) { 2268 mac_rx(afep->afe_mh, NULL, mp); 2269 } 2270 2271 return (DDI_INTR_CLAIMED); 2272 } 2273 2274 void 2275 afe_enableinterrupts(afe_t *afep) 2276 { 2277 unsigned mask = INT_WANTED; 2278 2279 if (afep->afe_wantw) 2280 mask |= INT_TXOK; 2281 2282 PUTCSR(afep, CSR_IER2, mask); 2283 2284 if (AFE_MODEL(afep) == MODEL_COMET) { 2285 /* 2286 * On the Comet, this is the internal transceiver 2287 * interrupt. We program the Comet's built-in PHY to 2288 * enable certain interrupts. 2289 */ 2290 PUTCSR16(afep, CSR_XIE, XIE_LDE | XIE_ANCE); 2291 } 2292 } 2293 2294 void 2295 afe_disableinterrupts(afe_t *afep) 2296 { 2297 /* disable further interrupts */ 2298 PUTCSR(afep, CSR_IER2, INT_NONE); 2299 2300 /* clear any pending interrupts */ 2301 PUTCSR(afep, CSR_SR2, INT_ALL); 2302 } 2303 2304 boolean_t 2305 afe_send(afe_t *afep, mblk_t *mp) 2306 { 2307 size_t len; 2308 afe_txbuf_t *txb; 2309 afe_desc_t *tmd; 2310 uint32_t control; 2311 int txsend; 2312 2313 ASSERT(mutex_owned(&afep->afe_xmtlock)); 2314 ASSERT(mp != NULL); 2315 2316 len = msgsize(mp); 2317 if (len > ETHERVLANMTU) { 2318 DBG(DXMIT, "frame too long: %d", len); 2319 afep->afe_macxmt_errors++; 2320 freemsg(mp); 2321 return (B_TRUE); 2322 } 2323 2324 if (afep->afe_txavail < AFE_TXRECLAIM) 2325 afe_reclaim(afep); 2326 2327 if (afep->afe_txavail == 0) { 2328 /* no more tmds */ 2329 afep->afe_wantw = B_TRUE; 2330 /* enable TX interrupt */ 2331 afe_enableinterrupts(afep); 2332 return (B_FALSE); 2333 } 2334 2335 txsend = afep->afe_txsend; 2336 2337 /* 2338 * For simplicity, we just do a copy into a preallocated 2339 * DMA buffer. 2340 */ 2341 2342 txb = afep->afe_txbufs[txsend]; 2343 mcopymsg(mp, txb->txb_buf); /* frees mp! */ 2344 2345 /* 2346 * Statistics. 2347 */ 2348 afep->afe_opackets++; 2349 afep->afe_obytes += len; 2350 if (txb->txb_buf[0] & 0x1) { 2351 if (bcmp(txb->txb_buf, afe_broadcast, ETHERADDRL) != 0) 2352 afep->afe_multixmt++; 2353 else 2354 afep->afe_brdcstxmt++; 2355 } 2356 2357 /* note len is already known to be a small unsigned */ 2358 control = len | TXCTL_FIRST | TXCTL_LAST | TXCTL_INTCMPLTE; 2359 2360 if (txsend == (AFE_TXRING - 1)) 2361 control |= TXCTL_ENDRING; 2362 2363 tmd = &afep->afe_txdescp[txsend]; 2364 2365 SYNCTXBUF(txb, len, DDI_DMA_SYNC_FORDEV); 2366 PUTTXDESC(afep, tmd->desc_control, control); 2367 PUTTXDESC(afep, tmd->desc_buffer1, txb->txb_paddr); 2368 PUTTXDESC(afep, tmd->desc_buffer2, 0); 2369 PUTTXDESC(afep, tmd->desc_status, TXSTAT_OWN); 2370 /* sync the descriptor out to the device */ 2371 SYNCTXDESC(afep, txsend, DDI_DMA_SYNC_FORDEV); 2372 2373 /* 2374 * Note the new values of txavail and txsend. 2375 */ 2376 afep->afe_txavail--; 2377 afep->afe_txsend = (txsend + 1) % AFE_TXRING; 2378 2379 /* 2380 * It should never, ever take more than 5 seconds to drain 2381 * the ring. If it happens, then we are stuck! 2382 */ 2383 afep->afe_txstall_time = gethrtime() + (5 * 1000000000ULL); 2384 2385 /* 2386 * wake up the chip ... inside the lock to protect against DR suspend, 2387 * etc. 2388 */ 2389 PUTCSR(afep, CSR_TDR, 0); 2390 2391 return (B_TRUE); 2392 } 2393 2394 /* 2395 * Reclaim buffers that have completed transmission. 2396 */ 2397 void 2398 afe_reclaim(afe_t *afep) 2399 { 2400 afe_desc_t *tmdp; 2401 2402 while (afep->afe_txavail != AFE_TXRING) { 2403 uint32_t status; 2404 uint32_t control; 2405 int index = afep->afe_txreclaim; 2406 2407 tmdp = &afep->afe_txdescp[index]; 2408 2409 /* sync it before we read it */ 2410 SYNCTXDESC(afep, index, DDI_DMA_SYNC_FORKERNEL); 2411 2412 control = GETTXDESC(afep, tmdp->desc_control); 2413 status = GETTXDESC(afep, tmdp->desc_status); 2414 2415 if (status & TXSTAT_OWN) { 2416 /* chip is still working on it, we're done */ 2417 break; 2418 } 2419 2420 afep->afe_txavail++; 2421 afep->afe_txreclaim = (index + 1) % AFE_TXRING; 2422 2423 /* in the most common successful case, all bits are clear */ 2424 if (status == 0) 2425 continue; 2426 2427 if ((control & TXCTL_LAST) == 0) 2428 continue; 2429 2430 if (status & TXSTAT_TXERR) { 2431 afep->afe_errxmt++; 2432 2433 if (status & TXSTAT_JABBER) { 2434 /* transmit jabber timeout */ 2435 afep->afe_macxmt_errors++; 2436 } 2437 if (status & 2438 (TXSTAT_CARRLOST | TXSTAT_NOCARR)) { 2439 afep->afe_carrier_errors++; 2440 } 2441 if (status & TXSTAT_UFLOW) { 2442 afep->afe_underflow++; 2443 } 2444 if (status & TXSTAT_LATECOL) { 2445 afep->afe_tx_late_collisions++; 2446 } 2447 if (status & TXSTAT_EXCOLL) { 2448 afep->afe_ex_collisions++; 2449 afep->afe_collisions += 16; 2450 } 2451 } 2452 2453 if (status & TXSTAT_DEFER) { 2454 afep->afe_defer_xmts++; 2455 } 2456 2457 /* collision counting */ 2458 if (TXCOLLCNT(status) == 1) { 2459 afep->afe_collisions++; 2460 afep->afe_first_collisions++; 2461 } else if (TXCOLLCNT(status)) { 2462 afep->afe_collisions += TXCOLLCNT(status); 2463 afep->afe_multi_collisions += TXCOLLCNT(status); 2464 } 2465 } 2466 2467 if (afep->afe_txavail >= AFE_TXRESCHED) { 2468 if (afep->afe_wantw) { 2469 /* 2470 * we were able to reclaim some packets, so 2471 * disable tx interrupts 2472 */ 2473 afep->afe_wantw = B_FALSE; 2474 afe_enableinterrupts(afep); 2475 mac_tx_update(afep->afe_mh); 2476 } 2477 } 2478 } 2479 2480 mblk_t * 2481 afe_receive(afe_t *afep) 2482 { 2483 unsigned len; 2484 afe_rxbuf_t *rxb; 2485 afe_desc_t *rmd; 2486 uint32_t status; 2487 mblk_t *mpchain, **mpp, *mp; 2488 int head, cnt; 2489 2490 mpchain = NULL; 2491 mpp = &mpchain; 2492 head = afep->afe_rxhead; 2493 2494 /* limit the number of packets we process to a half ring size */ 2495 for (cnt = 0; cnt < AFE_RXRING / 2; cnt++) { 2496 2497 DBG(DRECV, "receive at index %d", head); 2498 2499 rmd = &afep->afe_rxdescp[head]; 2500 rxb = afep->afe_rxbufs[head]; 2501 2502 SYNCRXDESC(afep, head, DDI_DMA_SYNC_FORKERNEL); 2503 status = GETRXDESC(afep, rmd->desc_status); 2504 if (status & RXSTAT_OWN) { 2505 /* chip is still chewing on it */ 2506 break; 2507 } 2508 2509 /* discard the ethernet frame checksum */ 2510 len = RXLENGTH(status) - ETHERFCSL; 2511 2512 DBG(DRECV, "recv length %d, status %x", len, status); 2513 2514 if ((status & (RXSTAT_ERRS | RXSTAT_FIRST | RXSTAT_LAST)) != 2515 (RXSTAT_FIRST | RXSTAT_LAST)) { 2516 2517 afep->afe_errrcv++; 2518 2519 /* 2520 * Abnormal status bits detected, analyze further. 2521 */ 2522 if ((status & (RXSTAT_LAST|RXSTAT_FIRST)) != 2523 (RXSTAT_LAST|RXSTAT_FIRST)) { 2524 DBG(DRECV, "rx packet overspill"); 2525 if (status & RXSTAT_FIRST) { 2526 afep->afe_toolong_errors++; 2527 } 2528 } else if (status & RXSTAT_DESCERR) { 2529 afep->afe_macrcv_errors++; 2530 2531 } else if (status & RXSTAT_RUNT) { 2532 afep->afe_runt++; 2533 2534 } else if (status & RXSTAT_COLLSEEN) { 2535 /* this should really be rx_late_collisions */ 2536 afep->afe_macrcv_errors++; 2537 2538 } else if (status & RXSTAT_DRIBBLE) { 2539 afep->afe_align_errors++; 2540 2541 } else if (status & RXSTAT_CRCERR) { 2542 afep->afe_fcs_errors++; 2543 2544 } else if (status & RXSTAT_OFLOW) { 2545 afep->afe_overflow++; 2546 } 2547 } 2548 2549 else if (len > ETHERVLANMTU) { 2550 afep->afe_errrcv++; 2551 afep->afe_toolong_errors++; 2552 } 2553 2554 /* 2555 * At this point, the chip thinks the packet is OK. 2556 */ 2557 else { 2558 mp = allocb(len + AFE_HEADROOM, 0); 2559 if (mp == NULL) { 2560 afep->afe_errrcv++; 2561 afep->afe_norcvbuf++; 2562 goto skip; 2563 } 2564 2565 /* sync the buffer before we look at it */ 2566 SYNCRXBUF(rxb, len, DDI_DMA_SYNC_FORKERNEL); 2567 mp->b_rptr += AFE_HEADROOM; 2568 mp->b_wptr = mp->b_rptr + len; 2569 bcopy((char *)rxb->rxb_buf, mp->b_rptr, len); 2570 2571 afep->afe_ipackets++; 2572 afep->afe_rbytes += len; 2573 if (status & RXSTAT_GROUP) { 2574 if (bcmp(mp->b_rptr, afe_broadcast, 2575 ETHERADDRL) == 0) 2576 afep->afe_brdcstrcv++; 2577 else 2578 afep->afe_multircv++; 2579 } 2580 *mpp = mp; 2581 mpp = &mp->b_next; 2582 } 2583 2584 skip: 2585 /* return ring entry to the hardware */ 2586 PUTRXDESC(afep, rmd->desc_status, RXSTAT_OWN); 2587 SYNCRXDESC(afep, head, DDI_DMA_SYNC_FORDEV); 2588 2589 /* advance to next RMD */ 2590 head = (head + 1) % AFE_RXRING; 2591 } 2592 2593 afep->afe_rxhead = head; 2594 2595 return (mpchain); 2596 } 2597 2598 int 2599 afe_getmiibit(afe_t *afep, uint16_t reg, uint16_t bit) 2600 { 2601 unsigned val; 2602 2603 mutex_enter(&afep->afe_xmtlock); 2604 if (afep->afe_flags & AFE_SUSPENDED) { 2605 mutex_exit(&afep->afe_xmtlock); 2606 /* device is suspended */ 2607 return (0); 2608 } 2609 val = afe_miiread(afep, afep->afe_phyaddr, reg); 2610 mutex_exit(&afep->afe_xmtlock); 2611 2612 return (val & bit ? 1 : 0); 2613 } 2614 #define GETMIIBIT(reg, bit) afe_getmiibit(afep, reg, bit) 2615 2616 int 2617 afe_m_stat(void *arg, uint_t stat, uint64_t *val) 2618 { 2619 afe_t *afep = arg; 2620 2621 mutex_enter(&afep->afe_xmtlock); 2622 if ((afep->afe_flags & (AFE_RUNNING|AFE_SUSPENDED)) == AFE_RUNNING) 2623 afe_reclaim(afep); 2624 mutex_exit(&afep->afe_xmtlock); 2625 2626 switch (stat) { 2627 case MAC_STAT_IFSPEED: 2628 *val = afep->afe_ifspeed; 2629 break; 2630 2631 case MAC_STAT_MULTIRCV: 2632 *val = afep->afe_multircv; 2633 break; 2634 2635 case MAC_STAT_BRDCSTRCV: 2636 *val = afep->afe_brdcstrcv; 2637 break; 2638 2639 case MAC_STAT_MULTIXMT: 2640 *val = afep->afe_multixmt; 2641 break; 2642 2643 case MAC_STAT_BRDCSTXMT: 2644 *val = afep->afe_brdcstxmt; 2645 break; 2646 2647 case MAC_STAT_IPACKETS: 2648 *val = afep->afe_ipackets; 2649 break; 2650 2651 case MAC_STAT_RBYTES: 2652 *val = afep->afe_rbytes; 2653 break; 2654 2655 case MAC_STAT_OPACKETS: 2656 *val = afep->afe_opackets; 2657 break; 2658 2659 case MAC_STAT_OBYTES: 2660 *val = afep->afe_obytes; 2661 break; 2662 2663 case MAC_STAT_NORCVBUF: 2664 *val = afep->afe_norcvbuf; 2665 break; 2666 2667 case MAC_STAT_NOXMTBUF: 2668 *val = 0; 2669 break; 2670 2671 case MAC_STAT_COLLISIONS: 2672 *val = afep->afe_collisions; 2673 break; 2674 2675 case MAC_STAT_IERRORS: 2676 *val = afep->afe_errrcv; 2677 break; 2678 2679 case MAC_STAT_OERRORS: 2680 *val = afep->afe_errxmt; 2681 break; 2682 2683 case ETHER_STAT_LINK_DUPLEX: 2684 *val = afep->afe_duplex; 2685 break; 2686 2687 case ETHER_STAT_ALIGN_ERRORS: 2688 *val = afep->afe_align_errors; 2689 break; 2690 2691 case ETHER_STAT_FCS_ERRORS: 2692 *val = afep->afe_fcs_errors; 2693 break; 2694 2695 case ETHER_STAT_SQE_ERRORS: 2696 *val = afep->afe_sqe_errors; 2697 break; 2698 2699 case ETHER_STAT_DEFER_XMTS: 2700 *val = afep->afe_defer_xmts; 2701 break; 2702 2703 case ETHER_STAT_FIRST_COLLISIONS: 2704 *val = afep->afe_first_collisions; 2705 break; 2706 2707 case ETHER_STAT_MULTI_COLLISIONS: 2708 *val = afep->afe_multi_collisions; 2709 break; 2710 2711 case ETHER_STAT_TX_LATE_COLLISIONS: 2712 *val = afep->afe_tx_late_collisions; 2713 break; 2714 2715 case ETHER_STAT_EX_COLLISIONS: 2716 *val = afep->afe_ex_collisions; 2717 break; 2718 2719 case ETHER_STAT_MACXMT_ERRORS: 2720 *val = afep->afe_macxmt_errors; 2721 break; 2722 2723 case ETHER_STAT_CARRIER_ERRORS: 2724 *val = afep->afe_carrier_errors; 2725 break; 2726 2727 case ETHER_STAT_TOOLONG_ERRORS: 2728 *val = afep->afe_toolong_errors; 2729 break; 2730 2731 case ETHER_STAT_MACRCV_ERRORS: 2732 *val = afep->afe_macrcv_errors; 2733 break; 2734 2735 case MAC_STAT_OVERFLOWS: 2736 *val = afep->afe_overflow; 2737 break; 2738 2739 case MAC_STAT_UNDERFLOWS: 2740 *val = afep->afe_underflow; 2741 break; 2742 2743 case ETHER_STAT_TOOSHORT_ERRORS: 2744 *val = afep->afe_runt; 2745 break; 2746 2747 case ETHER_STAT_JABBER_ERRORS: 2748 *val = afep->afe_jabber; 2749 break; 2750 2751 case ETHER_STAT_CAP_100T4: 2752 *val = afep->afe_cap_100T4; 2753 break; 2754 2755 case ETHER_STAT_CAP_100FDX: 2756 *val = afep->afe_cap_100fdx; 2757 break; 2758 2759 case ETHER_STAT_CAP_100HDX: 2760 *val = afep->afe_cap_100hdx; 2761 break; 2762 2763 case ETHER_STAT_CAP_10FDX: 2764 *val = afep->afe_cap_10fdx; 2765 break; 2766 2767 case ETHER_STAT_CAP_10HDX: 2768 *val = afep->afe_cap_10hdx; 2769 break; 2770 2771 case ETHER_STAT_CAP_AUTONEG: 2772 *val = afep->afe_cap_aneg; 2773 break; 2774 2775 case ETHER_STAT_LINK_AUTONEG: 2776 *val = ((afep->afe_adv_aneg != 0) && 2777 (GETMIIBIT(MII_AN_LPABLE, MII_AN_EXP_LPCANAN) != 0)); 2778 break; 2779 2780 case ETHER_STAT_ADV_CAP_100T4: 2781 *val = afep->afe_adv_100T4; 2782 break; 2783 2784 case ETHER_STAT_ADV_CAP_100FDX: 2785 *val = afep->afe_adv_100fdx; 2786 break; 2787 2788 case ETHER_STAT_ADV_CAP_100HDX: 2789 *val = afep->afe_adv_100hdx; 2790 break; 2791 2792 case ETHER_STAT_ADV_CAP_10FDX: 2793 *val = afep->afe_adv_10fdx; 2794 break; 2795 2796 case ETHER_STAT_ADV_CAP_10HDX: 2797 *val = afep->afe_adv_10hdx; 2798 break; 2799 2800 case ETHER_STAT_ADV_CAP_AUTONEG: 2801 *val = afep->afe_adv_aneg; 2802 break; 2803 2804 case ETHER_STAT_LP_CAP_100T4: 2805 *val = GETMIIBIT(MII_AN_LPABLE, MII_ABILITY_100BASE_T4); 2806 break; 2807 2808 case ETHER_STAT_LP_CAP_100FDX: 2809 *val = GETMIIBIT(MII_AN_LPABLE, MII_ABILITY_100BASE_TX_FD); 2810 break; 2811 2812 case ETHER_STAT_LP_CAP_100HDX: 2813 *val = GETMIIBIT(MII_AN_LPABLE, MII_ABILITY_100BASE_TX); 2814 break; 2815 2816 case ETHER_STAT_LP_CAP_10FDX: 2817 *val = GETMIIBIT(MII_AN_LPABLE, MII_ABILITY_10BASE_T_FD); 2818 break; 2819 2820 case ETHER_STAT_LP_CAP_10HDX: 2821 *val = GETMIIBIT(MII_AN_LPABLE, MII_ABILITY_10BASE_T); 2822 break; 2823 2824 case ETHER_STAT_LP_CAP_AUTONEG: 2825 *val = GETMIIBIT(MII_AN_EXPANSION, MII_AN_EXP_LPCANAN); 2826 break; 2827 2828 case ETHER_STAT_XCVR_ADDR: 2829 *val = afep->afe_phyaddr; 2830 break; 2831 2832 case ETHER_STAT_XCVR_ID: 2833 *val = afep->afe_phyid; 2834 break; 2835 2836 default: 2837 return (ENOTSUP); 2838 } 2839 return (0); 2840 } 2841 2842 /*ARGSUSED*/ 2843 int 2844 afe_m_getprop(void *arg, const char *name, mac_prop_id_t num, uint_t flags, 2845 uint_t sz, void *val, uint_t *perm) 2846 { 2847 afe_t *afep = arg; 2848 int err = 0; 2849 boolean_t dfl = flags & MAC_PROP_DEFAULT; 2850 2851 if (sz == 0) 2852 return (EINVAL); 2853 2854 *perm = MAC_PROP_PERM_RW; 2855 switch (num) { 2856 case MAC_PROP_DUPLEX: 2857 *perm = MAC_PROP_PERM_READ; 2858 if (sz >= sizeof (link_duplex_t)) { 2859 bcopy(&afep->afe_duplex, val, sizeof (link_duplex_t)); 2860 } else { 2861 err = EINVAL; 2862 } 2863 break; 2864 2865 case MAC_PROP_SPEED: 2866 *perm = MAC_PROP_PERM_READ; 2867 if (sz >= sizeof (uint64_t)) { 2868 bcopy(&afep->afe_ifspeed, val, sizeof (uint64_t)); 2869 } else { 2870 err = EINVAL; 2871 } 2872 break; 2873 2874 case MAC_PROP_AUTONEG: 2875 *(uint8_t *)val = 2876 dfl ? afep->afe_cap_aneg : afep->afe_adv_aneg; 2877 break; 2878 2879 #if 0 2880 case MAC_PROP_ADV_1000FDX_CAP: 2881 case MAC_PROP_EN_1000FDX_CAP: 2882 case MAC_PROP_ADV_1000HDX_CAP: 2883 case MAC_PROP_EN_1000HDX_CAP: 2884 /* We don't support gigabit! */ 2885 *(uint8_t *)val = 0; 2886 break; 2887 #endif 2888 2889 case MAC_PROP_ADV_100FDX_CAP: 2890 *perm = MAC_PROP_PERM_READ; 2891 *(uint8_t *)val = 2892 dfl ? afep->afe_cap_100fdx : afep->afe_adv_100fdx; 2893 break; 2894 case MAC_PROP_EN_100FDX_CAP: 2895 *(uint8_t *)val = 2896 dfl ? afep->afe_cap_100fdx : afep->afe_adv_100fdx; 2897 break; 2898 2899 case MAC_PROP_ADV_100HDX_CAP: 2900 *perm = MAC_PROP_PERM_READ; 2901 *(uint8_t *)val = 2902 dfl ? afep->afe_cap_100hdx : afep->afe_adv_100hdx; 2903 break; 2904 case MAC_PROP_EN_100HDX_CAP: 2905 *(uint8_t *)val = 2906 dfl ? afep->afe_cap_100hdx : afep->afe_adv_100hdx; 2907 break; 2908 2909 case MAC_PROP_ADV_10FDX_CAP: 2910 *perm = MAC_PROP_PERM_READ; 2911 *(uint8_t *)val = 2912 dfl ? afep->afe_cap_10fdx : afep->afe_adv_10fdx; 2913 break; 2914 case MAC_PROP_EN_10FDX_CAP: 2915 *(uint8_t *)val = 2916 dfl ? afep->afe_cap_10fdx : afep->afe_adv_10fdx; 2917 break; 2918 2919 case MAC_PROP_ADV_10HDX_CAP: 2920 *perm = MAC_PROP_PERM_READ; 2921 *(uint8_t *)val = 2922 dfl ? afep->afe_cap_10hdx : afep->afe_adv_10hdx; 2923 break; 2924 case MAC_PROP_EN_10HDX_CAP: 2925 *(uint8_t *)val = 2926 dfl ? afep->afe_cap_10hdx : afep->afe_adv_10hdx; 2927 break; 2928 2929 case MAC_PROP_ADV_100T4_CAP: 2930 *perm = MAC_PROP_PERM_READ; 2931 *(uint8_t *)val = 2932 dfl ? afep->afe_cap_100T4 : afep->afe_adv_100T4; 2933 break; 2934 case MAC_PROP_EN_100T4_CAP: 2935 *(uint8_t *)val = 2936 dfl ? afep->afe_cap_100T4 : afep->afe_adv_100T4; 2937 break; 2938 2939 default: 2940 err = ENOTSUP; 2941 } 2942 2943 return (err); 2944 } 2945 2946 /*ARGSUSED*/ 2947 int 2948 afe_m_setprop(void *arg, const char *name, mac_prop_id_t num, uint_t sz, 2949 const void *val) 2950 { 2951 afe_t *afep = arg; 2952 uint8_t *advp; 2953 uint8_t *capp; 2954 2955 switch (num) { 2956 case MAC_PROP_EN_100FDX_CAP: 2957 advp = &afep->afe_adv_100fdx; 2958 capp = &afep->afe_cap_100fdx; 2959 break; 2960 2961 case MAC_PROP_EN_100HDX_CAP: 2962 advp = &afep->afe_adv_100hdx; 2963 capp = &afep->afe_cap_100hdx; 2964 break; 2965 2966 case MAC_PROP_EN_10FDX_CAP: 2967 advp = &afep->afe_adv_10fdx; 2968 capp = &afep->afe_cap_10fdx; 2969 break; 2970 2971 case MAC_PROP_EN_10HDX_CAP: 2972 advp = &afep->afe_adv_10hdx; 2973 capp = &afep->afe_cap_10hdx; 2974 break; 2975 2976 case MAC_PROP_EN_100T4_CAP: 2977 advp = &afep->afe_adv_100T4; 2978 capp = &afep->afe_cap_100T4; 2979 break; 2980 2981 case MAC_PROP_AUTONEG: 2982 advp = &afep->afe_adv_aneg; 2983 capp = &afep->afe_cap_aneg; 2984 break; 2985 2986 default: 2987 return (ENOTSUP); 2988 } 2989 2990 if (*capp == 0) /* ensure phy can support value */ 2991 return (ENOTSUP); 2992 2993 mutex_enter(&afep->afe_intrlock); 2994 mutex_enter(&afep->afe_xmtlock); 2995 2996 if (*advp != *(const uint8_t *)val) { 2997 *advp = *(const uint8_t *)val; 2998 2999 if ((afep->afe_flags & (AFE_RUNNING|AFE_SUSPENDED)) == 3000 AFE_RUNNING) { 3001 /* 3002 * This re-initializes the phy, but it also 3003 * restarts transmit and receive rings. 3004 * Needless to say, changing the link 3005 * parameters is destructive to traffic in 3006 * progress. 3007 */ 3008 afe_resetall(afep); 3009 } 3010 } 3011 mutex_exit(&afep->afe_xmtlock); 3012 mutex_exit(&afep->afe_intrlock); 3013 3014 return (0); 3015 } 3016 3017 /* 3018 * Debugging and error reporting. 3019 */ 3020 void 3021 afe_error(dev_info_t *dip, char *fmt, ...) 3022 { 3023 va_list ap; 3024 char buf[256]; 3025 3026 va_start(ap, fmt); 3027 (void) vsnprintf(buf, sizeof (buf), fmt, ap); 3028 va_end(ap); 3029 3030 if (dip) { 3031 cmn_err(CE_WARN, "%s%d: %s", 3032 ddi_driver_name(dip), ddi_get_instance(dip), buf); 3033 } else { 3034 cmn_err(CE_WARN, "afe: %s", buf); 3035 } 3036 } 3037 3038 #ifdef DEBUG 3039 3040 void 3041 afe_dprintf(afe_t *afep, const char *func, int level, char *fmt, ...) 3042 { 3043 va_list ap; 3044 3045 va_start(ap, fmt); 3046 if (afe_debug & level) { 3047 char tag[64]; 3048 char buf[256]; 3049 3050 if (afep && afep->afe_dip) { 3051 (void) snprintf(tag, sizeof (tag), "%s%d", 3052 ddi_driver_name(afep->afe_dip), 3053 ddi_get_instance(afep->afe_dip)); 3054 } else { 3055 (void) snprintf(tag, sizeof (tag), "afe"); 3056 } 3057 3058 (void) snprintf(buf, sizeof (buf), "%s: %s: %s\n", 3059 tag, func, fmt); 3060 3061 vcmn_err(CE_CONT, buf, ap); 3062 } 3063 va_end(ap); 3064 } 3065 3066 #endif 3067