1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright (c) 1999 by Sun Microsystems, Inc. 24 * All rights reserved. 25 */ 26 27 #ifndef _RESET_INFO_H 28 #define _RESET_INFO_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* 37 * All of the following data structures and defines come from sun4u server 38 * POST. If the data in POST changes, then these structures must reflect 39 * those changes. 40 */ 41 42 #include <sys/fhc.h> /* To get MAX_BOARDS constant */ 43 44 /* BDA bit assignments */ 45 #define BOARD_PRESENT (1<<0) 46 #define BOARD_OK (1<<1) 47 #define BOARD_TYPE_MSK (7<<2) 48 #define BOARD_TYPE(x) (((x) & BOARD_TYPE_MSK) >> 2) 49 50 /* Board state mask and defines */ 51 #define BD_STATE_MASK 0x3 52 #define BD_LPM_FZN 0 53 #define BD_ONLINE_FAIL 1 54 #define BD_NOT_PRESENT 2 55 #define BD_ONLINE_NORMAL 3 56 57 /* define CPU 0 fields */ 58 #define CPU0_PRESENT (1<<8) 59 #define CPU0_OK (1<<9) 60 #define CPU0_FAIL_CODE_MSK (7<<10) 61 62 /* define CPU 1 fields */ 63 #define CPU1_PRESENT (1<<16) 64 #define CPU1_OK (1<<17) 65 #define CPU1_FAIL_CODE_MSK (7<<18) 66 67 /* supported board types */ 68 #define CPU_TYPE 0 69 #define MEM_TYPE 1 /* CPU/MEM board with only memory */ 70 #define IO_TYPE1 2 71 #define IO_TYPE2 3 72 #define IO_TYPE3 4 73 #define IO_TYPE4 5 /* same as IO TYPE 1 but no HM or PHY chip */ 74 #define CLOCK_TYPE 7 75 76 /* for CPU type UPA ports */ 77 typedef struct { 78 u_longlong_t afsr; /* Fault status register for CPU */ 79 u_longlong_t afar; /* Fault address register for CPU */ 80 } cpu_reset_state; 81 82 /* For the clock board */ 83 typedef struct { 84 unsigned long clk_ssr_1; /* reset status for the clock board */ 85 } clock_reset_state; 86 87 struct board_info { 88 u_longlong_t board_desc; 89 cpu_reset_state cpu[2]; /* could be a CPU */ 90 u_longlong_t ac_error_status; 91 u_longlong_t dc_shadow_chain; 92 uint_t fhc_csr; 93 uint_t fhc_rcsr; 94 }; 95 96 struct reset_info { 97 int length; /* size of the structure */ 98 int version; /* Version of the structure */ 99 struct board_info bd_reset_info[MAX_BOARDS]; 100 clock_reset_state clk; /* one clock board */ 101 unsigned char tod_timestamp[7]; 102 }; 103 104 #ifdef __cplusplus 105 } 106 #endif 107 108 #endif /* _RESET_INFO_H */ 109