1 /************************************************************************** 2 * 3 * tlan.c -- Etherboot device driver for the Texas Instruments ThunderLAN 4 * Written 2003-2003 by Timothy Legge <tlegge@rogers.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 * 20 * Portions of this code (almost all) based on: 21 * tlan.c: Linux ThunderLan Driver: 22 * 23 * by James Banks 24 * 25 * (C) 1997-1998 Caldera, Inc. 26 * (C) 1998 James Banks 27 * (C) 1999-2001 Torben Mathiasen 28 * (C) 2002 Samuel Chessman 29 * 30 * REVISION HISTORY: 31 * ================ 32 * v1.0 07-08-2003 timlegge Initial not quite working version 33 * 34 * Indent Style: indent -kr -i8 35 ***************************************************************************/ 36 37 /* 38 #include <asm/io.h> 39 #include <asm/types.h> 40 #include <linux/netdevice.h> 41 */ 42 43 typedef unsigned char u8; 44 typedef signed char s8; 45 typedef unsigned short u16; 46 typedef signed short s16; 47 typedef unsigned int u32; 48 typedef signed int s32; 49 /***************************************************************** 50 * TLan Definitions 51 * 52 ****************************************************************/ 53 54 #define FALSE 0 55 #define TRUE 1 56 57 #define TLAN_MIN_FRAME_SIZE 64 58 #define TLAN_MAX_FRAME_SIZE 1600 59 60 #define TLAN_NUM_RX_LISTS 4 61 #define TLAN_NUM_TX_LISTS 2 62 63 #define TLAN_IGNORE 0 64 #define TLAN_RECORD 1 65 /* 66 #define TLAN_DBG(lvl, format, args...) if (debug&lvl) printf("TLAN: " format, ##args ); 67 */ 68 #define TLAN_DEBUG_GNRL 0x0001 69 #define TLAN_DEBUG_TX 0x0002 70 #define TLAN_DEBUG_RX 0x0004 71 #define TLAN_DEBUG_LIST 0x0008 72 #define TLAN_DEBUG_PROBE 0x0010 73 74 #define TX_TIMEOUT (10*HZ) /* We need time for auto-neg */ 75 #define MAX_TLAN_BOARDS 8 /* Max number of boards installed at a time */ 76 77 78 /***************************************************************** 79 * Device Identification Definitions 80 * 81 ****************************************************************/ 82 83 #define PCI_DEVICE_ID_NETELLIGENT_10_T2 0xB012 84 #define PCI_DEVICE_ID_NETELLIGENT_10_100_WS_5100 0xB030 85 #ifndef PCI_DEVICE_ID_OLICOM_OC2183 86 #define PCI_DEVICE_ID_OLICOM_OC2183 0x0013 87 #endif 88 #ifndef PCI_DEVICE_ID_OLICOM_OC2325 89 #define PCI_DEVICE_ID_OLICOM_OC2325 0x0012 90 #endif 91 #ifndef PCI_DEVICE_ID_OLICOM_OC2326 92 #define PCI_DEVICE_ID_OLICOM_OC2326 0x0014 93 #endif 94 95 typedef struct tlan_adapter_entry { 96 u16 vendorId; 97 u16 deviceId; 98 char *deviceLabel; 99 u32 flags; 100 u16 addrOfs; 101 } TLanAdapterEntry; 102 103 #define TLAN_ADAPTER_NONE 0x00000000 104 #define TLAN_ADAPTER_UNMANAGED_PHY 0x00000001 105 #define TLAN_ADAPTER_BIT_RATE_PHY 0x00000002 106 #define TLAN_ADAPTER_USE_INTERN_10 0x00000004 107 #define TLAN_ADAPTER_ACTIVITY_LED 0x00000008 108 109 #define TLAN_SPEED_DEFAULT 0 110 #define TLAN_SPEED_10 10 111 #define TLAN_SPEED_100 100 112 113 #define TLAN_DUPLEX_DEFAULT 0 114 #define TLAN_DUPLEX_HALF 1 115 #define TLAN_DUPLEX_FULL 2 116 117 118 119 /***************************************************************** 120 * EISA Definitions 121 * 122 ****************************************************************/ 123 124 #define EISA_ID 0xc80 /* EISA ID Registers */ 125 #define EISA_ID0 0xc80 /* EISA ID Register 0 */ 126 #define EISA_ID1 0xc81 /* EISA ID Register 1 */ 127 #define EISA_ID2 0xc82 /* EISA ID Register 2 */ 128 #define EISA_ID3 0xc83 /* EISA ID Register 3 */ 129 #define EISA_CR 0xc84 /* EISA Control Register */ 130 #define EISA_REG0 0xc88 /* EISA Configuration Register 0 */ 131 #define EISA_REG1 0xc89 /* EISA Configuration Register 1 */ 132 #define EISA_REG2 0xc8a /* EISA Configuration Register 2 */ 133 #define EISA_REG3 0xc8f /* EISA Configuration Register 3 */ 134 #define EISA_APROM 0xc90 /* Ethernet Address PROM */ 135 136 137 138 /***************************************************************** 139 * Rx/Tx List Definitions 140 * 141 ****************************************************************/ 142 143 #define TLAN_BUFFERS_PER_LIST 10 144 #define TLAN_LAST_BUFFER 0x80000000 145 #define TLAN_CSTAT_UNUSED 0x8000 146 #define TLAN_CSTAT_FRM_CMP 0x4000 147 #define TLAN_CSTAT_READY 0x3000 148 #define TLAN_CSTAT_EOC 0x0800 149 #define TLAN_CSTAT_RX_ERROR 0x0400 150 #define TLAN_CSTAT_PASS_CRC 0x0200 151 #define TLAN_CSTAT_DP_PR 0x0100 152 153 154 155 156 157 158 /***************************************************************** 159 * PHY definitions 160 * 161 ****************************************************************/ 162 163 #define TLAN_PHY_MAX_ADDR 0x1F 164 #define TLAN_PHY_NONE 0x20 165 166 167 168 /***************************************************************** 169 * TLan Driver Timer Definitions 170 * 171 ****************************************************************/ 172 173 #define TLAN_TIMER_LINK_BEAT 1 174 #define TLAN_TIMER_ACTIVITY 2 175 #define TLAN_TIMER_PHY_PDOWN 3 176 #define TLAN_TIMER_PHY_PUP 4 177 #define TLAN_TIMER_PHY_RESET 5 178 #define TLAN_TIMER_PHY_START_LINK 6 179 #define TLAN_TIMER_PHY_FINISH_AN 7 180 #define TLAN_TIMER_FINISH_RESET 8 181 182 #define TLAN_TIMER_ACT_DELAY (HZ/10) 183 184 185 186 187 /***************************************************************** 188 * TLan Driver Eeprom Definitions 189 * 190 ****************************************************************/ 191 192 #define TLAN_EEPROM_ACK 0 193 #define TLAN_EEPROM_STOP 1 194 195 196 197 198 /***************************************************************** 199 * Host Register Offsets and Contents 200 * 201 ****************************************************************/ 202 203 #define TLAN_HOST_CMD 0x00 204 #define TLAN_HC_GO 0x80000000 205 #define TLAN_HC_STOP 0x40000000 206 #define TLAN_HC_ACK 0x20000000 207 #define TLAN_HC_CS_MASK 0x1FE00000 208 #define TLAN_HC_EOC 0x00100000 209 #define TLAN_HC_RT 0x00080000 210 #define TLAN_HC_NES 0x00040000 211 #define TLAN_HC_AD_RST 0x00008000 212 #define TLAN_HC_LD_TMR 0x00004000 213 #define TLAN_HC_LD_THR 0x00002000 214 #define TLAN_HC_REQ_INT 0x00001000 215 #define TLAN_HC_INT_OFF 0x00000800 216 #define TLAN_HC_INT_ON 0x00000400 217 #define TLAN_HC_AC_MASK 0x000000FF 218 #define TLAN_CH_PARM 0x04 219 #define TLAN_DIO_ADR 0x08 220 #define TLAN_DA_ADR_INC 0x8000 221 #define TLAN_DA_RAM_ADR 0x4000 222 #define TLAN_HOST_INT 0x0A 223 #define TLAN_HI_IV_MASK 0x1FE0 224 #define TLAN_HI_IT_MASK 0x001C 225 #define TLAN_DIO_DATA 0x0C 226 227 228 /* ThunderLAN Internal Register DIO Offsets */ 229 230 #define TLAN_NET_CMD 0x00 231 #define TLAN_NET_CMD_NRESET 0x80 232 #define TLAN_NET_CMD_NWRAP 0x40 233 #define TLAN_NET_CMD_CSF 0x20 234 #define TLAN_NET_CMD_CAF 0x10 235 #define TLAN_NET_CMD_NOBRX 0x08 236 #define TLAN_NET_CMD_DUPLEX 0x04 237 #define TLAN_NET_CMD_TRFRAM 0x02 238 #define TLAN_NET_CMD_TXPACE 0x01 239 #define TLAN_NET_SIO 0x01 240 #define TLAN_NET_SIO_MINTEN 0x80 241 #define TLAN_NET_SIO_ECLOK 0x40 242 #define TLAN_NET_SIO_ETXEN 0x20 243 #define TLAN_NET_SIO_EDATA 0x10 244 #define TLAN_NET_SIO_NMRST 0x08 245 #define TLAN_NET_SIO_MCLK 0x04 246 #define TLAN_NET_SIO_MTXEN 0x02 247 #define TLAN_NET_SIO_MDATA 0x01 248 #define TLAN_NET_STS 0x02 249 #define TLAN_NET_STS_MIRQ 0x80 250 #define TLAN_NET_STS_HBEAT 0x40 251 #define TLAN_NET_STS_TXSTOP 0x20 252 #define TLAN_NET_STS_RXSTOP 0x10 253 #define TLAN_NET_STS_RSRVD 0x0F 254 #define TLAN_NET_MASK 0x03 255 #define TLAN_NET_MASK_MASK7 0x80 256 #define TLAN_NET_MASK_MASK6 0x40 257 #define TLAN_NET_MASK_MASK5 0x20 258 #define TLAN_NET_MASK_MASK4 0x10 259 #define TLAN_NET_MASK_RSRVD 0x0F 260 #define TLAN_NET_CONFIG 0x04 261 #define TLAN_NET_CFG_RCLK 0x8000 262 #define TLAN_NET_CFG_TCLK 0x4000 263 #define TLAN_NET_CFG_BIT 0x2000 264 #define TLAN_NET_CFG_RXCRC 0x1000 265 #define TLAN_NET_CFG_PEF 0x0800 266 #define TLAN_NET_CFG_1FRAG 0x0400 267 #define TLAN_NET_CFG_1CHAN 0x0200 268 #define TLAN_NET_CFG_MTEST 0x0100 269 #define TLAN_NET_CFG_PHY_EN 0x0080 270 #define TLAN_NET_CFG_MSMASK 0x007F 271 #define TLAN_MAN_TEST 0x06 272 #define TLAN_DEF_VENDOR_ID 0x08 273 #define TLAN_DEF_DEVICE_ID 0x0A 274 #define TLAN_DEF_REVISION 0x0C 275 #define TLAN_DEF_SUBCLASS 0x0D 276 #define TLAN_DEF_MIN_LAT 0x0E 277 #define TLAN_DEF_MAX_LAT 0x0F 278 #define TLAN_AREG_0 0x10 279 #define TLAN_AREG_1 0x16 280 #define TLAN_AREG_2 0x1C 281 #define TLAN_AREG_3 0x22 282 #define TLAN_HASH_1 0x28 283 #define TLAN_HASH_2 0x2C 284 #define TLAN_GOOD_TX_FRMS 0x30 285 #define TLAN_TX_UNDERUNS 0x33 286 #define TLAN_GOOD_RX_FRMS 0x34 287 #define TLAN_RX_OVERRUNS 0x37 288 #define TLAN_DEFERRED_TX 0x38 289 #define TLAN_CRC_ERRORS 0x3A 290 #define TLAN_CODE_ERRORS 0x3B 291 #define TLAN_MULTICOL_FRMS 0x3C 292 #define TLAN_SINGLECOL_FRMS 0x3E 293 #define TLAN_EXCESSCOL_FRMS 0x40 294 #define TLAN_LATE_COLS 0x41 295 #define TLAN_CARRIER_LOSS 0x42 296 #define TLAN_ACOMMIT 0x43 297 #define TLAN_LED_REG 0x44 298 #define TLAN_LED_ACT 0x10 299 #define TLAN_LED_LINK 0x01 300 #define TLAN_BSIZE_REG 0x45 301 #define TLAN_MAX_RX 0x46 302 #define TLAN_INT_DIS 0x48 303 #define TLAN_ID_TX_EOC 0x04 304 #define TLAN_ID_RX_EOF 0x02 305 #define TLAN_ID_RX_EOC 0x01 306 307 308 309 /* ThunderLAN Interrupt Codes */ 310 311 #define TLAN_INT_NUMBER_OF_INTS 8 312 313 #define TLAN_INT_NONE 0x0000 314 #define TLAN_INT_TX_EOF 0x0001 315 #define TLAN_INT_STAT_OVERFLOW 0x0002 316 #define TLAN_INT_RX_EOF 0x0003 317 #define TLAN_INT_DUMMY 0x0004 318 #define TLAN_INT_TX_EOC 0x0005 319 #define TLAN_INT_STATUS_CHECK 0x0006 320 #define TLAN_INT_RX_EOC 0x0007 321 322 323 324 /* ThunderLAN MII Registers */ 325 326 /* Generic MII/PHY Registers */ 327 328 #define MII_GEN_CTL 0x00 329 #define MII_GC_RESET 0x8000 330 #define MII_GC_LOOPBK 0x4000 331 #define MII_GC_SPEEDSEL 0x2000 332 #define MII_GC_AUTOENB 0x1000 333 #define MII_GC_PDOWN 0x0800 334 #define MII_GC_ISOLATE 0x0400 335 #define MII_GC_AUTORSRT 0x0200 336 #define MII_GC_DUPLEX 0x0100 337 #define MII_GC_COLTEST 0x0080 338 #define MII_GC_RESERVED 0x007F 339 #define MII_GEN_STS 0x01 340 #define MII_GS_100BT4 0x8000 341 #define MII_GS_100BTXFD 0x4000 342 #define MII_GS_100BTXHD 0x2000 343 #define MII_GS_10BTFD 0x1000 344 #define MII_GS_10BTHD 0x0800 345 #define MII_GS_RESERVED 0x07C0 346 #define MII_GS_AUTOCMPLT 0x0020 347 #define MII_GS_RFLT 0x0010 348 #define MII_GS_AUTONEG 0x0008 349 #define MII_GS_LINK 0x0004 350 #define MII_GS_JABBER 0x0002 351 #define MII_GS_EXTCAP 0x0001 352 #define MII_GEN_ID_HI 0x02 353 #define MII_GEN_ID_LO 0x03 354 #define MII_GIL_OUI 0xFC00 355 #define MII_GIL_MODEL 0x03F0 356 #define MII_GIL_REVISION 0x000F 357 #define MII_AN_ADV 0x04 358 #define MII_AN_LPA 0x05 359 #define MII_AN_EXP 0x06 360 361 /* ThunderLAN Specific MII/PHY Registers */ 362 363 #define TLAN_TLPHY_ID 0x10 364 #define TLAN_TLPHY_CTL 0x11 365 #define TLAN_TC_IGLINK 0x8000 366 #define TLAN_TC_SWAPOL 0x4000 367 #define TLAN_TC_AUISEL 0x2000 368 #define TLAN_TC_SQEEN 0x1000 369 #define TLAN_TC_MTEST 0x0800 370 #define TLAN_TC_RESERVED 0x07F8 371 #define TLAN_TC_NFEW 0x0004 372 #define TLAN_TC_INTEN 0x0002 373 #define TLAN_TC_TINT 0x0001 374 #define TLAN_TLPHY_STS 0x12 375 #define TLAN_TS_MINT 0x8000 376 #define TLAN_TS_PHOK 0x4000 377 #define TLAN_TS_POLOK 0x2000 378 #define TLAN_TS_TPENERGY 0x1000 379 #define TLAN_TS_RESERVED 0x0FFF 380 #define TLAN_TLPHY_PAR 0x19 381 #define TLAN_PHY_CIM_STAT 0x0020 382 #define TLAN_PHY_SPEED_100 0x0040 383 #define TLAN_PHY_DUPLEX_FULL 0x0080 384 #define TLAN_PHY_AN_EN_STAT 0x0400 385 386 /* National Sem. & Level1 PHY id's */ 387 #define NAT_SEM_ID1 0x2000 388 #define NAT_SEM_ID2 0x5C01 389 #define LEVEL1_ID1 0x7810 390 #define LEVEL1_ID2 0x0000 391 392 #define CIRC_INC( a, b ) if ( ++a >= b ) a = 0 393 394 /* Routines to access internal registers. */ 395 396 inline u8 TLan_DioRead8(u16 base_addr, u16 internal_addr) 397 { 398 outw(internal_addr, base_addr + TLAN_DIO_ADR); 399 return (inb((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x3))); 400 401 } /* TLan_DioRead8 */ 402 403 404 405 406 inline u16 TLan_DioRead16(u16 base_addr, u16 internal_addr) 407 { 408 outw(internal_addr, base_addr + TLAN_DIO_ADR); 409 return (inw((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x2))); 410 411 } /* TLan_DioRead16 */ 412 413 414 415 416 inline u32 TLan_DioRead32(u16 base_addr, u16 internal_addr) 417 { 418 outw(internal_addr, base_addr + TLAN_DIO_ADR); 419 return (inl(base_addr + TLAN_DIO_DATA)); 420 421 } /* TLan_DioRead32 */ 422 423 424 425 426 inline void TLan_DioWrite8(u16 base_addr, u16 internal_addr, u8 data) 427 { 428 outw(internal_addr, base_addr + TLAN_DIO_ADR); 429 outb(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x3)); 430 431 } 432 433 434 435 436 inline void TLan_DioWrite16(u16 base_addr, u16 internal_addr, u16 data) 437 { 438 outw(internal_addr, base_addr + TLAN_DIO_ADR); 439 outw(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2)); 440 441 } 442 443 444 445 446 inline void TLan_DioWrite32(u16 base_addr, u16 internal_addr, u32 data) 447 { 448 outw(internal_addr, base_addr + TLAN_DIO_ADR); 449 outl(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2)); 450 451 } 452 453 454 455 #if 0 456 inline void TLan_ClearBit(u8 bit, u16 port) 457 { 458 outb_p(inb_p(port) & ~bit, port); 459 } 460 461 462 463 464 inline int TLan_GetBit(u8 bit, u16 port) 465 { 466 return ((int) (inb_p(port) & bit)); 467 } 468 469 470 471 472 inline void TLan_SetBit(u8 bit, u16 port) 473 { 474 outb_p(inb_p(port) | bit, port); 475 } 476 #endif 477 478 #define TLan_ClearBit( bit, port ) outb_p(inb_p(port) & ~bit, port) 479 #define TLan_GetBit( bit, port ) ((int) (inb_p(port) & bit)) 480 #define TLan_SetBit( bit, port ) outb_p(inb_p(port) | bit, port) 481 482 #ifdef I_LIKE_A_FAST_HASH_FUNCTION 483 /* given 6 bytes, view them as 8 6-bit numbers and return the XOR of those */ 484 /* the code below is about seven times as fast as the original code */ 485 inline u32 TLan_HashFunc(u8 * a) 486 { 487 u8 hash; 488 489 hash = (a[0] ^ a[3]); /* & 077 */ 490 hash ^= ((a[0] ^ a[3]) >> 6); /* & 003 */ 491 hash ^= ((a[1] ^ a[4]) << 2); /* & 074 */ 492 hash ^= ((a[1] ^ a[4]) >> 4); /* & 017 */ 493 hash ^= ((a[2] ^ a[5]) << 4); /* & 060 */ 494 hash ^= ((a[2] ^ a[5]) >> 2); /* & 077 */ 495 496 return (hash & 077); 497 } 498 499 #else /* original code */ 500 501 inline u32 xor(u32 a, u32 b) 502 { 503 return ((a && !b) || (!a && b)); 504 } 505 506 #define XOR8( a, b, c, d, e, f, g, h ) xor( a, xor( b, xor( c, xor( d, xor( e, xor( f, xor( g, h ) ) ) ) ) ) ) 507 #define DA( a, bit ) ( ( (u8) a[bit/8] ) & ( (u8) ( 1 << bit%8 ) ) ) 508 509 inline u32 TLan_HashFunc(u8 * a) 510 { 511 u32 hash; 512 513 hash = 514 XOR8(DA(a, 0), DA(a, 6), DA(a, 12), DA(a, 18), DA(a, 24), 515 DA(a, 30), DA(a, 36), DA(a, 42)); 516 hash |= 517 XOR8(DA(a, 1), DA(a, 7), DA(a, 13), DA(a, 19), DA(a, 25), 518 DA(a, 31), DA(a, 37), DA(a, 43)) << 1; 519 hash |= 520 XOR8(DA(a, 2), DA(a, 8), DA(a, 14), DA(a, 20), DA(a, 26), 521 DA(a, 32), DA(a, 38), DA(a, 44)) << 2; 522 hash |= 523 XOR8(DA(a, 3), DA(a, 9), DA(a, 15), DA(a, 21), DA(a, 27), 524 DA(a, 33), DA(a, 39), DA(a, 45)) << 3; 525 hash |= 526 XOR8(DA(a, 4), DA(a, 10), DA(a, 16), DA(a, 22), DA(a, 28), 527 DA(a, 34), DA(a, 40), DA(a, 46)) << 4; 528 hash |= 529 XOR8(DA(a, 5), DA(a, 11), DA(a, 17), DA(a, 23), DA(a, 29), 530 DA(a, 35), DA(a, 41), DA(a, 47)) << 5; 531 532 return hash; 533 534 } 535 536 #endif /* I_LIKE_A_FAST_HASH_FUNCTION */ 537