xref: /titanic_41/usr/src/grub/grub-0.97/netboot/pcnet32.c (revision e4d060fb4c00d44cd578713eb9a921f594b733b8)
1 /**************************************************************************
2 *
3 *    pcnet32.c -- Etherboot device driver for the AMD PCnet32
4 *    Written 2003-2003 by Timothy Legge <tlegge@rogers.com>
5 *
6 *    This program is free software; you can redistribute it and/or modify
7 *    it under the terms of the GNU General Public License as published by
8 *    the Free Software Foundation; either version 2 of the License, or
9 *    (at your option) any later version.
10 *
11 *    This program is distributed in the hope that it will be useful,
12 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
13 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 *    GNU General Public License for more details.
15 *
16 *    You should have received a copy of the GNU General Public License
17 *    along with this program; if not, write to the Free Software
18 *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 *
20 *    Portions of this code based on:
21 *		pcnet32.c: An AMD PCnet32 ethernet driver for linux:
22 *
23 *	(C) 1996-1999 Thomas Bogendoerfer
24 *		See Linux Driver for full information
25 *
26 *	The transmit and poll functions were written with reference to:
27 *	lance.c - LANCE NIC driver for Etherboot written by Ken Yap
28 *
29 *	Linux Driver Version 1.27a, 10.02.2002
30 *
31 *
32 *    REVISION HISTORY:
33 *    ================
34 *    v1.0	08-06-2003	timlegge	Initial port of Linux driver
35 *    v1.1	08-23-2003	timlegge	Add multicast support
36 *    v1.2	01-17-2004	timlegge	Initial driver output cleanup
37 *    v1.3	03-29-2004	timlegge	More driver cleanup
38 *
39 *    Indent Options: indent -kr -i8
40 ***************************************************************************/
41 
42 /* to get some global routines like printf */
43 #include "etherboot.h"
44 /* to get the interface to the body of the program */
45 #include "nic.h"
46 /* to get the PCI support functions, if this is a PCI NIC */
47 #include "pci.h"
48 /* Include the time functions */
49 #include "timer.h"
50 #include "mii.h"
51 /* void hex_dump(const char *data, const unsigned int len); */
52 
53 /* Etherboot Specific definations */
54 #define drv_version "v1.3"
55 #define drv_date "03-29-2004"
56 
57 typedef unsigned char u8;
58 typedef signed char s8;
59 typedef unsigned short u16;
60 typedef signed short s16;
61 typedef unsigned int u32;
62 typedef signed int s32;
63 
64 static u32 ioaddr;		/* Globally used for the card's io address */
65 
66 #ifdef EDEBUG
67 #define dprintf(x) printf x
68 #else
69 #define dprintf(x)
70 #endif
71 
72 /* Condensed operations for readability. */
73 #define virt_to_le32desc(addr)  cpu_to_le32(virt_to_bus(addr))
74 #define le32desc_to_virt(addr)  bus_to_virt(le32_to_cpu(addr))
75 
76 /* End Etherboot Specific */
77 
78 int cards_found /* __initdata */ ;
79 
80 #ifdef REMOVE
81 /* FIXME: Remove these they are probably pointless */
82 
83 /*
84  * VLB I/O addresses
85  */
86 static unsigned int pcnet32_portlist[] /*__initdata */  =
87 { 0x300, 0x320, 0x340, 0x360, 0 };
88 
89 static int pcnet32_debug = 1;
90 static int tx_start = 1;	/* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
91 static int pcnet32vlb;		/* check for VLB cards ? */
92 
93 static struct net_device *pcnet32_dev;
94 
95 static int max_interrupt_work = 80;
96 static int rx_copybreak = 200;
97 #endif
98 #define PCNET32_PORT_AUI      0x00
99 #define PCNET32_PORT_10BT     0x01
100 #define PCNET32_PORT_GPSI     0x02
101 #define PCNET32_PORT_MII      0x03
102 
103 #define PCNET32_PORT_PORTSEL  0x03
104 #define PCNET32_PORT_ASEL     0x04
105 #define PCNET32_PORT_100      0x40
106 #define PCNET32_PORT_FD	      0x80
107 
108 #define PCNET32_DMA_MASK 0xffffffff
109 
110 /*
111  * table to translate option values from tulip
112  * to internal options
113  */
114 static unsigned char options_mapping[] = {
115 	PCNET32_PORT_ASEL,	/*  0 Auto-select      */
116 	PCNET32_PORT_AUI,	/*  1 BNC/AUI          */
117 	PCNET32_PORT_AUI,	/*  2 AUI/BNC          */
118 	PCNET32_PORT_ASEL,	/*  3 not supported    */
119 	PCNET32_PORT_10BT | PCNET32_PORT_FD,	/*  4 10baseT-FD       */
120 	PCNET32_PORT_ASEL,	/*  5 not supported    */
121 	PCNET32_PORT_ASEL,	/*  6 not supported    */
122 	PCNET32_PORT_ASEL,	/*  7 not supported    */
123 	PCNET32_PORT_ASEL,	/*  8 not supported    */
124 	PCNET32_PORT_MII,	/*  9 MII 10baseT      */
125 	PCNET32_PORT_MII | PCNET32_PORT_FD,	/* 10 MII 10baseT-FD   */
126 	PCNET32_PORT_MII,	/* 11 MII (autosel)    */
127 	PCNET32_PORT_10BT,	/* 12 10BaseT          */
128 	PCNET32_PORT_MII | PCNET32_PORT_100,	/* 13 MII 100BaseTx    */
129 	PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD,	/* 14 MII 100BaseTx-FD */
130 	PCNET32_PORT_ASEL	/* 15 not supported    */
131 };
132 
133 #define MAX_UNITS 8		/* More are supported, limit only on options */
134 static int options[MAX_UNITS];
135 static int full_duplex[MAX_UNITS];
136 
137 /*
138  *				Theory of Operation
139  *
140  * This driver uses the same software structure as the normal lance
141  * driver. So look for a verbose description in lance.c. The differences
142  * to the normal lance driver is the use of the 32bit mode of PCnet32
143  * and PCnetPCI chips. Because these chips are 32bit chips, there is no
144  * 16MB limitation and we don't need bounce buffers.
145  */
146 
147 
148 
149 /*
150  * Set the number of Tx and Rx buffers, using Log_2(# buffers).
151  * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
152  * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
153  */
154 #ifndef PCNET32_LOG_TX_BUFFERS
155 #define PCNET32_LOG_TX_BUFFERS 1
156 #define PCNET32_LOG_RX_BUFFERS 2
157 #endif
158 
159 #define TX_RING_SIZE		(1 << (PCNET32_LOG_TX_BUFFERS))
160 #define TX_RING_MOD_MASK	(TX_RING_SIZE - 1)
161 /* FIXME: Fix this to allow multiple tx_ring descriptors */
162 #define TX_RING_LEN_BITS	0x0000	/*PCNET32_LOG_TX_BUFFERS) << 12) */
163 
164 #define RX_RING_SIZE		(1 << (PCNET32_LOG_RX_BUFFERS))
165 #define RX_RING_MOD_MASK	(RX_RING_SIZE - 1)
166 #define RX_RING_LEN_BITS	((PCNET32_LOG_RX_BUFFERS) << 4)
167 
168 #define PKT_BUF_SZ		1544
169 
170 /* Offsets from base I/O address. */
171 #define PCNET32_WIO_RDP		0x10
172 #define PCNET32_WIO_RAP		0x12
173 #define PCNET32_WIO_RESET	0x14
174 #define PCNET32_WIO_BDP		0x16
175 
176 #define PCNET32_DWIO_RDP	0x10
177 #define PCNET32_DWIO_RAP	0x14
178 #define PCNET32_DWIO_RESET	0x18
179 #define PCNET32_DWIO_BDP	0x1C
180 
181 #define PCNET32_TOTAL_SIZE	0x20
182 
183 /* Buffers for the tx and Rx */
184 
185 /* Create a static buffer of size PKT_BUF_SZ for each
186 TX Descriptor.  All descriptors point to a
187 part of this buffer */
188 static unsigned char txb[PKT_BUF_SZ * TX_RING_SIZE];
189 //    __attribute__ ((aligned(16)));
190 
191 /* Create a static buffer of size PKT_BUF_SZ for each
192 RX Descriptor   All descriptors point to a
193 part of this buffer */
194 static unsigned char rxb[RX_RING_SIZE * PKT_BUF_SZ];
195 //    __attribute__ ((aligned(16)));
196 
197 /* The PCNET32 Rx and Tx ring descriptors. */
198 struct pcnet32_rx_head {
199 	u32 base;
200 	s16 buf_length;
201 	s16 status;
202 	u32 msg_length;
203 	u32 reserved;
204 };
205 
206 struct pcnet32_tx_head {
207 	u32 base;
208 	s16 length;
209 	s16 status;
210 	u32 misc;
211 	u32 reserved;
212 };
213 
214 /* The PCNET32 32-Bit initialization block, described in databook. */
215 struct pcnet32_init_block {
216 	u16 mode;
217 	u16 tlen_rlen;
218 	u8 phys_addr[6];
219 	u16 reserved;
220 	u32 filter[2];
221 	/* Receive and transmit ring base, along with extra bits. */
222 	u32 rx_ring;
223 	u32 tx_ring;
224 };
225 /* PCnet32 access functions */
226 struct pcnet32_access {
227 	u16(*read_csr) (unsigned long, int);
228 	void (*write_csr) (unsigned long, int, u16);
229 	 u16(*read_bcr) (unsigned long, int);
230 	void (*write_bcr) (unsigned long, int, u16);
231 	 u16(*read_rap) (unsigned long);
232 	void (*write_rap) (unsigned long, u16);
233 	void (*reset) (unsigned long);
234 };
235 
236 /* Define the TX Descriptor */
237 static struct pcnet32_tx_head tx_ring[TX_RING_SIZE]
238     __attribute__ ((aligned(16)));
239 
240 
241 /* Define the RX Descriptor */
242 static struct pcnet32_rx_head rx_ring[RX_RING_SIZE]
243     __attribute__ ((aligned(16)));
244 
245 /* May need to be moved to mii.h */
246 struct mii_if_info {
247 	int phy_id;
248 	int advertising;
249 	unsigned int full_duplex:1;	/* is full duplex? */
250 };
251 
252 /*
253  * The first three fields of pcnet32_private are read by the ethernet device
254  * so we allocate the structure should be allocated by pci_alloc_consistent().
255  */
256 #define MII_CNT 4
257 struct pcnet32_private {
258 	struct pcnet32_init_block init_block;
259 	struct pci_dev *pci_dev;	/* Pointer to the associated pci device structure */
260 	const char *name;
261 	/* The saved address of a sent-in-place packet/buffer, for skfree(). */
262 	struct sk_buff *tx_skbuff[TX_RING_SIZE];
263 	struct sk_buff *rx_skbuff[RX_RING_SIZE];
264 	struct pcnet32_access a;
265 	unsigned int cur_rx, cur_tx;	/* The next free ring entry */
266 	char tx_full;
267 	int options;
268 	int shared_irq:1,	/* shared irq possible */
269 	 ltint:1,		/* enable TxDone-intr inhibitor */
270 	 dxsuflo:1,		/* disable transmit stop on uflo */
271 	 mii:1;			/* mii port available */
272 	struct mii_if_info mii_if;
273 	unsigned char phys[MII_CNT];
274 	struct net_device *next;
275 	int full_duplex:1;
276 } lpx;
277 
278 static struct pcnet32_private *lp;
279 
280 static int mdio_read(struct nic *nic __unused, int phy_id, int reg_num);
281 #if 0
282 static void mdio_write(struct nic *nic __unused, int phy_id, int reg_num,
283 		       int val);
284 #endif
285 enum pci_flags_bit {
286 	PCI_USES_IO = 1, PCI_USES_MEM = 2, PCI_USES_MASTER = 4,
287 	PCI_ADDR0 = 0x10 << 0, PCI_ADDR1 = 0x10 << 1, PCI_ADDR2 =
288 	    0x10 << 2, PCI_ADDR3 = 0x10 << 3,
289 };
290 
291 
292 static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
293 {
294 	outw(index, addr + PCNET32_WIO_RAP);
295 	return inw(addr + PCNET32_WIO_RDP);
296 }
297 
298 static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
299 {
300 	outw(index, addr + PCNET32_WIO_RAP);
301 	outw(val, addr + PCNET32_WIO_RDP);
302 }
303 
304 static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
305 {
306 	outw(index, addr + PCNET32_WIO_RAP);
307 	return inw(addr + PCNET32_WIO_BDP);
308 }
309 
310 static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
311 {
312 	outw(index, addr + PCNET32_WIO_RAP);
313 	outw(val, addr + PCNET32_WIO_BDP);
314 }
315 
316 static u16 pcnet32_wio_read_rap(unsigned long addr)
317 {
318 	return inw(addr + PCNET32_WIO_RAP);
319 }
320 
321 static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
322 {
323 	outw(val, addr + PCNET32_WIO_RAP);
324 }
325 
326 static void pcnet32_wio_reset(unsigned long addr)
327 {
328 	inw(addr + PCNET32_WIO_RESET);
329 }
330 
331 static int pcnet32_wio_check(unsigned long addr)
332 {
333 	outw(88, addr + PCNET32_WIO_RAP);
334 	return (inw(addr + PCNET32_WIO_RAP) == 88);
335 }
336 
337 static struct pcnet32_access pcnet32_wio = {
338       read_csr:pcnet32_wio_read_csr,
339       write_csr:pcnet32_wio_write_csr,
340       read_bcr:pcnet32_wio_read_bcr,
341       write_bcr:pcnet32_wio_write_bcr,
342       read_rap:pcnet32_wio_read_rap,
343       write_rap:pcnet32_wio_write_rap,
344       reset:pcnet32_wio_reset
345 };
346 
347 static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
348 {
349 	outl(index, addr + PCNET32_DWIO_RAP);
350 	return (inl(addr + PCNET32_DWIO_RDP) & 0xffff);
351 }
352 
353 static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
354 {
355 	outl(index, addr + PCNET32_DWIO_RAP);
356 	outl(val, addr + PCNET32_DWIO_RDP);
357 }
358 
359 static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
360 {
361 	outl(index, addr + PCNET32_DWIO_RAP);
362 	return (inl(addr + PCNET32_DWIO_BDP) & 0xffff);
363 }
364 
365 static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
366 {
367 	outl(index, addr + PCNET32_DWIO_RAP);
368 	outl(val, addr + PCNET32_DWIO_BDP);
369 }
370 
371 static u16 pcnet32_dwio_read_rap(unsigned long addr)
372 {
373 	return (inl(addr + PCNET32_DWIO_RAP) & 0xffff);
374 }
375 
376 static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
377 {
378 	outl(val, addr + PCNET32_DWIO_RAP);
379 }
380 
381 static void pcnet32_dwio_reset(unsigned long addr)
382 {
383 	inl(addr + PCNET32_DWIO_RESET);
384 }
385 
386 static int pcnet32_dwio_check(unsigned long addr)
387 {
388 	outl(88, addr + PCNET32_DWIO_RAP);
389 	return ((inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88);
390 }
391 
392 static struct pcnet32_access pcnet32_dwio = {
393       read_csr:pcnet32_dwio_read_csr,
394       write_csr:pcnet32_dwio_write_csr,
395       read_bcr:pcnet32_dwio_read_bcr,
396       write_bcr:pcnet32_dwio_write_bcr,
397       read_rap:pcnet32_dwio_read_rap,
398       write_rap:pcnet32_dwio_write_rap,
399       reset:pcnet32_dwio_reset
400 };
401 
402 
403 /* Initialize the PCNET32 Rx and Tx rings. */
404 static int pcnet32_init_ring(struct nic *nic)
405 {
406 	int i;
407 
408 	lp->tx_full = 0;
409 	lp->cur_rx = lp->cur_tx = 0;
410 
411 	for (i = 0; i < RX_RING_SIZE; i++) {
412 		rx_ring[i].base = (u32) virt_to_le32desc(&rxb[i]);
413 		rx_ring[i].buf_length = le16_to_cpu(-PKT_BUF_SZ);
414 		rx_ring[i].status = le16_to_cpu(0x8000);
415 	}
416 
417 	/* The Tx buffer address is filled in as needed, but we do need to clear
418 	   the upper ownership bit. */
419 	for (i = 0; i < TX_RING_SIZE; i++) {
420 		tx_ring[i].base = 0;
421 		tx_ring[i].status = 0;
422 	}
423 
424 
425 	lp->init_block.tlen_rlen =
426 	    le16_to_cpu(TX_RING_LEN_BITS | RX_RING_LEN_BITS);
427 	for (i = 0; i < 6; i++)
428 		lp->init_block.phys_addr[i] = nic->node_addr[i];
429 	lp->init_block.rx_ring = (u32) virt_to_le32desc(&rx_ring[0]);
430 	lp->init_block.tx_ring = (u32) virt_to_le32desc(&tx_ring[0]);
431 	return 0;
432 }
433 
434 /**************************************************************************
435 RESET - Reset adapter
436 ***************************************************************************/
437 static void pcnet32_reset(struct nic *nic)
438 {
439 	/* put the card in its initial state */
440 	u16 val;
441 	int i;
442 
443 	/* Reset the PCNET32 */
444 	lp->a.reset(ioaddr);
445 
446 	/* switch pcnet32 to 32bit mode */
447 	lp->a.write_bcr(ioaddr, 20, 2);
448 
449 	/* set/reset autoselect bit */
450 	val = lp->a.read_bcr(ioaddr, 2) & ~2;
451 	if (lp->options & PCNET32_PORT_ASEL)
452 		val |= 2;
453 	lp->a.write_bcr(ioaddr, 2, val);
454 	/* handle full duplex setting */
455 	if (lp->full_duplex) {
456 		val = lp->a.read_bcr(ioaddr, 9) & ~3;
457 		if (lp->options & PCNET32_PORT_FD) {
458 			val |= 1;
459 			if (lp->options ==
460 			    (PCNET32_PORT_FD | PCNET32_PORT_AUI))
461 				val |= 2;
462 		} else if (lp->options & PCNET32_PORT_ASEL) {
463 			/* workaround of xSeries250, turn on for 79C975 only */
464 			i = ((lp->a.
465 			      read_csr(ioaddr,
466 				       88) | (lp->a.read_csr(ioaddr,
467 							     89) << 16)) >>
468 			     12) & 0xffff;
469 			if (i == 0x2627)
470 				val |= 3;
471 		}
472 		lp->a.write_bcr(ioaddr, 9, val);
473 	}
474 
475 	/* set/reset GPSI bit in test register */
476 	val = lp->a.read_csr(ioaddr, 124) & ~0x10;
477 	if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
478 		val |= 0x10;
479 	lp->a.write_csr(ioaddr, 124, val);
480 
481 	if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
482 		val = lp->a.read_bcr(ioaddr, 32) & ~0x38;	/* disable Auto Negotiation, set 10Mpbs, HD */
483 		if (lp->options & PCNET32_PORT_FD)
484 			val |= 0x10;
485 		if (lp->options & PCNET32_PORT_100)
486 			val |= 0x08;
487 		lp->a.write_bcr(ioaddr, 32, val);
488 	} else {
489 		if (lp->options & PCNET32_PORT_ASEL) {	/* enable auto negotiate, setup, disable fd */
490 			val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
491 			val |= 0x20;
492 			lp->a.write_bcr(ioaddr, 32, val);
493 		}
494 	}
495 
496 #ifdef DO_DXSUFLO
497 	if (lp->dxsuflo) {	/* Disable transmit stop on underflow */
498 		val = lp->a.read_csr(ioaddr, 3);
499 		val |= 0x40;
500 		lp->a.write_csr(ioaddr, 3, val);
501 	}
502 #endif
503 
504 	if (lp->ltint) {	/* Enable TxDone-intr inhibitor */
505 		val = lp->a.read_csr(ioaddr, 5);
506 		val |= (1 << 14);
507 		lp->a.write_csr(ioaddr, 5, val);
508 	}
509 	lp->init_block.mode =
510 	    le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
511 	lp->init_block.filter[0] = 0xffffffff;
512 	lp->init_block.filter[1] = 0xffffffff;
513 
514 	pcnet32_init_ring(nic);
515 
516 
517 	/* Re-initialize the PCNET32, and start it when done. */
518 	lp->a.write_csr(ioaddr, 1,
519 			(virt_to_bus(&lp->init_block)) & 0xffff);
520 	lp->a.write_csr(ioaddr, 2, (virt_to_bus(&lp->init_block)) >> 16);
521 	lp->a.write_csr(ioaddr, 4, 0x0915);
522 	lp->a.write_csr(ioaddr, 0, 0x0001);
523 
524 
525 	i = 0;
526 	while (i++ < 100)
527 		if (lp->a.read_csr(ioaddr, 0) & 0x0100)
528 			break;
529 	/*
530 	 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
531 	 * reports that doing so triggers a bug in the '974.
532 	 */
533 	lp->a.write_csr(ioaddr, 0, 0x0042);
534 
535 	dprintf(("pcnet32 open, csr0 %hX.\n", lp->a.read_csr(ioaddr, 0)));
536 
537 }
538 
539 /**************************************************************************
540 POLL - Wait for a frame
541 ***************************************************************************/
542 static int pcnet32_poll(struct nic *nic __unused, int retrieve)
543 {
544 	/* return true if there's an ethernet packet ready to read */
545 	/* nic->packet should contain data on return */
546 	/* nic->packetlen should contain length of data */
547 
548 	int status;
549 	int entry;
550 
551 	entry = lp->cur_rx & RX_RING_MOD_MASK;
552 	status = ((short) le16_to_cpu(rx_ring[entry].status) >> 8);
553 
554 	if (status < 0)
555 		return 0;
556 
557 	if ( ! retrieve ) return 1;
558 
559 	if (status == 0x03) {
560 		nic->packetlen =
561 		    (le32_to_cpu(rx_ring[entry].msg_length) & 0xfff) - 4;
562 		memcpy(nic->packet, &rxb[entry], nic->packetlen);
563 
564 		/* Andrew Boyd of QNX reports that some revs of the 79C765
565 		 * clear the buffer length */
566 		rx_ring[entry].buf_length = le16_to_cpu(-PKT_BUF_SZ);
567 		rx_ring[entry].status |= le16_to_cpu(0x8000);	/* prime for next receive */
568 		/* Switch to the next Rx ring buffer */
569 		lp->cur_rx++;
570 
571 	} else {
572 		return 0;
573 	}
574 
575 	return 1;
576 }
577 
578 /**************************************************************************
579 TRANSMIT - Transmit a frame
580 ***************************************************************************/
581 static void pcnet32_transmit(struct nic *nic __unused, const char *d,	/* Destination */
582 			     unsigned int t,	/* Type */
583 			     unsigned int s,	/* size */
584 			     const char *p)
585 {				/* Packet */
586 	/* send the packet to destination */
587 	unsigned long time;
588 	u8 *ptxb;
589 	u16 nstype;
590 	u16 status;
591 	int entry = 0;		/*lp->cur_tx & TX_RING_MOD_MASK; */
592 
593 	status = 0x8300;
594 	/* point to the current txb incase multiple tx_rings are used */
595 	ptxb = txb + (lp->cur_tx * PKT_BUF_SZ);
596 
597 	/* copy the packet to ring buffer */
598 	memcpy(ptxb, d, ETH_ALEN);	/* dst */
599 	memcpy(ptxb + ETH_ALEN, nic->node_addr, ETH_ALEN);	/* src */
600 	nstype = htons((u16) t);	/* type */
601 	memcpy(ptxb + 2 * ETH_ALEN, (u8 *) & nstype, 2);	/* type */
602 	memcpy(ptxb + ETH_HLEN, p, s);
603 
604 	s += ETH_HLEN;
605 	while (s < ETH_ZLEN)	/* pad to min length */
606 		ptxb[s++] = '\0';
607 
608 	tx_ring[entry].length = le16_to_cpu(-s);
609 	tx_ring[entry].misc = 0x00000000;
610 	tx_ring[entry].base = (u32) virt_to_le32desc(ptxb);
611 
612 	/* we set the top byte as the very last thing */
613 	tx_ring[entry].status = le16_to_cpu(status);
614 
615 
616 	/* Trigger an immediate send poll */
617 	lp->a.write_csr(ioaddr, 0, 0x0048);
618 
619 	/* wait for transmit complete */
620 	lp->cur_tx = 0;		/* (lp->cur_tx + 1); */
621 	time = currticks() + TICKS_PER_SEC;	/* wait one second */
622 	while (currticks() < time &&
623 	       ((short) le16_to_cpu(tx_ring[entry].status) < 0));
624 
625 	if ((short) le16_to_cpu(tx_ring[entry].status) < 0)
626 		printf("PCNET32 timed out on transmit\n");
627 
628 	/* Stop pointing at the current txb
629 	 * otherwise the card continues to send the packet */
630 	tx_ring[entry].base = 0;
631 
632 }
633 
634 /**************************************************************************
635 DISABLE - Turn off ethernet interface
636 ***************************************************************************/
637 static void pcnet32_disable(struct dev *dev __unused)
638 {
639 	/* Stop the PCNET32 here -- it ocassionally polls memory if we don't */
640 	lp->a.write_csr(ioaddr, 0, 0x0004);
641 
642 	/*
643 	 * Switch back to 16-bit mode to avoid problesm with dumb
644 	 * DOS packet driver after a warm reboot
645 	 */
646 	lp->a.write_bcr(ioaddr, 20, 4);
647 }
648 
649 /**************************************************************************
650 IRQ - Enable, Disable, or Force interrupts
651 ***************************************************************************/
652 static void pcnet32_irq(struct nic *nic __unused, irq_action_t action __unused)
653 {
654   switch ( action ) {
655   case DISABLE :
656     break;
657   case ENABLE :
658     break;
659   case FORCE :
660     break;
661   }
662 }
663 
664 /**************************************************************************
665 PROBE - Look for an adapter, this routine's visible to the outside
666 You should omit the last argument struct pci_device * for a non-PCI NIC
667 ***************************************************************************/
668 static int pcnet32_probe(struct dev *dev, struct pci_device *pci)
669 {
670 	struct nic *nic = (struct nic *) dev;
671 	int i, media;
672 	int fdx, mii, fset, dxsuflo, ltint;
673 	int chip_version;
674 	char *chipname;
675 	struct pcnet32_access *a = NULL;
676 	u8 promaddr[6];
677 
678 	int shared = 1;
679 	if (pci->ioaddr == 0)
680 		return 0;
681 
682 	/* BASE is used throughout to address the card */
683 	ioaddr = pci->ioaddr;
684 	printf("pcnet32.c: Found %s, Vendor=0x%hX Device=0x%hX\n",
685 	       pci->name, pci->vendor, pci->dev_id);
686 
687 	nic->irqno  = 0;
688 	nic->ioaddr = pci->ioaddr & ~3;
689 
690 	/* reset the chip */
691 	pcnet32_wio_reset(ioaddr);
692 
693 	/* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
694 	if (pcnet32_wio_read_csr(ioaddr, 0) == 4
695 	    && pcnet32_wio_check(ioaddr)) {
696 		a = &pcnet32_wio;
697 	} else {
698 		pcnet32_dwio_reset(ioaddr);
699 		if (pcnet32_dwio_read_csr(ioaddr, 0) == 4
700 		    && pcnet32_dwio_check(ioaddr)) {
701 			a = &pcnet32_dwio;
702 		} else
703 			return 0;
704 	}
705 
706 	chip_version =
707 	    a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
708 
709 	dprintf(("PCnet chip version is %0xhX\n", chip_version));
710 	if ((chip_version & 0xfff) != 0x003)
711 		return 0;
712 
713 	/* initialize variables */
714 	fdx = mii = fset = dxsuflo = ltint = 0;
715 	chip_version = (chip_version >> 12) & 0xffff;
716 
717 	switch (chip_version) {
718 	case 0x2420:
719 		chipname = "PCnet/PCI 79C970";	/* PCI */
720 		break;
721 	case 0x2430:
722 		if (shared)
723 			chipname = "PCnet/PCI 79C970";	/* 970 gives the wrong chip id back */
724 		else
725 			chipname = "PCnet/32 79C965";	/* 486/VL bus */
726 		break;
727 	case 0x2621:
728 		chipname = "PCnet/PCI II 79C970A";	/* PCI */
729 		fdx = 1;
730 		break;
731 	case 0x2623:
732 		chipname = "PCnet/FAST 79C971";	/* PCI */
733 		fdx = 1;
734 		mii = 1;
735 		fset = 1;
736 		ltint = 1;
737 		break;
738 	case 0x2624:
739 		chipname = "PCnet/FAST+ 79C972";	/* PCI */
740 		fdx = 1;
741 		mii = 1;
742 		fset = 1;
743 		break;
744 	case 0x2625:
745 		chipname = "PCnet/FAST III 79C973";	/* PCI */
746 		fdx = 1;
747 		mii = 1;
748 		break;
749 	case 0x2626:
750 		chipname = "PCnet/Home 79C978";	/* PCI */
751 		fdx = 1;
752 		/*
753 		 * This is based on specs published at www.amd.com.  This section
754 		 * assumes that a card with a 79C978 wants to go into 1Mb HomePNA
755 		 * mode.  The 79C978 can also go into standard ethernet, and there
756 		 * probably should be some sort of module option to select the
757 		 * mode by which the card should operate
758 		 */
759 		/* switch to home wiring mode */
760 		media = a->read_bcr(ioaddr, 49);
761 
762 		printf("media reset to %#x.\n", media);
763 		a->write_bcr(ioaddr, 49, media);
764 		break;
765 	case 0x2627:
766 		chipname = "PCnet/FAST III 79C975";	/* PCI */
767 		fdx = 1;
768 		mii = 1;
769 		break;
770 	default:
771 		printf("PCnet version %#x, no PCnet32 chip.\n",
772 		       chip_version);
773 		return 0;
774 	}
775 
776 	/*
777 	 *  On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
778 	 *  starting until the packet is loaded. Strike one for reliability, lose
779 	 *  one for latency - although on PCI this isnt a big loss. Older chips
780 	 *  have FIFO's smaller than a packet, so you can't do this.
781 	 */
782 
783 	if (fset) {
784 		a->write_bcr(ioaddr, 18,
785 			     (a->read_bcr(ioaddr, 18) | 0x0800));
786 		a->write_csr(ioaddr, 80,
787 			     (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
788 		dxsuflo = 1;
789 		ltint = 1;
790 	}
791 
792 	dprintf(("%s at %hX,", chipname, ioaddr));
793 
794 	/* read PROM address */
795 	for (i = 0; i < 6; i++)
796 		promaddr[i] = inb(ioaddr + i);
797 
798 	/* Update the nic structure with the MAC Address */
799 	for (i = 0; i < ETH_ALEN; i++) {
800 		nic->node_addr[i] = promaddr[i];
801 	}
802 	/* Print out some hardware info */
803 	printf("%s: %! at ioaddr %hX, ", pci->name, nic->node_addr,
804 	       ioaddr);
805 
806 	/* Set to pci bus master */
807 	adjust_pci_device(pci);
808 
809 	/* point to private storage */
810 	lp = &lpx;
811 
812 #if EBDEBUG
813 	if (((chip_version + 1) & 0xfffe) == 0x2624) {	/* Version 0x2623 or 0x2624 */
814 		i = a->read_csr(ioaddr, 80) & 0x0C00;	/* Check tx_start_pt */
815 		dprintf(("    tx_start_pt(0x%hX):", i));
816 		switch (i >> 10) {
817 		case 0:
818 			dprintf(("  20 bytes,"));
819 			break;
820 		case 1:
821 			dprintf(("  64 bytes,"));
822 			break;
823 		case 2:
824 			dprintf((" 128 bytes,"));
825 			break;
826 		case 3:
827 			dprintf(("~220 bytes,"));
828 			break;
829 		}
830 		i = a->read_bcr(ioaddr, 18);	/* Check Burst/Bus control */
831 		dprintf((" BCR18(%hX):", i & 0xffff));
832 		if (i & (1 << 5))
833 			dprintf(("BurstWrEn "));
834 		if (i & (1 << 6))
835 			dprintf(("BurstRdEn "));
836 		if (i & (1 << 7))
837 			dprintf(("DWordIO "));
838 		if (i & (1 << 11))
839 			dprintf(("NoUFlow "));
840 		i = a->read_bcr(ioaddr, 25);
841 		dprintf(("    SRAMSIZE=0x%hX,", i << 8));
842 		i = a->read_bcr(ioaddr, 26);
843 		dprintf((" SRAM_BND=0x%hX,", i << 8));
844 		i = a->read_bcr(ioaddr, 27);
845 		if (i & (1 << 14))
846 			dprintf(("LowLatRx"));
847 	}
848 #endif
849 	lp->name = chipname;
850 	lp->shared_irq = shared;
851 	lp->full_duplex = fdx;
852 	lp->dxsuflo = dxsuflo;
853 	lp->ltint = ltint;
854 	lp->mii = mii;
855 	/* FIXME: Fix Options for only one card */
856 	if ((cards_found >= MAX_UNITS)
857 	    || ((unsigned int) options[cards_found] > sizeof(options_mapping)))
858 		lp->options = PCNET32_PORT_ASEL;
859 	else
860 		lp->options = options_mapping[options[cards_found]];
861 
862 	if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
863 	    ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
864 		lp->options |= PCNET32_PORT_FD;
865 
866 	if (!a) {
867 		printf("No access methods\n");
868 		return 0;
869 	}
870 	lp->a = *a;
871 
872 	/* detect special T1/E1 WAN card by checking for MAC address */
873 	if (nic->node_addr[0] == 0x00 && nic->node_addr[1] == 0xe0
874 	    && nic->node_addr[2] == 0x75)
875 		lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
876 
877 	lp->init_block.mode = le16_to_cpu(0x0003);	/* Disable Rx and Tx. */
878 	lp->init_block.tlen_rlen =
879 	    le16_to_cpu(TX_RING_LEN_BITS | RX_RING_LEN_BITS);
880 	for (i = 0; i < 6; i++)
881 		lp->init_block.phys_addr[i] = nic->node_addr[i];
882 	lp->init_block.filter[0] = 0xffffffff;
883 	lp->init_block.filter[1] = 0xffffffff;
884 	lp->init_block.rx_ring = virt_to_bus(&rx_ring);
885 	lp->init_block.tx_ring = virt_to_bus(&tx_ring);
886 
887 	/* switch pcnet32 to 32bit mode */
888 	a->write_bcr(ioaddr, 20, 2);
889 
890 
891 	a->write_csr(ioaddr, 1, (virt_to_bus(&lp->init_block)) & 0xffff);
892 	a->write_csr(ioaddr, 2, (virt_to_bus(&lp->init_block)) >> 16);
893 
894 	/*
895 	 * To auto-IRQ we enable the initialization-done and DMA error
896 	 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
897 	 * boards will work.
898 	 */
899 	/* Trigger an initialization just for the interrupt. */
900 
901 	a->write_csr(ioaddr, 0, 0x41);
902 	mdelay(1);
903 
904 	cards_found++;
905 
906 	/* point to NIC specific routines */
907 	pcnet32_reset(nic);
908 	if (1) {
909 	        int tmp;
910 		int phy, phy_idx = 0;
911 		u16 mii_lpa;
912 		lp->phys[0] = 1;	/* Default Setting */
913 		for (phy = 1; phy < 32 && phy_idx < MII_CNT; phy++) {
914 			int mii_status = mdio_read(nic, phy, MII_BMSR);
915 			if (mii_status != 0xffff && mii_status != 0x0000) {
916 				lp->phys[phy_idx++] = phy;
917 				lp->mii_if.advertising =
918 				    mdio_read(nic, phy, MII_ADVERTISE);
919 				if ((mii_status & 0x0040) == 0) {
920 				  tmp = phy;
921 				  dprintf (("MII PHY found at address %d, status "
922 					    "%hX advertising %hX\n", phy, mii_status,
923 					    lp->mii_if.advertising));
924 				}
925 			}
926 		}
927 		if (phy_idx == 0)
928 			printf("No MII transceiver found!\n");
929 		lp->mii_if.phy_id = lp->phys[0];
930 
931 		lp->mii_if.advertising =
932 		    mdio_read(nic, lp->phys[0], MII_ADVERTISE);
933 
934 		mii_lpa = mdio_read(nic, lp->phys[0], MII_LPA);
935 		lp->mii_if.advertising &= mii_lpa;
936 		if (lp->mii_if.advertising & ADVERTISE_100FULL)
937 			printf("100Mbps Full-Duplex\n");
938 		else if (lp->mii_if.advertising & ADVERTISE_100HALF)
939 			printf("100Mbps Half-Duplex\n");
940 		else if (lp->mii_if.advertising & ADVERTISE_10FULL)
941 			printf("10Mbps Full-Duplex\n");
942 		else if (lp->mii_if.advertising & ADVERTISE_10HALF)
943 			printf("10Mbps Half-Duplex\n");
944 		else
945 			printf("\n");
946 	}
947 
948 	nic->poll     = pcnet32_poll;
949 	nic->transmit = pcnet32_transmit;
950 	dev->disable  = pcnet32_disable;
951 	nic->irq      = pcnet32_irq;
952 
953 	return 1;
954 }
955 static int mdio_read(struct nic *nic __unused, int phy_id, int reg_num)
956 {
957 	u16 val_out;
958 	int phyaddr;
959 
960 	if (!lp->mii)
961 		return 0;
962 
963 	phyaddr = lp->a.read_bcr(ioaddr, 33);
964 
965 	lp->a.write_bcr(ioaddr, 33,
966 			((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
967 	val_out = lp->a.read_bcr(ioaddr, 34);
968 	lp->a.write_bcr(ioaddr, 33, phyaddr);
969 
970 	return val_out;
971 }
972 
973 #if 0
974 static void mdio_write(struct nic *nic __unused, int phy_id, int reg_num,
975 		       int val)
976 {
977 	int phyaddr;
978 
979 	if (!lp->mii)
980 		return;
981 
982 	phyaddr = lp->a.read_bcr(ioaddr, 33);
983 
984 	lp->a.write_bcr(ioaddr, 33,
985 			((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
986 	lp->a.write_bcr(ioaddr, 34, val);
987 	lp->a.write_bcr(ioaddr, 33, phyaddr);
988 }
989 #endif
990 
991 static struct pci_id pcnet32_nics[] = {
992 	PCI_ROM(0x1022, 0x2000, "lancepci", "AMD Lance/PCI"),
993 	PCI_ROM(0x1022, 0x2625, "pcnetfastiii", "AMD Lance/PCI PCNet/32"),
994 	PCI_ROM(0x1022, 0x2001, "amdhomepna", "AMD Lance/HomePNA"),
995 };
996 
997 struct pci_driver pcnet32_driver = {
998 	.type = NIC_DRIVER,
999 	.name = "PCNET32/PCI",
1000 	.probe = pcnet32_probe,
1001 	.ids = pcnet32_nics,
1002 	.id_count = sizeof(pcnet32_nics) / sizeof(pcnet32_nics[0]),
1003 	.class = 0,
1004 };
1005