1
2 /* epic100.c: A SMC 83c170 EPIC/100 fast ethernet driver for Etherboot */
3
4 /* 05/06/2003 timlegge Fixed relocation and implemented Multicast */
5 #define LINUX_OUT_MACROS
6
7 #include "etherboot.h"
8 #include "pci.h"
9 #include "nic.h"
10 #include "timer.h"
11 #include "epic100.h"
12
13 /* Condensed operations for readability */
14 #define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr))
15 #define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr))
16
17 #define TX_RING_SIZE 2 /* use at least 2 buffers for TX */
18 #define RX_RING_SIZE 2
19
20 #define PKT_BUF_SZ 1536 /* Size of each temporary Tx/Rx buffer.*/
21
22 /*
23 #define DEBUG_RX
24 #define DEBUG_TX
25 #define DEBUG_EEPROM
26 */
27
28 #define EPIC_DEBUG 0 /* debug level */
29
30 /* The EPIC100 Rx and Tx buffer descriptors. */
31 struct epic_rx_desc {
32 unsigned long status;
33 unsigned long bufaddr;
34 unsigned long buflength;
35 unsigned long next;
36 };
37 /* description of the tx descriptors control bits commonly used */
38 #define TD_STDFLAGS TD_LASTDESC
39
40 struct epic_tx_desc {
41 unsigned long status;
42 unsigned long bufaddr;
43 unsigned long buflength;
44 unsigned long next;
45 };
46
47 #define delay(nanosec) do { int _i = 3; while (--_i > 0) \
48 { __SLOW_DOWN_IO; }} while (0)
49
50 static void epic100_open(void);
51 static void epic100_init_ring(void);
52 static void epic100_disable(struct dev *dev);
53 static int epic100_poll(struct nic *nic, int retrieve);
54 static void epic100_transmit(struct nic *nic, const char *destaddr,
55 unsigned int type, unsigned int len, const char *data);
56 #ifdef DEBUG_EEPROM
57 static int read_eeprom(int location);
58 #endif
59 static int mii_read(int phy_id, int location);
60 static void epic100_irq(struct nic *nic, irq_action_t action);
61
62 static int ioaddr;
63
64 static int command;
65 static int intstat;
66 static int intmask;
67 static int genctl ;
68 static int eectl ;
69 static int test ;
70 static int mmctl ;
71 static int mmdata ;
72 static int lan0 ;
73 static int mc0 ;
74 static int rxcon ;
75 static int txcon ;
76 static int prcdar ;
77 static int ptcdar ;
78 static int eththr ;
79
80 static unsigned int cur_rx, cur_tx; /* The next free ring entry */
81 #ifdef DEBUG_EEPROM
82 static unsigned short eeprom[64];
83 #endif
84 static signed char phys[4]; /* MII device addresses. */
85 static struct epic_rx_desc rx_ring[RX_RING_SIZE]
86 __attribute__ ((aligned(4)));
87 static struct epic_tx_desc tx_ring[TX_RING_SIZE]
88 __attribute__ ((aligned(4)));
89 static unsigned char rx_packet[PKT_BUF_SZ * RX_RING_SIZE];
90 static unsigned char tx_packet[PKT_BUF_SZ * TX_RING_SIZE];
91
92 /***********************************************************************/
93 /* Externally visible functions */
94 /***********************************************************************/
95
96
97 static int
epic100_probe(struct dev * dev,struct pci_device * pci)98 epic100_probe(struct dev *dev, struct pci_device *pci)
99 {
100 struct nic *nic = (struct nic *)dev;
101 int i;
102 unsigned short* ap;
103 unsigned int phy, phy_idx;
104
105 if (pci->ioaddr == 0)
106 return 0;
107
108 /* Ideally we would detect all network cards in slot order. That would
109 be best done a central PCI probe dispatch, which wouldn't work
110 well with the current structure. So instead we detect just the
111 Epic cards in slot order. */
112
113 ioaddr = pci->ioaddr;
114 nic->irqno = 0;
115 nic->ioaddr = pci->ioaddr & ~3;
116
117 /* compute all used static epic100 registers address */
118 command = ioaddr + COMMAND; /* Control Register */
119 intstat = ioaddr + INTSTAT; /* Interrupt Status */
120 intmask = ioaddr + INTMASK; /* Interrupt Mask */
121 genctl = ioaddr + GENCTL; /* General Control */
122 eectl = ioaddr + EECTL; /* EEPROM Control */
123 test = ioaddr + TEST; /* Test register (clocks) */
124 mmctl = ioaddr + MMCTL; /* MII Management Interface Control */
125 mmdata = ioaddr + MMDATA; /* MII Management Interface Data */
126 lan0 = ioaddr + LAN0; /* MAC address. (0x40-0x48) */
127 mc0 = ioaddr + MC0; /* Multicast Control */
128 rxcon = ioaddr + RXCON; /* Receive Control */
129 txcon = ioaddr + TXCON; /* Transmit Control */
130 prcdar = ioaddr + PRCDAR; /* PCI Receive Current Descr Address */
131 ptcdar = ioaddr + PTCDAR; /* PCI Transmit Current Descr Address */
132 eththr = ioaddr + ETHTHR; /* Early Transmit Threshold */
133
134 /* Reset the chip & bring it out of low-power mode. */
135 outl(GC_SOFT_RESET, genctl);
136
137 /* Disable ALL interrupts by setting the interrupt mask. */
138 outl(INTR_DISABLE, intmask);
139
140 /*
141 * set the internal clocks:
142 * Application Note 7.15 says:
143 * In order to set the CLOCK TEST bit in the TEST register,
144 * perform the following:
145 *
146 * Write 0x0008 to the test register at least sixteen
147 * consecutive times.
148 *
149 * The CLOCK TEST bit is Write-Only. Writing it several times
150 * consecutively insures a successful write to the bit...
151 */
152
153 for (i = 0; i < 16; i++) {
154 outl(0x00000008, test);
155 }
156
157 #ifdef DEBUG_EEPROM
158 {
159 unsigned short sum = 0;
160 unsigned short value;
161 for (i = 0; i < 64; i++) {
162 value = read_eeprom(i);
163 eeprom[i] = value;
164 sum += value;
165 }
166 }
167
168 #if (EPIC_DEBUG > 1)
169 printf("EEPROM contents\n");
170 for (i = 0; i < 64; i++) {
171 printf(" %hhX%s", eeprom[i], i % 16 == 15 ? "\n" : "");
172 }
173 #endif
174 #endif
175
176 /* This could also be read from the EEPROM. */
177 ap = (unsigned short*)nic->node_addr;
178 for (i = 0; i < 3; i++)
179 *ap++ = inw(lan0 + i*4);
180
181 printf(" I/O %#hX %! ", ioaddr, nic->node_addr);
182
183 /* Find the connected MII xcvrs. */
184 for (phy = 0, phy_idx = 0; phy < 32 && phy_idx < sizeof(phys); phy++) {
185 int mii_status = mii_read(phy, 0);
186
187 if (mii_status != 0xffff && mii_status != 0x0000) {
188 phys[phy_idx++] = phy;
189 #if (EPIC_DEBUG > 1)
190 printf("MII transceiver found at address %d.\n", phy);
191 #endif
192 }
193 }
194 if (phy_idx == 0) {
195 #if (EPIC_DEBUG > 1)
196 printf("***WARNING***: No MII transceiver found!\n");
197 #endif
198 /* Use the known PHY address of the EPII. */
199 phys[0] = 3;
200 }
201
202 epic100_open();
203
204 dev->disable = epic100_disable;
205 nic->poll = epic100_poll;
206 nic->transmit = epic100_transmit;
207 nic->irq = epic100_irq;
208
209 return 1;
210 }
211
set_rx_mode(void)212 static void set_rx_mode(void)
213 {
214 unsigned char mc_filter[8];
215 int i;
216 memset(mc_filter, 0xff, sizeof(mc_filter));
217 outl(0x0C, rxcon);
218 for(i = 0; i < 4; i++)
219 outw(((unsigned short *)mc_filter)[i], mc0 + i*4);
220 return;
221 }
222
223 static void
epic100_open(void)224 epic100_open(void)
225 {
226 int mii_reg5;
227 int full_duplex = 0;
228 unsigned long tmp;
229
230 epic100_init_ring();
231
232 /* Pull the chip out of low-power mode, and set for PCI read multiple. */
233 outl(GC_RX_FIFO_THR_64 | GC_MRC_READ_MULT | GC_ONE_COPY, genctl);
234
235 outl(TX_FIFO_THRESH, eththr);
236
237 tmp = TC_EARLY_TX_ENABLE | TX_SLOT_TIME;
238
239 mii_reg5 = mii_read(phys[0], 5);
240 if (mii_reg5 != 0xffff && (mii_reg5 & 0x0100)) {
241 full_duplex = 1;
242 printf(" full-duplex mode");
243 tmp |= TC_LM_FULL_DPX;
244 } else
245 tmp |= TC_LM_NORMAL;
246
247 outl(tmp, txcon);
248
249 /* Give adress of RX and TX ring to the chip */
250 outl(virt_to_le32desc(&rx_ring), prcdar);
251 outl(virt_to_le32desc(&tx_ring), ptcdar);
252
253 /* Start the chip's Rx process: receive unicast and broadcast */
254 set_rx_mode();
255 outl(CR_START_RX | CR_QUEUE_RX, command);
256
257 putchar('\n');
258 }
259
260 /* Initialize the Rx and Tx rings. */
261 static void
epic100_init_ring(void)262 epic100_init_ring(void)
263 {
264 int i;
265
266 cur_rx = cur_tx = 0;
267
268 for (i = 0; i < RX_RING_SIZE; i++) {
269 rx_ring[i].status = cpu_to_le32(RRING_OWN); /* Owned by Epic chip */
270 rx_ring[i].buflength = cpu_to_le32(PKT_BUF_SZ);
271 rx_ring[i].bufaddr = virt_to_bus(&rx_packet[i * PKT_BUF_SZ]);
272 rx_ring[i].next = virt_to_le32desc(&rx_ring[i + 1]) ;
273 }
274 /* Mark the last entry as wrapping the ring. */
275 rx_ring[i-1].next = virt_to_le32desc(&rx_ring[0]);
276
277 /*
278 *The Tx buffer descriptor is filled in as needed,
279 * but we do need to clear the ownership bit.
280 */
281
282 for (i = 0; i < TX_RING_SIZE; i++) {
283 tx_ring[i].status = 0x0000; /* Owned by CPU */
284 tx_ring[i].buflength = 0x0000 | cpu_to_le32(TD_STDFLAGS << 16);
285 tx_ring[i].bufaddr = virt_to_bus(&tx_packet[i * PKT_BUF_SZ]);
286 tx_ring[i].next = virt_to_le32desc(&tx_ring[i + 1]);
287 }
288 tx_ring[i-1].next = virt_to_le32desc(&tx_ring[0]);
289 }
290
291 /* function: epic100_transmit
292 * This transmits a packet.
293 *
294 * Arguments: char d[6]: destination ethernet address.
295 * unsigned short t: ethernet protocol type.
296 * unsigned short s: size of the data-part of the packet.
297 * char *p: the data for the packet.
298 * returns: void.
299 */
300 static void
epic100_transmit(struct nic * nic,const char * destaddr,unsigned int type,unsigned int len,const char * data)301 epic100_transmit(struct nic *nic, const char *destaddr, unsigned int type,
302 unsigned int len, const char *data)
303 {
304 unsigned short nstype;
305 unsigned char *txp;
306 int entry;
307
308 /* Calculate the next Tx descriptor entry. */
309 entry = cur_tx % TX_RING_SIZE;
310
311 if ((tx_ring[entry].status & TRING_OWN) == TRING_OWN) {
312 printf("eth_transmit: Unable to transmit. status=%hX. Resetting...\n",
313 tx_ring[entry].status);
314
315 epic100_open();
316 return;
317 }
318
319 txp = tx_packet + (entry * PKT_BUF_SZ);
320
321 memcpy(txp, destaddr, ETH_ALEN);
322 memcpy(txp + ETH_ALEN, nic->node_addr, ETH_ALEN);
323 nstype = htons(type);
324 memcpy(txp + 12, (char*)&nstype, 2);
325 memcpy(txp + ETH_HLEN, data, len);
326
327 len += ETH_HLEN;
328 len &= 0x0FFF;
329 while(len < ETH_ZLEN)
330 txp[len++] = '\0';
331 /*
332 * Caution: the write order is important here,
333 * set the base address with the "ownership"
334 * bits last.
335 */
336
337 tx_ring[entry].buflength |= cpu_to_le32(len);
338 tx_ring[entry].status = cpu_to_le32(len << 16) |
339 cpu_to_le32(TRING_OWN); /* Pass ownership to the chip. */
340
341 cur_tx++;
342
343 /* Trigger an immediate transmit demand. */
344 outl(CR_QUEUE_TX, command);
345
346 load_timer2(10*TICKS_PER_MS); /* timeout 10 ms for transmit */
347 while ((le32_to_cpu(tx_ring[entry].status) & (TRING_OWN)) && timer2_running())
348 /* Wait */;
349
350 if ((le32_to_cpu(tx_ring[entry].status) & TRING_OWN) != 0)
351 printf("Oops, transmitter timeout, status=%hX\n",
352 tx_ring[entry].status);
353 }
354
355 /* function: epic100_poll / eth_poll
356 * This receives a packet from the network.
357 *
358 * Arguments: none
359 *
360 * returns: 1 if a packet was received.
361 * 0 if no pacet was received.
362 * side effects:
363 * returns the packet in the array nic->packet.
364 * returns the length of the packet in nic->packetlen.
365 */
366
367 static int
epic100_poll(struct nic * nic,int retrieve)368 epic100_poll(struct nic *nic, int retrieve)
369 {
370 int entry;
371 int retcode;
372 int status;
373 entry = cur_rx % RX_RING_SIZE;
374
375 if ((rx_ring[entry].status & cpu_to_le32(RRING_OWN)) == RRING_OWN)
376 return (0);
377
378 if ( ! retrieve ) return 1;
379
380 status = le32_to_cpu(rx_ring[entry].status);
381 /* We own the next entry, it's a new packet. Send it up. */
382
383 #if (EPIC_DEBUG > 4)
384 printf("epic_poll: entry %d status %hX\n", entry, status);
385 #endif
386
387 cur_rx++;
388 if (status & 0x2000) {
389 printf("epic_poll: Giant packet\n");
390 retcode = 0;
391 } else if (status & 0x0006) {
392 /* Rx Frame errors are counted in hardware. */
393 printf("epic_poll: Frame received with errors\n");
394 retcode = 0;
395 } else {
396 /* Omit the four octet CRC from the length. */
397 nic->packetlen = le32_to_cpu((rx_ring[entry].buflength))- 4;
398 memcpy(nic->packet, &rx_packet[entry * PKT_BUF_SZ], nic->packetlen);
399 retcode = 1;
400 }
401
402 /* Clear all error sources. */
403 outl(status & INTR_CLEARERRS, intstat);
404
405 /* Give the descriptor back to the chip */
406 rx_ring[entry].status = RRING_OWN;
407
408 /* Restart Receiver */
409 outl(CR_START_RX | CR_QUEUE_RX, command);
410
411 return retcode;
412 }
413
414
415 static void
epic100_disable(struct dev * dev __unused)416 epic100_disable(struct dev *dev __unused)
417 {
418 /* Soft reset the chip. */
419 outl(GC_SOFT_RESET, genctl);
420 }
421
epic100_irq(struct nic * nic __unused,irq_action_t action __unused)422 static void epic100_irq(struct nic *nic __unused, irq_action_t action __unused)
423 {
424 switch ( action ) {
425 case DISABLE :
426 break;
427 case ENABLE :
428 break;
429 case FORCE :
430 break;
431 }
432 }
433
434 #ifdef DEBUG_EEPROM
435 /* Serial EEPROM section. */
436
437 /* EEPROM_Ctrl bits. */
438 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
439 #define EE_CS 0x02 /* EEPROM chip select. */
440 #define EE_DATA_WRITE 0x08 /* EEPROM chip data in. */
441 #define EE_WRITE_0 0x01
442 #define EE_WRITE_1 0x09
443 #define EE_DATA_READ 0x10 /* EEPROM chip data out. */
444 #define EE_ENB (0x0001 | EE_CS)
445
446 /* The EEPROM commands include the alway-set leading bit. */
447 #define EE_WRITE_CMD (5 << 6)
448 #define EE_READ_CMD (6 << 6)
449 #define EE_ERASE_CMD (7 << 6)
450
451 #define eeprom_delay(n) delay(n)
452
453 static int
read_eeprom(int location)454 read_eeprom(int location)
455 {
456 int i;
457 int retval = 0;
458 int read_cmd = location | EE_READ_CMD;
459
460 outl(EE_ENB & ~EE_CS, eectl);
461 outl(EE_ENB, eectl);
462
463 /* Shift the read command bits out. */
464 for (i = 10; i >= 0; i--) {
465 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
466 outl(EE_ENB | dataval, eectl);
467 eeprom_delay(100);
468 outl(EE_ENB | dataval | EE_SHIFT_CLK, eectl);
469 eeprom_delay(150);
470 outl(EE_ENB | dataval, eectl); /* Finish EEPROM a clock tick. */
471 eeprom_delay(250);
472 }
473 outl(EE_ENB, eectl);
474
475 for (i = 16; i > 0; i--) {
476 outl(EE_ENB | EE_SHIFT_CLK, eectl);
477 eeprom_delay(100);
478 retval = (retval << 1) | ((inl(eectl) & EE_DATA_READ) ? 1 : 0);
479 outl(EE_ENB, eectl);
480 eeprom_delay(100);
481 }
482
483 /* Terminate the EEPROM access. */
484 outl(EE_ENB & ~EE_CS, eectl);
485 return retval;
486 }
487 #endif
488
489
490 #define MII_READOP 1
491 #define MII_WRITEOP 2
492
493 static int
mii_read(int phy_id,int location)494 mii_read(int phy_id, int location)
495 {
496 int i;
497
498 outl((phy_id << 9) | (location << 4) | MII_READOP, mmctl);
499 /* Typical operation takes < 50 ticks. */
500
501 for (i = 4000; i > 0; i--)
502 if ((inl(mmctl) & MII_READOP) == 0)
503 break;
504 return inw(mmdata);
505 }
506
507
508 static struct pci_id epic100_nics[] = {
509 PCI_ROM(0x10b8, 0x0005, "epic100", "SMC EtherPowerII"), /* SMC 83c170 EPIC/100 */
510 PCI_ROM(0x10b8, 0x0006, "smc-83c175", "SMC EPIC/C 83c175"),
511 };
512
513 struct pci_driver epic100_driver = {
514 .type = NIC_DRIVER,
515 .name = "EPIC100",
516 .probe = epic100_probe,
517 .ids = epic100_nics,
518 .id_count = sizeof(epic100_nics)/sizeof(epic100_nics[0]),
519 .class = 0,
520 };
521