1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * 24 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 25 * Use is subject to license terms. 26 */ 27 28 #pragma ident "%Z%%M% %I% %E% SMI" 29 30 #include <mcamd_api.h> 31 #include <mcamd_err.h> 32 #include <mcamd_rowcol_impl.h> 33 34 /* 35 * Chip-Select Bank Address Mode Encodings - BKDG 3.29 3.5.6 36 */ 37 static const struct bankaddr_mode bankaddr_modes_pre_d[]; 38 static const struct bankaddr_mode bankaddr_modes_d_e[]; 39 40 static const struct bam_desc { 41 int rev; 42 int nmodes; 43 const struct bankaddr_mode *modetbl; 44 } bankaddr_modes[] = { 45 { MC_REV_PRE_D, 7, bankaddr_modes_pre_d }, 46 { MC_REV_D_E, 11, bankaddr_modes_d_e }, 47 }; 48 49 /* 50 * DRAM Address Mappings for bank/row/column - BKDG 3.29 3.5.6.1 51 */ 52 static const struct csrcb_map_tbl dram_addrmap_pre_d_128; 53 static const struct csrcb_map_tbl dram_addrmap_pre_d_64; 54 static const struct csrcb_map_tbl dram_addrmap_d_e_64; 55 static const struct csrcb_map_tbl dram_addrmap_d_e_128; 56 57 static const struct rcbmap_desc { 58 int nmodes; 59 const struct csrcb_map_tbl *rcbmap; 60 } rcbmaps[] = { 61 { 7, &dram_addrmap_pre_d_64 }, 62 { 7, &dram_addrmap_pre_d_128 }, 63 { 11, &dram_addrmap_d_e_64 }, 64 { 11, &dram_addrmap_d_e_128 }, 65 }; 66 67 /* 68 * Lookup the Chip-Select Bank Address Mode Encoding table for a given 69 * chip revision and chip-select mode. 70 */ 71 const struct bankaddr_mode * 72 rct_bankaddr_mode(uint_t mcrev, uint_t csmode) 73 { 74 int i; 75 const struct bam_desc *bdp = bankaddr_modes; 76 77 for (i = 0; i < sizeof (bankaddr_modes) / sizeof (struct bam_desc); 78 i++, bdp++) { 79 if (bdp->rev == mcrev && csmode < bdp->nmodes) 80 return (&bdp->modetbl[csmode]); 81 82 } 83 84 return (NULL); 85 } 86 87 /* 88 * Lookup the DRAM Address Mapping table for a given chip revision, access 89 * width, bank-swizzle and chip-select mode. 90 */ 91 const struct csrcb_map * 92 rct_rcbmap(uint_t mcrev, int width, uint_t csmode) 93 { 94 const struct csrcb_map_tbl *rcbm; 95 int i; 96 97 for (i = 0; i < sizeof (rcbmaps) / sizeof (struct rcbmap_desc); i++) { 98 rcbm = rcbmaps[i].rcbmap; 99 if (rcbm->mt_rev == mcrev && rcbm->mt_width == width && 100 csmode < rcbmaps[i].nmodes) 101 return (&rcbm->mt_csmap[csmode]); 102 } 103 104 return (NULL); 105 } 106 107 /* 108 * DRAM Address Mapping in Interleaving Mode - BKDG 3.29 section 3.5.6.2. 109 * 110 * Chip-select interleave is performed by addressing across the columns 111 * of the first row of internal bank-select 0 on a chip-select, then the 112 * next row on internal bank-select 1, then 2 then 3; instead of then 113 * moving on to the next row of this chip-select we then rotate across 114 * other chip-selects in the interleave. The row/column/bank mappings 115 * described elsewhere in this file show that a DRAM InputAddr breaks down 116 * as follows (example is the first line of table 7 which is for a 32MB 117 * chip-select requiring 25 bits to address all of it) for the non-interleaved 118 * case: 119 * 120 * chip-selection bits | offset within chip-select bits | 121 * | row bits | bank bits | column bits | - | 122 * 24 13 12 11 10 3 2 0 123 * 124 * The high-order chip-selection bits select the chip-select and the 125 * offset bits offset within the chosen chip-select. 126 * 127 * To establish say a 2-way interleave in which we consume all of one 128 * row number and all internal bank numbers on one cs before moving on 129 * to the next to do the same we will target the first row bit - bit 13; 130 * a 4-way interleave would use bits 14 and 13, and an 8-way interleave 131 * bits 15, 14 and 13. We swap the chosen bits with the least significant 132 * high order chip-selection bits. 133 * 134 * Tables 13-16 of BKDG 3.5.6.2 really just describe the above. Working 135 * out the high-order bits to swap is easy since that is derived directly 136 * from the chip-select size. The low-order bits depend on the device 137 * parameters since we need to target the least significant row address bits - 138 * but we have that information from the rcbmaps since the first row bit 139 * simply follows the last bank address bit. 140 * 141 * Short version: we will do tables 13 to 16 programatically rather than 142 * replicating those tables. 143 */ 144 145 /* 146 * Yet another highbit function. This really needs to go to common source. 147 * Returns range 0 to 64 inclusive; 148 */ 149 static int 150 topbit(uint64_t i) 151 { 152 int h = 1; 153 154 if (i == 0) 155 return (0); 156 157 if (i & 0xffffffff00000000ULL) { 158 h += 32; 159 i >>= 32; 160 } 161 162 if (i & 0xffff0000) { 163 h += 16; 164 i >>= 16; 165 } 166 167 if (i & 0xff00) { 168 h += 8; 169 i >>= 8; 170 } 171 172 if (i & 0xf0) { 173 h += 4; 174 i >>= 4; 175 } 176 177 if (i & 0xc) { 178 h += 2; 179 i >>= 2; 180 } 181 182 if (i & 0x2) 183 h += 1; 184 185 return (h); 186 } 187 188 void 189 rct_csintlv_bits(uint_t mcrev, int width, uint_t csmode, int factor, 190 struct csintlv_desc *csid) 191 { 192 int i, lstbnkbit; 193 size_t csz; 194 const struct bankaddr_mode *bam; 195 const struct csrcb_map *rcm; 196 197 /* 198 * 8-way cs interleave for some large cs sizes in 128-bit mode is 199 * not implemented. 200 */ 201 if (factor == 8 && width == 128 && 202 ((mcrev == MC_REV_PRE_D && csmode == 0x6) || 203 (mcrev == MC_REV_D_E && (csmode == 0x9 || csmode == 0xa)))) { 204 csid->csi_factor = 0; 205 return; 206 } 207 208 if ((bam = rct_bankaddr_mode(mcrev, csmode)) == NULL || 209 (rcm = rct_rcbmap(mcrev, width, csmode)) == NULL) { 210 csid->csi_factor = 0; 211 return; 212 } 213 214 csz = MC_CS_SIZE(bam, width); 215 216 switch (factor) { 217 case 2: 218 csid->csi_nbits = 1; 219 break; 220 case 4: 221 csid->csi_nbits = 2; 222 break; 223 case 8: 224 csid->csi_nbits = 3; 225 break; 226 default: 227 csid->csi_factor = 0; 228 return; 229 } 230 231 csid->csi_hibit = topbit(csz) - 1; 232 233 lstbnkbit = 0; 234 for (i = 0; i < MC_RC_BANKBITS; i++) { 235 /* first bank arg for a bit is "real" bank bit */ 236 if (rcm->csrcb_bankargs[i][0] > lstbnkbit) 237 lstbnkbit = rcm->csrcb_bankargs[i][0]; 238 } 239 240 /* first row bit is immediately after last bank bit */ 241 csid->csi_lobit = lstbnkbit + 1; 242 243 csid->csi_factor = factor; 244 } 245 246 247 /* 248 * General notes for CS Bank Address Mode Encoding tables. 249 * 250 * These are the tables of BKDG 3.29 section 3.5.6. They are indexed 251 * by chip-select mode. Where the numbers of rows and columns is 252 * ambiguous (as it is for a number of rev CG and earlier cases) 253 * the bam_config should be initialized to 1 and the numbers of rows 254 * and columns should be the maximums. 255 */ 256 257 /* 258 * Chip Select Bank Address Mode Encoding for rev CG and earlier. 259 */ 260 static const struct bankaddr_mode bankaddr_modes_pre_d[] = { 261 { /* 000 */ 262 32, 12, 8 263 }, 264 { /* 001 */ 265 64, 12, 9 266 }, 267 { /* 010 */ 268 128, 13, 10, 1 269 }, 270 { /* 011 */ 271 256, 13, 11, 1 272 }, 273 { /* 100 */ 274 512, 14, 11, 1 275 }, 276 { /* 101 */ 277 1024, 14, 12, 1 278 }, 279 { /* 110 */ 280 2048, 14, 12 281 } 282 }; 283 284 /* 285 * Chip Select Bank Address Mode Encoding for revs D and E. 286 */ 287 static const struct bankaddr_mode bankaddr_modes_d_e[] = { 288 { /* 0000 */ 289 32, 12, 8 290 }, 291 { /* 0001 */ 292 64, 12, 9 293 }, 294 { /* 0010 */ 295 128, 13, 9 296 }, 297 { /* 0011 */ 298 128, 12, 10 299 }, 300 { /* 0100 */ 301 256, 13, 10 302 }, 303 { /* 0101 */ 304 512, 14, 10 305 }, 306 { /* 0110 */ 307 256, 12, 11 308 }, 309 { /* 0111 */ 310 512, 13, 11 311 }, 312 { /* 1000 */ 313 1024, 14, 11 314 }, 315 { /* 1001 */ 316 1024, 13, 12 317 }, 318 { /* 1010 */ 319 2048, 14, 12 320 } 321 }; 322 323 /* 324 * General notes on Row/Column/Bank table initialisation. 325 * 326 * These are the tables 7, 8, 9, 10, 11 and 12 of BKDG 3.29 section 3.5.6.1. 327 * They apply in non-interleave (node or cs) mode and describe how for 328 * a given revision, access width, bank-swizzle mode, and current chip-select 329 * mode the row, column and internal sdram bank are derived from the 330 * normalizied InputAddr presented to the DRAM controller. 331 * 332 * The mt_csmap array is indexed by chip-select mode. Within it the 333 * bankargs, rowbits and colbits arrays are indexed by bit number, so 334 * match the BKDG tables if the latter are read right-to-left. 335 * 336 * The bankargs list up to three bit numbers per bank bit. For revisions 337 * CG and earlier there is no bank swizzling, so just a single number 338 * should be listed. Revisions D and E have the same row/column/bank mapping, 339 * but rev E has the additional feature of being able to xor two row bits 340 * into each bank bit. The consumer will know whether they are using bank 341 * swizzling - if so then they should xor the bankargs bits together. 342 * The first argument must be the bit number not already used in forming 343 * part of the row address - eg in table 12 for csmode 0000b bank address 344 * bit 0 is bit 12 xor bit 18 xor bit 21, and 18 and 21 are also mentioned in 345 * the row address (bits 10 and 1) so we must list bit 12 first. We will 346 * use this information in chip-select interleave decoding in which we need 347 * to know which is the first bit after column and bank address bits. 348 * 349 * Column address A10 is always used for the Precharge All signal. Where 350 * "PC" appears in the BKDG tables we will include MC_PC_ALL in the 351 * corresponding bit position. 352 * 353 * For some rev CG and earlier chipselect modes the number of rows and columns 354 * is ambiguous. This is reflected in these tables by some bit being 355 * duplicated between row and column address. In practice we will follow 356 * the convention of always assigning the floating bit to the row address. 357 */ 358 359 /* 360 * Row/Column/Bank address mappings for rev CG in 64-bit mode, no interleave. 361 * See BKDG 3.29 3.5.6 Table 7. 362 */ 363 static const struct csrcb_map_tbl dram_addrmap_pre_d_64 = { 364 MC_REV_PRE_D, 365 64, 366 { 367 { /* 000 */ 368 { { 11 }, { 12 } }, 369 { 19, 20, 21, 22, 23, 24, 13, 14, 15, 16, 17, 18 }, 370 { 3, 4, 5, 6, 7, 8, 9, 10 } 371 }, 372 { /* 001 */ 373 { { 13 }, { 12 } }, 374 { 19, 20, 21, 22, 23, 24, 25, 14, 15, 16, 17, 18 }, 375 { 3, 4, 5, 6, 7, 8, 9, 10, 11 } 376 }, 377 { /* 010 */ 378 { { 13 }, { 12 } }, 379 { 19, 20, 21, 22, 23, 24, 25, 14, 15, 16, 17, 18, 26 }, 380 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 26 } 381 }, 382 { /* 011 */ 383 { { 13 }, { 14 } }, 384 { 19, 20, 21, 22, 23, 24, 25, 26, 15, 16, 17, 18, 27 }, 385 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 27 } 386 }, 387 { /* 100 */ 388 { { 13 }, { 14 } }, 389 { 19, 20, 21, 22, 23, 24, 25, 26, 15, 16, 17, 18, 27, 28 }, 390 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 28 } 391 }, 392 { /* 101 */ 393 { { 15 }, { 14 } }, 394 { 19, 20, 21, 22, 23, 24, 25, 26, 29, 16, 17, 18, 27, 28 }, 395 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13, 28 } 396 }, 397 { /* 110 */ 398 { { 15 }, { 14 } }, 399 { 19, 20, 21, 22, 23, 24, 25, 26, 29, 16, 17, 18, 27, 28 }, 400 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13, 30 } 401 }, 402 /* 403 * remainder unused 404 */ 405 } 406 407 }; 408 409 /* 410 * Row/Column/Bank address mappings for rev CG in 128-bit mode, no interleave. 411 * See BKDG 3.29 3.5.6 Table 8. 412 */ 413 static const struct csrcb_map_tbl dram_addrmap_pre_d_128 = { 414 MC_REV_PRE_D, 415 128, 416 { 417 { /* 000 */ 418 { { 12 }, { 13 } }, 419 { 20, 21, 22, 23, 24, 25, 14, 15, 16, 17, 18, 19 }, 420 { 4, 5, 6, 7, 8, 9, 10, 11 } 421 }, 422 { /* 001 */ 423 { { 14 }, { 13 } }, 424 { 20, 21, 22, 23, 24, 25, 26, 15, 16, 17, 18, 19 }, 425 { 4, 5, 6, 7, 8, 9, 10, 11, 12 } 426 }, 427 { /* 010 */ 428 { { 14 }, { 13 } }, 429 { 20, 21, 22, 23, 24, 25, 26, 15, 16, 17, 18, 19, 27 }, 430 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 27 } 431 }, 432 { /* 011 */ 433 { { 14 }, { 15 } }, 434 { 20, 21, 22, 23, 24, 25, 26, 27, 16, 17, 18, 19, 28 }, 435 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 28 } 436 }, 437 { /* 100 */ 438 { { 14 }, { 15 } }, 439 { 20, 21, 22, 23, 24, 25, 26, 27, 16, 17, 18, 19, 28, 29 }, 440 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 29 } 441 }, 442 { /* 101 */ 443 { { 16 }, { 15 } }, 444 { 20, 21, 22, 23, 24, 25, 26, 27, 30, 17, 18, 19, 28, 29 }, 445 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 14, 29 } 446 }, 447 { /* 110 */ 448 { { 16 }, { 15 } }, 449 { 20, 21, 22, 23, 24, 25, 26, 27, 30, 17, 18, 19, 28, 29 }, 450 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 14, 31 } 451 }, 452 /* 453 * remainder unused 454 */ 455 } 456 }; 457 458 /* 459 * Row/Column/Bank address mappings for rev D/E in 64-bit mode, no interleave. 460 * See BKDG 3.29 3.5.6 Table 9. 461 */ 462 static const struct csrcb_map_tbl dram_addrmap_d_e_64 = { 463 MC_REV_D_E, 464 64, 465 { 466 { /* 0000 */ 467 { { 11, 17, 20 }, { 12, 18, 21 } }, 468 { 19, 20, 21, 22, 23, 24, 13, 14, 15, 16, 17, 18 }, 469 { 3, 4, 5, 6, 7, 8, 9, 10 } 470 }, 471 { /* 0001 */ 472 { { 12, 17, 20 }, { 13, 18, 21 } }, 473 { 19, 20, 21, 22, 23, 24, 25, 14, 15, 16, 17, 18, 26 }, 474 { 3, 4, 5, 6, 7, 8, 9, 10, 11 } 475 }, 476 { /* 0010 */ 477 { { 12, 17, 20 }, { 13, 18, 21 } }, 478 { 19, 20, 21, 22, 23, 24, 25, 14, 15, 16, 17, 18, 26 }, 479 { 3, 4, 5, 6, 7, 8, 9, 10, 11 } 480 }, 481 { /* 0011 */ 482 { { 13, 17, 20 }, { 14, 18, 21 } }, 483 { 19, 20, 21, 22, 23, 24, 25, 26, 15, 16, 17, 18, 27, 28 }, 484 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 } 485 }, 486 { /* 0100 */ 487 { { 13, 17, 20 }, { 14, 18, 21 } }, 488 { 19, 20, 21, 22, 23, 24, 25, 26, 15, 16, 17, 18, 27, 28 }, 489 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 } 490 }, 491 { /* 0101 */ 492 { { 13, 17, 20 }, { 14, 18, 21 } }, 493 { 19, 20, 21, 22, 23, 24, 25, 26, 15, 16, 17, 18, 27, 28 }, 494 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 } 495 }, 496 { /* 0110 */ 497 { { 14, 17, 20 }, { 15, 18, 21 } }, 498 { 19, 20, 21, 22, 23, 24, 25, 26, 27, 16, 17, 18, 28, 29 }, 499 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13 } 500 }, 501 { /* 0111 */ 502 { { 14, 17, 20 }, { 15, 18, 21 } }, 503 { 19, 20, 21, 22, 23, 24, 25, 26, 27, 16, 17, 18, 28, 29 }, 504 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13 } 505 }, 506 { /* 1000 */ 507 { { 14, 17, 20 }, { 15, 18, 21 } }, 508 { 19, 20, 21, 22, 23, 24, 25, 26, 27, 16, 17, 18, 28, 29 }, 509 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13 } 510 }, 511 { /* 1001 */ 512 { { 15, 17, 20 }, { 16, 18, 21 } }, 513 { 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 17, 18, 29, 30 }, 514 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13, 14 } 515 }, 516 { /* 1010 */ 517 { { 15, 17, 20 }, { 16, 18, 21 } }, 518 { 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 17, 18, 29, 30 }, 519 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13, 14 } 520 }, 521 /* 522 * remainder unused 523 */ 524 } 525 }; 526 527 /* 528 * Row/Column/Bank address mappings for rev D/E in 128-bit mode, no interleave. 529 * See BKDG 3.29 3.5.6 Table 9. 530 */ 531 static const struct csrcb_map_tbl dram_addrmap_d_e_128 = { 532 MC_REV_D_E, 533 128, 534 { 535 { /* 0000 */ 536 { { 12, 18, 21 }, { 13, 19, 22 } }, 537 { 20, 21, 22, 23, 24, 25, 14, 15, 16, 17, 18, 19 }, 538 { 4, 5, 6, 7, 8, 9, 10, 11 } 539 }, 540 { /* 0001 */ 541 { { 13, 18, 21 }, { 14, 19, 22 } }, 542 { 20, 21, 22, 23, 24, 25, 26, 15, 16, 17, 18, 19, 27 }, 543 { 4, 5, 6, 7, 8, 9, 10, 11, 12 } 544 }, 545 { /* 0010 */ 546 { { 13, 18, 21 }, { 14, 19, 22 } }, 547 { 20, 21, 22, 23, 24, 25, 26, 15, 16, 17, 18, 19, 27 }, 548 { 4, 5, 6, 7, 8, 9, 10, 11, 12 } 549 }, 550 { /* 0011 */ 551 { { 14, 18, 21 }, { 15, 19, 22 } }, 552 { 20, 21, 22, 23, 24, 25, 26, 27, 16, 17, 18, 19, 28, 29 }, 553 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 } 554 }, 555 { /* 0100 */ 556 { { 14, 18, 21 }, { 15, 19, 22 } }, 557 { 20, 21, 22, 23, 24, 25, 26, 27, 16, 17, 18, 19, 28, 29 }, 558 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 } 559 }, 560 { /* 0101 */ 561 { { 14, 18, 21 }, { 15, 19, 22 } }, 562 { 20, 21, 22, 23, 24, 25, 26, 27, 16, 17, 18, 19, 28, 29 }, 563 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 } 564 }, 565 { /* 0110 */ 566 { { 15, 18, 21 }, { 16, 19, 22 } }, 567 { 20, 21, 22, 23, 24, 25, 26, 27, 28, 17, 18, 19, 29, 30 }, 568 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 14 } 569 }, 570 { /* 0111 */ 571 { { 15, 18, 21 }, { 16, 19, 22 } }, 572 { 20, 21, 22, 23, 24, 25, 26, 27, 28, 17, 18, 19, 29, 30 }, 573 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 14 } 574 }, 575 { /* 1000 */ 576 { { 15, 18, 21 }, { 16, 19, 22 } }, 577 { 20, 21, 22, 23, 24, 25, 26, 27, 28, 17, 18, 19, 29, 30 }, 578 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 14 } 579 }, 580 { /* 1001 */ 581 { { 16, 18, 21 }, { 17, 19, 22 } }, 582 { 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 18, 19, 30, 31 }, 583 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 14, 15 } 584 }, 585 { /* 1010 */ 586 { { 16, 18, 21 }, { 17, 19, 22 } }, 587 { 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 18, 19, 30, 31 }, 588 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 14, 15 } 589 }, 590 /* 591 * remainder unused 592 */ 593 } 594 }; 595