xref: /titanic_41/usr/src/cmd/devfsadm/cfg_link.h (revision 2f0fcb93196badcdd803715656c809058d9f3114)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 /* private devlink info interfaces */
27 
28 #ifndef	_CFG_LINK_H
29 #define	_CFG_LINK_H
30 
31 #include <devfsadm.h>
32 
33 #ifdef	__cplusplus
34 extern "C" {
35 #endif
36 
37 #define	SCSI_CFG_LINK_RE	"^cfg/c[0-9]+$"
38 #define	SBD_CFG_LINK_RE		"^cfg/((((N[0-9]+[.])?(SB|IB))?[0-9]+)|[abcd])$"
39 #define	USB_CFG_LINK_RE		"^cfg/((usb[0-9]+)/([0-9]+)([.]([0-9])+)*)$"
40 #define	PCI_CFG_LINK_RE		"^cfg/[:alnum:]$"
41 #define	IB_CFG_LINK_RE		"^cfg/(hca[0-9A-F]+)$"
42 #define	SATA_CFG_LINK_RE	"^cfg/((sata[0-9]+)/([0-9]+)([.]([0-9])+)*)$"
43 #define	SDCARD_CFG_LINK_RE	"^cfg/sdcard[0-9]+/[0-9]+$"
44 #define	PCI_CFG_PATH_LINK_RE	\
45 	"^cfg/(.*(pci[0-9]|pcie[0-9]|Slot[0-9]|\\<pci\\>|\\<pcie\\>).*)$"
46 
47 #define	CFG_DIRNAME		"cfg"
48 
49 #define	PROPVAL_PCIEX		"pciex"
50 #define	DEVTYPE_PCIE		"pcie"
51 #define	IOB_PRE			"iob"
52 #define	AP_PATH_SEP		":"
53 #define	AP_PATH_IOB_SEP		"."
54 #define	IEEE_SUN_ID		0x080020
55 #define	APNODE_DEFNAME		0x1
56 #define	PCIDEV_NIL		((minor_t)-1)
57 
58 /* converts size in bits to a mask covering those bit positions */
59 #define	SIZE2MASK(s)		((1 << (s)) - 1)
60 #define	SIZE2MASK64(s)		((1LL << (s)) - 1LL)
61 
62 /*
63  * macros for the ieee1275 "reg" property
64  * naming format and semantics:
65  *
66  * REG_<cell>_SIZE_<field> = bit size of <field> in <cell>
67  * REG_<cell>_OFF_<field> = starting bit position of <field> in <cell>
68  *
69  * REG_<cell>_<field>(r) = returns the value of <field> in <cell> using:
70  *	(((r) >> REG_<cell>_OFF_<field>) & SIZE2MASK(REG_<cell>_SIZE_<field>))
71  */
72 #define	REG_PHYSHI_SIZE_PCIDEV	5
73 #define	REG_PHYSHI_OFF_PCIDEV	11
74 #define	REG_PHYSHI_PCIDEV(r)	\
75 	(((r) >> REG_PHYSHI_OFF_PCIDEV) & SIZE2MASK(REG_PHYSHI_SIZE_PCIDEV))
76 
77 /* rp = ptr to 5-tuple int array */
78 #define	REG_PHYSHI_INDEX	0
79 #define	REG_PHYSHI(rp)		((rp)[REG_PHYSHI_INDEX])
80 
81 #define	REG_PCIDEV(rp)		(REG_PHYSHI_PCIDEV(REG_PHYSHI(rp)))
82 
83 
84 #define	DEV "/dev"
85 #define	DEV_LEN 4
86 #define	DEVICES "/devices"
87 #define	DEVICES_LEN 8
88 
89 #ifdef	__cplusplus
90 }
91 #endif
92 
93 #endif /* _CFG_LINK_H */
94