1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* Copyright (c) 1984, 1986, 1987, 1988, 1989 AT&T */ 27 /* All Rights Reserved */ 28 29 /* 30 * Portions of this source code were derived from Berkeley 4.3 BSD 31 * under license from the Regents of the University of California. 32 */ 33 34 #pragma ident "%Z%%M% %I% %E% SMI" 35 36 /* 37 * UNIX machine dependent virtual memory support. 38 */ 39 40 #include <sys/vm.h> 41 #include <sys/exec.h> 42 #include <sys/cmn_err.h> 43 #include <sys/cpu_module.h> 44 #include <sys/cpu.h> 45 #include <sys/elf_SPARC.h> 46 #include <sys/archsystm.h> 47 #include <vm/hat_sfmmu.h> 48 #include <sys/memnode.h> 49 #include <sys/mem_cage.h> 50 #include <vm/vm_dep.h> 51 #include <sys/error.h> 52 #include <sys/machsystm.h> 53 #include <vm/seg_kmem.h> 54 55 uint_t page_colors = 0; 56 uint_t page_colors_mask = 0; 57 uint_t page_coloring_shift = 0; 58 int consistent_coloring; 59 60 uint_t mmu_page_sizes = MMU_PAGE_SIZES; 61 uint_t max_mmu_page_sizes = MMU_PAGE_SIZES; 62 uint_t mmu_hashcnt = MAX_HASHCNT; 63 uint_t max_mmu_hashcnt = MAX_HASHCNT; 64 size_t mmu_ism_pagesize = DEFAULT_ISM_PAGESIZE; 65 66 /* 67 * A bitmask of the page sizes supported by hardware based upon szc. 68 * The base pagesize (p_szc == 0) must always be supported by the hardware. 69 */ 70 int mmu_exported_pagesize_mask; 71 uint_t mmu_exported_page_sizes; 72 73 uint_t szc_2_userszc[MMU_PAGE_SIZES]; 74 uint_t userszc_2_szc[MMU_PAGE_SIZES]; 75 76 extern uint_t vac_colors_mask; 77 extern int vac_shift; 78 79 hw_pagesize_t hw_page_array[] = { 80 {MMU_PAGESIZE, MMU_PAGESHIFT, 0, MMU_PAGESIZE >> MMU_PAGESHIFT}, 81 {MMU_PAGESIZE64K, MMU_PAGESHIFT64K, 0, 82 MMU_PAGESIZE64K >> MMU_PAGESHIFT}, 83 {MMU_PAGESIZE512K, MMU_PAGESHIFT512K, 0, 84 MMU_PAGESIZE512K >> MMU_PAGESHIFT}, 85 {MMU_PAGESIZE4M, MMU_PAGESHIFT4M, 0, MMU_PAGESIZE4M >> MMU_PAGESHIFT}, 86 {MMU_PAGESIZE32M, MMU_PAGESHIFT32M, 0, 87 MMU_PAGESIZE32M >> MMU_PAGESHIFT}, 88 {MMU_PAGESIZE256M, MMU_PAGESHIFT256M, 0, 89 MMU_PAGESIZE256M >> MMU_PAGESHIFT}, 90 {0, 0, 0, 0} 91 }; 92 93 /* 94 * Enable usage of 64k/4M pages for text and 64k pages for initdata for 95 * all sun4v platforms. These variables can be overwritten by the platmod 96 * or the CPU module. User can also change the setting via /etc/system. 97 */ 98 99 int use_text_pgsz64k = 1; 100 int use_text_pgsz4m = 1; 101 int use_initdata_pgsz64k = 1; 102 103 /* 104 * disable_text_largepages and disable_initdata_largepages bitmaks reflect 105 * both unconfigured and undesirable page sizes. Current implementation 106 * supports 64K and 4M page sizes for text and only 64K for data. Rest of 107 * the page sizes are not currently supported, hence disabled below. In 108 * future, when support is added for any other page size, it should be 109 * reflected below. 110 * 111 * Note that these bitmask can be set in platform or CPU specific code to 112 * disable page sizes that should not be used. These variables normally 113 * shouldn't be changed via /etc/system. 114 * 115 * These bitmasks are also updated within hat_init to reflect unsupported 116 * page sizes on a sun4v processor per mmu_exported_pagesize_mask global 117 * variable. 118 */ 119 120 int disable_text_largepages = 121 (1 << TTE512K) | (1 << TTE32M) | (1 << TTE256M) | (1 << TTE2G) | 122 (1 << TTE16G); 123 int disable_initdata_largepages = 124 (1 << TTE512K) | (1 << TTE4M) | (1 << TTE32M) | (1 << TTE256M) | 125 (1 << TTE2G) | (1 << TTE16G); 126 127 /* 128 * Minimum segment size tunables before 64K or 4M large pages 129 * should be used to map it. 130 */ 131 size_t text_pgsz64k_minsize = MMU_PAGESIZE64K; 132 size_t text_pgsz4m_minsize = MMU_PAGESIZE4M; 133 size_t initdata_pgsz64k_minsize = MMU_PAGESIZE64K; 134 135 size_t max_shm_lpsize = MMU_PAGESIZE4M; 136 137 /* Auto large page tunables. */ 138 int auto_lpg_tlb_threshold = 32; 139 int auto_lpg_minszc = TTE64K; 140 int auto_lpg_maxszc = TTE64K; 141 size_t auto_lpg_heap_default = MMU_PAGESIZE64K; 142 size_t auto_lpg_stack_default = MMU_PAGESIZE64K; 143 size_t auto_lpg_va_default = MMU_PAGESIZE64K; 144 size_t auto_lpg_remap_threshold = 0; /* always remap */ 145 /* 146 * Number of pages in 1 GB. Don't enable automatic large pages if we have 147 * fewer than this many pages. 148 */ 149 pgcnt_t auto_lpg_min_physmem = 1 << (30 - MMU_PAGESHIFT); 150 151 /* 152 * map_addr_proc() is the routine called when the system is to 153 * choose an address for the user. We will pick an address 154 * range which is just below the current stack limit. The 155 * algorithm used for cache consistency on machines with virtual 156 * address caches is such that offset 0 in the vnode is always 157 * on a shm_alignment'ed aligned address. Unfortunately, this 158 * means that vnodes which are demand paged will not be mapped 159 * cache consistently with the executable images. When the 160 * cache alignment for a given object is inconsistent, the 161 * lower level code must manage the translations so that this 162 * is not seen here (at the cost of efficiency, of course). 163 * 164 * addrp is a value/result parameter. 165 * On input it is a hint from the user to be used in a completely 166 * machine dependent fashion. For MAP_ALIGN, addrp contains the 167 * minimal alignment. 168 * 169 * On output it is NULL if no address can be found in the current 170 * processes address space or else an address that is currently 171 * not mapped for len bytes with a page of red zone on either side. 172 * If vacalign is true, then the selected address will obey the alignment 173 * constraints of a vac machine based on the given off value. 174 */ 175 /*ARGSUSED3*/ 176 void 177 map_addr_proc(caddr_t *addrp, size_t len, offset_t off, int vacalign, 178 caddr_t userlimit, struct proc *p, uint_t flags) 179 { 180 struct as *as = p->p_as; 181 caddr_t addr; 182 caddr_t base; 183 size_t slen; 184 uintptr_t align_amount; 185 int allow_largepage_alignment = 1; 186 187 base = p->p_brkbase; 188 if (userlimit < as->a_userlimit) { 189 /* 190 * This happens when a program wants to map something in 191 * a range that's accessible to a program in a smaller 192 * address space. For example, a 64-bit program might 193 * be calling mmap32(2) to guarantee that the returned 194 * address is below 4Gbytes. 195 */ 196 ASSERT(userlimit > base); 197 slen = userlimit - base; 198 } else { 199 slen = p->p_usrstack - base - (((size_t)rctl_enforced_value( 200 rctlproc_legacy[RLIMIT_STACK], p->p_rctls, p) + PAGEOFFSET) 201 & PAGEMASK); 202 } 203 len = (len + PAGEOFFSET) & PAGEMASK; 204 205 /* 206 * Redzone for each side of the request. This is done to leave 207 * one page unmapped between segments. This is not required, but 208 * it's useful for the user because if their program strays across 209 * a segment boundary, it will catch a fault immediately making 210 * debugging a little easier. 211 */ 212 len += (2 * PAGESIZE); 213 214 /* 215 * If the request is larger than the size of a particular 216 * mmu level, then we use that level to map the request. 217 * But this requires that both the virtual and the physical 218 * addresses be aligned with respect to that level, so we 219 * do the virtual bit of nastiness here. 220 * 221 * For 32-bit processes, only those which have specified 222 * MAP_ALIGN or an addr will be aligned on a page size > 4MB. Otherwise 223 * we can potentially waste up to 256MB of the 4G process address 224 * space just for alignment. 225 * 226 * XXXQ Should iterate trough hw_page_array here to catch 227 * all supported pagesizes 228 */ 229 if (p->p_model == DATAMODEL_ILP32 && ((flags & MAP_ALIGN) == 0 || 230 ((uintptr_t)*addrp) != 0)) { 231 allow_largepage_alignment = 0; 232 } 233 if ((mmu_page_sizes == max_mmu_page_sizes) && 234 allow_largepage_alignment && 235 (len >= MMU_PAGESIZE256M)) { /* 256MB mappings */ 236 align_amount = MMU_PAGESIZE256M; 237 } else if ((mmu_page_sizes == max_mmu_page_sizes) && 238 allow_largepage_alignment && 239 (len >= MMU_PAGESIZE32M)) { /* 32MB mappings */ 240 align_amount = MMU_PAGESIZE32M; 241 } else if (len >= MMU_PAGESIZE4M) { /* 4MB mappings */ 242 align_amount = MMU_PAGESIZE4M; 243 } else if (len >= MMU_PAGESIZE512K) { /* 512KB mappings */ 244 align_amount = MMU_PAGESIZE512K; 245 } else if (len >= MMU_PAGESIZE64K) { /* 64KB mappings */ 246 align_amount = MMU_PAGESIZE64K; 247 } else { 248 /* 249 * Align virtual addresses on a 64K boundary to ensure 250 * that ELF shared libraries are mapped with the appropriate 251 * alignment constraints by the run-time linker. 252 */ 253 align_amount = ELF_SPARC_MAXPGSZ; 254 if ((flags & MAP_ALIGN) && ((uintptr_t)*addrp != 0) && 255 ((uintptr_t)*addrp < align_amount)) 256 align_amount = (uintptr_t)*addrp; 257 } 258 259 /* 260 * 64-bit processes require 1024K alignment of ELF shared libraries. 261 */ 262 if (p->p_model == DATAMODEL_LP64) 263 align_amount = MAX(align_amount, ELF_SPARCV9_MAXPGSZ); 264 #ifdef VAC 265 if (vac && vacalign && (align_amount < shm_alignment)) 266 align_amount = shm_alignment; 267 #endif 268 269 if ((flags & MAP_ALIGN) && ((uintptr_t)*addrp > align_amount)) { 270 align_amount = (uintptr_t)*addrp; 271 } 272 len += align_amount; 273 274 /* 275 * Look for a large enough hole starting below the stack limit. 276 * After finding it, use the upper part. Addition of PAGESIZE is 277 * for the redzone as described above. 278 */ 279 as_purge(as); 280 if (as_gap(as, len, &base, &slen, AH_HI, NULL) == 0) { 281 caddr_t as_addr; 282 283 addr = base + slen - len + PAGESIZE; 284 as_addr = addr; 285 /* 286 * Round address DOWN to the alignment amount, 287 * add the offset, and if this address is less 288 * than the original address, add alignment amount. 289 */ 290 addr = (caddr_t)((uintptr_t)addr & (~(align_amount - 1l))); 291 addr += (long)(off & (align_amount - 1l)); 292 if (addr < as_addr) { 293 addr += align_amount; 294 } 295 296 ASSERT(addr <= (as_addr + align_amount)); 297 ASSERT(((uintptr_t)addr & (align_amount - 1l)) == 298 ((uintptr_t)(off & (align_amount - 1l)))); 299 *addrp = addr; 300 301 } else { 302 *addrp = NULL; /* no more virtual space */ 303 } 304 } 305 306 /* 307 * Platform-dependent page scrub call. 308 * We call hypervisor to scrub the page. 309 */ 310 void 311 pagescrub(page_t *pp, uint_t off, uint_t len) 312 { 313 uint64_t pa, length; 314 315 pa = (uint64_t)(pp->p_pagenum << MMU_PAGESHIFT + off); 316 length = (uint64_t)len; 317 318 (void) mem_scrub(pa, length); 319 } 320 321 void 322 sync_data_memory(caddr_t va, size_t len) 323 { 324 /* Call memory sync function */ 325 mem_sync(va, len); 326 } 327 328 size_t 329 mmu_get_kernel_lpsize(size_t lpsize) 330 { 331 extern int mmu_exported_pagesize_mask; 332 uint_t tte; 333 334 if (lpsize == 0) { 335 /* no setting for segkmem_lpsize in /etc/system: use default */ 336 if (mmu_exported_pagesize_mask & (1 << TTE256M)) { 337 lpsize = MMU_PAGESIZE256M; 338 } else if (mmu_exported_pagesize_mask & (1 << TTE4M)) { 339 lpsize = MMU_PAGESIZE4M; 340 } else if (mmu_exported_pagesize_mask & (1 << TTE64K)) { 341 lpsize = MMU_PAGESIZE64K; 342 } else { 343 lpsize = MMU_PAGESIZE; 344 } 345 346 return (lpsize); 347 } 348 349 for (tte = TTE8K; tte <= TTE256M; tte++) { 350 351 if ((mmu_exported_pagesize_mask & (1 << tte)) == 0) 352 continue; 353 354 if (lpsize == TTEBYTES(tte)) 355 return (lpsize); 356 } 357 358 lpsize = TTEBYTES(TTE8K); 359 return (lpsize); 360 } 361 362 void 363 mmu_init_kcontext() 364 { 365 } 366 367 /*ARGSUSED*/ 368 void 369 mmu_init_kernel_pgsz(struct hat *hat) 370 { 371 } 372 373 #define QUANTUM_SIZE 64 374 375 static vmem_t *contig_mem_slab_arena; 376 static vmem_t *contig_mem_arena; 377 378 uint_t contig_mem_slab_size = MMU_PAGESIZE4M; 379 380 static void * 381 contig_mem_span_alloc(vmem_t *vmp, size_t size, int vmflag) 382 { 383 page_t *ppl; 384 page_t *rootpp; 385 caddr_t addr = NULL; 386 pgcnt_t npages = btopr(size); 387 page_t **ppa; 388 int pgflags; 389 int i = 0; 390 391 392 /* 393 * The import request should be at least 394 * contig_mem_slab_size because that is the 395 * slab arena's quantum. The size can be 396 * further restricted since contiguous 397 * allocations larger than contig_mem_slab_size 398 * are not supported here. 399 */ 400 ASSERT(size == contig_mem_slab_size); 401 402 if ((addr = vmem_xalloc(vmp, size, size, 0, 0, 403 NULL, NULL, vmflag)) == NULL) { 404 return (NULL); 405 } 406 407 /* The address should be slab-size aligned. */ 408 ASSERT(((uintptr_t)addr & (contig_mem_slab_size - 1)) == 0); 409 410 if (page_resv(npages, vmflag & VM_KMFLAGS) == 0) { 411 vmem_xfree(vmp, addr, size); 412 return (NULL); 413 } 414 415 pgflags = PG_EXCL; 416 if ((vmflag & VM_NOSLEEP) == 0) 417 pgflags |= PG_WAIT; 418 if (vmflag & VM_PANIC) 419 pgflags |= PG_PANIC; 420 if (vmflag & VM_PUSHPAGE) 421 pgflags |= PG_PUSHPAGE; 422 423 ppl = page_create_va_large(&kvp, (u_offset_t)(uintptr_t)addr, size, 424 pgflags, &kvseg, addr, NULL); 425 426 if (ppl == NULL) { 427 vmem_xfree(vmp, addr, size); 428 page_unresv(npages); 429 return (NULL); 430 } 431 432 rootpp = ppl; 433 ppa = kmem_zalloc(npages * sizeof (page_t *), KM_SLEEP); 434 while (ppl != NULL) { 435 page_t *pp = ppl; 436 ppa[i++] = pp; 437 page_sub(&ppl, pp); 438 ASSERT(page_iolock_assert(pp)); 439 page_io_unlock(pp); 440 } 441 442 /* 443 * Load the locked entry. It's OK to preload the entry into 444 * the TSB since we now support large mappings in the kernel TSB. 445 */ 446 hat_memload_array(kas.a_hat, (caddr_t)rootpp->p_offset, size, 447 ppa, (PROT_ALL & ~PROT_USER) | HAT_NOSYNC, HAT_LOAD_LOCK); 448 449 for (--i; i >= 0; --i) { 450 (void) page_pp_lock(ppa[i], 0, 1); 451 page_unlock(ppa[i]); 452 } 453 454 kmem_free(ppa, npages * sizeof (page_t *)); 455 return (addr); 456 } 457 458 void 459 contig_mem_span_free(vmem_t *vmp, void *inaddr, size_t size) 460 { 461 page_t *pp; 462 caddr_t addr = inaddr; 463 caddr_t eaddr; 464 pgcnt_t npages = btopr(size); 465 pgcnt_t pgs_left = npages; 466 page_t *rootpp = NULL; 467 468 ASSERT(((uintptr_t)addr & (contig_mem_slab_size - 1)) == 0); 469 470 hat_unload(kas.a_hat, addr, size, HAT_UNLOAD_UNLOCK); 471 472 for (eaddr = addr + size; addr < eaddr; addr += PAGESIZE) { 473 pp = page_lookup(&kvp, (u_offset_t)(uintptr_t)addr, SE_EXCL); 474 if (pp == NULL) 475 panic("contig_mem_span_free: page not found"); 476 477 ASSERT(PAGE_EXCL(pp)); 478 page_pp_unlock(pp, 0, 1); 479 480 if (rootpp == NULL) 481 rootpp = pp; 482 if (--pgs_left == 0) { 483 /* 484 * similar logic to segspt_free_pages, but we know we 485 * have one large page. 486 */ 487 page_destroy_pages(rootpp); 488 } 489 } 490 page_unresv(npages); 491 492 if (vmp != NULL) 493 vmem_xfree(vmp, inaddr, size); 494 } 495 496 static void * 497 contig_vmem_xalloc_aligned_wrapper(vmem_t *vmp, size_t size, int vmflag) 498 { 499 return (vmem_xalloc(vmp, size, size, 0, 0, NULL, NULL, vmflag)); 500 } 501 502 /* 503 * conting_mem_alloc_align allocates real contiguous memory with the specified 504 * alignment upto contig_mem_slab_size. The alignment must be a power of 2. 505 */ 506 void * 507 contig_mem_alloc_align(size_t size, size_t align) 508 { 509 ASSERT(align <= contig_mem_slab_size); 510 511 if ((align & (align - 1)) != 0) 512 return (NULL); 513 514 return (vmem_xalloc(contig_mem_arena, size, align, 0, 0, 515 NULL, NULL, VM_NOSLEEP)); 516 } 517 518 /* 519 * Allocates size aligned contiguous memory upto contig_mem_slab_size. 520 * Size must be a power of 2. 521 */ 522 void * 523 contig_mem_alloc(size_t size) 524 { 525 ASSERT((size & (size - 1)) == 0); 526 return (contig_mem_alloc_align(size, size)); 527 } 528 529 void 530 contig_mem_free(void *vaddr, size_t size) 531 { 532 vmem_xfree(contig_mem_arena, vaddr, size); 533 } 534 535 /* 536 * We create a set of stacked vmem arenas to enable us to 537 * allocate large >PAGESIZE chucks of contiguous Real Address space 538 * This is what the Dynamics TSB support does for TSBs. 539 * The contig_mem_arena import functions are exactly the same as the 540 * TSB kmem_default arena import functions. 541 */ 542 void 543 contig_mem_init(void) 544 { 545 546 contig_mem_slab_arena = vmem_create("contig_mem_slab_arena", NULL, 0, 547 contig_mem_slab_size, contig_vmem_xalloc_aligned_wrapper, 548 vmem_xfree, heap_arena, 0, VM_SLEEP); 549 550 contig_mem_arena = vmem_create("contig_mem_arena", NULL, 0, 551 QUANTUM_SIZE, contig_mem_span_alloc, contig_mem_span_free, 552 contig_mem_slab_arena, 0, VM_SLEEP | VM_BESTFIT); 553 554 } 555