1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* Copyright (c) 1984, 1986, 1987, 1988, 1989 AT&T */ 27 /* All Rights Reserved */ 28 29 /* 30 * Portions of this source code were derived from Berkeley 4.3 BSD 31 * under license from the Regents of the University of California. 32 */ 33 34 #pragma ident "%Z%%M% %I% %E% SMI" 35 36 /* 37 * UNIX machine dependent virtual memory support. 38 */ 39 40 #include <sys/vm.h> 41 #include <sys/exec.h> 42 #include <sys/cmn_err.h> 43 #include <sys/cpu_module.h> 44 #include <sys/cpu.h> 45 #include <sys/elf_SPARC.h> 46 #include <sys/archsystm.h> 47 #include <vm/hat_sfmmu.h> 48 #include <sys/memnode.h> 49 #include <sys/mem_cage.h> 50 #include <vm/vm_dep.h> 51 #include <sys/error.h> 52 #include <sys/machsystm.h> 53 #include <vm/seg_kmem.h> 54 55 uint_t page_colors = 0; 56 uint_t page_colors_mask = 0; 57 uint_t page_coloring_shift = 0; 58 int consistent_coloring; 59 60 uint_t mmu_page_sizes = MMU_PAGE_SIZES; 61 uint_t max_mmu_page_sizes = MMU_PAGE_SIZES; 62 uint_t mmu_hashcnt = MAX_HASHCNT; 63 uint_t max_mmu_hashcnt = MAX_HASHCNT; 64 size_t mmu_ism_pagesize = DEFAULT_ISM_PAGESIZE; 65 66 /* 67 * A bitmask of the page sizes supported by hardware based upon szc. 68 * The base pagesize (p_szc == 0) must always be supported by the hardware. 69 */ 70 int mmu_exported_pagesize_mask; 71 uint_t mmu_exported_page_sizes; 72 73 uint_t szc_2_userszc[MMU_PAGE_SIZES]; 74 uint_t userszc_2_szc[MMU_PAGE_SIZES]; 75 76 extern uint_t vac_colors_mask; 77 extern int vac_shift; 78 79 hw_pagesize_t hw_page_array[] = { 80 {MMU_PAGESIZE, MMU_PAGESHIFT, MMU_PAGESIZE >> MMU_PAGESHIFT}, 81 {MMU_PAGESIZE64K, MMU_PAGESHIFT64K, MMU_PAGESIZE64K >> MMU_PAGESHIFT}, 82 {MMU_PAGESIZE512K, MMU_PAGESHIFT512K, 83 MMU_PAGESIZE512K >> MMU_PAGESHIFT}, 84 {MMU_PAGESIZE4M, MMU_PAGESHIFT4M, MMU_PAGESIZE4M >> MMU_PAGESHIFT}, 85 {MMU_PAGESIZE32M, MMU_PAGESHIFT32M, MMU_PAGESIZE32M >> MMU_PAGESHIFT}, 86 {MMU_PAGESIZE256M, MMU_PAGESHIFT256M, 87 MMU_PAGESIZE256M >> MMU_PAGESHIFT}, 88 {0, 0, 0} 89 }; 90 91 /* 92 * Enable usage of 64k/4M pages for text and 64k pages for initdata for 93 * all sun4v platforms. These variables can be overwritten by the platmod 94 * or the CPU module. User can also change the setting via /etc/system. 95 */ 96 97 int use_text_pgsz64k = 1; 98 int use_text_pgsz4m = 1; 99 int use_initdata_pgsz64k = 1; 100 101 /* 102 * disable_text_largepages and disable_initdata_largepages bitmaks reflect 103 * both unconfigured and undesirable page sizes. Current implementation 104 * supports 64K and 4M page sizes for text and only 64K for data. Rest of 105 * the page sizes are not currently supported, hence disabled below. In 106 * future, when support is added for any other page size, it should be 107 * reflected below. 108 * 109 * Note that these bitmask can be set in platform or CPU specific code to 110 * disable page sizes that should not be used. These variables normally 111 * shouldn't be changed via /etc/system. 112 * 113 * These bitmasks are also updated within hat_init to reflect unsupported 114 * page sizes on a sun4v processor per mmu_exported_pagesize_mask global 115 * variable. 116 */ 117 118 int disable_text_largepages = 119 (1 << TTE512K) | (1 << TTE32M) | (1 << TTE256M) | (1 << TTE2G) | 120 (1 << TTE16G); 121 int disable_initdata_largepages = 122 (1 << TTE512K) | (1 << TTE4M) | (1 << TTE32M) | (1 << TTE256M) | 123 (1 << TTE2G) | (1 << TTE16G); 124 125 /* 126 * Minimum segment size tunables before 64K or 4M large pages 127 * should be used to map it. 128 */ 129 size_t text_pgsz64k_minsize = MMU_PAGESIZE64K; 130 size_t text_pgsz4m_minsize = MMU_PAGESIZE4M; 131 size_t initdata_pgsz64k_minsize = MMU_PAGESIZE64K; 132 133 size_t max_shm_lpsize = MMU_PAGESIZE4M; 134 135 /* Auto large page tunables. */ 136 int auto_lpg_tlb_threshold = 32; 137 int auto_lpg_minszc = TTE64K; 138 int auto_lpg_maxszc = TTE64K; 139 size_t auto_lpg_heap_default = MMU_PAGESIZE64K; 140 size_t auto_lpg_stack_default = MMU_PAGESIZE64K; 141 size_t auto_lpg_va_default = MMU_PAGESIZE64K; 142 size_t auto_lpg_remap_threshold = 0; /* always remap */ 143 /* 144 * Number of pages in 1 GB. Don't enable automatic large pages if we have 145 * fewer than this many pages. 146 */ 147 pgcnt_t auto_lpg_min_physmem = 1 << (30 - MMU_PAGESHIFT); 148 149 /* 150 * map_addr_proc() is the routine called when the system is to 151 * choose an address for the user. We will pick an address 152 * range which is just below the current stack limit. The 153 * algorithm used for cache consistency on machines with virtual 154 * address caches is such that offset 0 in the vnode is always 155 * on a shm_alignment'ed aligned address. Unfortunately, this 156 * means that vnodes which are demand paged will not be mapped 157 * cache consistently with the executable images. When the 158 * cache alignment for a given object is inconsistent, the 159 * lower level code must manage the translations so that this 160 * is not seen here (at the cost of efficiency, of course). 161 * 162 * addrp is a value/result parameter. 163 * On input it is a hint from the user to be used in a completely 164 * machine dependent fashion. For MAP_ALIGN, addrp contains the 165 * minimal alignment. 166 * 167 * On output it is NULL if no address can be found in the current 168 * processes address space or else an address that is currently 169 * not mapped for len bytes with a page of red zone on either side. 170 * If vacalign is true, then the selected address will obey the alignment 171 * constraints of a vac machine based on the given off value. 172 */ 173 /*ARGSUSED3*/ 174 void 175 map_addr_proc(caddr_t *addrp, size_t len, offset_t off, int vacalign, 176 caddr_t userlimit, struct proc *p, uint_t flags) 177 { 178 struct as *as = p->p_as; 179 caddr_t addr; 180 caddr_t base; 181 size_t slen; 182 uintptr_t align_amount; 183 int allow_largepage_alignment = 1; 184 185 base = p->p_brkbase; 186 if (userlimit < as->a_userlimit) { 187 /* 188 * This happens when a program wants to map something in 189 * a range that's accessible to a program in a smaller 190 * address space. For example, a 64-bit program might 191 * be calling mmap32(2) to guarantee that the returned 192 * address is below 4Gbytes. 193 */ 194 ASSERT(userlimit > base); 195 slen = userlimit - base; 196 } else { 197 slen = p->p_usrstack - base - (((size_t)rctl_enforced_value( 198 rctlproc_legacy[RLIMIT_STACK], p->p_rctls, p) + PAGEOFFSET) 199 & PAGEMASK); 200 } 201 len = (len + PAGEOFFSET) & PAGEMASK; 202 203 /* 204 * Redzone for each side of the request. This is done to leave 205 * one page unmapped between segments. This is not required, but 206 * it's useful for the user because if their program strays across 207 * a segment boundary, it will catch a fault immediately making 208 * debugging a little easier. 209 */ 210 len += (2 * PAGESIZE); 211 212 /* 213 * If the request is larger than the size of a particular 214 * mmu level, then we use that level to map the request. 215 * But this requires that both the virtual and the physical 216 * addresses be aligned with respect to that level, so we 217 * do the virtual bit of nastiness here. 218 * 219 * For 32-bit processes, only those which have specified 220 * MAP_ALIGN or an addr will be aligned on a page size > 4MB. Otherwise 221 * we can potentially waste up to 256MB of the 4G process address 222 * space just for alignment. 223 * 224 * XXXQ Should iterate trough hw_page_array here to catch 225 * all supported pagesizes 226 */ 227 if (p->p_model == DATAMODEL_ILP32 && ((flags & MAP_ALIGN) == 0 || 228 ((uintptr_t)*addrp) != 0)) { 229 allow_largepage_alignment = 0; 230 } 231 if ((mmu_page_sizes == max_mmu_page_sizes) && 232 allow_largepage_alignment && 233 (len >= MMU_PAGESIZE256M)) { /* 256MB mappings */ 234 align_amount = MMU_PAGESIZE256M; 235 } else if ((mmu_page_sizes == max_mmu_page_sizes) && 236 allow_largepage_alignment && 237 (len >= MMU_PAGESIZE32M)) { /* 32MB mappings */ 238 align_amount = MMU_PAGESIZE32M; 239 } else if (len >= MMU_PAGESIZE4M) { /* 4MB mappings */ 240 align_amount = MMU_PAGESIZE4M; 241 } else if (len >= MMU_PAGESIZE512K) { /* 512KB mappings */ 242 align_amount = MMU_PAGESIZE512K; 243 } else if (len >= MMU_PAGESIZE64K) { /* 64KB mappings */ 244 align_amount = MMU_PAGESIZE64K; 245 } else { 246 /* 247 * Align virtual addresses on a 64K boundary to ensure 248 * that ELF shared libraries are mapped with the appropriate 249 * alignment constraints by the run-time linker. 250 */ 251 align_amount = ELF_SPARC_MAXPGSZ; 252 if ((flags & MAP_ALIGN) && ((uintptr_t)*addrp != 0) && 253 ((uintptr_t)*addrp < align_amount)) 254 align_amount = (uintptr_t)*addrp; 255 } 256 257 /* 258 * 64-bit processes require 1024K alignment of ELF shared libraries. 259 */ 260 if (p->p_model == DATAMODEL_LP64) 261 align_amount = MAX(align_amount, ELF_SPARCV9_MAXPGSZ); 262 #ifdef VAC 263 if (vac && vacalign && (align_amount < shm_alignment)) 264 align_amount = shm_alignment; 265 #endif 266 267 if ((flags & MAP_ALIGN) && ((uintptr_t)*addrp > align_amount)) { 268 align_amount = (uintptr_t)*addrp; 269 } 270 len += align_amount; 271 272 /* 273 * Look for a large enough hole starting below the stack limit. 274 * After finding it, use the upper part. Addition of PAGESIZE is 275 * for the redzone as described above. 276 */ 277 as_purge(as); 278 if (as_gap(as, len, &base, &slen, AH_HI, NULL) == 0) { 279 caddr_t as_addr; 280 281 addr = base + slen - len + PAGESIZE; 282 as_addr = addr; 283 /* 284 * Round address DOWN to the alignment amount, 285 * add the offset, and if this address is less 286 * than the original address, add alignment amount. 287 */ 288 addr = (caddr_t)((uintptr_t)addr & (~(align_amount - 1l))); 289 addr += (long)(off & (align_amount - 1l)); 290 if (addr < as_addr) { 291 addr += align_amount; 292 } 293 294 ASSERT(addr <= (as_addr + align_amount)); 295 ASSERT(((uintptr_t)addr & (align_amount - 1l)) == 296 ((uintptr_t)(off & (align_amount - 1l)))); 297 *addrp = addr; 298 299 } else { 300 *addrp = NULL; /* no more virtual space */ 301 } 302 } 303 304 /* 305 * Platform-dependent page scrub call. 306 * We call hypervisor to scrub the page. 307 */ 308 void 309 pagescrub(page_t *pp, uint_t off, uint_t len) 310 { 311 uint64_t pa, length; 312 313 pa = (uint64_t)(pp->p_pagenum << MMU_PAGESHIFT + off); 314 length = (uint64_t)len; 315 316 (void) mem_scrub(pa, length); 317 } 318 319 void 320 sync_data_memory(caddr_t va, size_t len) 321 { 322 /* Call memory sync function */ 323 mem_sync(va, len); 324 } 325 326 size_t 327 mmu_get_kernel_lpsize(size_t lpsize) 328 { 329 extern int mmu_exported_pagesize_mask; 330 uint_t tte; 331 332 if (lpsize == 0) { 333 /* no setting for segkmem_lpsize in /etc/system: use default */ 334 if (mmu_exported_pagesize_mask & (1 << TTE256M)) { 335 lpsize = MMU_PAGESIZE256M; 336 } else if (mmu_exported_pagesize_mask & (1 << TTE4M)) { 337 lpsize = MMU_PAGESIZE4M; 338 } else if (mmu_exported_pagesize_mask & (1 << TTE64K)) { 339 lpsize = MMU_PAGESIZE64K; 340 } else { 341 lpsize = MMU_PAGESIZE; 342 } 343 344 return (lpsize); 345 } 346 347 for (tte = TTE8K; tte <= TTE256M; tte++) { 348 349 if ((mmu_exported_pagesize_mask & (1 << tte)) == 0) 350 continue; 351 352 if (lpsize == TTEBYTES(tte)) 353 return (lpsize); 354 } 355 356 lpsize = TTEBYTES(TTE8K); 357 return (lpsize); 358 } 359 360 void 361 mmu_init_kcontext() 362 { 363 } 364 365 /*ARGSUSED*/ 366 void 367 mmu_init_kernel_pgsz(struct hat *hat) 368 { 369 } 370 371 #define QUANTUM_SIZE 64 372 373 static vmem_t *contig_mem_slab_arena; 374 static vmem_t *contig_mem_arena; 375 376 uint_t contig_mem_slab_size = MMU_PAGESIZE4M; 377 378 static void * 379 contig_mem_span_alloc(vmem_t *vmp, size_t size, int vmflag) 380 { 381 page_t *ppl; 382 page_t *rootpp; 383 caddr_t addr = NULL; 384 pgcnt_t npages = btopr(size); 385 page_t **ppa; 386 int pgflags; 387 int i = 0; 388 389 390 /* 391 * The import request should be at least 392 * contig_mem_slab_size because that is the 393 * slab arena's quantum. The size can be 394 * further restricted since contiguous 395 * allocations larger than contig_mem_slab_size 396 * are not supported here. 397 */ 398 ASSERT(size == contig_mem_slab_size); 399 400 if ((addr = vmem_xalloc(vmp, size, size, 0, 0, 401 NULL, NULL, vmflag)) == NULL) { 402 return (NULL); 403 } 404 405 /* The address should be slab-size aligned. */ 406 ASSERT(((uintptr_t)addr & (contig_mem_slab_size - 1)) == 0); 407 408 if (page_resv(npages, vmflag & VM_KMFLAGS) == 0) { 409 vmem_xfree(vmp, addr, size); 410 return (NULL); 411 } 412 413 pgflags = PG_EXCL; 414 if ((vmflag & VM_NOSLEEP) == 0) 415 pgflags |= PG_WAIT; 416 if (vmflag & VM_PANIC) 417 pgflags |= PG_PANIC; 418 if (vmflag & VM_PUSHPAGE) 419 pgflags |= PG_PUSHPAGE; 420 421 ppl = page_create_va_large(&kvp, (u_offset_t)(uintptr_t)addr, size, 422 pgflags, &kvseg, addr, NULL); 423 424 if (ppl == NULL) { 425 vmem_xfree(vmp, addr, size); 426 page_unresv(npages); 427 return (NULL); 428 } 429 430 rootpp = ppl; 431 ppa = kmem_zalloc(npages * sizeof (page_t *), KM_SLEEP); 432 while (ppl != NULL) { 433 page_t *pp = ppl; 434 ppa[i++] = pp; 435 page_sub(&ppl, pp); 436 ASSERT(page_iolock_assert(pp)); 437 page_io_unlock(pp); 438 } 439 440 /* 441 * Load the locked entry. It's OK to preload the entry into 442 * the TSB since we now support large mappings in the kernel TSB. 443 */ 444 hat_memload_array(kas.a_hat, (caddr_t)rootpp->p_offset, size, 445 ppa, (PROT_ALL & ~PROT_USER) | HAT_NOSYNC, HAT_LOAD_LOCK); 446 447 for (--i; i >= 0; --i) { 448 (void) page_pp_lock(ppa[i], 0, 1); 449 page_unlock(ppa[i]); 450 } 451 452 kmem_free(ppa, npages * sizeof (page_t *)); 453 return (addr); 454 } 455 456 void 457 contig_mem_span_free(vmem_t *vmp, void *inaddr, size_t size) 458 { 459 page_t *pp; 460 caddr_t addr = inaddr; 461 caddr_t eaddr; 462 pgcnt_t npages = btopr(size); 463 pgcnt_t pgs_left = npages; 464 page_t *rootpp = NULL; 465 466 ASSERT(((uintptr_t)addr & (contig_mem_slab_size - 1)) == 0); 467 468 hat_unload(kas.a_hat, addr, size, HAT_UNLOAD_UNLOCK); 469 470 for (eaddr = addr + size; addr < eaddr; addr += PAGESIZE) { 471 pp = page_lookup(&kvp, (u_offset_t)(uintptr_t)addr, SE_EXCL); 472 if (pp == NULL) 473 panic("contig_mem_span_free: page not found"); 474 475 ASSERT(PAGE_EXCL(pp)); 476 page_pp_unlock(pp, 0, 1); 477 478 if (rootpp == NULL) 479 rootpp = pp; 480 if (--pgs_left == 0) { 481 /* 482 * similar logic to segspt_free_pages, but we know we 483 * have one large page. 484 */ 485 page_destroy_pages(rootpp); 486 } 487 } 488 page_unresv(npages); 489 490 if (vmp != NULL) 491 vmem_xfree(vmp, inaddr, size); 492 } 493 494 static void * 495 contig_vmem_xalloc_aligned_wrapper(vmem_t *vmp, size_t size, int vmflag) 496 { 497 return (vmem_xalloc(vmp, size, size, 0, 0, NULL, NULL, vmflag)); 498 } 499 500 /* 501 * conting_mem_alloc_align allocates real contiguous memory with the specified 502 * alignment upto contig_mem_slab_size. The alignment must be a power of 2. 503 */ 504 void * 505 contig_mem_alloc_align(size_t size, size_t align) 506 { 507 ASSERT(align <= contig_mem_slab_size); 508 509 if ((align & (align - 1)) != 0) 510 return (NULL); 511 512 return (vmem_xalloc(contig_mem_arena, size, align, 0, 0, 513 NULL, NULL, VM_NOSLEEP)); 514 } 515 516 /* 517 * Allocates size aligned contiguous memory upto contig_mem_slab_size. 518 * Size must be a power of 2. 519 */ 520 void * 521 contig_mem_alloc(size_t size) 522 { 523 ASSERT((size & (size - 1)) == 0); 524 return (contig_mem_alloc_align(size, size)); 525 } 526 527 void 528 contig_mem_free(void *vaddr, size_t size) 529 { 530 vmem_xfree(contig_mem_arena, vaddr, size); 531 } 532 533 /* 534 * We create a set of stacked vmem arenas to enable us to 535 * allocate large >PAGESIZE chucks of contiguous Real Address space 536 * This is what the Dynamics TSB support does for TSBs. 537 * The contig_mem_arena import functions are exactly the same as the 538 * TSB kmem_default arena import functions. 539 */ 540 void 541 contig_mem_init(void) 542 { 543 544 contig_mem_slab_arena = vmem_create("contig_mem_slab_arena", NULL, 0, 545 contig_mem_slab_size, contig_vmem_xalloc_aligned_wrapper, 546 vmem_xfree, heap_arena, 0, VM_SLEEP); 547 548 contig_mem_arena = vmem_create("contig_mem_arena", NULL, 0, 549 QUANTUM_SIZE, contig_mem_span_alloc, contig_mem_span_free, 550 contig_mem_slab_arena, 0, VM_SLEEP | VM_BESTFIT); 551 552 } 553