17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 50400e0b7Sha137994 * Common Development and Distribution License (the "License"). 60400e0b7Sha137994 * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 22bb121940Sdp78419 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 237c478bd9Sstevel@tonic-gate * Use is subject to license terms. 247c478bd9Sstevel@tonic-gate */ 257c478bd9Sstevel@tonic-gate 267c478bd9Sstevel@tonic-gate /* Copyright (c) 1984, 1986, 1987, 1988, 1989 AT&T */ 277c478bd9Sstevel@tonic-gate /* All Rights Reserved */ 287c478bd9Sstevel@tonic-gate 297c478bd9Sstevel@tonic-gate /* 307c478bd9Sstevel@tonic-gate * Portions of this source code were derived from Berkeley 4.3 BSD 317c478bd9Sstevel@tonic-gate * under license from the Regents of the University of California. 327c478bd9Sstevel@tonic-gate */ 337c478bd9Sstevel@tonic-gate 347c478bd9Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 357c478bd9Sstevel@tonic-gate 367c478bd9Sstevel@tonic-gate /* 377c478bd9Sstevel@tonic-gate * UNIX machine dependent virtual memory support. 387c478bd9Sstevel@tonic-gate */ 397c478bd9Sstevel@tonic-gate 407c478bd9Sstevel@tonic-gate #include <sys/vm.h> 417c478bd9Sstevel@tonic-gate #include <sys/exec.h> 427c478bd9Sstevel@tonic-gate #include <sys/cmn_err.h> 437c478bd9Sstevel@tonic-gate #include <sys/cpu_module.h> 447c478bd9Sstevel@tonic-gate #include <sys/cpu.h> 457c478bd9Sstevel@tonic-gate #include <sys/elf_SPARC.h> 467c478bd9Sstevel@tonic-gate #include <sys/archsystm.h> 477c478bd9Sstevel@tonic-gate #include <vm/hat_sfmmu.h> 487c478bd9Sstevel@tonic-gate #include <sys/memnode.h> 497c478bd9Sstevel@tonic-gate #include <sys/mem_cage.h> 507c478bd9Sstevel@tonic-gate #include <vm/vm_dep.h> 517c478bd9Sstevel@tonic-gate #include <sys/error.h> 527c478bd9Sstevel@tonic-gate #include <sys/machsystm.h> 537c478bd9Sstevel@tonic-gate #include <vm/seg_kmem.h> 54102033aaSdp78419 #include <sys/stack.h> 55102033aaSdp78419 #include <sys/atomic.h> 567c478bd9Sstevel@tonic-gate 577c478bd9Sstevel@tonic-gate uint_t page_colors = 0; 587c478bd9Sstevel@tonic-gate uint_t page_colors_mask = 0; 597c478bd9Sstevel@tonic-gate uint_t page_coloring_shift = 0; 607c478bd9Sstevel@tonic-gate int consistent_coloring; 617c478bd9Sstevel@tonic-gate 627c478bd9Sstevel@tonic-gate uint_t mmu_page_sizes = MMU_PAGE_SIZES; 637c478bd9Sstevel@tonic-gate uint_t max_mmu_page_sizes = MMU_PAGE_SIZES; 647c478bd9Sstevel@tonic-gate uint_t mmu_hashcnt = MAX_HASHCNT; 657c478bd9Sstevel@tonic-gate uint_t max_mmu_hashcnt = MAX_HASHCNT; 667c478bd9Sstevel@tonic-gate size_t mmu_ism_pagesize = DEFAULT_ISM_PAGESIZE; 677c478bd9Sstevel@tonic-gate 687c478bd9Sstevel@tonic-gate /* 697c478bd9Sstevel@tonic-gate * A bitmask of the page sizes supported by hardware based upon szc. 707c478bd9Sstevel@tonic-gate * The base pagesize (p_szc == 0) must always be supported by the hardware. 717c478bd9Sstevel@tonic-gate */ 727c478bd9Sstevel@tonic-gate int mmu_exported_pagesize_mask; 737c478bd9Sstevel@tonic-gate uint_t mmu_exported_page_sizes; 747c478bd9Sstevel@tonic-gate 757c478bd9Sstevel@tonic-gate uint_t szc_2_userszc[MMU_PAGE_SIZES]; 767c478bd9Sstevel@tonic-gate uint_t userszc_2_szc[MMU_PAGE_SIZES]; 777c478bd9Sstevel@tonic-gate 787c478bd9Sstevel@tonic-gate extern uint_t vac_colors_mask; 797c478bd9Sstevel@tonic-gate extern int vac_shift; 807c478bd9Sstevel@tonic-gate 817c478bd9Sstevel@tonic-gate hw_pagesize_t hw_page_array[] = { 825d07b933Sdp78419 {MMU_PAGESIZE, MMU_PAGESHIFT, 0, MMU_PAGESIZE >> MMU_PAGESHIFT}, 835d07b933Sdp78419 {MMU_PAGESIZE64K, MMU_PAGESHIFT64K, 0, 845d07b933Sdp78419 MMU_PAGESIZE64K >> MMU_PAGESHIFT}, 855d07b933Sdp78419 {MMU_PAGESIZE512K, MMU_PAGESHIFT512K, 0, 867c478bd9Sstevel@tonic-gate MMU_PAGESIZE512K >> MMU_PAGESHIFT}, 875d07b933Sdp78419 {MMU_PAGESIZE4M, MMU_PAGESHIFT4M, 0, MMU_PAGESIZE4M >> MMU_PAGESHIFT}, 885d07b933Sdp78419 {MMU_PAGESIZE32M, MMU_PAGESHIFT32M, 0, 895d07b933Sdp78419 MMU_PAGESIZE32M >> MMU_PAGESHIFT}, 905d07b933Sdp78419 {MMU_PAGESIZE256M, MMU_PAGESHIFT256M, 0, 917c478bd9Sstevel@tonic-gate MMU_PAGESIZE256M >> MMU_PAGESHIFT}, 925d07b933Sdp78419 {0, 0, 0, 0} 937c478bd9Sstevel@tonic-gate }; 947c478bd9Sstevel@tonic-gate 957c478bd9Sstevel@tonic-gate /* 96bb121940Sdp78419 * Maximum page size used to map 64-bit memory segment kmem64_base..kmem64_end 97bb121940Sdp78419 */ 98bb121940Sdp78419 int max_bootlp_tteszc = TTE256M; 99bb121940Sdp78419 100bb121940Sdp78419 /* 101ec25b48fSsusans * Maximum and default segment size tunables for user heap, stack, private 102ec25b48fSsusans * and shared anonymous memory, and user text and initialized data. 1037c478bd9Sstevel@tonic-gate */ 104ec25b48fSsusans size_t max_uheap_lpsize = MMU_PAGESIZE64K; 105ec25b48fSsusans size_t default_uheap_lpsize = MMU_PAGESIZE64K; 106ec25b48fSsusans size_t max_ustack_lpsize = MMU_PAGESIZE64K; 107ec25b48fSsusans size_t default_ustack_lpsize = MMU_PAGESIZE64K; 108ec25b48fSsusans size_t max_privmap_lpsize = MMU_PAGESIZE64K; 109ec25b48fSsusans size_t max_uidata_lpsize = MMU_PAGESIZE64K; 110ec25b48fSsusans size_t max_utext_lpsize = MMU_PAGESIZE4M; 11107b65a64Saguzovsk size_t max_shm_lpsize = MMU_PAGESIZE4M; 11207b65a64Saguzovsk 1137c478bd9Sstevel@tonic-gate /* 114*aaa10e67Sha137994 * Contiguous memory allocator data structures and variables. 115*aaa10e67Sha137994 * 116*aaa10e67Sha137994 * The sun4v kernel must provide a means to allocate physically 117*aaa10e67Sha137994 * contiguous, non-relocatable memory. The contig_mem_arena 118*aaa10e67Sha137994 * and contig_mem_slab_arena exist for this purpose. Allocations 119*aaa10e67Sha137994 * that require physically contiguous non-relocatable memory should 120*aaa10e67Sha137994 * be made using contig_mem_alloc() or contig_mem_alloc_align() 121*aaa10e67Sha137994 * which return memory from contig_mem_arena or contig_mem_reloc_arena. 122*aaa10e67Sha137994 * These arenas import memory from the contig_mem_slab_arena one 123*aaa10e67Sha137994 * contiguous chunk at a time. 124*aaa10e67Sha137994 * 125*aaa10e67Sha137994 * When importing slabs, an attempt is made to allocate a large page 126*aaa10e67Sha137994 * to use as backing. As a result of the non-relocatable requirement, 127*aaa10e67Sha137994 * slabs are allocated from the kernel cage freelists. If the cage does 128*aaa10e67Sha137994 * not contain any free contiguous chunks large enough to satisfy the 129*aaa10e67Sha137994 * slab allocation, the slab size will be downsized and the operation 130*aaa10e67Sha137994 * retried. Large slab sizes are tried first to minimize cage 131*aaa10e67Sha137994 * fragmentation. If the slab allocation is unsuccessful still, the slab 132*aaa10e67Sha137994 * is allocated from outside the kernel cage. This is undesirable because, 133*aaa10e67Sha137994 * until slabs are freed, it results in non-relocatable chunks scattered 134*aaa10e67Sha137994 * throughout physical memory. 135*aaa10e67Sha137994 * 136*aaa10e67Sha137994 * Allocations from the contig_mem_arena are backed by slabs from the 137*aaa10e67Sha137994 * cage. Allocations from the contig_mem_reloc_arena are backed by 138*aaa10e67Sha137994 * slabs allocated outside the cage. Slabs are left share locked while 139*aaa10e67Sha137994 * in use to prevent non-cage slabs from being relocated. 140*aaa10e67Sha137994 * 141*aaa10e67Sha137994 * Since there is no guarantee that large pages will be available in 142*aaa10e67Sha137994 * the kernel cage, contiguous memory is reserved and added to the 143*aaa10e67Sha137994 * contig_mem_arena at boot time, making it available for later 144*aaa10e67Sha137994 * contiguous memory allocations. This reserve will be used to satisfy 145*aaa10e67Sha137994 * contig_mem allocations first and it is only when the reserve is 146*aaa10e67Sha137994 * completely allocated that new slabs will need to be imported. 147*aaa10e67Sha137994 */ 148*aaa10e67Sha137994 static vmem_t *contig_mem_slab_arena; 149*aaa10e67Sha137994 static vmem_t *contig_mem_arena; 150*aaa10e67Sha137994 static vmem_t *contig_mem_reloc_arena; 151*aaa10e67Sha137994 static kmutex_t contig_mem_lock; 152*aaa10e67Sha137994 #define CONTIG_MEM_ARENA_QUANTUM 64 153*aaa10e67Sha137994 #define CONTIG_MEM_SLAB_ARENA_QUANTUM MMU_PAGESIZE64K 154*aaa10e67Sha137994 155*aaa10e67Sha137994 /* contig_mem_arena import slab sizes, in decreasing size order */ 156*aaa10e67Sha137994 static size_t contig_mem_import_sizes[] = { 157*aaa10e67Sha137994 MMU_PAGESIZE4M, 158*aaa10e67Sha137994 MMU_PAGESIZE512K, 159*aaa10e67Sha137994 MMU_PAGESIZE64K 160*aaa10e67Sha137994 }; 161*aaa10e67Sha137994 #define NUM_IMPORT_SIZES \ 162*aaa10e67Sha137994 (sizeof (contig_mem_import_sizes) / sizeof (size_t)) 163*aaa10e67Sha137994 static size_t contig_mem_import_size_max = MMU_PAGESIZE4M; 164*aaa10e67Sha137994 size_t contig_mem_slab_size = MMU_PAGESIZE4M; 165*aaa10e67Sha137994 166*aaa10e67Sha137994 /* Boot-time allocated buffer to pre-populate the contig_mem_arena */ 167*aaa10e67Sha137994 static size_t prealloc_size; 168*aaa10e67Sha137994 static void *prealloc_buf; 169*aaa10e67Sha137994 170*aaa10e67Sha137994 /* 1717c478bd9Sstevel@tonic-gate * map_addr_proc() is the routine called when the system is to 1727c478bd9Sstevel@tonic-gate * choose an address for the user. We will pick an address 1737c478bd9Sstevel@tonic-gate * range which is just below the current stack limit. The 1747c478bd9Sstevel@tonic-gate * algorithm used for cache consistency on machines with virtual 1757c478bd9Sstevel@tonic-gate * address caches is such that offset 0 in the vnode is always 1767c478bd9Sstevel@tonic-gate * on a shm_alignment'ed aligned address. Unfortunately, this 1777c478bd9Sstevel@tonic-gate * means that vnodes which are demand paged will not be mapped 1787c478bd9Sstevel@tonic-gate * cache consistently with the executable images. When the 1797c478bd9Sstevel@tonic-gate * cache alignment for a given object is inconsistent, the 1807c478bd9Sstevel@tonic-gate * lower level code must manage the translations so that this 1817c478bd9Sstevel@tonic-gate * is not seen here (at the cost of efficiency, of course). 1827c478bd9Sstevel@tonic-gate * 1837c478bd9Sstevel@tonic-gate * addrp is a value/result parameter. 1847c478bd9Sstevel@tonic-gate * On input it is a hint from the user to be used in a completely 1857c478bd9Sstevel@tonic-gate * machine dependent fashion. For MAP_ALIGN, addrp contains the 1867c478bd9Sstevel@tonic-gate * minimal alignment. 1877c478bd9Sstevel@tonic-gate * 1887c478bd9Sstevel@tonic-gate * On output it is NULL if no address can be found in the current 1897c478bd9Sstevel@tonic-gate * processes address space or else an address that is currently 1907c478bd9Sstevel@tonic-gate * not mapped for len bytes with a page of red zone on either side. 1917c478bd9Sstevel@tonic-gate * If vacalign is true, then the selected address will obey the alignment 1927c478bd9Sstevel@tonic-gate * constraints of a vac machine based on the given off value. 1937c478bd9Sstevel@tonic-gate */ 1947c478bd9Sstevel@tonic-gate /*ARGSUSED3*/ 1957c478bd9Sstevel@tonic-gate void 1967c478bd9Sstevel@tonic-gate map_addr_proc(caddr_t *addrp, size_t len, offset_t off, int vacalign, 1977c478bd9Sstevel@tonic-gate caddr_t userlimit, struct proc *p, uint_t flags) 1987c478bd9Sstevel@tonic-gate { 1997c478bd9Sstevel@tonic-gate struct as *as = p->p_as; 2007c478bd9Sstevel@tonic-gate caddr_t addr; 2017c478bd9Sstevel@tonic-gate caddr_t base; 2027c478bd9Sstevel@tonic-gate size_t slen; 2037c478bd9Sstevel@tonic-gate uintptr_t align_amount; 2047c478bd9Sstevel@tonic-gate int allow_largepage_alignment = 1; 2057c478bd9Sstevel@tonic-gate 2067c478bd9Sstevel@tonic-gate base = p->p_brkbase; 2077c478bd9Sstevel@tonic-gate if (userlimit < as->a_userlimit) { 2087c478bd9Sstevel@tonic-gate /* 2097c478bd9Sstevel@tonic-gate * This happens when a program wants to map something in 2107c478bd9Sstevel@tonic-gate * a range that's accessible to a program in a smaller 2117c478bd9Sstevel@tonic-gate * address space. For example, a 64-bit program might 2127c478bd9Sstevel@tonic-gate * be calling mmap32(2) to guarantee that the returned 2137c478bd9Sstevel@tonic-gate * address is below 4Gbytes. 2147c478bd9Sstevel@tonic-gate */ 2157c478bd9Sstevel@tonic-gate ASSERT(userlimit > base); 2167c478bd9Sstevel@tonic-gate slen = userlimit - base; 2177c478bd9Sstevel@tonic-gate } else { 2187c478bd9Sstevel@tonic-gate slen = p->p_usrstack - base - (((size_t)rctl_enforced_value( 2197c478bd9Sstevel@tonic-gate rctlproc_legacy[RLIMIT_STACK], p->p_rctls, p) + PAGEOFFSET) 2207c478bd9Sstevel@tonic-gate & PAGEMASK); 2217c478bd9Sstevel@tonic-gate } 2227c478bd9Sstevel@tonic-gate len = (len + PAGEOFFSET) & PAGEMASK; 2237c478bd9Sstevel@tonic-gate 2247c478bd9Sstevel@tonic-gate /* 2257c478bd9Sstevel@tonic-gate * Redzone for each side of the request. This is done to leave 2267c478bd9Sstevel@tonic-gate * one page unmapped between segments. This is not required, but 2277c478bd9Sstevel@tonic-gate * it's useful for the user because if their program strays across 2287c478bd9Sstevel@tonic-gate * a segment boundary, it will catch a fault immediately making 2297c478bd9Sstevel@tonic-gate * debugging a little easier. 2307c478bd9Sstevel@tonic-gate */ 2317c478bd9Sstevel@tonic-gate len += (2 * PAGESIZE); 2327c478bd9Sstevel@tonic-gate 2337c478bd9Sstevel@tonic-gate /* 2347c478bd9Sstevel@tonic-gate * If the request is larger than the size of a particular 2357c478bd9Sstevel@tonic-gate * mmu level, then we use that level to map the request. 2367c478bd9Sstevel@tonic-gate * But this requires that both the virtual and the physical 2377c478bd9Sstevel@tonic-gate * addresses be aligned with respect to that level, so we 2387c478bd9Sstevel@tonic-gate * do the virtual bit of nastiness here. 2397c478bd9Sstevel@tonic-gate * 2407c478bd9Sstevel@tonic-gate * For 32-bit processes, only those which have specified 2417c478bd9Sstevel@tonic-gate * MAP_ALIGN or an addr will be aligned on a page size > 4MB. Otherwise 2427c478bd9Sstevel@tonic-gate * we can potentially waste up to 256MB of the 4G process address 2437c478bd9Sstevel@tonic-gate * space just for alignment. 2447c478bd9Sstevel@tonic-gate * 2457c478bd9Sstevel@tonic-gate * XXXQ Should iterate trough hw_page_array here to catch 2467c478bd9Sstevel@tonic-gate * all supported pagesizes 2477c478bd9Sstevel@tonic-gate */ 2487c478bd9Sstevel@tonic-gate if (p->p_model == DATAMODEL_ILP32 && ((flags & MAP_ALIGN) == 0 || 2497c478bd9Sstevel@tonic-gate ((uintptr_t)*addrp) != 0)) { 2507c478bd9Sstevel@tonic-gate allow_largepage_alignment = 0; 2517c478bd9Sstevel@tonic-gate } 2527c478bd9Sstevel@tonic-gate if ((mmu_page_sizes == max_mmu_page_sizes) && 2537c478bd9Sstevel@tonic-gate allow_largepage_alignment && 2547c478bd9Sstevel@tonic-gate (len >= MMU_PAGESIZE256M)) { /* 256MB mappings */ 2557c478bd9Sstevel@tonic-gate align_amount = MMU_PAGESIZE256M; 2567c478bd9Sstevel@tonic-gate } else if ((mmu_page_sizes == max_mmu_page_sizes) && 2577c478bd9Sstevel@tonic-gate allow_largepage_alignment && 2587c478bd9Sstevel@tonic-gate (len >= MMU_PAGESIZE32M)) { /* 32MB mappings */ 2597c478bd9Sstevel@tonic-gate align_amount = MMU_PAGESIZE32M; 2607c478bd9Sstevel@tonic-gate } else if (len >= MMU_PAGESIZE4M) { /* 4MB mappings */ 2617c478bd9Sstevel@tonic-gate align_amount = MMU_PAGESIZE4M; 2627c478bd9Sstevel@tonic-gate } else if (len >= MMU_PAGESIZE512K) { /* 512KB mappings */ 2637c478bd9Sstevel@tonic-gate align_amount = MMU_PAGESIZE512K; 2647c478bd9Sstevel@tonic-gate } else if (len >= MMU_PAGESIZE64K) { /* 64KB mappings */ 2657c478bd9Sstevel@tonic-gate align_amount = MMU_PAGESIZE64K; 2667c478bd9Sstevel@tonic-gate } else { 2677c478bd9Sstevel@tonic-gate /* 2687c478bd9Sstevel@tonic-gate * Align virtual addresses on a 64K boundary to ensure 2697c478bd9Sstevel@tonic-gate * that ELF shared libraries are mapped with the appropriate 2707c478bd9Sstevel@tonic-gate * alignment constraints by the run-time linker. 2717c478bd9Sstevel@tonic-gate */ 2727c478bd9Sstevel@tonic-gate align_amount = ELF_SPARC_MAXPGSZ; 2737c478bd9Sstevel@tonic-gate if ((flags & MAP_ALIGN) && ((uintptr_t)*addrp != 0) && 2747c478bd9Sstevel@tonic-gate ((uintptr_t)*addrp < align_amount)) 2757c478bd9Sstevel@tonic-gate align_amount = (uintptr_t)*addrp; 2767c478bd9Sstevel@tonic-gate } 2777c478bd9Sstevel@tonic-gate 2787c478bd9Sstevel@tonic-gate /* 2797c478bd9Sstevel@tonic-gate * 64-bit processes require 1024K alignment of ELF shared libraries. 2807c478bd9Sstevel@tonic-gate */ 2817c478bd9Sstevel@tonic-gate if (p->p_model == DATAMODEL_LP64) 2827c478bd9Sstevel@tonic-gate align_amount = MAX(align_amount, ELF_SPARCV9_MAXPGSZ); 2837c478bd9Sstevel@tonic-gate #ifdef VAC 2847c478bd9Sstevel@tonic-gate if (vac && vacalign && (align_amount < shm_alignment)) 2857c478bd9Sstevel@tonic-gate align_amount = shm_alignment; 2867c478bd9Sstevel@tonic-gate #endif 2877c478bd9Sstevel@tonic-gate 2887c478bd9Sstevel@tonic-gate if ((flags & MAP_ALIGN) && ((uintptr_t)*addrp > align_amount)) { 2897c478bd9Sstevel@tonic-gate align_amount = (uintptr_t)*addrp; 2907c478bd9Sstevel@tonic-gate } 2917c478bd9Sstevel@tonic-gate len += align_amount; 2927c478bd9Sstevel@tonic-gate 2937c478bd9Sstevel@tonic-gate /* 2947c478bd9Sstevel@tonic-gate * Look for a large enough hole starting below the stack limit. 2957c478bd9Sstevel@tonic-gate * After finding it, use the upper part. Addition of PAGESIZE is 2967c478bd9Sstevel@tonic-gate * for the redzone as described above. 2977c478bd9Sstevel@tonic-gate */ 2987c478bd9Sstevel@tonic-gate as_purge(as); 2997c478bd9Sstevel@tonic-gate if (as_gap(as, len, &base, &slen, AH_HI, NULL) == 0) { 3007c478bd9Sstevel@tonic-gate caddr_t as_addr; 3017c478bd9Sstevel@tonic-gate 3027c478bd9Sstevel@tonic-gate addr = base + slen - len + PAGESIZE; 3037c478bd9Sstevel@tonic-gate as_addr = addr; 3047c478bd9Sstevel@tonic-gate /* 3057c478bd9Sstevel@tonic-gate * Round address DOWN to the alignment amount, 3067c478bd9Sstevel@tonic-gate * add the offset, and if this address is less 3077c478bd9Sstevel@tonic-gate * than the original address, add alignment amount. 3087c478bd9Sstevel@tonic-gate */ 3097c478bd9Sstevel@tonic-gate addr = (caddr_t)((uintptr_t)addr & (~(align_amount - 1l))); 3107c478bd9Sstevel@tonic-gate addr += (long)(off & (align_amount - 1l)); 3117c478bd9Sstevel@tonic-gate if (addr < as_addr) { 3127c478bd9Sstevel@tonic-gate addr += align_amount; 3137c478bd9Sstevel@tonic-gate } 3147c478bd9Sstevel@tonic-gate 3157c478bd9Sstevel@tonic-gate ASSERT(addr <= (as_addr + align_amount)); 3167c478bd9Sstevel@tonic-gate ASSERT(((uintptr_t)addr & (align_amount - 1l)) == 3177c478bd9Sstevel@tonic-gate ((uintptr_t)(off & (align_amount - 1l)))); 3187c478bd9Sstevel@tonic-gate *addrp = addr; 3197c478bd9Sstevel@tonic-gate 3207c478bd9Sstevel@tonic-gate } else { 3217c478bd9Sstevel@tonic-gate *addrp = NULL; /* no more virtual space */ 3227c478bd9Sstevel@tonic-gate } 3237c478bd9Sstevel@tonic-gate } 3247c478bd9Sstevel@tonic-gate 3257c478bd9Sstevel@tonic-gate /* 3267c478bd9Sstevel@tonic-gate * Platform-dependent page scrub call. 3277c478bd9Sstevel@tonic-gate * We call hypervisor to scrub the page. 3287c478bd9Sstevel@tonic-gate */ 3297c478bd9Sstevel@tonic-gate void 3307c478bd9Sstevel@tonic-gate pagescrub(page_t *pp, uint_t off, uint_t len) 3317c478bd9Sstevel@tonic-gate { 3327c478bd9Sstevel@tonic-gate uint64_t pa, length; 3337c478bd9Sstevel@tonic-gate 3347c478bd9Sstevel@tonic-gate pa = (uint64_t)(pp->p_pagenum << MMU_PAGESHIFT + off); 3357c478bd9Sstevel@tonic-gate length = (uint64_t)len; 3367c478bd9Sstevel@tonic-gate 3377c478bd9Sstevel@tonic-gate (void) mem_scrub(pa, length); 3387c478bd9Sstevel@tonic-gate } 3397c478bd9Sstevel@tonic-gate 3407c478bd9Sstevel@tonic-gate void 3417c478bd9Sstevel@tonic-gate sync_data_memory(caddr_t va, size_t len) 3427c478bd9Sstevel@tonic-gate { 3437c478bd9Sstevel@tonic-gate /* Call memory sync function */ 3442ae0af4bSep32863 (void) mem_sync(va, len); 3457c478bd9Sstevel@tonic-gate } 3467c478bd9Sstevel@tonic-gate 3477c478bd9Sstevel@tonic-gate size_t 3487c478bd9Sstevel@tonic-gate mmu_get_kernel_lpsize(size_t lpsize) 3497c478bd9Sstevel@tonic-gate { 3507c478bd9Sstevel@tonic-gate extern int mmu_exported_pagesize_mask; 3517c478bd9Sstevel@tonic-gate uint_t tte; 3527c478bd9Sstevel@tonic-gate 3537c478bd9Sstevel@tonic-gate if (lpsize == 0) { 3547c478bd9Sstevel@tonic-gate /* no setting for segkmem_lpsize in /etc/system: use default */ 3557c478bd9Sstevel@tonic-gate if (mmu_exported_pagesize_mask & (1 << TTE256M)) { 3567c478bd9Sstevel@tonic-gate lpsize = MMU_PAGESIZE256M; 3577c478bd9Sstevel@tonic-gate } else if (mmu_exported_pagesize_mask & (1 << TTE4M)) { 3587c478bd9Sstevel@tonic-gate lpsize = MMU_PAGESIZE4M; 3597c478bd9Sstevel@tonic-gate } else if (mmu_exported_pagesize_mask & (1 << TTE64K)) { 3607c478bd9Sstevel@tonic-gate lpsize = MMU_PAGESIZE64K; 3617c478bd9Sstevel@tonic-gate } else { 3627c478bd9Sstevel@tonic-gate lpsize = MMU_PAGESIZE; 3637c478bd9Sstevel@tonic-gate } 3647c478bd9Sstevel@tonic-gate 3657c478bd9Sstevel@tonic-gate return (lpsize); 3667c478bd9Sstevel@tonic-gate } 3677c478bd9Sstevel@tonic-gate 3687c478bd9Sstevel@tonic-gate for (tte = TTE8K; tte <= TTE256M; tte++) { 3697c478bd9Sstevel@tonic-gate 3707c478bd9Sstevel@tonic-gate if ((mmu_exported_pagesize_mask & (1 << tte)) == 0) 3717c478bd9Sstevel@tonic-gate continue; 3727c478bd9Sstevel@tonic-gate 3737c478bd9Sstevel@tonic-gate if (lpsize == TTEBYTES(tte)) 3747c478bd9Sstevel@tonic-gate return (lpsize); 3757c478bd9Sstevel@tonic-gate } 3767c478bd9Sstevel@tonic-gate 3777c478bd9Sstevel@tonic-gate lpsize = TTEBYTES(TTE8K); 3787c478bd9Sstevel@tonic-gate return (lpsize); 3797c478bd9Sstevel@tonic-gate } 3807c478bd9Sstevel@tonic-gate 3817c478bd9Sstevel@tonic-gate void 3827c478bd9Sstevel@tonic-gate mmu_init_kcontext() 3837c478bd9Sstevel@tonic-gate { 3847c478bd9Sstevel@tonic-gate } 3857c478bd9Sstevel@tonic-gate 3867c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 3877c478bd9Sstevel@tonic-gate void 3887c478bd9Sstevel@tonic-gate mmu_init_kernel_pgsz(struct hat *hat) 3897c478bd9Sstevel@tonic-gate { 3907c478bd9Sstevel@tonic-gate } 3917c478bd9Sstevel@tonic-gate 3927c478bd9Sstevel@tonic-gate static void * 3937c478bd9Sstevel@tonic-gate contig_mem_span_alloc(vmem_t *vmp, size_t size, int vmflag) 3947c478bd9Sstevel@tonic-gate { 3957c478bd9Sstevel@tonic-gate page_t *ppl; 3967c478bd9Sstevel@tonic-gate page_t *rootpp; 3977c478bd9Sstevel@tonic-gate caddr_t addr = NULL; 3987c478bd9Sstevel@tonic-gate pgcnt_t npages = btopr(size); 3997c478bd9Sstevel@tonic-gate page_t **ppa; 4007c478bd9Sstevel@tonic-gate int pgflags; 401*aaa10e67Sha137994 spgcnt_t i = 0; 4027c478bd9Sstevel@tonic-gate 4037c478bd9Sstevel@tonic-gate 404*aaa10e67Sha137994 ASSERT(size <= contig_mem_import_size_max); 405*aaa10e67Sha137994 ASSERT((size & (size - 1)) == 0); 4060400e0b7Sha137994 4077c478bd9Sstevel@tonic-gate if ((addr = vmem_xalloc(vmp, size, size, 0, 0, 4087c478bd9Sstevel@tonic-gate NULL, NULL, vmflag)) == NULL) { 4097c478bd9Sstevel@tonic-gate return (NULL); 4107c478bd9Sstevel@tonic-gate } 4117c478bd9Sstevel@tonic-gate 4120400e0b7Sha137994 /* The address should be slab-size aligned. */ 413*aaa10e67Sha137994 ASSERT(((uintptr_t)addr & (size - 1)) == 0); 4147c478bd9Sstevel@tonic-gate 4157c478bd9Sstevel@tonic-gate if (page_resv(npages, vmflag & VM_KMFLAGS) == 0) { 4167c478bd9Sstevel@tonic-gate vmem_xfree(vmp, addr, size); 4177c478bd9Sstevel@tonic-gate return (NULL); 4187c478bd9Sstevel@tonic-gate } 4197c478bd9Sstevel@tonic-gate 4207c478bd9Sstevel@tonic-gate pgflags = PG_EXCL; 421*aaa10e67Sha137994 if (vmflag & VM_NORELOC) 422*aaa10e67Sha137994 pgflags |= PG_NORELOC; 4237c478bd9Sstevel@tonic-gate 4247c478bd9Sstevel@tonic-gate ppl = page_create_va_large(&kvp, (u_offset_t)(uintptr_t)addr, size, 4257c478bd9Sstevel@tonic-gate pgflags, &kvseg, addr, NULL); 4267c478bd9Sstevel@tonic-gate 4277c478bd9Sstevel@tonic-gate if (ppl == NULL) { 4287c478bd9Sstevel@tonic-gate vmem_xfree(vmp, addr, size); 4297c478bd9Sstevel@tonic-gate page_unresv(npages); 4307c478bd9Sstevel@tonic-gate return (NULL); 4317c478bd9Sstevel@tonic-gate } 4327c478bd9Sstevel@tonic-gate 4337c478bd9Sstevel@tonic-gate rootpp = ppl; 4347c478bd9Sstevel@tonic-gate ppa = kmem_zalloc(npages * sizeof (page_t *), KM_SLEEP); 4357c478bd9Sstevel@tonic-gate while (ppl != NULL) { 4367c478bd9Sstevel@tonic-gate page_t *pp = ppl; 4377c478bd9Sstevel@tonic-gate ppa[i++] = pp; 4387c478bd9Sstevel@tonic-gate page_sub(&ppl, pp); 4397c478bd9Sstevel@tonic-gate ASSERT(page_iolock_assert(pp)); 440*aaa10e67Sha137994 ASSERT(PAGE_EXCL(pp)); 4417c478bd9Sstevel@tonic-gate page_io_unlock(pp); 4427c478bd9Sstevel@tonic-gate } 4437c478bd9Sstevel@tonic-gate 4447c478bd9Sstevel@tonic-gate /* 4457c478bd9Sstevel@tonic-gate * Load the locked entry. It's OK to preload the entry into 4467c478bd9Sstevel@tonic-gate * the TSB since we now support large mappings in the kernel TSB. 4477c478bd9Sstevel@tonic-gate */ 4487c478bd9Sstevel@tonic-gate hat_memload_array(kas.a_hat, (caddr_t)rootpp->p_offset, size, 4497c478bd9Sstevel@tonic-gate ppa, (PROT_ALL & ~PROT_USER) | HAT_NOSYNC, HAT_LOAD_LOCK); 4507c478bd9Sstevel@tonic-gate 451*aaa10e67Sha137994 ASSERT(i == page_get_pagecnt(ppa[0]->p_szc)); 4527c478bd9Sstevel@tonic-gate for (--i; i >= 0; --i) { 453*aaa10e67Sha137994 ASSERT(ppa[i]->p_szc == ppa[0]->p_szc); 454*aaa10e67Sha137994 ASSERT(page_pptonum(ppa[i]) == page_pptonum(ppa[0]) + i); 4557c478bd9Sstevel@tonic-gate (void) page_pp_lock(ppa[i], 0, 1); 456*aaa10e67Sha137994 /* 457*aaa10e67Sha137994 * Leave the page share locked. For non-cage pages, 458*aaa10e67Sha137994 * this would prevent memory DR if it were supported 459*aaa10e67Sha137994 * on sun4v. 460*aaa10e67Sha137994 */ 461*aaa10e67Sha137994 page_downgrade(ppa[i]); 4627c478bd9Sstevel@tonic-gate } 4637c478bd9Sstevel@tonic-gate 4647c478bd9Sstevel@tonic-gate kmem_free(ppa, npages * sizeof (page_t *)); 4657c478bd9Sstevel@tonic-gate return (addr); 4667c478bd9Sstevel@tonic-gate } 4677c478bd9Sstevel@tonic-gate 468*aaa10e67Sha137994 /* 469*aaa10e67Sha137994 * Allocates a slab by first trying to use the largest slab size 470*aaa10e67Sha137994 * in contig_mem_import_sizes and then falling back to smaller slab 471*aaa10e67Sha137994 * sizes still large enough for the allocation. The sizep argument 472*aaa10e67Sha137994 * is a pointer to the requested size. When a slab is successfully 473*aaa10e67Sha137994 * allocated, the slab size, which must be >= *sizep and <= 474*aaa10e67Sha137994 * contig_mem_import_size_max, is returned in the *sizep argument. 475*aaa10e67Sha137994 * Returns the virtual address of the new slab. 476*aaa10e67Sha137994 */ 477*aaa10e67Sha137994 static void * 478*aaa10e67Sha137994 span_alloc_downsize(vmem_t *vmp, size_t *sizep, size_t align, int vmflag) 479*aaa10e67Sha137994 { 480*aaa10e67Sha137994 int i; 481*aaa10e67Sha137994 482*aaa10e67Sha137994 ASSERT(*sizep <= contig_mem_import_size_max); 483*aaa10e67Sha137994 484*aaa10e67Sha137994 for (i = 0; i < NUM_IMPORT_SIZES; i++) { 485*aaa10e67Sha137994 size_t page_size = contig_mem_import_sizes[i]; 486*aaa10e67Sha137994 487*aaa10e67Sha137994 /* 488*aaa10e67Sha137994 * Check that the alignment is also less than the 489*aaa10e67Sha137994 * import (large page) size. In the case where the 490*aaa10e67Sha137994 * alignment is larger than the size, a large page 491*aaa10e67Sha137994 * large enough for the allocation is not necessarily 492*aaa10e67Sha137994 * physical-address aligned to satisfy the requested 493*aaa10e67Sha137994 * alignment. Since alignment is required to be a 494*aaa10e67Sha137994 * power-of-2, any large page >= size && >= align will 495*aaa10e67Sha137994 * suffice. 496*aaa10e67Sha137994 */ 497*aaa10e67Sha137994 if (*sizep <= page_size && align <= page_size) { 498*aaa10e67Sha137994 void *addr; 499*aaa10e67Sha137994 addr = contig_mem_span_alloc(vmp, page_size, vmflag); 500*aaa10e67Sha137994 if (addr == NULL) 501*aaa10e67Sha137994 continue; 502*aaa10e67Sha137994 *sizep = page_size; 503*aaa10e67Sha137994 return (addr); 504*aaa10e67Sha137994 } 505*aaa10e67Sha137994 return (NULL); 506*aaa10e67Sha137994 } 507*aaa10e67Sha137994 508*aaa10e67Sha137994 return (NULL); 509*aaa10e67Sha137994 } 510*aaa10e67Sha137994 511*aaa10e67Sha137994 static void * 512*aaa10e67Sha137994 contig_mem_span_xalloc(vmem_t *vmp, size_t *sizep, size_t align, int vmflag) 513*aaa10e67Sha137994 { 514*aaa10e67Sha137994 return (span_alloc_downsize(vmp, sizep, align, vmflag | VM_NORELOC)); 515*aaa10e67Sha137994 } 516*aaa10e67Sha137994 517*aaa10e67Sha137994 static void * 518*aaa10e67Sha137994 contig_mem_reloc_span_xalloc(vmem_t *vmp, size_t *sizep, size_t align, 519*aaa10e67Sha137994 int vmflag) 520*aaa10e67Sha137994 { 521*aaa10e67Sha137994 ASSERT((vmflag & VM_NORELOC) == 0); 522*aaa10e67Sha137994 return (span_alloc_downsize(vmp, sizep, align, vmflag)); 523*aaa10e67Sha137994 } 524*aaa10e67Sha137994 525*aaa10e67Sha137994 /* 526*aaa10e67Sha137994 * Free a span, which is always exactly one large page. 527*aaa10e67Sha137994 */ 528*aaa10e67Sha137994 static void 5297c478bd9Sstevel@tonic-gate contig_mem_span_free(vmem_t *vmp, void *inaddr, size_t size) 5307c478bd9Sstevel@tonic-gate { 5317c478bd9Sstevel@tonic-gate page_t *pp; 5327c478bd9Sstevel@tonic-gate caddr_t addr = inaddr; 5337c478bd9Sstevel@tonic-gate caddr_t eaddr; 5347c478bd9Sstevel@tonic-gate pgcnt_t npages = btopr(size); 5357c478bd9Sstevel@tonic-gate page_t *rootpp = NULL; 5367c478bd9Sstevel@tonic-gate 537*aaa10e67Sha137994 ASSERT(size <= contig_mem_import_size_max); 538*aaa10e67Sha137994 /* All slabs should be size aligned */ 539*aaa10e67Sha137994 ASSERT(((uintptr_t)addr & (size - 1)) == 0); 5407c478bd9Sstevel@tonic-gate 5417c478bd9Sstevel@tonic-gate hat_unload(kas.a_hat, addr, size, HAT_UNLOAD_UNLOCK); 5427c478bd9Sstevel@tonic-gate 5437c478bd9Sstevel@tonic-gate for (eaddr = addr + size; addr < eaddr; addr += PAGESIZE) { 544*aaa10e67Sha137994 pp = page_find(&kvp, (u_offset_t)(uintptr_t)addr); 545*aaa10e67Sha137994 if (pp == NULL) { 546*aaa10e67Sha137994 panic("contig_mem_span_free: page not found"); 547*aaa10e67Sha137994 } 548*aaa10e67Sha137994 if (!page_tryupgrade(pp)) { 549*aaa10e67Sha137994 page_unlock(pp); 550*aaa10e67Sha137994 pp = page_lookup(&kvp, 551*aaa10e67Sha137994 (u_offset_t)(uintptr_t)addr, SE_EXCL); 5527c478bd9Sstevel@tonic-gate if (pp == NULL) 5537c478bd9Sstevel@tonic-gate panic("contig_mem_span_free: page not found"); 554*aaa10e67Sha137994 } 5557c478bd9Sstevel@tonic-gate 5567c478bd9Sstevel@tonic-gate ASSERT(PAGE_EXCL(pp)); 557*aaa10e67Sha137994 ASSERT(size == page_get_pagesize(pp->p_szc)); 558*aaa10e67Sha137994 ASSERT(rootpp == NULL || rootpp->p_szc == pp->p_szc); 559*aaa10e67Sha137994 ASSERT(rootpp == NULL || (page_pptonum(rootpp) + 560*aaa10e67Sha137994 (pgcnt_t)btop(addr - (caddr_t)inaddr) == page_pptonum(pp))); 561*aaa10e67Sha137994 5627c478bd9Sstevel@tonic-gate page_pp_unlock(pp, 0, 1); 5637c478bd9Sstevel@tonic-gate 5647c478bd9Sstevel@tonic-gate if (rootpp == NULL) 5657c478bd9Sstevel@tonic-gate rootpp = pp; 566*aaa10e67Sha137994 } 5677c478bd9Sstevel@tonic-gate page_destroy_pages(rootpp); 5687c478bd9Sstevel@tonic-gate page_unresv(npages); 5697c478bd9Sstevel@tonic-gate 5707c478bd9Sstevel@tonic-gate if (vmp != NULL) 5717c478bd9Sstevel@tonic-gate vmem_xfree(vmp, inaddr, size); 5727c478bd9Sstevel@tonic-gate } 5737c478bd9Sstevel@tonic-gate 5747c478bd9Sstevel@tonic-gate static void * 575*aaa10e67Sha137994 contig_vmem_xalloc_aligned_wrapper(vmem_t *vmp, size_t *sizep, size_t align, 576*aaa10e67Sha137994 int vmflag) 5777c478bd9Sstevel@tonic-gate { 578*aaa10e67Sha137994 ASSERT((align & (align - 1)) == 0); 579*aaa10e67Sha137994 return (vmem_xalloc(vmp, *sizep, align, 0, 0, NULL, NULL, vmflag)); 5807c478bd9Sstevel@tonic-gate } 5817c478bd9Sstevel@tonic-gate 582ea841a36Sarao /* 583*aaa10e67Sha137994 * contig_mem_alloc, contig_mem_alloc_align 584*aaa10e67Sha137994 * 585*aaa10e67Sha137994 * Caution: contig_mem_alloc and contig_mem_alloc_align should be 586*aaa10e67Sha137994 * used only when physically contiguous non-relocatable memory is 587*aaa10e67Sha137994 * required. Furthermore, use of these allocation routines should be 588*aaa10e67Sha137994 * minimized as well as should the allocation size. As described in the 589*aaa10e67Sha137994 * contig_mem_arena comment block above, slab allocations fall back to 590*aaa10e67Sha137994 * being outside of the cage. Therefore, overuse of these allocation 591*aaa10e67Sha137994 * routines can lead to non-relocatable large pages being allocated 592*aaa10e67Sha137994 * outside the cage. Such pages prevent the allocation of a larger page 593*aaa10e67Sha137994 * occupying overlapping pages. This can impact performance for 594*aaa10e67Sha137994 * applications that utilize e.g. 256M large pages. 595ea841a36Sarao */ 596ea841a36Sarao 597ea841a36Sarao /* 598*aaa10e67Sha137994 * Allocates size aligned contiguous memory up to contig_mem_import_size_max. 599ea841a36Sarao * Size must be a power of 2. 600ea841a36Sarao */ 6017c478bd9Sstevel@tonic-gate void * 6027c478bd9Sstevel@tonic-gate contig_mem_alloc(size_t size) 6037c478bd9Sstevel@tonic-gate { 604ea841a36Sarao ASSERT((size & (size - 1)) == 0); 605ea841a36Sarao return (contig_mem_alloc_align(size, size)); 6067c478bd9Sstevel@tonic-gate } 6077c478bd9Sstevel@tonic-gate 608*aaa10e67Sha137994 /* 609*aaa10e67Sha137994 * contig_mem_alloc_align allocates real contiguous memory with the specified 610*aaa10e67Sha137994 * alignment up to contig_mem_import_size_max. The alignment must be a 611*aaa10e67Sha137994 * power of 2 and no greater than contig_mem_import_size_max. We assert 612*aaa10e67Sha137994 * the aligment is a power of 2. For non-debug, vmem_xalloc will panic 613*aaa10e67Sha137994 * for non power of 2 alignments. 614*aaa10e67Sha137994 */ 615*aaa10e67Sha137994 void * 616*aaa10e67Sha137994 contig_mem_alloc_align(size_t size, size_t align) 617*aaa10e67Sha137994 { 618*aaa10e67Sha137994 void *buf; 619*aaa10e67Sha137994 620*aaa10e67Sha137994 ASSERT(size <= contig_mem_import_size_max); 621*aaa10e67Sha137994 ASSERT(align <= contig_mem_import_size_max); 622*aaa10e67Sha137994 ASSERT((align & (align - 1)) == 0); 623*aaa10e67Sha137994 624*aaa10e67Sha137994 if (align < CONTIG_MEM_ARENA_QUANTUM) 625*aaa10e67Sha137994 align = CONTIG_MEM_ARENA_QUANTUM; 626*aaa10e67Sha137994 627*aaa10e67Sha137994 /* 628*aaa10e67Sha137994 * We take the lock here to serialize span allocations. 629*aaa10e67Sha137994 * We do not lose concurrency for the common case, since 630*aaa10e67Sha137994 * allocations that don't require new span allocations 631*aaa10e67Sha137994 * are serialized by vmem_xalloc. Serializing span 632*aaa10e67Sha137994 * allocations also prevents us from trying to allocate 633*aaa10e67Sha137994 * more spans that necessary. 634*aaa10e67Sha137994 */ 635*aaa10e67Sha137994 mutex_enter(&contig_mem_lock); 636*aaa10e67Sha137994 637*aaa10e67Sha137994 buf = vmem_xalloc(contig_mem_arena, size, align, 0, 0, 638*aaa10e67Sha137994 NULL, NULL, VM_NOSLEEP | VM_NORELOC); 639*aaa10e67Sha137994 640*aaa10e67Sha137994 if ((buf == NULL) && (size <= MMU_PAGESIZE)) { 641*aaa10e67Sha137994 mutex_exit(&contig_mem_lock); 642*aaa10e67Sha137994 return (vmem_xalloc(static_alloc_arena, size, align, 0, 0, 643*aaa10e67Sha137994 NULL, NULL, VM_NOSLEEP)); 644*aaa10e67Sha137994 } 645*aaa10e67Sha137994 646*aaa10e67Sha137994 if (buf == NULL) { 647*aaa10e67Sha137994 buf = vmem_xalloc(contig_mem_reloc_arena, size, align, 0, 0, 648*aaa10e67Sha137994 NULL, NULL, VM_NOSLEEP); 649*aaa10e67Sha137994 } 650*aaa10e67Sha137994 651*aaa10e67Sha137994 mutex_exit(&contig_mem_lock); 652*aaa10e67Sha137994 653*aaa10e67Sha137994 return (buf); 654*aaa10e67Sha137994 } 655*aaa10e67Sha137994 6567c478bd9Sstevel@tonic-gate void 6577c478bd9Sstevel@tonic-gate contig_mem_free(void *vaddr, size_t size) 6587c478bd9Sstevel@tonic-gate { 659*aaa10e67Sha137994 if (vmem_contains(contig_mem_arena, vaddr, size)) { 6607c478bd9Sstevel@tonic-gate vmem_xfree(contig_mem_arena, vaddr, size); 661*aaa10e67Sha137994 } else if (size > MMU_PAGESIZE) { 662*aaa10e67Sha137994 vmem_xfree(contig_mem_reloc_arena, vaddr, size); 663*aaa10e67Sha137994 } else { 664*aaa10e67Sha137994 vmem_xfree(static_alloc_arena, vaddr, size); 665*aaa10e67Sha137994 } 6667c478bd9Sstevel@tonic-gate } 6677c478bd9Sstevel@tonic-gate 6687c478bd9Sstevel@tonic-gate /* 6697c478bd9Sstevel@tonic-gate * We create a set of stacked vmem arenas to enable us to 670*aaa10e67Sha137994 * allocate large >PAGESIZE chucks of contiguous Real Address space. 671*aaa10e67Sha137994 * The vmem_xcreate interface is used to create the contig_mem_arena 672*aaa10e67Sha137994 * allowing the import routine to downsize the requested slab size 673*aaa10e67Sha137994 * and return a smaller slab. 6747c478bd9Sstevel@tonic-gate */ 6757c478bd9Sstevel@tonic-gate void 6767c478bd9Sstevel@tonic-gate contig_mem_init(void) 6777c478bd9Sstevel@tonic-gate { 678*aaa10e67Sha137994 mutex_init(&contig_mem_lock, NULL, MUTEX_DEFAULT, NULL); 6797c478bd9Sstevel@tonic-gate 680*aaa10e67Sha137994 contig_mem_slab_arena = vmem_xcreate("contig_mem_slab_arena", NULL, 0, 681*aaa10e67Sha137994 CONTIG_MEM_SLAB_ARENA_QUANTUM, contig_vmem_xalloc_aligned_wrapper, 682*aaa10e67Sha137994 vmem_xfree, heap_arena, 0, VM_SLEEP | VMC_XALIGN); 6837c478bd9Sstevel@tonic-gate 684*aaa10e67Sha137994 contig_mem_arena = vmem_xcreate("contig_mem_arena", NULL, 0, 685*aaa10e67Sha137994 CONTIG_MEM_ARENA_QUANTUM, contig_mem_span_xalloc, 686*aaa10e67Sha137994 contig_mem_span_free, contig_mem_slab_arena, 0, 687*aaa10e67Sha137994 VM_SLEEP | VM_BESTFIT | VMC_XALIGN); 6887c478bd9Sstevel@tonic-gate 689*aaa10e67Sha137994 contig_mem_reloc_arena = vmem_xcreate("contig_mem_reloc_arena", NULL, 0, 690*aaa10e67Sha137994 CONTIG_MEM_ARENA_QUANTUM, contig_mem_reloc_span_xalloc, 691*aaa10e67Sha137994 contig_mem_span_free, contig_mem_slab_arena, 0, 692*aaa10e67Sha137994 VM_SLEEP | VM_BESTFIT | VMC_XALIGN); 693*aaa10e67Sha137994 694*aaa10e67Sha137994 if (vmem_add(contig_mem_arena, prealloc_buf, prealloc_size, 695*aaa10e67Sha137994 VM_SLEEP) == NULL) 696*aaa10e67Sha137994 cmn_err(CE_PANIC, "Failed to pre-populate contig_mem_arena"); 6977c478bd9Sstevel@tonic-gate } 698102033aaSdp78419 699*aaa10e67Sha137994 /* 700*aaa10e67Sha137994 * In calculating how much memory to pre-allocate, we include a small 701*aaa10e67Sha137994 * amount per-CPU to account for per-CPU buffers in line with measured 702*aaa10e67Sha137994 * values for different size systems. contig_mem_prealloc_base is the 703*aaa10e67Sha137994 * base fixed amount to be preallocated before considering per-CPU 704*aaa10e67Sha137994 * requirements and memory size. We take the minimum of 705*aaa10e67Sha137994 * contig_mem_prealloc_base and a small percentage of physical memory 706*aaa10e67Sha137994 * to prevent allocating too much on smaller systems. 707*aaa10e67Sha137994 */ 708*aaa10e67Sha137994 #define PREALLOC_PER_CPU (256 * 1024) /* 256K */ 709*aaa10e67Sha137994 #define PREALLOC_PERCENT (4) /* 4% */ 710*aaa10e67Sha137994 #define PREALLOC_MIN (16 * 1024 * 1024) /* 16M */ 711*aaa10e67Sha137994 size_t contig_mem_prealloc_base = 0; 712*aaa10e67Sha137994 713*aaa10e67Sha137994 /* 714*aaa10e67Sha137994 * Called at boot-time allowing pre-allocation of contiguous memory. 715*aaa10e67Sha137994 * The argument 'alloc_base' is the requested base address for the 716*aaa10e67Sha137994 * allocation and originates in startup_memlist. 717*aaa10e67Sha137994 */ 718*aaa10e67Sha137994 caddr_t 719*aaa10e67Sha137994 contig_mem_prealloc(caddr_t alloc_base, pgcnt_t npages) 720*aaa10e67Sha137994 { 721*aaa10e67Sha137994 prealloc_size = MIN((PREALLOC_PER_CPU * ncpu_guest_max) + 722*aaa10e67Sha137994 contig_mem_prealloc_base, (ptob(npages) * PREALLOC_PERCENT) / 100); 723*aaa10e67Sha137994 prealloc_size = MAX(prealloc_size, PREALLOC_MIN); 724*aaa10e67Sha137994 prealloc_size = P2ROUNDUP(prealloc_size, MMU_PAGESIZE4M); 725*aaa10e67Sha137994 726*aaa10e67Sha137994 alloc_base = (caddr_t)roundup((uintptr_t)alloc_base, MMU_PAGESIZE4M); 727*aaa10e67Sha137994 prealloc_buf = alloc_base; 728*aaa10e67Sha137994 alloc_base += prealloc_size; 729*aaa10e67Sha137994 730*aaa10e67Sha137994 return (alloc_base); 731*aaa10e67Sha137994 } 732102033aaSdp78419 733102033aaSdp78419 static uint_t sp_color_stride = 16; 734102033aaSdp78419 static uint_t sp_color_mask = 0x1f; 735102033aaSdp78419 static uint_t sp_current_color = (uint_t)-1; 736102033aaSdp78419 737102033aaSdp78419 size_t 738102033aaSdp78419 exec_get_spslew(void) 739102033aaSdp78419 { 740102033aaSdp78419 uint_t spcolor = atomic_inc_32_nv(&sp_current_color); 741102033aaSdp78419 return ((size_t)((spcolor & sp_color_mask) * SA(sp_color_stride))); 742102033aaSdp78419 } 743