17c478bd9Sstevel@tonic-gate /* 27636cb21Slm66018 * CDDL HEADER START 37636cb21Slm66018 * 47636cb21Slm66018 * The contents of this file are subject to the terms of the 57636cb21Slm66018 * Common Development and Distribution License (the "License"). 67636cb21Slm66018 * You may not use this file except in compliance with the License. 77636cb21Slm66018 * 87636cb21Slm66018 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97636cb21Slm66018 * or http://www.opensolaris.org/os/licensing. 107636cb21Slm66018 * See the License for the specific language governing permissions 117636cb21Slm66018 * and limitations under the License. 127636cb21Slm66018 * 137636cb21Slm66018 * When distributing Covered Code, include this CDDL HEADER in each 147636cb21Slm66018 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157636cb21Slm66018 * If applicable, add the following below this CDDL HEADER, with the 167636cb21Slm66018 * fields enclosed by brackets "[]" replaced with your own identifying 177636cb21Slm66018 * information: Portions Copyright [yyyy] [name of copyright owner] 187636cb21Slm66018 * 197636cb21Slm66018 * CDDL HEADER END 207636cb21Slm66018 */ 217636cb21Slm66018 227636cb21Slm66018 /* 2360972f37Sjb145095 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 247c478bd9Sstevel@tonic-gate * Use is subject to license terms. 257c478bd9Sstevel@tonic-gate */ 267c478bd9Sstevel@tonic-gate 277c478bd9Sstevel@tonic-gate #ifndef _SYS_MMU_H 287c478bd9Sstevel@tonic-gate #define _SYS_MMU_H 297c478bd9Sstevel@tonic-gate 307c478bd9Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 317c478bd9Sstevel@tonic-gate 327c478bd9Sstevel@tonic-gate #ifdef __cplusplus 337c478bd9Sstevel@tonic-gate extern "C" { 347c478bd9Sstevel@tonic-gate #endif 357c478bd9Sstevel@tonic-gate 367c478bd9Sstevel@tonic-gate #ifndef _ASM 377c478bd9Sstevel@tonic-gate #include <sys/types.h> 387c478bd9Sstevel@tonic-gate #endif 397c478bd9Sstevel@tonic-gate #include <sys/hypervisor_api.h> 407c478bd9Sstevel@tonic-gate 417c478bd9Sstevel@tonic-gate /* 427c478bd9Sstevel@tonic-gate * Definitions for the SOFT MMU 437c478bd9Sstevel@tonic-gate */ 447c478bd9Sstevel@tonic-gate 457c478bd9Sstevel@tonic-gate #define FAST_IMMU_MISS_TT 0x64 467c478bd9Sstevel@tonic-gate #define FAST_DMMU_MISS_TT 0x68 477c478bd9Sstevel@tonic-gate #define FAST_PROT_TT 0x6c 487c478bd9Sstevel@tonic-gate 497c478bd9Sstevel@tonic-gate /* 507c478bd9Sstevel@tonic-gate * Constants defining alternate spaces 517c478bd9Sstevel@tonic-gate * and register layouts within them, 527c478bd9Sstevel@tonic-gate * and a few other interesting assembly constants. 537c478bd9Sstevel@tonic-gate */ 547c478bd9Sstevel@tonic-gate 557c478bd9Sstevel@tonic-gate /* 567c478bd9Sstevel@tonic-gate * vaddr offsets of various registers 577c478bd9Sstevel@tonic-gate */ 587c478bd9Sstevel@tonic-gate #define MMU_PCONTEXT 0x08 /* primary context number */ 597c478bd9Sstevel@tonic-gate #define MMU_SCONTEXT 0x10 /* secondary context number */ 607c478bd9Sstevel@tonic-gate 6105d3dc4bSpaulsan #define MMU_PCONTEXT0 MMU_PCONTEXT /* primary context# 0 */ 6205d3dc4bSpaulsan #define MMU_PCONTEXT1 0x108 /* primary context# 1 */ 6305d3dc4bSpaulsan #define MMU_SCONTEXT0 MMU_SCONTEXT /* secondary context# 0 */ 6405d3dc4bSpaulsan #define MMU_SCONTEXT1 0x110 /* secondary context# 1 */ 6505d3dc4bSpaulsan 667c478bd9Sstevel@tonic-gate /* 677c478bd9Sstevel@tonic-gate * Pseudo Synchronous Fault Status Register Layout 687c478bd9Sstevel@tonic-gate * 697c478bd9Sstevel@tonic-gate * IMMU and DMMU maintain their own pseudo SFSR Register 707c478bd9Sstevel@tonic-gate * 717c478bd9Sstevel@tonic-gate * +------------------------------------------------+ 727c478bd9Sstevel@tonic-gate * | Reserved | Context | FT | 737c478bd9Sstevel@tonic-gate * +----------------------|-------------------------+ 747c478bd9Sstevel@tonic-gate * 63 32 31 16 15 0 757c478bd9Sstevel@tonic-gate * 767c478bd9Sstevel@tonic-gate */ 777c478bd9Sstevel@tonic-gate #define SFSR_FT 0x0000FFFF /* fault type mask */ 787c478bd9Sstevel@tonic-gate #define SFSR_CTX 0xFFFF0000 /* fault context mask */ 797c478bd9Sstevel@tonic-gate 807c478bd9Sstevel@tonic-gate /* 817c478bd9Sstevel@tonic-gate * Definition of FT (Fault Type) bit field of sfsr. 827c478bd9Sstevel@tonic-gate */ 837c478bd9Sstevel@tonic-gate #define FT_NONE 0x00 847c478bd9Sstevel@tonic-gate #define FT_PRIV MMFSA_F_PRIV /* privilege violation */ 857c478bd9Sstevel@tonic-gate #define FT_SPEC_LD MMFSA_F_SOPG /* speculative ld to e page */ 867c478bd9Sstevel@tonic-gate #define FT_ATOMIC_NC MMFSA_F_NCATM /* atomic to nc page */ 877c478bd9Sstevel@tonic-gate #define FT_ILL_ALT MMFSA_F_INVASI /* illegal lda/sta */ 887c478bd9Sstevel@tonic-gate #define FT_NFO MMFSA_F_NFO /* normal access to nfo page */ 897c478bd9Sstevel@tonic-gate #define FT_RANGE MMFSA_F_INVVA /* dmmu or immu address out of range */ 907c478bd9Sstevel@tonic-gate #define FT_NEW_FMISS MMFSA_F_FMISS /* fast miss */ 917c478bd9Sstevel@tonic-gate #define FT_NEW_FPROT MMFSA_F_FPROT /* fast protection */ 927c478bd9Sstevel@tonic-gate #define FT_NEW_MISS MMFSA_F_MISS /* mmu miss */ 937c478bd9Sstevel@tonic-gate #define FT_NEW_INVRA MMFSA_F_INVRA /* invalid RA */ 947c478bd9Sstevel@tonic-gate #define FT_NEW_PROT MMFSA_F_PROT /* protection violation */ 957c478bd9Sstevel@tonic-gate #define FT_NEW_PRVACT MMFSA_F_PRVACT /* privileged action */ 967c478bd9Sstevel@tonic-gate #define FT_NEW_WPT MMFSA_F_WPT /* watchpoint hit */ 977c478bd9Sstevel@tonic-gate #define FT_NEW_UNALIGN MMFSA_F_UNALIGN /* unaligned access */ 987c478bd9Sstevel@tonic-gate #define FT_NEW_INVPGSZ MMFSA_F_INVPGSZ /* invalid page size */ 997c478bd9Sstevel@tonic-gate 1007c478bd9Sstevel@tonic-gate #define SFSR_FT_SHIFT 0 /* amt. to shift right to get flt type */ 1017c478bd9Sstevel@tonic-gate #define SFSR_CTX_SHIFT 16 /* to shift right to get context */ 1027c478bd9Sstevel@tonic-gate #define X_FAULT_TYPE(x) (((x) & SFSR_FT) >> SFSR_FT_SHIFT) 1037c478bd9Sstevel@tonic-gate #define X_FAULT_CTX(x) (((x) & SFSR_CTX) >> SFSR_CTX_SHIFT) 1047c478bd9Sstevel@tonic-gate 1057c478bd9Sstevel@tonic-gate /* 1067c478bd9Sstevel@tonic-gate * MMU TAG TARGET register Layout 1077c478bd9Sstevel@tonic-gate * 10860972f37Sjb145095 * +---------------+------+-------------------------+ 10960972f37Sjb145095 * | context | -- | virtual address [63:22] | 11060972f37Sjb145095 * +---------------+------+-------------------------+ 11160972f37Sjb145095 * 63 48 47 42 41 0 11260972f37Sjb145095 * 11360972f37Sjb145095 * Some sun4v processors only use a 13-bit context ID, so bits 61-63 will be 11460972f37Sjb145095 * zero in that case. This layout allows us to use the same code for any sun4v 11560972f37Sjb145095 * processors, whether they support 13 bit or 16 bit context IDs (or something 11660972f37Sjb145095 * in between). 1177c478bd9Sstevel@tonic-gate */ 1187c478bd9Sstevel@tonic-gate #define TTARGET_CTX_SHIFT 48 1197c478bd9Sstevel@tonic-gate #define TTARGET_VA_SHIFT 22 1207c478bd9Sstevel@tonic-gate 1217c478bd9Sstevel@tonic-gate /* 12260972f37Sjb145095 * Pseudo MMU TAG ACCESS register Layout 1237c478bd9Sstevel@tonic-gate * 1247c478bd9Sstevel@tonic-gate * +-------------------------+------------------+ 12560972f37Sjb145095 * | virtual address [63:13] | 0 | type | 1267c478bd9Sstevel@tonic-gate * +-------------------------+------------------+ 12760972f37Sjb145095 * 63 13 12 2 1 0 12860972f37Sjb145095 * 12960972f37Sjb145095 * 16-bit context IDs don't fit into the 13 bit field as they did on sun4u, 13060972f37Sjb145095 * so we use a context type, 0 = kernel context, 1 = invalid context, 13160972f37Sjb145095 * 2 = user context. 1327c478bd9Sstevel@tonic-gate */ 1337c478bd9Sstevel@tonic-gate #define TAGACC_CTX_MASK 0x1FFF 1347c478bd9Sstevel@tonic-gate #define TAGACC_SHIFT 13 1357c478bd9Sstevel@tonic-gate #define TAGACC_VADDR_MASK (~TAGACC_CTX_MASK) 1367c478bd9Sstevel@tonic-gate #define TAGACC_CTX_LSHIFT (64 - TAGACC_SHIFT) 1377c478bd9Sstevel@tonic-gate 1387c478bd9Sstevel@tonic-gate /* 1397c478bd9Sstevel@tonic-gate * The kernel always runs in KCONTEXT, and no user mappings 1407c478bd9Sstevel@tonic-gate * are ever valid in it (so any user access pagefaults). 1417c478bd9Sstevel@tonic-gate */ 1427c478bd9Sstevel@tonic-gate #define KCONTEXT 0 1437c478bd9Sstevel@tonic-gate 1447c478bd9Sstevel@tonic-gate /* 1457c478bd9Sstevel@tonic-gate * FLUSH_ADDR is used in the flush instruction to guarantee stores to mmu 1467c478bd9Sstevel@tonic-gate * registers complete. It is selected so it won't miss in the tlb. 1477c478bd9Sstevel@tonic-gate */ 1487c478bd9Sstevel@tonic-gate #define FLUSH_ADDR (KERNELBASE + 2 * MMU_PAGESIZE4M) 1497c478bd9Sstevel@tonic-gate 1501ae08745Sheppo #define MAX_NCTXS_BITS 16 /* sun4v max. contexts bits */ 1511ae08745Sheppo #define MIN_NCTXS_BITS 2 1521ae08745Sheppo #define MAX_NCTXS (1ull << MAX_NCTXS_BITS) 1531ae08745Sheppo 15405d3dc4bSpaulsan /* 155*7dacfc44Spaulsan * MIN_NSHCONTEXTS and MIN_NTSBS are the minimum number of shared contexts 156*7dacfc44Spaulsan * and tsbs necessary for shared context support. 15705d3dc4bSpaulsan */ 15805d3dc4bSpaulsan #define MIN_NSHCONTEXTS 1 15905d3dc4bSpaulsan #define MIN_NTSBS 4 16005d3dc4bSpaulsan 1617c478bd9Sstevel@tonic-gate #ifdef __cplusplus 1627c478bd9Sstevel@tonic-gate } 1637c478bd9Sstevel@tonic-gate #endif 1647c478bd9Sstevel@tonic-gate 1657c478bd9Sstevel@tonic-gate #endif /* _SYS_MMU_H */ 166