xref: /illumos-gate/usr/src/uts/sun4v/sys/machcpuvar.h (revision fbd1c0dae6f4a2ccc2ce0527c7f19d3dd5ea90b8)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef	_SYS_MACHCPUVAR_H
27 #define	_SYS_MACHCPUVAR_H
28 
29 #pragma ident	"%Z%%M%	%I%	%E% SMI"
30 
31 #include <sys/intr.h>
32 #include <sys/clock.h>
33 #include <sys/machparam.h>
34 #include <sys/machpcb.h>
35 #include <sys/privregs.h>
36 #include <sys/machlock.h>
37 #include <sys/async.h>
38 #include <sys/error.h>
39 
40 #ifdef	__cplusplus
41 extern "C" {
42 #endif
43 
44 #ifndef	_ASM
45 
46 #include <sys/obpdefs.h>
47 #include <sys/async.h>
48 #include <sys/fm/protocol.h>
49 
50 /*
51  * CPU state ptl1_panic save.
52  */
53 typedef struct ptl1_trapregs {
54 	uint32_t	ptl1_tl;
55 	uint32_t	ptl1_tt;
56 	uint64_t	ptl1_tstate;
57 	uint64_t	ptl1_tpc;
58 	uint64_t	ptl1_tnpc;
59 } ptl1_trapregs_t;
60 
61 typedef struct ptl1_gregs {
62 	uint64_t	ptl1_gl;
63 	uint64_t	ptl1_g1;
64 	uint64_t	ptl1_g2;
65 	uint64_t	ptl1_g3;
66 	uint64_t	ptl1_g4;
67 	uint64_t	ptl1_g5;
68 	uint64_t	ptl1_g6;
69 	uint64_t	ptl1_g7;
70 } ptl1_gregs_t;
71 
72 typedef struct ptl1_regs {
73 	ptl1_trapregs_t	ptl1_trap_regs[PTL1_MAXTL];
74 	ptl1_gregs_t	ptl1_gregs[PTL1_MAXGL + 1];
75 	uint64_t	ptl1_tick;
76 	uint64_t	ptl1_dmmu_type;
77 	uint64_t	ptl1_dmmu_addr;
78 	uint64_t	ptl1_dmmu_ctx;
79 	uint64_t	ptl1_immu_type;
80 	uint64_t	ptl1_immu_addr;
81 	uint64_t	ptl1_immu_ctx;
82 	struct rwindow	ptl1_rwindow[MAXWIN];
83 	uint32_t	ptl1_softint;
84 	uint16_t	ptl1_pstate;
85 	uint8_t		ptl1_pil;
86 	uint8_t		ptl1_cwp;
87 	uint8_t		ptl1_wstate;
88 	uint8_t		ptl1_otherwin;
89 	uint8_t		ptl1_cleanwin;
90 	uint8_t		ptl1_cansave;
91 	uint8_t		ptl1_canrestore;
92 } ptl1_regs_t;
93 
94 typedef struct ptl1_state {
95 	ptl1_regs_t	ptl1_regs;
96 	uint32_t	ptl1_entry_count;
97 	uintptr_t	ptl1_stktop;
98 	ulong_t		ptl1_stk[1];
99 } ptl1_state_t;
100 
101 /*
102  * For cpu_chip and cpu_core in machcpu structure if we cannot get
103  * any chip id or core id information from MD.
104  */
105 #define	CPU_CHIPID_INVALID	-1
106 #define	CPU_COREID_INVALID	-1
107 
108 /*
109  * Machine specific fields of the cpu struct
110  * defined in common/sys/cpuvar.h.
111  */
112 struct	machcpu {
113 	struct machpcb	*mpcb;
114 	uint64_t	mpcb_pa;
115 	int		mutex_ready;
116 	int		in_prom;
117 	int		tl1_hdlr;
118 	char		cpu_tstat_flags;	/* tstat flags */
119 	uint16_t	divisor;	/* Estar %tick clock ratio */
120 	uint8_t		intrcnt;	/* number of back-to-back interrupts */
121 	u_longlong_t	tmp1;		/* per-cpu tmps */
122 	u_longlong_t	tmp2;		/*  used in trap processing */
123 	u_longlong_t	tmp3;
124 	u_longlong_t	tmp4;
125 
126 	label_t		*ofd[HIGH_LEVELS];	/* saved pil ofd */
127 	uintptr_t	lfd[HIGH_LEVELS];	/* saved ret PC */
128 	struct on_trap_data *otd[HIGH_LEVELS];	/* saved pil otd */
129 
130 	struct intr_vec	*intr_head[PIL_LEVELS];	/* intr queue heads per pil */
131 	struct intr_vec	*intr_tail[PIL_LEVELS];	/* intr queue tails per pil */
132 	boolean_t	poke_cpu_outstanding;
133 	/*
134 	 * The cpu module allocates a private data structure for the
135 	 * E$ data, which is needed for the specific cpu type.
136 	 */
137 	void		*cpu_private;		/* ptr to cpu private data */
138 	/*
139 	 * per-MMU ctxdom CPU data.
140 	 */
141 	uint_t		cpu_mmu_idx;
142 	struct mmu_ctx	*cpu_mmu_ctxp;
143 
144 	ptl1_state_t	ptl1_state;
145 
146 	uint64_t	pil_high_start[HIGH_LEVELS];	/* high-level intrs */
147 
148 	/*
149 	 * intrstat[][] is used to keep track of ticks used at a given pil
150 	 * level. intrstat[pil][0] is cumulative and exported via kstats.
151 	 * intrstat[pil][1] is used in intr_get_time() and is private.
152 	 * 2-dimensional array improves cache locality.
153 	 */
154 
155 	uint64_t	intrstat[PIL_MAX+1][2];
156 
157 	int		kwbuf_full;
158 	caddr_t		kwbuf_sp;
159 	struct rwindow	kwbuf;
160 
161 	caddr_t		cpu_q_va;	/* cpu intrq base VA */
162 	caddr_t		dev_q_va;	/* dev intrq base VA */
163 	uint64_t	cpu_q_base_pa;	/* cpu intrq base PA */
164 	uint64_t	cpu_q_size;
165 	uint64_t	dev_q_base_pa;	/* dev intrq base PA */
166 	uint64_t	dev_q_size;
167 	caddr_t		cpu_rq_va;	/* resumable Q base VA */
168 	caddr_t		cpu_nrq_va;	/* nonresumable Q base VA */
169 	uint64_t	cpu_rq_base_pa;	/* resumable Q base PA */
170 	uint64_t	cpu_rq_size;	/* resumable Q size */
171 	uint64_t	cpu_nrq_base_pa;	/* nonresumable Q base PA */
172 	uint64_t	cpu_nrq_size;		/* nonresumable Q size */
173 	errh_er_t	*cpu_rq_lastre;		/* most recent RE */
174 	errh_er_t	*cpu_nrq_lastnre;	/* most recent NRE */
175 	caddr_t		mondo_data;		/* send mondo data */
176 	uint64_t	mondo_data_ra;		/* mono data pa */
177 	uint16_t	*cpu_list;		/* uint16_t [NCPU] */
178 	uint64_t	cpu_list_ra;		/* cpu list ra */
179 	id_t		cpu_ipipe;		/* cpu int exec unit id */
180 	id_t		cpu_fpu;		/* cpu fpu unit id */
181 	id_t		cpu_core;		/* cpu core id */
182 	id_t		cpu_chip;		/* cpu chip id */
183 	kthread_t	*startup_thread;
184 };
185 
186 typedef	struct machcpu	machcpu_t;
187 
188 #define	cpu_startup_thread	cpu_m.startup_thread
189 #define	CPU_MMU_IDX(cp)		((cp)->cpu_m.cpu_mmu_idx)
190 #define	CPU_MMU_CTXP(cp)	((cp)->cpu_m.cpu_mmu_ctxp)
191 #define	NINTR_THREADS	(LOCK_LEVEL)	/* number of interrupt threads */
192 
193 /*
194  * Macro to access the "cpu private" data structure.
195  */
196 #define	CPU_PRIVATE(cp)		((cp)->cpu_m.cpu_private)
197 
198 /*
199  * The OpenBoot Standalone Interface supplies the kernel with
200  * implementation dependent parameters through the devinfo/property mechanism
201  */
202 #define	MAXSYSNAME	20
203 
204 /*
205  * Used to indicate busy/idle state of a cpu.
206  * msram field will be set with ECACHE_CPU_MIRROR if we are on
207  * mirrored sram module.
208  */
209 #define	ECACHE_CPU_IDLE		0x0		/* CPU is idle */
210 #define	ECACHE_CPU_BUSY		0x1		/* CPU is busy */
211 #define	ECACHE_CPU_MIRROR 	0x2		/* E$ is mirrored */
212 #define	ECACHE_CPU_NON_MIRROR	0x3		/* E$ is not mirrored */
213 
214 /*
215  * A CPU FRU FMRI string minus the unum component.
216  */
217 #define	CPU_FRU_FMRI		FM_FMRI_SCHEME_HC":///" \
218     FM_FMRI_LEGACY_HC"="
219 
220 struct cpu_node {
221 	char	name[MAXSYSNAME];
222 	char	fru_fmri[sizeof (CPU_FRU_FMRI) + UNUM_NAMLEN];
223 	int	cpuid;
224 	pnode_t	nodeid;
225 	uint64_t	clock_freq;
226 	uint_t	tick_nsec_scale;
227 	union {
228 		int	dummy;
229 	}	u_info;
230 	int	ecache_size;
231 	int	ecache_linesize;
232 	int	ecache_associativity;
233 	int	ecache_setsize;
234 	uint64_t	device_id;
235 	id_t	exec_unit_mapping;
236 	id_t	fpu_mapping;
237 	id_t	l2_cache_mapping;
238 	id_t	core_mapping;
239 };
240 
241 extern struct cpu_node cpunodes[];
242 
243 #endif	/* _ASM */
244 
245 #ifdef	__cplusplus
246 }
247 #endif
248 
249 #endif	/* _SYS_MACHCPUVAR_H */
250