1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_HYPERVISOR_API_H 28 #define _SYS_HYPERVISOR_API_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 /* 33 * sun4v Hypervisor API 34 * 35 * Reference: api.pdf Revision 0.12 dated May 12, 2004. 36 * io-api.txt version 1.11 dated 10/19/2004 37 */ 38 39 #ifdef __cplusplus 40 extern "C" { 41 #endif 42 43 /* 44 * Trap types 45 */ 46 #define FAST_TRAP 0x80 /* Function # in %o5 */ 47 #define CPU_TICK_NPT 0x81 48 #define CPU_STICK_NPT 0x82 49 #define MMU_MAP_ADDR 0x83 50 #define MMU_UNMAP_ADDR 0x84 51 52 /* 53 * Error returns in %o0. 54 * (Additional result is returned in %o1.) 55 */ 56 #define H_EOK 0 /* Successful return */ 57 #define H_ENOCPU 1 /* Invalid CPU id */ 58 #define H_ENORADDR 2 /* Invalid real address */ 59 #define H_ENOINTR 3 /* Invalid interrupt id */ 60 #define H_EBADPGSZ 4 /* Invalid pagesize encoding */ 61 #define H_EBADTSB 5 /* Invalid TSB description */ 62 #define H_EINVAL 6 /* Invalid argument */ 63 #define H_EBADTRAP 7 /* Invalid function number */ 64 #define H_EBADALIGN 8 /* Invalid address alignment */ 65 #define H_EWOULDBLOCK 9 /* Cannot complete operation */ 66 /* without blocking */ 67 #define H_ENOACCESS 10 /* No access to resource */ 68 #define H_EIO 11 /* I/O error */ 69 #define H_ECPUERROR 12 /* CPU is in error state */ 70 #define H_ENOTSUPPORTED 13 /* Function not supported */ 71 #define H_ENOMAP 14 /* Mapping is not valid, */ 72 /* no translation exists */ 73 #define H_EBUSY 17 /* Resource busy */ 74 75 #define H_BREAK -1 /* Console Break */ 76 #define H_HUP -2 /* Console Break */ 77 78 /* 79 * Mondo CPU ID argument processing. 80 */ 81 #define HV_SEND_MONDO_ENTRYDONE 0xffff 82 83 /* 84 * Function numbers for FAST_TRAP. 85 */ 86 #define HV_MACH_EXIT 0x00 87 #define HV_MACH_DESC 0x01 88 #define HV_CPU_YIELD 0x12 89 #define CPU_QCONF 0x14 90 #define HV_CPU_STATE 0x17 91 #define MMU_TSB_CTX0 0x20 92 #define MMU_TSB_CTXNON0 0x21 93 #define MMU_DEMAP_PAGE 0x22 94 #define MMU_DEMAP_CTX 0x23 95 #define MMU_DEMAP_ALL 0x24 96 #define MAP_PERM_ADDR 0x25 97 #define MMU_SET_INFOPTR 0x26 98 #define UNMAP_PERM_ADDR 0x28 99 #define HV_MEM_SCRUB 0x31 100 #define HV_MEM_SYNC 0x32 101 #define HV_INTR_SEND 0x42 102 #define TOD_GET 0x50 103 #define TOD_SET 0x51 104 #define CONS_READ 0x60 105 #define CONS_WRITE 0x61 106 107 #define SVC_SEND 0x80 108 #define SVC_RECV 0x81 109 #define SVC_GETSTATUS 0x82 110 #define SVC_SETSTATUS 0x83 111 #define SVC_CLRSTATUS 0x84 112 113 #define TTRACE_BUF_CONF 0x90 114 #define TTRACE_BUF_INFO 0x91 115 #define TTRACE_ENABLE 0x92 116 #define TTRACE_FREEZE 0x93 117 118 #define DUMP_BUF_UPDATE 0x94 119 120 #define HVIO_INTR_DEVINO2SYSINO 0xa0 121 #define HVIO_INTR_GETVALID 0xa1 122 #define HVIO_INTR_SETVALID 0xa2 123 #define HVIO_INTR_GETSTATE 0xa3 124 #define HVIO_INTR_SETSTATE 0xa4 125 #define HVIO_INTR_GETTARGET 0xa5 126 #define HVIO_INTR_SETTARGET 0xa6 127 128 #ifdef SET_MMU_STATS 129 #define MMU_STAT_AREA 0xfc 130 #endif /* SET_MMU_STATS */ 131 132 #define HV_NCS_REQUEST 0x110 133 134 #define HV_RA2PA 0x200 135 #define HV_HPRIV 0x201 136 137 /* 138 * Bits for MMU functions flags argument: 139 * arg3 of MMU_MAP_ADDR 140 * arg3 of MMU_DEMAP_CTX 141 * arg2 of MMU_DEMAP_ALL 142 */ 143 #define MAP_DTLB 0x1 144 #define MAP_ITLB 0x2 145 146 147 /* 148 * Interrupt state manipulation definitions. 149 */ 150 151 #define HV_INTR_IDLE_STATE 0 152 #define HV_INTR_RECEIVED_STATE 1 153 #define HV_INTR_DELIVERED_STATE 2 154 155 #define HV_INTR_NOTVALID 0 156 #define HV_INTR_VALID 1 157 158 #ifndef _ASM 159 160 /* 161 * TSB description structure for MMU_TSB_CTX0 and MMU_TSB_CTXNON0. 162 */ 163 typedef struct hv_tsb_info { 164 uint16_t hvtsb_idxpgsz; /* page size used to index TSB */ 165 uint16_t hvtsb_assoc; /* TSB associativity */ 166 uint32_t hvtsb_ntte; /* TSB size (#TTE entries) */ 167 uint32_t hvtsb_ctx_index; /* context reg index */ 168 uint32_t hvtsb_pgszs; /* sizes in use */ 169 uint64_t hvtsb_pa; /* real address of TSB base */ 170 uint64_t hvtsb_rsvd; /* reserved */ 171 } hv_tsb_info_t; 172 173 #define HVTSB_SHARE_INDEX ((uint32_t)-1) 174 175 #ifdef SET_MMU_STATS 176 #ifndef TTE4V_NPGSZ 177 #define TTE4V_NPGSZ 8 178 #endif /* TTE4V_NPGSZ */ 179 /* 180 * MMU statistics structure for MMU_STAT_AREA 181 */ 182 struct mmu_stat_one { 183 uint64_t hit_ctx0[TTE4V_NPGSZ]; 184 uint64_t hit_ctxn0[TTE4V_NPGSZ]; 185 uint64_t tsb_miss; 186 uint64_t tlb_miss; /* miss, no TSB set */ 187 uint64_t map_ctx0[TTE4V_NPGSZ]; 188 uint64_t map_ctxn0[TTE4V_NPGSZ]; 189 }; 190 191 struct mmu_stat { 192 struct mmu_stat_one immu_stat; 193 struct mmu_stat_one dmmu_stat; 194 uint64_t set_ctx0; 195 uint64_t set_ctxn0; 196 }; 197 #endif /* SET_MMU_STATS */ 198 199 #endif /* _ASM */ 200 201 /* 202 * CPU States 203 */ 204 #define CPU_STATE_INVALID 0x0 205 #define CPU_STATE_IDLE 0x1 /* cpu not started */ 206 #define CPU_STATE_GUEST 0x2 /* cpu running guest code */ 207 #define CPU_STATE_ERROR 0x3 /* cpu is in the error state */ 208 #define CPU_STATE_LAST_PUBLIC CPU_STATE_ERROR /* last valid state */ 209 210 /* 211 * MMU fault status area 212 */ 213 214 #define MMFSA_TYPE_ 0x00 /* fault type */ 215 #define MMFSA_ADDR_ 0x08 /* fault address */ 216 #define MMFSA_CTX_ 0x10 /* fault context */ 217 218 #define MMFSA_I_ 0x00 /* start of fields for I */ 219 #define MMFSA_I_TYPE (MMFSA_I_ + MMFSA_TYPE_) /* instruction fault type */ 220 #define MMFSA_I_ADDR (MMFSA_I_ + MMFSA_ADDR_) /* instruction fault address */ 221 #define MMFSA_I_CTX (MMFSA_I_ + MMFSA_CTX_) /* instruction fault context */ 222 223 #define MMFSA_D_ 0x40 /* start of fields for D */ 224 #define MMFSA_D_TYPE (MMFSA_D_ + MMFSA_TYPE_) /* data fault type */ 225 #define MMFSA_D_ADDR (MMFSA_D_ + MMFSA_ADDR_) /* data fault address */ 226 #define MMFSA_D_CTX (MMFSA_D_ + MMFSA_CTX_) /* data fault context */ 227 228 #define MMFSA_F_FMISS 1 /* fast miss */ 229 #define MMFSA_F_FPROT 2 /* fast protection */ 230 #define MMFSA_F_MISS 3 /* mmu miss */ 231 #define MMFSA_F_INVRA 4 /* invalid RA */ 232 #define MMFSA_F_PRIV 5 /* privilege violation */ 233 #define MMFSA_F_PROT 6 /* protection violation */ 234 #define MMFSA_F_NFO 7 /* NFO access */ 235 #define MMFSA_F_SOPG 8 /* so page */ 236 #define MMFSA_F_INVVA 9 /* invalid VA */ 237 #define MMFSA_F_INVASI 10 /* invalid ASI */ 238 #define MMFSA_F_NCATM 11 /* non-cacheable atomic */ 239 #define MMFSA_F_PRVACT 12 /* privileged action */ 240 #define MMFSA_F_WPT 13 /* watchpoint hit */ 241 #define MMFSA_F_UNALIGN 14 /* unaligned access */ 242 #define MMFSA_F_INVPGSZ 15 /* invalid page size */ 243 244 #define MMFSA_SIZE 0x80 /* in bytes, 64 byte aligned */ 245 246 /* 247 * MMU fault status - MMFSA_IFS and MMFSA_DFS 248 */ 249 #define MMFS_FV 0x00000001 250 #define MMFS_OW 0x00000002 251 #define MMFS_W 0x00000004 252 #define MMFS_PR 0x00000008 253 #define MMFS_CT 0x00000030 254 #define MMFS_E 0x00000040 255 #define MMFS_FT 0x00003f80 256 #define MMFS_ME 0x00004000 257 #define MMFS_TM 0x00008000 258 #define MMFS_ASI 0x00ff0000 259 #define MMFS_NF 0x01000000 260 261 /* 262 * DMA sync parameter definitions 263 */ 264 #define HVIO_DMA_SYNC_DIR_TO_DEV 0x01 265 #define HVIO_DMA_SYNC_DIR_FROM_DEV 0x02 266 267 #ifndef _ASM 268 269 extern uint64_t hv_mmu_map_perm_addr(void *, int, uint64_t, int); 270 extern uint64_t hv_mmu_unmap_perm_addr(void *, int, int); 271 extern uint64_t hv_set_ctx0(uint64_t, uint64_t); 272 extern uint64_t hv_set_ctxnon0(uint64_t, uint64_t); 273 #ifdef SET_MMU_STATS 274 extern uint64_t hv_mmu_set_stat_area(uint64_t, uint64_t); 275 #endif /* SET_MMU_STATS */ 276 277 extern uint64_t hv_cpu_qconf(int queue, uint64_t paddr, int size); 278 extern uint64_t hv_cpu_yield(); 279 280 extern uint64_t hv_cpu_state(uint64_t cpuid, uint64_t *cpu_state); 281 extern uint64_t hv_mem_scrub(uint64_t real_addr, uint64_t length, 282 uint64_t *scrubbed_len); 283 extern uint64_t hv_mem_sync(uint64_t real_addr, uint64_t length, 284 uint64_t *flushed_len); 285 286 extern uint64_t hv_service_recv(uint64_t s_id, uint64_t buf_pa, 287 uint64_t size, uint64_t *recv_bytes); 288 extern uint64_t hv_service_send(uint64_t s_id, uint64_t buf_pa, 289 uint64_t size, uint64_t *send_bytes); 290 extern uint64_t hv_service_getstatus(uint64_t s_id, uint64_t *vreg); 291 extern uint64_t hv_service_setstatus(uint64_t s_id, uint64_t bits); 292 extern uint64_t hv_service_clrstatus(uint64_t s_id, uint64_t bits); 293 294 extern uint64_t hv_mach_desc(uint64_t buffer_ra, uint64_t *buffer_sizep); 295 296 extern uint64_t hv_ttrace_buf_info(uint64_t *, uint64_t *); 297 extern uint64_t hv_ttrace_buf_conf(uint64_t, uint64_t, uint64_t *); 298 extern uint64_t hv_ttrace_enable(uint64_t, uint64_t *); 299 extern uint64_t hv_ttrace_freeze(uint64_t, uint64_t *); 300 extern uint64_t hv_dump_buf_update(uint64_t, uint64_t, uint64_t *); 301 302 extern int64_t hv_cnputchar(uint8_t); 303 extern int64_t hv_cngetchar(uint8_t *); 304 305 extern uint64_t hv_tod_get(uint64_t *seconds); 306 extern uint64_t hv_tod_set(uint64_t); 307 308 extern uint64_t hvio_intr_devino_to_sysino(uint64_t dev_hdl, uint32_t devino, 309 uint64_t *sysino); 310 extern uint64_t hvio_intr_getvalid(uint64_t sysino, 311 int *intr_valid_state); 312 extern uint64_t hvio_intr_setvalid(uint64_t sysino, 313 int intr_valid_state); 314 extern uint64_t hvio_intr_getstate(uint64_t sysino, 315 int *intr_state); 316 extern uint64_t hvio_intr_setstate(uint64_t sysino, int intr_state); 317 extern uint64_t hvio_intr_gettarget(uint64_t sysino, uint32_t *cpuid); 318 extern uint64_t hvio_intr_settarget(uint64_t sysino, uint32_t cpuid); 319 320 #endif 321 322 #ifdef __cplusplus 323 } 324 #endif 325 326 #endif /* _SYS_HYPERVISOR_API_H */ 327