1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <sys/types.h> 27 #include <sys/systm.h> 28 #include <sys/archsystm.h> 29 #include <sys/t_lock.h> 30 #include <sys/uadmin.h> 31 #include <sys/panic.h> 32 #include <sys/reboot.h> 33 #include <sys/autoconf.h> 34 #include <sys/machsystm.h> 35 #include <sys/promif.h> 36 #include <sys/membar.h> 37 #include <vm/hat_sfmmu.h> 38 #include <sys/cpu_module.h> 39 #include <sys/cpu_sgnblk_defs.h> 40 #include <sys/intreg.h> 41 #include <sys/consdev.h> 42 #include <sys/kdi_impl.h> 43 #include <sys/traptrace.h> 44 #include <sys/hypervisor_api.h> 45 #include <sys/vmsystm.h> 46 #include <sys/dtrace.h> 47 #include <sys/xc_impl.h> 48 #include <sys/callb.h> 49 #include <sys/mdesc.h> 50 #include <sys/mach_descrip.h> 51 #include <sys/wdt.h> 52 #include <sys/soft_state.h> 53 #include <sys/promimpl.h> 54 #include <sys/hsvc.h> 55 #include <sys/ldoms.h> 56 57 /* 58 * hvdump_buf_va is a pointer to the currently-configured hvdump_buf. 59 * A value of NULL indicates that this area is not configured. 60 * hvdump_buf_sz is tunable but will be clamped to HVDUMP_SIZE_MAX. 61 */ 62 63 caddr_t hvdump_buf_va; 64 uint64_t hvdump_buf_sz = HVDUMP_SIZE_DEFAULT; 65 static uint64_t hvdump_buf_pa; 66 67 u_longlong_t panic_tick; 68 69 extern u_longlong_t gettick(); 70 static void reboot_machine(char *); 71 static void update_hvdump_buffer(void); 72 73 /* 74 * For xt_sync synchronization. 75 */ 76 extern uint64_t xc_tick_limit; 77 extern uint64_t xc_tick_jump_limit; 78 extern uint64_t xc_sync_tick_limit; 79 80 /* 81 * We keep our own copies, used for cache flushing, because we can be called 82 * before cpu_fiximpl(). 83 */ 84 static int kdi_dcache_size; 85 static int kdi_dcache_linesize; 86 static int kdi_icache_size; 87 static int kdi_icache_linesize; 88 89 /* 90 * Assembly support for generic modules in sun4v/ml/mach_xc.s 91 */ 92 extern void init_mondo_nocheck(xcfunc_t *func, uint64_t arg1, uint64_t arg2); 93 extern void kdi_flush_idcache(int, int, int, int); 94 extern uint64_t get_cpuaddr(uint64_t, uint64_t); 95 96 97 #define BOOT_CMD_MAX_LEN 256 98 #define BOOT_CMD_BASE "boot " 99 100 /* 101 * In an LDoms system we do not save the user's boot args in NVRAM 102 * as is done on legacy systems. Instead, we format and send a 103 * 'reboot-command' variable to the variable service. The contents 104 * of the variable are retrieved by OBP and used verbatim for 105 * the next boot. 106 */ 107 static void 108 store_boot_cmd(char *args, boolean_t add_boot_str) 109 { 110 static char cmd_buf[BOOT_CMD_MAX_LEN]; 111 size_t len = 1; 112 pnode_t node; 113 size_t base_len = 0; 114 size_t args_len; 115 size_t args_max; 116 117 if (add_boot_str) { 118 (void) strcpy(cmd_buf, BOOT_CMD_BASE); 119 120 base_len = strlen(BOOT_CMD_BASE); 121 len = base_len + 1; 122 } 123 124 if (args != NULL) { 125 args_len = strlen(args); 126 args_max = BOOT_CMD_MAX_LEN - len; 127 128 if (args_len > args_max) { 129 cmn_err(CE_WARN, "Reboot command too long (%ld), " 130 "truncating command arguments", len + args_len); 131 132 args_len = args_max; 133 } 134 135 len += args_len; 136 (void) strncpy(&cmd_buf[base_len], args, args_len); 137 } 138 139 node = prom_optionsnode(); 140 if ((node == OBP_NONODE) || (node == OBP_BADNODE) || 141 prom_setprop(node, "reboot-command", cmd_buf, len) == -1) 142 cmn_err(CE_WARN, "Unable to store boot command for " 143 "use on reboot"); 144 } 145 146 147 /* 148 * Machine dependent code to reboot. 149 * 150 * "bootstr", when non-null, points to a string to be used as the 151 * argument string when rebooting. 152 * 153 * "invoke_cb" is a boolean. It is set to true when mdboot() can safely 154 * invoke CB_CL_MDBOOT callbacks before shutting the system down, i.e. when 155 * we are in a normal shutdown sequence (interrupts are not blocked, the 156 * system is not panic'ing or being suspended). 157 */ 158 /*ARGSUSED*/ 159 void 160 mdboot(int cmd, int fcn, char *bootstr, boolean_t invoke_cb) 161 { 162 extern void pm_cfb_check_and_powerup(void); 163 164 /* 165 * XXX - rconsvp is set to NULL to ensure that output messages 166 * are sent to the underlying "hardware" device using the 167 * monitor's printf routine since we are in the process of 168 * either rebooting or halting the machine. 169 */ 170 rconsvp = NULL; 171 172 switch (fcn) { 173 case AD_HALT: 174 /* 175 * LDoms: By storing a no-op command 176 * in the 'reboot-command' variable we cause OBP 177 * to ignore the setting of 'auto-boot?' after 178 * it completes the reset. This causes the system 179 * to stop at the ok prompt. 180 */ 181 if (domaining_enabled() && invoke_cb) 182 store_boot_cmd("noop", B_FALSE); 183 break; 184 185 case AD_POWEROFF: 186 break; 187 188 default: 189 if (bootstr == NULL) { 190 switch (fcn) { 191 192 case AD_BOOT: 193 bootstr = ""; 194 break; 195 196 case AD_IBOOT: 197 bootstr = "-a"; 198 break; 199 200 case AD_SBOOT: 201 bootstr = "-s"; 202 break; 203 204 case AD_SIBOOT: 205 bootstr = "-sa"; 206 break; 207 default: 208 cmn_err(CE_WARN, 209 "mdboot: invalid function %d", fcn); 210 bootstr = ""; 211 break; 212 } 213 } 214 215 /* 216 * If LDoms is running, we must save the boot string 217 * before we enter restricted mode. This is possible 218 * only if we are not being called from panic. 219 */ 220 if (domaining_enabled() && invoke_cb) 221 store_boot_cmd(bootstr, B_TRUE); 222 } 223 224 /* 225 * At a high interrupt level we can't: 226 * 1) bring up the console 227 * or 228 * 2) wait for pending interrupts prior to redistribution 229 * to the current CPU 230 * 231 * so we do them now. 232 */ 233 pm_cfb_check_and_powerup(); 234 235 /* make sure there are no more changes to the device tree */ 236 devtree_freeze(); 237 238 if (invoke_cb) 239 (void) callb_execute_class(CB_CL_MDBOOT, NULL); 240 241 /* 242 * Clear any unresolved UEs from memory. 243 */ 244 page_retire_mdboot(); 245 246 /* 247 * stop other cpus which also raise our priority. since there is only 248 * one active cpu after this, and our priority will be too high 249 * for us to be preempted, we're essentially single threaded 250 * from here on out. 251 */ 252 stop_other_cpus(); 253 254 /* 255 * try and reset leaf devices. reset_leaves() should only 256 * be called when there are no other threads that could be 257 * accessing devices 258 */ 259 reset_leaves(); 260 261 watchdog_clear(); 262 263 if (fcn == AD_HALT) { 264 mach_set_soft_state(SIS_TRANSITION, 265 &SOLARIS_SOFT_STATE_HALT_MSG); 266 halt((char *)NULL); 267 } else if (fcn == AD_POWEROFF) { 268 mach_set_soft_state(SIS_TRANSITION, 269 &SOLARIS_SOFT_STATE_POWER_MSG); 270 power_down(NULL); 271 } else { 272 mach_set_soft_state(SIS_TRANSITION, 273 &SOLARIS_SOFT_STATE_REBOOT_MSG); 274 reboot_machine(bootstr); 275 } 276 /* MAYBE REACHED */ 277 } 278 279 /* mdpreboot - may be called prior to mdboot while root fs still mounted */ 280 /*ARGSUSED*/ 281 void 282 mdpreboot(int cmd, int fcn, char *bootstr) 283 { 284 } 285 286 /* 287 * Halt the machine and then reboot with the device 288 * and arguments specified in bootstr. 289 */ 290 static void 291 reboot_machine(char *bootstr) 292 { 293 flush_windows(); 294 stop_other_cpus(); /* send stop signal to other CPUs */ 295 prom_printf("rebooting...\n"); 296 /* 297 * For platforms that use CPU signatures, we 298 * need to set the signature block to OS and 299 * the state to exiting for all the processors. 300 */ 301 CPU_SIGNATURE(OS_SIG, SIGST_EXIT, SIGSUBST_REBOOT, -1); 302 prom_reboot(bootstr); 303 /*NOTREACHED*/ 304 } 305 306 /* 307 * We use the x-trap mechanism and idle_stop_xcall() to stop the other CPUs. 308 * Once in panic_idle() they raise spl, record their location, and spin. 309 */ 310 static void 311 panic_idle(void) 312 { 313 (void) spl7(); 314 315 debug_flush_windows(); 316 (void) setjmp(&curthread->t_pcb); 317 318 CPU->cpu_m.in_prom = 1; 319 membar_stld(); 320 321 for (;;) 322 ; 323 } 324 325 /* 326 * Force the other CPUs to trap into panic_idle(), and then remove them 327 * from the cpu_ready_set so they will no longer receive cross-calls. 328 */ 329 /*ARGSUSED*/ 330 void 331 panic_stopcpus(cpu_t *cp, kthread_t *t, int spl) 332 { 333 cpuset_t cps; 334 int i; 335 336 (void) splzs(); 337 CPUSET_ALL_BUT(cps, cp->cpu_id); 338 xt_some(cps, (xcfunc_t *)idle_stop_xcall, (uint64_t)&panic_idle, NULL); 339 340 for (i = 0; i < NCPU; i++) { 341 if (i != cp->cpu_id && CPU_XCALL_READY(i)) { 342 int ntries = 0x10000; 343 344 while (!cpu[i]->cpu_m.in_prom && ntries) { 345 DELAY(50); 346 ntries--; 347 } 348 349 if (!cpu[i]->cpu_m.in_prom) 350 printf("panic: failed to stop cpu%d\n", i); 351 352 cpu[i]->cpu_flags &= ~CPU_READY; 353 cpu[i]->cpu_flags |= CPU_QUIESCED; 354 CPUSET_DEL(cpu_ready_set, cpu[i]->cpu_id); 355 } 356 } 357 } 358 359 /* 360 * Platform callback following each entry to panicsys(). If we've panicked at 361 * level 14, we examine t_panic_trap to see if a fatal trap occurred. If so, 362 * we disable further %tick_cmpr interrupts. If not, an explicit call to panic 363 * was made and so we re-enqueue an interrupt request structure to allow 364 * further level 14 interrupts to be processed once we lower PIL. This allows 365 * us to handle panics from the deadman() CY_HIGH_LEVEL cyclic. 366 */ 367 void 368 panic_enter_hw(int spl) 369 { 370 if (!panic_tick) { 371 panic_tick = gettick(); 372 if (mach_htraptrace_enable) { 373 uint64_t prev_freeze; 374 375 /* there are no possible error codes for this hcall */ 376 (void) hv_ttrace_freeze((uint64_t)TRAP_TFREEZE_ALL, 377 &prev_freeze); 378 } 379 #ifdef TRAPTRACE 380 TRAPTRACE_FREEZE; 381 #endif 382 } 383 384 mach_set_soft_state(SIS_TRANSITION, &SOLARIS_SOFT_STATE_PANIC_MSG); 385 386 if (spl == ipltospl(PIL_14)) { 387 uint_t opstate = disable_vec_intr(); 388 389 if (curthread->t_panic_trap != NULL) { 390 tickcmpr_disable(); 391 intr_dequeue_req(PIL_14, cbe_level14_inum); 392 } else { 393 if (!tickcmpr_disabled()) 394 intr_enqueue_req(PIL_14, cbe_level14_inum); 395 /* 396 * Clear SOFTINT<14>, SOFTINT<0> (TICK_INT) 397 * and SOFTINT<16> (STICK_INT) to indicate 398 * that the current level 14 has been serviced. 399 */ 400 wr_clr_softint((1 << PIL_14) | 401 TICK_INT_MASK | STICK_INT_MASK); 402 } 403 404 enable_vec_intr(opstate); 405 } 406 } 407 408 /* 409 * Miscellaneous hardware-specific code to execute after panicstr is set 410 * by the panic code: we also print and record PTL1 panic information here. 411 */ 412 /*ARGSUSED*/ 413 void 414 panic_quiesce_hw(panic_data_t *pdp) 415 { 416 extern uint_t getpstate(void); 417 extern void setpstate(uint_t); 418 419 /* 420 * Turn off TRAPTRACE and save the current %tick value in panic_tick. 421 */ 422 if (!panic_tick) { 423 panic_tick = gettick(); 424 if (mach_htraptrace_enable) { 425 uint64_t prev_freeze; 426 427 /* there are no possible error codes for this hcall */ 428 (void) hv_ttrace_freeze((uint64_t)TRAP_TFREEZE_ALL, 429 &prev_freeze); 430 } 431 #ifdef TRAPTRACE 432 TRAPTRACE_FREEZE; 433 #endif 434 } 435 /* 436 * For Platforms that use CPU signatures, we 437 * need to set the signature block to OS, the state to 438 * exiting, and the substate to panic for all the processors. 439 */ 440 CPU_SIGNATURE(OS_SIG, SIGST_EXIT, SIGSUBST_PANIC, -1); 441 442 update_hvdump_buffer(); 443 444 /* 445 * Disable further ECC errors from the bus nexus. 446 */ 447 (void) bus_func_invoke(BF_TYPE_ERRDIS); 448 449 /* 450 * Redirect all interrupts to the current CPU. 451 */ 452 intr_redist_all_cpus_shutdown(); 453 454 /* 455 * This call exists solely to support dumps to network 456 * devices after sync from OBP. 457 * 458 * If we came here via the sync callback, then on some 459 * platforms, interrupts may have arrived while we were 460 * stopped in OBP. OBP will arrange for those interrupts to 461 * be redelivered if you say "go", but not if you invoke a 462 * client callback like 'sync'. For some dump devices 463 * (network swap devices), we need interrupts to be 464 * delivered in order to dump, so we have to call the bus 465 * nexus driver to reset the interrupt state machines. 466 */ 467 (void) bus_func_invoke(BF_TYPE_RESINTR); 468 469 setpstate(getpstate() | PSTATE_IE); 470 } 471 472 /* 473 * Platforms that use CPU signatures need to set the signature block to OS and 474 * the state to exiting for all CPUs. PANIC_CONT indicates that we're about to 475 * write the crash dump, which tells the SSP/SMS to begin a timeout routine to 476 * reboot the machine if the dump never completes. 477 */ 478 /*ARGSUSED*/ 479 void 480 panic_dump_hw(int spl) 481 { 482 CPU_SIGNATURE(OS_SIG, SIGST_EXIT, SIGSUBST_DUMP, -1); 483 } 484 485 /* 486 * for ptl1_panic 487 */ 488 void 489 ptl1_init_cpu(struct cpu *cpu) 490 { 491 ptl1_state_t *pstate = &cpu->cpu_m.ptl1_state; 492 493 /*CONSTCOND*/ 494 if (sizeof (struct cpu) + PTL1_SSIZE > CPU_ALLOC_SIZE) { 495 panic("ptl1_init_cpu: not enough space left for ptl1_panic " 496 "stack, sizeof (struct cpu) = %lu", 497 (unsigned long)sizeof (struct cpu)); 498 } 499 500 pstate->ptl1_stktop = (uintptr_t)cpu + CPU_ALLOC_SIZE; 501 cpu_pa[cpu->cpu_id] = va_to_pa(cpu); 502 } 503 504 void 505 ptl1_panic_handler(ptl1_state_t *pstate) 506 { 507 static const char *ptl1_reasons[] = { 508 #ifdef PTL1_PANIC_DEBUG 509 "trap for debug purpose", /* PTL1_BAD_DEBUG */ 510 #else 511 "unknown trap", /* PTL1_BAD_DEBUG */ 512 #endif 513 "register window trap", /* PTL1_BAD_WTRAP */ 514 "kernel MMU miss", /* PTL1_BAD_KMISS */ 515 "kernel protection fault", /* PTL1_BAD_KPROT_FAULT */ 516 "ISM MMU miss", /* PTL1_BAD_ISM */ 517 "kernel MMU trap", /* PTL1_BAD_MMUTRAP */ 518 "kernel trap handler state", /* PTL1_BAD_TRAP */ 519 "floating point trap", /* PTL1_BAD_FPTRAP */ 520 #ifdef DEBUG 521 "pointer to intr_vec", /* PTL1_BAD_INTR_VEC */ 522 #else 523 "unknown trap", /* PTL1_BAD_INTR_VEC */ 524 #endif 525 #ifdef TRAPTRACE 526 "TRACE_PTR state", /* PTL1_BAD_TRACE_PTR */ 527 #else 528 "unknown trap", /* PTL1_BAD_TRACE_PTR */ 529 #endif 530 "stack overflow", /* PTL1_BAD_STACK */ 531 "DTrace flags", /* PTL1_BAD_DTRACE_FLAGS */ 532 "attempt to steal locked ctx", /* PTL1_BAD_CTX_STEAL */ 533 "CPU ECC error loop", /* PTL1_BAD_ECC */ 534 "unexpected error from hypervisor call", /* PTL1_BAD_HCALL */ 535 "unexpected global level(%gl)", /* PTL1_BAD_GL */ 536 "Watchdog Reset", /* PTL1_BAD_WATCHDOG */ 537 "unexpected RED mode trap", /* PTL1_BAD_RED */ 538 "return value EINVAL from hcall: "\ 539 "UNMAP_PERM_ADDR", /* PTL1_BAD_HCALL_UNMAP_PERM_EINVAL */ 540 "return value ENOMAP from hcall: "\ 541 "UNMAP_PERM_ADDR", /* PTL1_BAD_HCALL_UNMAP_PERM_ENOMAP */ 542 "error raising a TSB exception", /* PTL1_BAD_RAISE_TSBEXCP */ 543 "missing shared TSB" /* PTL1_NO_SCDTSB8K */ 544 }; 545 546 uint_t reason = pstate->ptl1_regs.ptl1_gregs[0].ptl1_g1; 547 uint_t tl = pstate->ptl1_regs.ptl1_trap_regs[0].ptl1_tl; 548 struct panic_trap_info ti = { 0 }; 549 550 /* 551 * Use trap_info for a place holder to call panic_savetrap() and 552 * panic_showtrap() to save and print out ptl1_panic information. 553 */ 554 if (curthread->t_panic_trap == NULL) 555 curthread->t_panic_trap = &ti; 556 557 if (reason < sizeof (ptl1_reasons) / sizeof (ptl1_reasons[0])) 558 panic("bad %s at TL %u", ptl1_reasons[reason], tl); 559 else 560 panic("ptl1_panic reason 0x%x at TL %u", reason, tl); 561 } 562 563 void 564 clear_watchdog_on_exit(void) 565 { 566 if (watchdog_enabled && watchdog_activated) { 567 prom_printf("Debugging requested; hardware watchdog " 568 "suspended.\n"); 569 (void) watchdog_suspend(); 570 } 571 } 572 573 /* 574 * Restore the watchdog timer when returning from a debugger 575 * after a panic or L1-A and resume watchdog pat. 576 */ 577 void 578 restore_watchdog_on_entry() 579 { 580 watchdog_resume(); 581 } 582 583 int 584 kdi_watchdog_disable(void) 585 { 586 watchdog_suspend(); 587 588 return (0); 589 } 590 591 void 592 kdi_watchdog_restore(void) 593 { 594 watchdog_resume(); 595 } 596 597 void 598 mach_dump_buffer_init(void) 599 { 600 uint64_t ret, minsize = 0; 601 602 if (hvdump_buf_sz > HVDUMP_SIZE_MAX) 603 hvdump_buf_sz = HVDUMP_SIZE_MAX; 604 605 hvdump_buf_va = contig_mem_alloc_align(hvdump_buf_sz, PAGESIZE); 606 if (hvdump_buf_va == NULL) 607 return; 608 609 hvdump_buf_pa = va_to_pa(hvdump_buf_va); 610 611 ret = hv_dump_buf_update(hvdump_buf_pa, hvdump_buf_sz, 612 &minsize); 613 614 if (ret != H_EOK) { 615 contig_mem_free(hvdump_buf_va, hvdump_buf_sz); 616 hvdump_buf_va = NULL; 617 cmn_err(CE_NOTE, "!Error in setting up hvstate" 618 "dump buffer. Error = 0x%lx, size = 0x%lx," 619 "buf_pa = 0x%lx", ret, hvdump_buf_sz, 620 hvdump_buf_pa); 621 622 if (ret == H_EINVAL) { 623 cmn_err(CE_NOTE, "!Buffer size too small." 624 "Available buffer size = 0x%lx," 625 "Minimum buffer size required = 0x%lx", 626 hvdump_buf_sz, minsize); 627 } 628 } 629 } 630 631 632 static void 633 update_hvdump_buffer(void) 634 { 635 uint64_t ret, dummy_val; 636 637 if (hvdump_buf_va == NULL) 638 return; 639 640 ret = hv_dump_buf_update(hvdump_buf_pa, hvdump_buf_sz, 641 &dummy_val); 642 if (ret != H_EOK) { 643 cmn_err(CE_NOTE, "!Cannot update hvstate dump" 644 "buffer. Error = 0x%lx", ret); 645 } 646 } 647 648 649 static int 650 getintprop(pnode_t node, char *name, int deflt) 651 { 652 int value; 653 654 switch (prom_getproplen(node, name)) { 655 case 0: 656 value = 1; /* boolean properties */ 657 break; 658 659 case sizeof (int): 660 (void) prom_getprop(node, name, (caddr_t)&value); 661 break; 662 663 default: 664 value = deflt; 665 break; 666 } 667 668 return (value); 669 } 670 671 /* 672 * Called by setcpudelay 673 */ 674 void 675 cpu_init_tick_freq(void) 676 { 677 md_t *mdp; 678 mde_cookie_t rootnode; 679 int listsz; 680 mde_cookie_t *listp = NULL; 681 int num_nodes; 682 uint64_t stick_prop; 683 684 if (broken_md_flag) { 685 sys_tick_freq = cpunodes[CPU->cpu_id].clock_freq; 686 return; 687 } 688 689 if ((mdp = md_get_handle()) == NULL) 690 panic("stick_frequency property not found in MD"); 691 692 rootnode = md_root_node(mdp); 693 ASSERT(rootnode != MDE_INVAL_ELEM_COOKIE); 694 695 num_nodes = md_node_count(mdp); 696 697 ASSERT(num_nodes > 0); 698 listsz = num_nodes * sizeof (mde_cookie_t); 699 listp = (mde_cookie_t *)prom_alloc((caddr_t)0, listsz, 0); 700 701 if (listp == NULL) 702 panic("cannot allocate list for MD properties"); 703 704 num_nodes = md_scan_dag(mdp, rootnode, md_find_name(mdp, "platform"), 705 md_find_name(mdp, "fwd"), listp); 706 707 ASSERT(num_nodes == 1); 708 709 if (md_get_prop_val(mdp, *listp, "stick-frequency", &stick_prop) != 0) 710 panic("stick_frequency property not found in MD"); 711 712 sys_tick_freq = stick_prop; 713 714 prom_free((caddr_t)listp, listsz); 715 (void) md_fini_handle(mdp); 716 } 717 718 int shipit(int n, uint64_t cpu_list_ra); 719 720 #ifdef DEBUG 721 #define SEND_MONDO_STATS 1 722 #endif 723 724 #ifdef SEND_MONDO_STATS 725 uint32_t x_one_stimes[64]; 726 uint32_t x_one_ltimes[16]; 727 uint32_t x_set_stimes[64]; 728 uint32_t x_set_ltimes[16]; 729 uint32_t x_set_cpus[NCPU]; 730 #endif 731 732 void 733 send_one_mondo(int cpuid) 734 { 735 int retries, stat; 736 uint64_t starttick, endtick, tick, lasttick; 737 struct machcpu *mcpup = &(CPU->cpu_m); 738 739 CPU_STATS_ADDQ(CPU, sys, xcalls, 1); 740 starttick = lasttick = gettick(); 741 mcpup->cpu_list[0] = (uint16_t)cpuid; 742 stat = shipit(1, mcpup->cpu_list_ra); 743 endtick = starttick + xc_tick_limit; 744 retries = 0; 745 while (stat != H_EOK) { 746 if (stat != H_EWOULDBLOCK) { 747 if (panic_quiesce) 748 return; 749 if (stat == H_ECPUERROR) 750 cmn_err(CE_PANIC, "send_one_mondo: " 751 "cpuid: 0x%x has been marked in " 752 "error", cpuid); 753 else 754 cmn_err(CE_PANIC, "send_one_mondo: " 755 "unexpected hypervisor error 0x%x " 756 "while sending a mondo to cpuid: " 757 "0x%x", stat, cpuid); 758 } 759 tick = gettick(); 760 /* 761 * If there is a big jump between the current tick 762 * count and lasttick, we have probably hit a break 763 * point. Adjust endtick accordingly to avoid panic. 764 */ 765 if (tick > (lasttick + xc_tick_jump_limit)) 766 endtick += (tick - lasttick); 767 lasttick = tick; 768 if (tick > endtick) { 769 if (panic_quiesce) 770 return; 771 cmn_err(CE_PANIC, "send mondo timeout " 772 "(target 0x%x) [retries: 0x%x hvstat: 0x%x]", 773 cpuid, retries, stat); 774 } 775 drv_usecwait(1); 776 stat = shipit(1, mcpup->cpu_list_ra); 777 retries++; 778 } 779 #ifdef SEND_MONDO_STATS 780 { 781 uint64_t n = gettick() - starttick; 782 if (n < 8192) 783 x_one_stimes[n >> 7]++; 784 else if (n < 15*8192) 785 x_one_ltimes[n >> 13]++; 786 else 787 x_one_ltimes[0xf]++; 788 } 789 #endif 790 } 791 792 void 793 send_mondo_set(cpuset_t set) 794 { 795 uint64_t starttick, endtick, tick, lasttick; 796 uint_t largestid, smallestid; 797 int i, j; 798 int ncpuids = 0; 799 int shipped = 0; 800 int retries = 0; 801 struct machcpu *mcpup = &(CPU->cpu_m); 802 803 ASSERT(!CPUSET_ISNULL(set)); 804 CPUSET_BOUNDS(set, smallestid, largestid); 805 if (smallestid == CPUSET_NOTINSET) { 806 return; 807 } 808 809 starttick = lasttick = gettick(); 810 endtick = starttick + xc_tick_limit; 811 812 /* 813 * Assemble CPU list for HV argument. We already know 814 * smallestid and largestid are members of set. 815 */ 816 mcpup->cpu_list[ncpuids++] = (uint16_t)smallestid; 817 if (largestid != smallestid) { 818 for (i = smallestid+1; i <= largestid-1; i++) { 819 if (CPU_IN_SET(set, i)) { 820 mcpup->cpu_list[ncpuids++] = (uint16_t)i; 821 } 822 } 823 mcpup->cpu_list[ncpuids++] = (uint16_t)largestid; 824 } 825 826 do { 827 int stat; 828 829 stat = shipit(ncpuids, mcpup->cpu_list_ra); 830 if (stat == H_EOK) { 831 shipped += ncpuids; 832 break; 833 } 834 835 /* 836 * Either not all CPU mondos were sent, or an 837 * error occurred. CPUs that were sent mondos 838 * have their CPU IDs overwritten in cpu_list. 839 * Reset cpu_list so that it only holds those 840 * CPU IDs that still need to be sent. 841 */ 842 for (i = 0, j = 0; i < ncpuids; i++) { 843 if (mcpup->cpu_list[i] == HV_SEND_MONDO_ENTRYDONE) { 844 shipped++; 845 } else { 846 mcpup->cpu_list[j++] = mcpup->cpu_list[i]; 847 } 848 } 849 ncpuids = j; 850 851 /* 852 * Now handle possible errors returned 853 * from hypervisor. 854 */ 855 if (stat == H_ECPUERROR) { 856 int errorcpus; 857 858 if (!panic_quiesce) 859 cmn_err(CE_CONT, "send_mondo_set: cpuid(s) "); 860 861 /* 862 * Remove any CPUs in the error state from 863 * cpu_list. At this point cpu_list only 864 * contains the CPU IDs for mondos not 865 * succesfully sent. 866 */ 867 for (i = 0, errorcpus = 0; i < ncpuids; i++) { 868 uint64_t state = CPU_STATE_INVALID; 869 uint16_t id = mcpup->cpu_list[i]; 870 871 (void) hv_cpu_state(id, &state); 872 if (state == CPU_STATE_ERROR) { 873 if (!panic_quiesce) 874 cmn_err(CE_CONT, "0x%x ", id); 875 errorcpus++; 876 } else if (errorcpus > 0) { 877 mcpup->cpu_list[i - errorcpus] = 878 mcpup->cpu_list[i]; 879 } 880 } 881 ncpuids -= errorcpus; 882 883 if (!panic_quiesce) { 884 if (errorcpus == 0) { 885 cmn_err(CE_CONT, "<none> have been " 886 "marked in error\n"); 887 cmn_err(CE_PANIC, "send_mondo_set: " 888 "hypervisor returned " 889 "H_ECPUERROR but no CPU in " 890 "cpu_list in error state"); 891 } else { 892 cmn_err(CE_CONT, "have been marked in " 893 "error\n"); 894 cmn_err(CE_PANIC, "send_mondo_set: " 895 "CPU(s) in error state"); 896 } 897 } 898 } else if (stat != H_EWOULDBLOCK) { 899 if (panic_quiesce) 900 return; 901 /* 902 * For all other errors, panic. 903 */ 904 cmn_err(CE_CONT, "send_mondo_set: unexpected " 905 "hypervisor error 0x%x while sending a " 906 "mondo to cpuid(s):", stat); 907 for (i = 0; i < ncpuids; i++) { 908 cmn_err(CE_CONT, " 0x%x", mcpup->cpu_list[i]); 909 } 910 cmn_err(CE_CONT, "\n"); 911 cmn_err(CE_PANIC, "send_mondo_set: unexpected " 912 "hypervisor error"); 913 } 914 915 tick = gettick(); 916 /* 917 * If there is a big jump between the current tick 918 * count and lasttick, we have probably hit a break 919 * point. Adjust endtick accordingly to avoid panic. 920 */ 921 if (tick > (lasttick + xc_tick_jump_limit)) 922 endtick += (tick - lasttick); 923 lasttick = tick; 924 if (tick > endtick) { 925 if (panic_quiesce) 926 return; 927 cmn_err(CE_CONT, "send mondo timeout " 928 "[retries: 0x%x] cpuids: ", retries); 929 for (i = 0; i < ncpuids; i++) 930 cmn_err(CE_CONT, " 0x%x", mcpup->cpu_list[i]); 931 cmn_err(CE_CONT, "\n"); 932 cmn_err(CE_PANIC, "send_mondo_set: timeout"); 933 } 934 935 while (gettick() < (tick + sys_clock_mhz)) 936 ; 937 retries++; 938 } while (ncpuids > 0); 939 940 CPU_STATS_ADDQ(CPU, sys, xcalls, shipped); 941 942 #ifdef SEND_MONDO_STATS 943 { 944 uint64_t n = gettick() - starttick; 945 if (n < 8192) 946 x_set_stimes[n >> 7]++; 947 else if (n < 15*8192) 948 x_set_ltimes[n >> 13]++; 949 else 950 x_set_ltimes[0xf]++; 951 } 952 x_set_cpus[shipped]++; 953 #endif 954 } 955 956 void 957 syncfpu(void) 958 { 959 } 960 961 void 962 sticksync_slave(void) 963 {} 964 965 void 966 sticksync_master(void) 967 {} 968 969 void 970 cpu_init_cache_scrub(void) 971 { 972 mach_set_soft_state(SIS_NORMAL, &SOLARIS_SOFT_STATE_RUN_MSG); 973 } 974 975 int 976 dtrace_blksuword32_err(uintptr_t addr, uint32_t *data) 977 { 978 int ret, watched; 979 980 watched = watch_disable_addr((void *)addr, 4, S_WRITE); 981 ret = dtrace_blksuword32(addr, data, 0); 982 if (watched) 983 watch_enable_addr((void *)addr, 4, S_WRITE); 984 985 return (ret); 986 } 987 988 int 989 dtrace_blksuword32(uintptr_t addr, uint32_t *data, int tryagain) 990 { 991 if (suword32((void *)addr, *data) == -1) 992 return (tryagain ? dtrace_blksuword32_err(addr, data) : -1); 993 dtrace_flush_sec(addr); 994 995 return (0); 996 } 997 998 /*ARGSUSED*/ 999 void 1000 cpu_faulted_enter(struct cpu *cp) 1001 { 1002 } 1003 1004 /*ARGSUSED*/ 1005 void 1006 cpu_faulted_exit(struct cpu *cp) 1007 { 1008 } 1009 1010 static int 1011 kdi_cpu_ready_iter(int (*cb)(int, void *), void *arg) 1012 { 1013 int rc, i; 1014 1015 for (rc = 0, i = 0; i < NCPU; i++) { 1016 if (CPU_IN_SET(cpu_ready_set, i)) 1017 rc += cb(i, arg); 1018 } 1019 1020 return (rc); 1021 } 1022 1023 /* 1024 * Sends a cross-call to a specified processor. The caller assumes 1025 * responsibility for repetition of cross-calls, as appropriate (MARSA for 1026 * debugging). 1027 */ 1028 static int 1029 kdi_xc_one(int cpuid, void (*func)(uintptr_t, uintptr_t), uintptr_t arg1, 1030 uintptr_t arg2) 1031 { 1032 int stat; 1033 struct machcpu *mcpup; 1034 uint64_t cpuaddr_reg = 0, cpuaddr_scr = 0; 1035 1036 mcpup = &(((cpu_t *)get_cpuaddr(cpuaddr_reg, cpuaddr_scr))->cpu_m); 1037 1038 /* 1039 * if (idsr_busy()) 1040 * return (KDI_XC_RES_ERR); 1041 */ 1042 1043 init_mondo_nocheck((xcfunc_t *)func, arg1, arg2); 1044 1045 mcpup->cpu_list[0] = (uint16_t)cpuid; 1046 stat = shipit(1, mcpup->cpu_list_ra); 1047 1048 if (stat == 0) 1049 return (KDI_XC_RES_OK); 1050 else 1051 return (KDI_XC_RES_NACK); 1052 } 1053 1054 static void 1055 kdi_tickwait(clock_t nticks) 1056 { 1057 clock_t endtick = gettick() + nticks; 1058 1059 while (gettick() < endtick) 1060 ; 1061 } 1062 1063 static void 1064 kdi_cpu_init(int dcache_size, int dcache_linesize, int icache_size, 1065 int icache_linesize) 1066 { 1067 kdi_dcache_size = dcache_size; 1068 kdi_dcache_linesize = dcache_linesize; 1069 kdi_icache_size = icache_size; 1070 kdi_icache_linesize = icache_linesize; 1071 } 1072 1073 /* used directly by kdi_read/write_phys */ 1074 void 1075 kdi_flush_caches(void) 1076 { 1077 /* 1078 * May not be implemented by all sun4v architectures. 1079 * 1080 * Cannot use hsvc_version to see if the group is already 1081 * negotiated or not because, this function is called by 1082 * KMDB when it is at the console prompt which is running 1083 * at highest PIL. hsvc_version grabs an adaptive mutex and 1084 * this is a no-no at this PIL level. 1085 */ 1086 if (hsvc_kdi_mem_iflush_negotiated) { 1087 uint64_t status = hv_mem_iflush_all(); 1088 if (status != H_EOK) 1089 cmn_err(CE_PANIC, "Flushing all I$ entries failed"); 1090 } 1091 } 1092 1093 /*ARGSUSED*/ 1094 int 1095 kdi_get_stick(uint64_t *stickp) 1096 { 1097 return (-1); 1098 } 1099 1100 void 1101 cpu_kdi_init(kdi_t *kdi) 1102 { 1103 /* 1104 * Any API negotiation this early in the boot will be unsuccessful. 1105 * Therefore firmware for Sun4v platforms that have incoherent I$ are 1106 * assumed to support pre-negotiated MEM_IFLUSH APIs. Successful 1107 * invokation the MEM_IFLUSH_ALL is a test for is availability. 1108 * Set a flag if successful indicating its availabitlity. 1109 */ 1110 if (hv_mem_iflush_all() == 0) 1111 hsvc_kdi_mem_iflush_negotiated = B_TRUE; 1112 1113 kdi->kdi_flush_caches = kdi_flush_caches; 1114 kdi->mkdi_cpu_init = kdi_cpu_init; 1115 kdi->mkdi_cpu_ready_iter = kdi_cpu_ready_iter; 1116 kdi->mkdi_xc_one = kdi_xc_one; 1117 kdi->mkdi_tickwait = kdi_tickwait; 1118 kdi->mkdi_get_stick = kdi_get_stick; 1119 } 1120 1121 uint64_t soft_state_message_ra[SOLARIS_SOFT_STATE_MSG_CNT]; 1122 static uint64_t soft_state_saved_state = (uint64_t)-1; 1123 static int soft_state_initialized = 0; 1124 static uint64_t soft_state_sup_minor; /* Supported minor number */ 1125 static hsvc_info_t soft_state_hsvc = { 1126 HSVC_REV_1, NULL, HSVC_GROUP_SOFT_STATE, 1, 0, NULL }; 1127 1128 1129 static void 1130 sun4v_system_claim(void) 1131 { 1132 watchdog_suspend(); 1133 /* 1134 * For "mdb -K", set soft state to debugging 1135 */ 1136 if (soft_state_saved_state == -1) { 1137 mach_get_soft_state(&soft_state_saved_state, 1138 &SOLARIS_SOFT_STATE_SAVED_MSG); 1139 } 1140 /* 1141 * check again as the read above may or may not have worked and if 1142 * it didn't then soft state will still be -1 1143 */ 1144 if (soft_state_saved_state != -1) { 1145 mach_set_soft_state(SIS_TRANSITION, 1146 &SOLARIS_SOFT_STATE_DEBUG_MSG); 1147 } 1148 } 1149 1150 static void 1151 sun4v_system_release(void) 1152 { 1153 watchdog_resume(); 1154 /* 1155 * For "mdb -K", set soft_state state back to original state on exit 1156 */ 1157 if (soft_state_saved_state != -1) { 1158 mach_set_soft_state(soft_state_saved_state, 1159 &SOLARIS_SOFT_STATE_SAVED_MSG); 1160 soft_state_saved_state = -1; 1161 } 1162 } 1163 1164 void 1165 plat_kdi_init(kdi_t *kdi) 1166 { 1167 kdi->pkdi_system_claim = sun4v_system_claim; 1168 kdi->pkdi_system_release = sun4v_system_release; 1169 } 1170 1171 /* 1172 * Routine to return memory information associated 1173 * with a physical address and syndrome. 1174 */ 1175 /* ARGSUSED */ 1176 int 1177 cpu_get_mem_info(uint64_t synd, uint64_t afar, 1178 uint64_t *mem_sizep, uint64_t *seg_sizep, uint64_t *bank_sizep, 1179 int *segsp, int *banksp, int *mcidp) 1180 { 1181 return (ENOTSUP); 1182 } 1183 1184 /* 1185 * This routine returns the size of the kernel's FRU name buffer. 1186 */ 1187 size_t 1188 cpu_get_name_bufsize() 1189 { 1190 return (UNUM_NAMLEN); 1191 } 1192 1193 /* 1194 * This routine is a more generic interface to cpu_get_mem_unum(), 1195 * that may be used by other modules (e.g. mm). 1196 */ 1197 /* ARGSUSED */ 1198 int 1199 cpu_get_mem_name(uint64_t synd, uint64_t *afsr, uint64_t afar, 1200 char *buf, int buflen, int *lenp) 1201 { 1202 return (ENOTSUP); 1203 } 1204 1205 /* ARGSUSED */ 1206 int 1207 cpu_get_mem_sid(char *unum, char *buf, int buflen, int *lenp) 1208 { 1209 return (ENOTSUP); 1210 } 1211 1212 /* ARGSUSED */ 1213 int 1214 cpu_get_mem_addr(char *unum, char *sid, uint64_t offset, uint64_t *addrp) 1215 { 1216 return (ENOTSUP); 1217 } 1218 1219 /* 1220 * xt_sync - wait for previous x-traps to finish 1221 */ 1222 void 1223 xt_sync(cpuset_t cpuset) 1224 { 1225 union { 1226 uint8_t volatile byte[NCPU]; 1227 uint64_t volatile xword[NCPU / 8]; 1228 } cpu_sync; 1229 uint64_t starttick, endtick, tick, lasttick, traptrace_id; 1230 uint_t largestid, smallestid; 1231 int i, j; 1232 1233 kpreempt_disable(); 1234 CPUSET_DEL(cpuset, CPU->cpu_id); 1235 CPUSET_AND(cpuset, cpu_ready_set); 1236 1237 CPUSET_BOUNDS(cpuset, smallestid, largestid); 1238 if (smallestid == CPUSET_NOTINSET) 1239 goto out; 1240 1241 /* 1242 * Sun4v uses a queue for receiving mondos. Successful 1243 * transmission of a mondo only indicates that the mondo 1244 * has been written into the queue. 1245 * 1246 * We use an array of bytes to let each cpu to signal back 1247 * to the cross trap sender that the cross trap has been 1248 * executed. Set the byte to 1 before sending the cross trap 1249 * and wait until other cpus reset it to 0. 1250 */ 1251 bzero((void *)&cpu_sync, NCPU); 1252 cpu_sync.byte[smallestid] = 1; 1253 if (largestid != smallestid) { 1254 for (i = (smallestid + 1); i <= (largestid - 1); i++) 1255 if (CPU_IN_SET(cpuset, i)) 1256 cpu_sync.byte[i] = 1; 1257 cpu_sync.byte[largestid] = 1; 1258 } 1259 1260 /* 1261 * To help debug xt_sync panic, each mondo is uniquely identified 1262 * by passing the tick value, traptrace_id as the second mondo 1263 * argument to xt_some which is logged in CPU's mondo queue, 1264 * traptrace buffer and the panic message. 1265 */ 1266 traptrace_id = gettick(); 1267 xt_some(cpuset, (xcfunc_t *)xt_sync_tl1, 1268 (uint64_t)cpu_sync.byte, traptrace_id); 1269 1270 starttick = lasttick = gettick(); 1271 endtick = starttick + xc_sync_tick_limit; 1272 1273 for (i = (smallestid / 8); i <= (largestid / 8); i++) { 1274 while (cpu_sync.xword[i] != 0) { 1275 tick = gettick(); 1276 /* 1277 * If there is a big jump between the current tick 1278 * count and lasttick, we have probably hit a break 1279 * point. Adjust endtick accordingly to avoid panic. 1280 */ 1281 if (tick > (lasttick + xc_tick_jump_limit)) { 1282 endtick += (tick - lasttick); 1283 } 1284 lasttick = tick; 1285 if (tick > endtick) { 1286 if (panic_quiesce) 1287 goto out; 1288 cmn_err(CE_CONT, "Cross trap sync timeout: " 1289 "at cpu_sync.xword[%d]: 0x%lx " 1290 "cpu_sync.byte: 0x%lx " 1291 "starttick: 0x%lx endtick: 0x%lx " 1292 "traptrace_id = 0x%lx\n", 1293 i, cpu_sync.xword[i], 1294 (uint64_t)cpu_sync.byte, 1295 starttick, endtick, traptrace_id); 1296 cmn_err(CE_CONT, "CPUIDs:"); 1297 for (j = (i * 8); j <= largestid; j++) { 1298 if (cpu_sync.byte[j] != 0) 1299 cmn_err(CE_CONT, " 0x%x", j); 1300 } 1301 cmn_err(CE_PANIC, "xt_sync: timeout"); 1302 } 1303 } 1304 } 1305 1306 out: 1307 kpreempt_enable(); 1308 } 1309 1310 #define QFACTOR 200 1311 /* 1312 * Recalculate the values of the cross-call timeout variables based 1313 * on the value of the 'inter-cpu-latency' property of the platform node. 1314 * The property sets the number of nanosec to wait for a cross-call 1315 * to be acknowledged. Other timeout variables are derived from it. 1316 * 1317 * N.B. This implementation is aware of the internals of xc_init() 1318 * and updates many of the same variables. 1319 */ 1320 void 1321 recalc_xc_timeouts(void) 1322 { 1323 typedef union { 1324 uint64_t whole; 1325 struct { 1326 uint_t high; 1327 uint_t low; 1328 } half; 1329 } u_number; 1330 1331 /* See x_call.c for descriptions of these extern variables. */ 1332 extern uint64_t xc_tick_limit_scale; 1333 extern uint64_t xc_mondo_time_limit; 1334 extern uint64_t xc_func_time_limit; 1335 extern uint64_t xc_scale; 1336 extern uint64_t xc_mondo_multiplier; 1337 extern uint_t nsec_shift; 1338 1339 /* Temp versions of the target variables */ 1340 uint64_t tick_limit; 1341 uint64_t tick_jump_limit; 1342 uint64_t mondo_time_limit; 1343 uint64_t func_time_limit; 1344 uint64_t scale; 1345 1346 uint64_t latency; /* nanoseconds */ 1347 uint64_t maxfreq; 1348 uint64_t tick_limit_save = xc_tick_limit; 1349 uint64_t sync_tick_limit_save = xc_sync_tick_limit; 1350 uint_t tick_scale; 1351 uint64_t top; 1352 uint64_t bottom; 1353 u_number tk; 1354 1355 md_t *mdp; 1356 int nrnode; 1357 mde_cookie_t *platlist; 1358 1359 /* 1360 * Look up the 'inter-cpu-latency' (optional) property in the 1361 * platform node of the MD. The units are nanoseconds. 1362 */ 1363 if ((mdp = md_get_handle()) == NULL) { 1364 cmn_err(CE_WARN, "recalc_xc_timeouts: " 1365 "Unable to initialize machine description"); 1366 return; 1367 } 1368 1369 nrnode = md_alloc_scan_dag(mdp, 1370 md_root_node(mdp), "platform", "fwd", &platlist); 1371 1372 ASSERT(nrnode == 1); 1373 if (nrnode < 1) { 1374 cmn_err(CE_WARN, "recalc_xc_timeouts: platform node missing"); 1375 goto done; 1376 } 1377 if (md_get_prop_val(mdp, platlist[0], 1378 "inter-cpu-latency", &latency) == -1) 1379 goto done; 1380 1381 /* 1382 * clock.h defines an assembly-language macro 1383 * (NATIVE_TIME_TO_NSEC_SCALE) to convert from %stick 1384 * units to nanoseconds. Since the inter-cpu-latency 1385 * units are nanoseconds and the xc_* variables require 1386 * %stick units, we need the inverse of that function. 1387 * The trick is to perform the calculation without 1388 * floating point, but also without integer truncation 1389 * or overflow. To understand the calculation below, 1390 * please read the discussion of the macro in clock.h. 1391 * Since this new code will be invoked infrequently, 1392 * we can afford to implement it in C. 1393 * 1394 * tick_scale is the reciprocal of nsec_scale which is 1395 * calculated at startup in setcpudelay(). The calc 1396 * of tick_limit parallels that of NATIVE_TIME_TO_NSEC_SCALE 1397 * except we use tick_scale instead of nsec_scale and 1398 * C instead of assembler. 1399 */ 1400 tick_scale = (uint_t)(((u_longlong_t)sys_tick_freq 1401 << (32 - nsec_shift)) / NANOSEC); 1402 1403 tk.whole = latency; 1404 top = ((uint64_t)tk.half.high << 4) * tick_scale; 1405 bottom = (((uint64_t)tk.half.low << 4) * (uint64_t)tick_scale) >> 32; 1406 tick_limit = top + bottom; 1407 1408 /* 1409 * xc_init() calculated 'maxfreq' by looking at all the cpus, 1410 * and used it to derive some of the timeout variables that we 1411 * recalculate below. We can back into the original value by 1412 * using the inverse of one of those calculations. 1413 */ 1414 maxfreq = xc_mondo_time_limit / xc_scale; 1415 1416 /* 1417 * Don't allow the new timeout (xc_tick_limit) to fall below 1418 * the system tick frequency (stick). Allowing the timeout 1419 * to be set more tightly than this empirically determined 1420 * value may cause panics. 1421 */ 1422 tick_limit = tick_limit < sys_tick_freq ? sys_tick_freq : tick_limit; 1423 1424 tick_jump_limit = tick_limit / 32; 1425 tick_limit *= xc_tick_limit_scale; 1426 1427 /* 1428 * Recalculate xc_scale since it is used in a callback function 1429 * (xc_func_timeout_adj) to adjust two of the timeouts dynamically. 1430 * Make the change in xc_scale proportional to the change in 1431 * xc_tick_limit. 1432 */ 1433 scale = (xc_scale * tick_limit + sys_tick_freq / 2) / tick_limit_save; 1434 if (scale == 0) 1435 scale = 1; 1436 1437 mondo_time_limit = maxfreq * scale; 1438 func_time_limit = mondo_time_limit * xc_mondo_multiplier; 1439 1440 /* 1441 * Don't modify the timeouts if nothing has changed. Else, 1442 * stuff the variables with the freshly calculated (temp) 1443 * variables. This minimizes the window where the set of 1444 * values could be inconsistent. 1445 */ 1446 if (tick_limit != xc_tick_limit) { 1447 xc_tick_limit = tick_limit; 1448 xc_tick_jump_limit = tick_jump_limit; 1449 xc_scale = scale; 1450 xc_mondo_time_limit = mondo_time_limit; 1451 xc_func_time_limit = func_time_limit; 1452 } 1453 1454 done: 1455 /* 1456 * Increase the timeout limit for xt_sync() cross calls. 1457 */ 1458 xc_sync_tick_limit = xc_tick_limit * (cpu_q_entries / QFACTOR); 1459 xc_sync_tick_limit = xc_sync_tick_limit < xc_tick_limit ? 1460 xc_tick_limit : xc_sync_tick_limit; 1461 1462 /* 1463 * Force the new values to be used for future cross calls. 1464 * This is necessary only when we increase the timeouts. 1465 */ 1466 if ((xc_tick_limit > tick_limit_save) || (xc_sync_tick_limit > 1467 sync_tick_limit_save)) { 1468 cpuset_t cpuset = cpu_ready_set; 1469 xt_sync(cpuset); 1470 } 1471 1472 if (nrnode > 0) 1473 md_free_scan_dag(mdp, &platlist); 1474 (void) md_fini_handle(mdp); 1475 } 1476 1477 void 1478 mach_soft_state_init(void) 1479 { 1480 int i; 1481 uint64_t ra; 1482 1483 /* 1484 * Try to register soft_state api. If it fails, soft_state api has not 1485 * been implemented in the firmware, so do not bother to setup 1486 * soft_state in the kernel. 1487 */ 1488 if ((i = hsvc_register(&soft_state_hsvc, &soft_state_sup_minor)) != 0) { 1489 return; 1490 } 1491 for (i = 0; i < SOLARIS_SOFT_STATE_MSG_CNT; i++) { 1492 ASSERT(strlen((const char *)(void *) 1493 soft_state_message_strings + i) < SSM_SIZE); 1494 if ((ra = va_to_pa( 1495 (void *)(soft_state_message_strings + i))) == -1ll) { 1496 return; 1497 } 1498 soft_state_message_ra[i] = ra; 1499 } 1500 /* 1501 * Tell OBP that we are supporting Guest State 1502 */ 1503 prom_sun4v_soft_state_supported(); 1504 soft_state_initialized = 1; 1505 } 1506 1507 void 1508 mach_set_soft_state(uint64_t state, uint64_t *string_ra) 1509 { 1510 uint64_t rc; 1511 1512 if (soft_state_initialized && *string_ra) { 1513 rc = hv_soft_state_set(state, *string_ra); 1514 if (rc != H_EOK) { 1515 cmn_err(CE_WARN, 1516 "hv_soft_state_set returned %ld\n", rc); 1517 } 1518 } 1519 } 1520 1521 void 1522 mach_get_soft_state(uint64_t *state, uint64_t *string_ra) 1523 { 1524 uint64_t rc; 1525 1526 if (soft_state_initialized && *string_ra) { 1527 rc = hv_soft_state_get(*string_ra, state); 1528 if (rc != H_EOK) { 1529 cmn_err(CE_WARN, 1530 "hv_soft_state_get returned %ld\n", rc); 1531 *state = -1; 1532 } 1533 } 1534 } 1535