1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/machsystm.h> 30 #include <sys/cmp.h> 31 #include <sys/cmt.h> 32 33 /* 34 * Note: For now assume the chip ID as 0 for all the cpus until additional 35 * information is available via machine description table 36 */ 37 38 /* 39 * Returns 1 if cpuid is CMP-capable, 0 otherwise. 40 */ 41 /*ARGSUSED*/ 42 int 43 cmp_cpu_is_cmp(processorid_t cpuid) 44 { 45 return (0); 46 } 47 48 /* 49 * Indicate that this core (cpuid) resides on the chip indicated by chipid. 50 * Called during boot and DR add. 51 */ 52 /*ARGSUSED*/ 53 void 54 cmp_add_cpu(chipid_t chipid, processorid_t cpuid) 55 { 56 } 57 58 /* 59 * Indicate that this core (cpuid) is being DR removed. 60 */ 61 /*ARGSUSED*/ 62 void 63 cmp_delete_cpu(processorid_t cpuid) 64 { 65 } 66 67 /* 68 * Called when cpuid is being onlined or offlined. If the offlined 69 * processor is CMP-capable then current target of the CMP Error Steering 70 * Register is set to either the lowest numbered on-line sibling core, if 71 * one exists, or else to this core. 72 */ 73 /*ARGSUSED*/ 74 void 75 cmp_error_resteer(processorid_t cpuid) 76 { 77 } 78 79 /* 80 * Return 0, shortterm workaround until MD table is updated 81 * to provide cpu-chip mapping 82 */ 83 84 /*ARGSUSED*/ 85 chipid_t 86 cmp_cpu_to_chip(processorid_t cpuid) 87 { 88 return (cpu[cpuid]->cpu_m.cpu_chip); 89 } 90 91 /*ARGSUSED*/ 92 int 93 pg_plat_hw_shared(cpu_t *cp, pghw_type_t hw) 94 { 95 switch (hw) { 96 case PGHW_IPIPE: 97 return (1); 98 case PGHW_FPU: 99 return (1); 100 case PGHW_MPIPE: 101 return (1); 102 } 103 return (0); 104 } 105 106 int 107 pg_plat_cpus_share(cpu_t *cpu_a, cpu_t *cpu_b, pghw_type_t hw) 108 { 109 if (pg_plat_hw_shared(cpu_a, hw) == 0 || 110 pg_plat_hw_shared(cpu_b, hw) == 0) 111 return (0); 112 113 return (pg_plat_hw_instance_id(cpu_a, hw) == 114 pg_plat_hw_instance_id(cpu_b, hw)); 115 } 116 117 id_t 118 pg_plat_hw_instance_id(cpu_t *cpu, pghw_type_t hw) 119 { 120 switch (hw) { 121 case PGHW_IPIPE: 122 return (cpu->cpu_m.cpu_ipipe); 123 case PGHW_CHIP: 124 return (cpu->cpu_m.cpu_chip); 125 case PGHW_MPIPE: 126 return (cpu->cpu_m.cpu_mpipe); 127 case PGHW_FPU: 128 return (cpu->cpu_m.cpu_fpu); 129 default: 130 return (-1); 131 } 132 } 133 134 /* 135 * Order the relevant hw sharing relationships 136 * from least, to greatest physical scope. 137 * 138 * The hierarchy *must* be defined for all hw that 139 * pg_plat_hw_shared() returns non-zero. 140 */ 141 int 142 pg_plat_hw_level(pghw_type_t hw) 143 { 144 int i; 145 static pghw_type_t hw_hier[] = { 146 PGHW_IPIPE, 147 PGHW_FPU, 148 PGHW_MPIPE, 149 PGHW_NUM_COMPONENTS 150 }; 151 152 for (i = 0; hw_hier[i] != PGHW_NUM_COMPONENTS; i++) { 153 if (hw_hier[i] == hw) 154 return (i); 155 } 156 return (-1); 157 } 158 159 /* 160 * Return 1 if CMT load balancing policies should be 161 * implemented across instances of the specified hardware 162 * sharing relationship. 163 */ 164 int 165 pg_plat_cmt_load_bal_hw(pghw_type_t hw) 166 { 167 if (hw == PGHW_IPIPE || 168 hw == PGHW_FPU || 169 hw == PGHW_MPIPE) 170 return (1); 171 else 172 return (0); 173 } 174 175 176 /* 177 * Return 1 if thread affinity polices should be implemented 178 * for instances of the specifed hardware sharing relationship. 179 */ 180 int 181 pg_plat_cmt_affinity_hw(pghw_type_t hw) 182 { 183 if (hw == PGHW_CACHE) 184 return (1); 185 else 186 return (0); 187 } 188 189 id_t 190 pg_plat_get_core_id(cpu_t *cpu) 191 { 192 return (cpu->cpu_m.cpu_core); 193 } 194 195 void 196 cmp_set_nosteal_interval(void) 197 { 198 nosteal_nsec = 0; 199 } 200 /* 201 * Return 1 if CMT load balancing policies should be 202 * implemented across instances of the specified hardware 203 * sharing relationship. 204 */ 205 int 206 pg_cmt_load_bal_hw(pghw_type_t hw) 207 { 208 if (hw == PGHW_IPIPE || 209 hw == PGHW_FPU || 210 hw == PGHW_MPIPE) 211 return (1); 212 else 213 return (0); 214 } 215 /* 216 * Return 1 if thread affinity polices should be implemented 217 * for instances of the specifed hardware sharing relationship. 218 */ 219 int 220 pg_cmt_affinity_hw(pghw_type_t hw) 221 { 222 if (hw == PGHW_CACHE) 223 return (1); 224 else 225 return (0); 226 } 227