1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. 24 */ 25 26/* 27 * Hypervisor calls 28 */ 29 30#include <sys/asm_linkage.h> 31#include <sys/machasi.h> 32#include <sys/machparam.h> 33#include <sys/hypervisor_api.h> 34 35 /* 36 * int hv_mach_exit(uint64_t exit_code) 37 */ 38 ENTRY(hv_mach_exit) 39 mov HV_MACH_EXIT, %o5 40 ta FAST_TRAP 41 retl 42 nop 43 SET_SIZE(hv_mach_exit) 44 45 /* 46 * uint64_t hv_mach_sir(void) 47 */ 48 ENTRY(hv_mach_sir) 49 mov HV_MACH_SIR, %o5 50 ta FAST_TRAP 51 retl 52 nop 53 SET_SIZE(hv_mach_sir) 54 55 /* 56 * hv_cpu_start(uint64_t cpuid, uint64_t pc, ui64_t rtba, 57 * uint64_t arg) 58 */ 59 ENTRY(hv_cpu_start) 60 mov HV_CPU_START, %o5 61 ta FAST_TRAP 62 retl 63 nop 64 SET_SIZE(hv_cpu_start) 65 66 /* 67 * hv_cpu_stop(uint64_t cpuid) 68 */ 69 ENTRY(hv_cpu_stop) 70 mov HV_CPU_STOP, %o5 71 ta FAST_TRAP 72 retl 73 nop 74 SET_SIZE(hv_cpu_stop) 75 76 /* 77 * hv_cpu_set_rtba(uint64_t *rtba) 78 */ 79 ENTRY(hv_cpu_set_rtba) 80 mov %o0, %o2 81 ldx [%o2], %o0 82 mov HV_CPU_SET_RTBA, %o5 83 ta FAST_TRAP 84 stx %o1, [%o2] 85 retl 86 nop 87 SET_SIZE(hv_cpu_set_rtba) 88 89 /* 90 * int64_t hv_cnputchar(uint8_t ch) 91 */ 92 ENTRY(hv_cnputchar) 93 mov CONS_PUTCHAR, %o5 94 ta FAST_TRAP 95 retl 96 nop 97 SET_SIZE(hv_cnputchar) 98 99 /* 100 * int64_t hv_cngetchar(uint8_t *ch) 101 */ 102 ENTRY(hv_cngetchar) 103 mov %o0, %o2 104 mov CONS_GETCHAR, %o5 105 ta FAST_TRAP 106 brnz,a %o0, 1f ! failure, just return error 107 nop 108 109 cmp %o1, H_BREAK 110 be 1f 111 mov %o1, %o0 112 113 cmp %o1, H_HUP 114 be 1f 115 mov %o1, %o0 116 117 stb %o1, [%o2] ! success, save character and return 0 118 mov 0, %o0 1191: 120 retl 121 nop 122 SET_SIZE(hv_cngetchar) 123 124 ENTRY(hv_tod_get) 125 mov %o0, %o4 126 mov TOD_GET, %o5 127 ta FAST_TRAP 128 retl 129 stx %o1, [%o4] 130 SET_SIZE(hv_tod_get) 131 132 ENTRY(hv_tod_set) 133 mov TOD_SET, %o5 134 ta FAST_TRAP 135 retl 136 nop 137 SET_SIZE(hv_tod_set) 138 139 /* 140 * Map permanent address 141 * arg0 vaddr (%o0) 142 * arg1 context (%o1) 143 * arg2 tte (%o2) 144 * arg3 flags (%o3) 0x1=d 0x2=i 145 */ 146 ENTRY(hv_mmu_map_perm_addr) 147 mov MAP_PERM_ADDR, %o5 148 ta FAST_TRAP 149 retl 150 nop 151 SET_SIZE(hv_mmu_map_perm_addr) 152 153 /* 154 * hv_mmu_fault_area_conf(void *raddr) 155 */ 156 ENTRY(hv_mmu_fault_area_conf) 157 mov %o0, %o2 158 ldx [%o2], %o0 159 mov MMU_SET_INFOPTR, %o5 160 ta FAST_TRAP 161 stx %o1, [%o2] 162 retl 163 nop 164 SET_SIZE(hv_mmu_fault_area_conf) 165 166 /* 167 * Unmap permanent address 168 * arg0 vaddr (%o0) 169 * arg1 context (%o1) 170 * arg2 flags (%o2) 0x1=d 0x2=i 171 */ 172 ENTRY(hv_mmu_unmap_perm_addr) 173 mov UNMAP_PERM_ADDR, %o5 174 ta FAST_TRAP 175 retl 176 nop 177 SET_SIZE(hv_mmu_unmap_perm_addr) 178 179 /* 180 * Set TSB for context 0 181 * arg0 ntsb_descriptor (%o0) 182 * arg1 desc_ra (%o1) 183 */ 184 ENTRY(hv_set_ctx0) 185 mov MMU_TSB_CTX0, %o5 186 ta FAST_TRAP 187 retl 188 nop 189 SET_SIZE(hv_set_ctx0) 190 191 /* 192 * Set TSB for context non0 193 * arg0 ntsb_descriptor (%o0) 194 * arg1 desc_ra (%o1) 195 */ 196 ENTRY(hv_set_ctxnon0) 197 mov MMU_TSB_CTXNON0, %o5 198 ta FAST_TRAP 199 retl 200 nop 201 SET_SIZE(hv_set_ctxnon0) 202 203#ifdef SET_MMU_STATS 204 /* 205 * Returns old stat area on success 206 */ 207 ENTRY(hv_mmu_set_stat_area) 208 mov MMU_STAT_AREA, %o5 209 ta FAST_TRAP 210 retl 211 nop 212 SET_SIZE(hv_mmu_set_stat_area) 213#endif /* SET_MMU_STATS */ 214 215 /* 216 * CPU Q Configure 217 * arg0 queue (%o0) 218 * arg1 Base address RA (%o1) 219 * arg2 Size (%o2) 220 */ 221 ENTRY(hv_cpu_qconf) 222 mov HV_CPU_QCONF, %o5 223 ta FAST_TRAP 224 retl 225 nop 226 SET_SIZE(hv_cpu_qconf) 227 228 /* 229 * arg0 - devhandle 230 * arg1 - devino 231 * 232 * ret0 - status 233 * ret1 - sysino 234 */ 235 ENTRY(hvio_intr_devino_to_sysino) 236 mov HVIO_INTR_DEVINO2SYSINO, %o5 237 ta FAST_TRAP 238 brz,a %o0, 1f 239 stx %o1, [%o2] 2401: retl 241 nop 242 SET_SIZE(hvio_intr_devino_to_sysino) 243 244 /* 245 * arg0 - sysino 246 * 247 * ret0 - status 248 * ret1 - intr_valid_state 249 */ 250 ENTRY(hvio_intr_getvalid) 251 mov %o1, %o2 252 mov HVIO_INTR_GETVALID, %o5 253 ta FAST_TRAP 254 brz,a %o0, 1f 255 stuw %o1, [%o2] 2561: retl 257 nop 258 SET_SIZE(hvio_intr_getvalid) 259 260 /* 261 * arg0 - sysino 262 * arg1 - intr_valid_state 263 * 264 * ret0 - status 265 */ 266 ENTRY(hvio_intr_setvalid) 267 mov HVIO_INTR_SETVALID, %o5 268 ta FAST_TRAP 269 retl 270 nop 271 SET_SIZE(hvio_intr_setvalid) 272 273 /* 274 * arg0 - sysino 275 * 276 * ret0 - status 277 * ret1 - intr_state 278 */ 279 ENTRY(hvio_intr_getstate) 280 mov %o1, %o2 281 mov HVIO_INTR_GETSTATE, %o5 282 ta FAST_TRAP 283 brz,a %o0, 1f 284 stuw %o1, [%o2] 2851: retl 286 nop 287 SET_SIZE(hvio_intr_getstate) 288 289 /* 290 * arg0 - sysino 291 * arg1 - intr_state 292 * 293 * ret0 - status 294 */ 295 ENTRY(hvio_intr_setstate) 296 mov HVIO_INTR_SETSTATE, %o5 297 ta FAST_TRAP 298 retl 299 nop 300 SET_SIZE(hvio_intr_setstate) 301 302 /* 303 * arg0 - sysino 304 * 305 * ret0 - status 306 * ret1 - cpu_id 307 */ 308 ENTRY(hvio_intr_gettarget) 309 mov %o1, %o2 310 mov HVIO_INTR_GETTARGET, %o5 311 ta FAST_TRAP 312 brz,a %o0, 1f 313 stuw %o1, [%o2] 3141: retl 315 nop 316 SET_SIZE(hvio_intr_gettarget) 317 318 /* 319 * arg0 - sysino 320 * arg1 - cpu_id 321 * 322 * ret0 - status 323 */ 324 ENTRY(hvio_intr_settarget) 325 mov HVIO_INTR_SETTARGET, %o5 326 ta FAST_TRAP 327 retl 328 nop 329 SET_SIZE(hvio_intr_settarget) 330 331 /* 332 * hv_cpu_yield(void) 333 */ 334 ENTRY(hv_cpu_yield) 335 mov HV_CPU_YIELD, %o5 336 ta FAST_TRAP 337 retl 338 nop 339 SET_SIZE(hv_cpu_yield) 340 341 /* 342 * int hv_cpu_state(uint64_t cpuid, uint64_t *cpu_state); 343 */ 344 ENTRY(hv_cpu_state) 345 mov %o1, %o4 ! save datap 346 mov HV_CPU_STATE, %o5 347 ta FAST_TRAP 348 brz,a %o0, 1f 349 stx %o1, [%o4] 3501: 351 retl 352 nop 353 SET_SIZE(hv_cpu_state) 354 355 /* 356 * HV state dump zone Configure 357 * arg0 real adrs of dump buffer (%o0) 358 * arg1 size of dump buffer (%o1) 359 * ret0 status (%o0) 360 * ret1 size of buffer on success and min size on EINVAL (%o1) 361 * hv_dump_buf_update(uint64_t paddr, uint64_t size, uint64_t *ret_size) 362 */ 363 ENTRY(hv_dump_buf_update) 364 mov DUMP_BUF_UPDATE, %o5 365 ta FAST_TRAP 366 retl 367 stx %o1, [%o2] 368 SET_SIZE(hv_dump_buf_update) 369 370 /* 371 * arg0 - timeout value (%o0) 372 * 373 * ret0 - status (%o0) 374 * ret1 - time_remaining (%o1) 375 * hv_mach_set_watchdog(uint64_t timeout, uint64_t *time_remaining) 376 */ 377 ENTRY(hv_mach_set_watchdog) 378 mov %o1, %o2 379 mov MACH_SET_WATCHDOG, %o5 380 ta FAST_TRAP 381 retl 382 stx %o1, [%o2] 383 SET_SIZE(hv_mach_set_watchdog) 384 385 /* 386 * For memory scrub 387 * int hv_mem_scrub(uint64_t real_addr, uint64_t length, 388 * uint64_t *scrubbed_len); 389 * Retun %o0 -- status 390 * %o1 -- bytes scrubbed 391 */ 392 ENTRY(hv_mem_scrub) 393 mov %o2, %o4 394 mov HV_MEM_SCRUB, %o5 395 ta FAST_TRAP 396 retl 397 stx %o1, [%o4] 398 SET_SIZE(hv_mem_scrub) 399 400 /* 401 * Flush ecache 402 * int hv_mem_sync(uint64_t real_addr, uint64_t length, 403 * uint64_t *flushed_len); 404 * Retun %o0 -- status 405 * %o1 -- bytes flushed 406 */ 407 ENTRY(hv_mem_sync) 408 mov %o2, %o4 409 mov HV_MEM_SYNC, %o5 410 ta FAST_TRAP 411 retl 412 stx %o1, [%o4] 413 SET_SIZE(hv_mem_sync) 414 415 /* 416 * uint64_t hv_tm_enable(uint64_t enable) 417 */ 418 ENTRY(hv_tm_enable) 419 mov HV_TM_ENABLE, %o5 420 ta FAST_TRAP 421 retl 422 nop 423 SET_SIZE(hv_tm_enable) 424 425 /* 426 * TTRACE_BUF_CONF Configure 427 * arg0 RA base of buffer (%o0) 428 * arg1 buf size in no. of entries (%o1) 429 * ret0 status (%o0) 430 * ret1 minimum size in no. of entries on failure, 431 * actual size in no. of entries on success (%o1) 432 */ 433 ENTRY(hv_ttrace_buf_conf) 434 mov TTRACE_BUF_CONF, %o5 435 ta FAST_TRAP 436 retl 437 stx %o1, [%o2] 438 SET_SIZE(hv_ttrace_buf_conf) 439 440 /* 441 * TTRACE_BUF_INFO 442 * ret0 status (%o0) 443 * ret1 RA base of buffer (%o1) 444 * ret2 size in no. of entries (%o2) 445 */ 446 ENTRY(hv_ttrace_buf_info) 447 mov %o0, %o3 448 mov %o1, %o4 449 mov TTRACE_BUF_INFO, %o5 450 ta FAST_TRAP 451 stx %o1, [%o3] 452 retl 453 stx %o2, [%o4] 454 SET_SIZE(hv_ttrace_buf_info) 455 456 /* 457 * TTRACE_ENABLE 458 * arg0 enable/ disable (%o0) 459 * ret0 status (%o0) 460 * ret1 previous enable state (%o1) 461 */ 462 ENTRY(hv_ttrace_enable) 463 mov %o1, %o2 464 mov TTRACE_ENABLE, %o5 465 ta FAST_TRAP 466 retl 467 stx %o1, [%o2] 468 SET_SIZE(hv_ttrace_enable) 469 470 /* 471 * TTRACE_FREEZE 472 * arg0 enable/ freeze (%o0) 473 * ret0 status (%o0) 474 * ret1 previous freeze state (%o1) 475 */ 476 ENTRY(hv_ttrace_freeze) 477 mov %o1, %o2 478 mov TTRACE_FREEZE, %o5 479 ta FAST_TRAP 480 retl 481 stx %o1, [%o2] 482 SET_SIZE(hv_ttrace_freeze) 483 484 /* 485 * MACH_DESC 486 * arg0 buffer real address 487 * arg1 pointer to uint64_t for size of buffer 488 * ret0 status 489 * ret1 return required size of buffer / returned data size 490 */ 491 ENTRY(hv_mach_desc) 492 mov %o1, %o4 ! save datap 493 ldx [%o1], %o1 494 mov HV_MACH_DESC, %o5 495 ta FAST_TRAP 496 retl 497 stx %o1, [%o4] 498 SET_SIZE(hv_mach_desc) 499 500 /* 501 * hv_ra2pa(uint64_t ra) 502 * 503 * MACH_DESC 504 * arg0 Real address to convert 505 * ret0 Returned physical address or -1 on error 506 */ 507 ENTRY(hv_ra2pa) 508 mov HV_RA2PA, %o5 509 ta FAST_TRAP 510 cmp %o0, 0 511 move %xcc, %o1, %o0 512 movne %xcc, -1, %o0 513 retl 514 nop 515 SET_SIZE(hv_ra2pa) 516 517 /* 518 * hv_hpriv(void *func, uint64_t arg1, uint64_t arg2, uint64_t arg3) 519 * 520 * MACH_DESC 521 * arg0 OS function to call 522 * arg1 First arg to OS function 523 * arg2 Second arg to OS function 524 * arg3 Third arg to OS function 525 * ret0 Returned value from function 526 */ 527 528 ENTRY(hv_hpriv) 529 mov HV_HPRIV, %o5 530 ta FAST_TRAP 531 retl 532 nop 533 SET_SIZE(hv_hpriv) 534 535 /* 536 * hv_ldc_tx_qconf(uint64_t channel, uint64_t ra_base, 537 * uint64_t nentries); 538 */ 539 ENTRY(hv_ldc_tx_qconf) 540 mov LDC_TX_QCONF, %o5 541 ta FAST_TRAP 542 retl 543 nop 544 SET_SIZE(hv_ldc_tx_qconf) 545 546 547 /* 548 * hv_ldc_tx_qinfo(uint64_t channel, uint64_t *ra_base, 549 * uint64_t *nentries); 550 */ 551 ENTRY(hv_ldc_tx_qinfo) 552 mov %o1, %g1 553 mov %o2, %g2 554 mov LDC_TX_QINFO, %o5 555 ta FAST_TRAP 556 stx %o1, [%g1] 557 retl 558 stx %o2, [%g2] 559 SET_SIZE(hv_ldc_tx_qinfo) 560 561 562 /* 563 * hv_ldc_tx_get_state(uint64_t channel, 564 * uint64_t *headp, uint64_t *tailp, uint64_t *state); 565 */ 566 ENTRY(hv_ldc_tx_get_state) 567 mov LDC_TX_GET_STATE, %o5 568 mov %o1, %g1 569 mov %o2, %g2 570 mov %o3, %g3 571 ta FAST_TRAP 572 stx %o1, [%g1] 573 stx %o2, [%g2] 574 retl 575 stx %o3, [%g3] 576 SET_SIZE(hv_ldc_tx_get_state) 577 578 579 /* 580 * hv_ldc_tx_set_qtail(uint64_t channel, uint64_t tail) 581 */ 582 ENTRY(hv_ldc_tx_set_qtail) 583 mov LDC_TX_SET_QTAIL, %o5 584 ta FAST_TRAP 585 retl 586 SET_SIZE(hv_ldc_tx_set_qtail) 587 588 589 /* 590 * hv_ldc_rx_qconf(uint64_t channel, uint64_t ra_base, 591 * uint64_t nentries); 592 */ 593 ENTRY(hv_ldc_rx_qconf) 594 mov LDC_RX_QCONF, %o5 595 ta FAST_TRAP 596 retl 597 nop 598 SET_SIZE(hv_ldc_rx_qconf) 599 600 601 /* 602 * hv_ldc_rx_qinfo(uint64_t channel, uint64_t *ra_base, 603 * uint64_t *nentries); 604 */ 605 ENTRY(hv_ldc_rx_qinfo) 606 mov %o1, %g1 607 mov %o2, %g2 608 mov LDC_RX_QINFO, %o5 609 ta FAST_TRAP 610 stx %o1, [%g1] 611 retl 612 stx %o2, [%g2] 613 SET_SIZE(hv_ldc_rx_qinfo) 614 615 616 /* 617 * hv_ldc_rx_get_state(uint64_t channel, 618 * uint64_t *headp, uint64_t *tailp, uint64_t *state); 619 */ 620 ENTRY(hv_ldc_rx_get_state) 621 mov LDC_RX_GET_STATE, %o5 622 mov %o1, %g1 623 mov %o2, %g2 624 mov %o3, %g3 625 ta FAST_TRAP 626 stx %o1, [%g1] 627 stx %o2, [%g2] 628 retl 629 stx %o3, [%g3] 630 SET_SIZE(hv_ldc_rx_get_state) 631 632 633 /* 634 * hv_ldc_rx_set_qhead(uint64_t channel, uint64_t head) 635 */ 636 ENTRY(hv_ldc_rx_set_qhead) 637 mov LDC_RX_SET_QHEAD, %o5 638 ta FAST_TRAP 639 retl 640 SET_SIZE(hv_ldc_rx_set_qhead) 641 642 /* 643 * hv_ldc_set_map_table(uint64_t channel, uint64_t tbl_ra, 644 * uint64_t tbl_entries) 645 */ 646 ENTRY(hv_ldc_set_map_table) 647 mov LDC_SET_MAP_TABLE, %o5 648 ta FAST_TRAP 649 retl 650 nop 651 SET_SIZE(hv_ldc_set_map_table) 652 653 654 /* 655 * hv_ldc_get_map_table(uint64_t channel, uint64_t *tbl_ra, 656 * uint64_t *tbl_entries) 657 */ 658 ENTRY(hv_ldc_get_map_table) 659 mov %o1, %g1 660 mov %o2, %g2 661 mov LDC_GET_MAP_TABLE, %o5 662 ta FAST_TRAP 663 stx %o1, [%g1] 664 retl 665 stx %o2, [%g2] 666 SET_SIZE(hv_ldc_get_map_table) 667 668 669 /* 670 * hv_ldc_copy(uint64_t channel, uint64_t request, uint64_t cookie, 671 * uint64_t raddr, uint64_t length, uint64_t *lengthp); 672 */ 673 ENTRY(hv_ldc_copy) 674 mov %o5, %g1 675 mov LDC_COPY, %o5 676 ta FAST_TRAP 677 retl 678 stx %o1, [%g1] 679 SET_SIZE(hv_ldc_copy) 680 681 682 /* 683 * hv_ldc_mapin(uint64_t channel, uint64_t cookie, uint64_t *raddr, 684 * uint64_t *perm) 685 */ 686 ENTRY(hv_ldc_mapin) 687 mov %o2, %g1 688 mov %o3, %g2 689 mov LDC_MAPIN, %o5 690 ta FAST_TRAP 691 stx %o1, [%g1] 692 retl 693 stx %o2, [%g2] 694 SET_SIZE(hv_ldc_mapin) 695 696 697 /* 698 * hv_ldc_unmap(uint64_t raddr) 699 */ 700 ENTRY(hv_ldc_unmap) 701 mov LDC_UNMAP, %o5 702 ta FAST_TRAP 703 retl 704 nop 705 SET_SIZE(hv_ldc_unmap) 706 707 708 /* 709 * hv_ldc_revoke(uint64_t channel, uint64_t cookie, 710 * uint64_t revoke_cookie 711 */ 712 ENTRY(hv_ldc_revoke) 713 mov LDC_REVOKE, %o5 714 ta FAST_TRAP 715 retl 716 nop 717 SET_SIZE(hv_ldc_revoke) 718 719 /* 720 * hv_ldc_mapin_size_max(uint64_t tbl_type, uint64_t *sz) 721 */ 722 ENTRY(hv_ldc_mapin_size_max) 723 mov %o1, %g1 724 mov LDC_MAPIN_SIZE_MAX, %o5 725 ta FAST_TRAP 726 retl 727 stx %o1, [%g1] 728 SET_SIZE(hv_ldc_mapin_size_max) 729 730 /* 731 * hvldc_intr_getcookie(uint64_t dev_hdl, uint32_t devino, 732 * uint64_t *cookie); 733 */ 734 ENTRY(hvldc_intr_getcookie) 735 mov %o2, %g1 736 mov VINTR_GET_COOKIE, %o5 737 ta FAST_TRAP 738 retl 739 stx %o1, [%g1] 740 SET_SIZE(hvldc_intr_getcookie) 741 742 /* 743 * hvldc_intr_setcookie(uint64_t dev_hdl, uint32_t devino, 744 * uint64_t cookie); 745 */ 746 ENTRY(hvldc_intr_setcookie) 747 mov VINTR_SET_COOKIE, %o5 748 ta FAST_TRAP 749 retl 750 nop 751 SET_SIZE(hvldc_intr_setcookie) 752 753 754 /* 755 * hvldc_intr_getvalid(uint64_t dev_hdl, uint32_t devino, 756 * int *intr_valid_state); 757 */ 758 ENTRY(hvldc_intr_getvalid) 759 mov %o2, %g1 760 mov VINTR_GET_VALID, %o5 761 ta FAST_TRAP 762 retl 763 stuw %o1, [%g1] 764 SET_SIZE(hvldc_intr_getvalid) 765 766 /* 767 * hvldc_intr_setvalid(uint64_t dev_hdl, uint32_t devino, 768 * int intr_valid_state); 769 */ 770 ENTRY(hvldc_intr_setvalid) 771 mov VINTR_SET_VALID, %o5 772 ta FAST_TRAP 773 retl 774 nop 775 SET_SIZE(hvldc_intr_setvalid) 776 777 /* 778 * hvldc_intr_getstate(uint64_t dev_hdl, uint32_t devino, 779 * int *intr_state); 780 */ 781 ENTRY(hvldc_intr_getstate) 782 mov %o2, %g1 783 mov VINTR_GET_STATE, %o5 784 ta FAST_TRAP 785 retl 786 stuw %o1, [%g1] 787 SET_SIZE(hvldc_intr_getstate) 788 789 /* 790 * hvldc_intr_setstate(uint64_t dev_hdl, uint32_t devino, 791 * int intr_state); 792 */ 793 ENTRY(hvldc_intr_setstate) 794 mov VINTR_SET_STATE, %o5 795 ta FAST_TRAP 796 retl 797 nop 798 SET_SIZE(hvldc_intr_setstate) 799 800 /* 801 * hvldc_intr_gettarget(uint64_t dev_hdl, uint32_t devino, 802 * uint32_t *cpuid); 803 */ 804 ENTRY(hvldc_intr_gettarget) 805 mov %o2, %g1 806 mov VINTR_GET_TARGET, %o5 807 ta FAST_TRAP 808 retl 809 stuw %o1, [%g1] 810 SET_SIZE(hvldc_intr_gettarget) 811 812 /* 813 * hvldc_intr_settarget(uint64_t dev_hdl, uint32_t devino, 814 * uint32_t cpuid); 815 */ 816 ENTRY(hvldc_intr_settarget) 817 mov VINTR_SET_TARGET, %o5 818 ta FAST_TRAP 819 retl 820 nop 821 SET_SIZE(hvldc_intr_settarget) 822 823 /* 824 * hv_api_get_version(uint64_t api_group, uint64_t *majorp, 825 * uint64_t *minorp) 826 * 827 * API_GET_VERSION 828 * arg0 API group 829 * ret0 status 830 * ret1 major number 831 * ret2 minor number 832 */ 833 ENTRY(hv_api_get_version) 834 mov %o1, %o3 835 mov %o2, %o4 836 mov API_GET_VERSION, %o5 837 ta CORE_TRAP 838 stx %o1, [%o3] 839 retl 840 stx %o2, [%o4] 841 SET_SIZE(hv_api_get_version) 842 843 /* 844 * hv_api_set_version(uint64_t api_group, uint64_t major, 845 * uint64_t minor, uint64_t *supported_minor) 846 * 847 * API_SET_VERSION 848 * arg0 API group 849 * arg1 major number 850 * arg2 requested minor number 851 * ret0 status 852 * ret1 actual minor number 853 */ 854 ENTRY(hv_api_set_version) 855 mov %o3, %o4 856 mov API_SET_VERSION, %o5 857 ta CORE_TRAP 858 retl 859 stx %o1, [%o4] 860 SET_SIZE(hv_api_set_version) 861 862 /* 863 * %o0 - buffer real address 864 * %o1 - buffer size 865 * %o2 - &characters written 866 * returns 867 * status 868 */ 869 ENTRY(hv_cnwrite) 870 mov CONS_WRITE, %o5 871 ta FAST_TRAP 872 retl 873 stx %o1, [%o2] 874 SET_SIZE(hv_cnwrite) 875 876 /* 877 * %o0 character buffer ra 878 * %o1 buffer size 879 * %o2 pointer to returned size 880 * return values: 881 * 0 success 882 * hv_errno failure 883 */ 884 ENTRY(hv_cnread) 885 mov CONS_READ, %o5 886 ta FAST_TRAP 887 brnz,a %o0, 1f ! failure, just return error 888 nop 889 890 cmp %o1, H_BREAK 891 be 1f 892 mov %o1, %o0 893 894 cmp %o1, H_HUP 895 be 1f 896 mov %o1, %o0 897 898 stx %o1, [%o2] ! success, save count and return 0 899 mov 0, %o0 9001: 901 retl 902 nop 903 SET_SIZE(hv_cnread) 904 905 /* 906 * SOFT_STATE_SET 907 * arg0 state (%o0) 908 * arg1 string (%o1) 909 * ret0 status (%o0) 910 */ 911 ENTRY(hv_soft_state_set) 912 mov SOFT_STATE_SET, %o5 913 ta FAST_TRAP 914 retl 915 nop 916 SET_SIZE(hv_soft_state_set) 917 918 /* 919 * SOFT_STATE_GET 920 * arg0 string buffer (%o0) 921 * ret0 status (%o0) 922 * ret1 current state (%o1) 923 */ 924 ENTRY(hv_soft_state_get) 925 mov %o1, %o2 926 mov SOFT_STATE_GET, %o5 927 ta FAST_TRAP 928 retl 929 stx %o1, [%o2] 930 SET_SIZE(hv_soft_state_get) 931 932 ENTRY(hv_guest_suspend) 933 mov GUEST_SUSPEND, %o5 934 ta FAST_TRAP 935 retl 936 nop 937 SET_SIZE(hv_guest_suspend) 938 939 ENTRY(hv_tick_set_npt) 940 mov TICK_SET_NPT, %o5 941 ta FAST_TRAP 942 retl 943 nop 944 SET_SIZE(hv_tick_set_npt) 945 946 ENTRY(hv_stick_set_npt) 947 mov STICK_SET_NPT, %o5 948 ta FAST_TRAP 949 retl 950 nop 951 SET_SIZE(hv_stick_set_npt) 952 953 /* 954 * REBOOT_DATA_SET 955 * arg0 buffer real address 956 * arg1 buffer length 957 * ret0 status 958 */ 959 ENTRY(hv_reboot_data_set) 960 mov HV_REBOOT_DATA_SET, %o5 961 ta FAST_TRAP 962 retl 963 nop 964 SET_SIZE(hv_reboot_data_set) 965 966