xref: /illumos-gate/usr/src/uts/sun4v/io/px/px_libhv.c (revision 726fad2a65f16c200a03969c29cb5c86c2d427db)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #include <sys/types.h>
27 #include <sys/sysmacros.h>
28 #include <sys/ddi.h>
29 #include <sys/async.h>
30 #include <sys/sunddi.h>
31 #include <sys/ddifm.h>
32 #include <sys/fm/protocol.h>
33 #include <sys/vmem.h>
34 #include <sys/intr.h>
35 #include <sys/ivintr.h>
36 #include <sys/errno.h>
37 #include <sys/hypervisor_api.h>
38 #include <sys/hsvc.h>
39 #include <sys/pci_cfgacc.h>
40 #include <sys/pci_cfgacc_4v.h>
41 #include <px_obj.h>
42 #include <sys/machsystm.h>
43 #include "px_lib4v.h"
44 
45 #define	MPS_SET		0
46 #define	MPS_GET		1
47 
48 static uint64_t hvio_rp_mps(devhandle_t dev_hdl, pci_device_t bdf, int32_t *mps,
49 	int op);
50 
51 uint64_t
52 hvio_get_rp_mps_cap(devhandle_t dev_hdl, pci_device_t bdf, int32_t *mps_cap)
53 {
54 	return (hvio_rp_mps(dev_hdl, bdf, mps_cap, MPS_GET));
55 }
56 
57 uint64_t
58 hvio_set_rp_mps(devhandle_t dev_hdl, pci_device_t bdf, int32_t mps)
59 {
60 	return (hvio_rp_mps(dev_hdl, bdf, &mps, MPS_SET));
61 }
62 
63 uint64_t
64 hvio_rp_mps(devhandle_t dev_hdl, pci_device_t bdf, int32_t *mps, int op)
65 {
66 	uint64_t	data, hdr, hdr_next_ptr, hdr_cap_id;
67 	uint16_t	offset = PCI_CONF_STAT;
68 	int		deadcount = 0;
69 	pci_cfg_data_t	dataw;
70 
71 	if ((hvio_config_get(dev_hdl, bdf, PCI_CONF_VENID, 4,
72 	    (pci_cfg_data_t *)&data)) != H_EOK)
73 		return (H_ENOACCESS);
74 
75 	if ((data & 0xffff) != 0x108e)
76 		return (H_ENOACCESS);
77 
78 	if ((hvio_config_get(dev_hdl, bdf, PCI_CONF_COMM, 4,
79 	    (pci_cfg_data_t *)&hdr)) != H_EOK)
80 		return (H_ENOACCESS);
81 
82 	if (!(hdr & (PCI_STAT_CAP << 16)))
83 		return (H_ENOACCESS);
84 
85 	(void) hvio_config_get(dev_hdl, bdf, PCI_CONF_CAP_PTR, 4,
86 	    (pci_cfg_data_t *)&hdr);
87 
88 	hdr_next_ptr = hdr & 0xFF;
89 	hdr_cap_id = 0;
90 
91 	while ((hdr_next_ptr != PCI_CAP_NEXT_PTR_NULL) &&
92 	    (hdr_cap_id != PCI_CAP_ID_PCI_E)) {
93 
94 		offset = hdr_next_ptr;
95 
96 		if (hdr_next_ptr < 0x40)
97 			break;
98 
99 		(void) hvio_config_get(dev_hdl, bdf, hdr_next_ptr, 4,
100 		    (pci_cfg_data_t *)&hdr);
101 
102 		hdr_next_ptr = (hdr >> 8) & 0xFF;
103 		hdr_cap_id = hdr & 0xFF;
104 
105 		if (deadcount++ > 100)
106 			break;
107 	}
108 
109 	if (hdr_cap_id != PCI_CAP_ID_PCI_E)
110 		return (H_ENOACCESS);
111 
112 	if (op == MPS_SET) {
113 
114 		/* Write the MPS */
115 
116 		(void) hvio_config_get(dev_hdl, bdf, offset + PCIE_DEVCTL,
117 		    4, (pci_cfg_data_t *)&data);
118 
119 		data = (data & 0xffffff1f) | (*mps << 5);
120 
121 		dataw.qw = data;
122 
123 		(void) hvio_config_put(dev_hdl, bdf, offset + PCIE_DEVCTL,
124 		    4, dataw);
125 	} else {
126 
127 		/* Read the MPS Capabilities */
128 
129 		(void) hvio_config_get(dev_hdl, bdf, offset + PCIE_DEVCAP,
130 		    4, (pci_cfg_data_t *)&data);
131 
132 		*mps = data & 0x7;
133 	}
134 
135 	return (H_EOK);
136 }
137