1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PX_LIB4V_H 27 #define _SYS_PX_LIB4V_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 /* 32 * SUN4V IO API - Version 1.11 33 */ 34 35 #ifdef __cplusplus 36 extern "C" { 37 #endif 38 39 /* 40 * The device handle uniquely identifies a SUN4V device. 41 * It consists of the lower 28-bits of the hi-cell of the 42 * first entry of the SUN4V device's "reg" property as 43 * defined by the SUN4V Bus Binding to Open Firmware. 44 */ 45 #define DEVHDLE_MASK 0xFFFFFFF 46 47 /* PX BDF Shift in a Phyiscal Address - used FMA Fabric only */ 48 #define PX_RA_BDF_SHIFT 8 49 50 #define PX_ADDR2PFN(addr, index, flags, i) \ 51 ((flags & MMU_MAP_PFN) ? \ 52 PX_GET_MP_PFN((ddi_dma_impl_t *)(addr), (index + i)) : \ 53 hat_getpfnum(kas.a_hat, ((caddr_t)addr + (MMU_PAGE_SIZE * i)))) 54 55 /* 56 * VPCI API versioning. 57 * 58 * Currently PX nexus driver supports VPCI API version 1.0. 59 */ 60 #define PX_VPCI_MAJOR_VER_1 0x1ull 61 #define PX_VPCI_MAJOR_VER PX_VPCI_MAJOR_VER_1 62 63 #define PX_VPCI_MINOR_VER_0 0x0ull 64 #define PX_VPCI_MINOR_VER PX_VPCI_MINOR_VER_0 65 66 extern uint64_t hvio_config_get(devhandle_t dev_hdl, pci_device_t bdf, 67 pci_config_offset_t off, pci_config_size_t size, pci_cfg_data_t *data_p); 68 extern uint64_t hvio_config_put(devhandle_t dev_hdl, pci_device_t bdf, 69 pci_config_offset_t off, pci_config_size_t size, pci_cfg_data_t data); 70 71 extern uint64_t hvio_iommu_map(devhandle_t dev_hdl, tsbid_t tsbid, 72 pages_t pages, io_attributes_t attr, io_page_list_t *io_page_list_p, 73 pages_t *pages_mapped); 74 extern uint64_t hvio_iommu_demap(devhandle_t dev_hdl, tsbid_t tsbid, 75 pages_t pages, pages_t *pages_demapped); 76 extern uint64_t hvio_iommu_getmap(devhandle_t dev_hdl, tsbid_t tsbid, 77 io_attributes_t *attr_p, r_addr_t *r_addr_p); 78 extern uint64_t hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra, 79 io_attributes_t attr, io_addr_t *io_addr_p); 80 extern uint64_t hvio_dma_sync(devhandle_t dev_hdl, r_addr_t ra, 81 size_t num_bytes, io_sync_direction_t io_sync_direction, 82 size_t *bytes_synched); 83 84 /* 85 * MSIQ Functions: 86 */ 87 extern uint64_t hvio_msiq_conf(devhandle_t dev_hdl, msiqid_t msiq_id, 88 r_addr_t ra, uint_t msiq_rec_cnt); 89 extern uint64_t hvio_msiq_info(devhandle_t dev_hdl, msiqid_t msiq_id, 90 r_addr_t *ra_p, uint_t *msiq_rec_cnt_p); 91 extern uint64_t hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 92 pci_msiq_valid_state_t *msiq_valid_state); 93 extern uint64_t hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 94 pci_msiq_valid_state_t msiq_valid_state); 95 extern uint64_t hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id, 96 pci_msiq_state_t *msiq_state); 97 extern uint64_t hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id, 98 pci_msiq_state_t msiq_state); 99 extern uint64_t hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id, 100 msiqhead_t *msiq_head); 101 extern uint64_t hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id, 102 msiqhead_t msiq_head); 103 extern uint64_t hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id, 104 msiqtail_t *msiq_tail); 105 106 /* 107 * MSI Functions: 108 */ 109 extern uint64_t hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num, 110 msiqid_t *msiq_id); 111 extern uint64_t hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num, 112 msiqid_t msiq_id, msi_type_t msitype); 113 extern uint64_t hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num, 114 pci_msi_valid_state_t *msi_valid_state); 115 extern uint64_t hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num, 116 pci_msi_valid_state_t msi_valid_state); 117 extern uint64_t hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num, 118 pci_msi_state_t *msi_state); 119 extern uint64_t hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num, 120 pci_msi_state_t msi_state); 121 122 /* 123 * MSG Functions: 124 */ 125 extern uint64_t hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 126 msiqid_t *msiq_id); 127 extern uint64_t hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 128 msiqid_t msiq_id); 129 extern uint64_t hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 130 pcie_msg_valid_state_t *msg_valid_state); 131 extern uint64_t hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 132 pcie_msg_valid_state_t msg_valid_state); 133 134 typedef struct px_config_acc_pvt { 135 dev_info_t *dip; 136 uint32_t raddr; 137 uint32_t vaddr; 138 } px_config_acc_pvt_t; 139 140 /* 141 * Peek/poke functionality: 142 */ 143 144 extern uint64_t hvio_peek(devhandle_t dev_hdl, r_addr_t ra, size_t size, 145 uint32_t *status, uint64_t *data_p); 146 extern uint64_t hvio_poke(devhandle_t dev_hdl, r_addr_t ra, size_t size, 147 uint64_t data, pci_device_t bdf, uint32_t *wrt_stat); 148 149 /* 150 * Priviledged physical access: 151 */ 152 extern uint64_t hv_ra2pa(uint64_t ra); 153 extern uint64_t hv_hpriv(void *func, uint64_t arg1, uint64_t arg2, 154 uint64_t arg3); 155 extern int px_phys_acc_4v(uint64_t dummy, uint64_t from_addr, uint64_t to_addr); 156 157 #ifdef __cplusplus 158 } 159 #endif 160 161 #endif /* _SYS_PX_LIB4V_H */ 162