1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_PX_LIB4V_H 28 #define _SYS_PX_LIB4V_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 /* 33 * SUN4V IO API - Version 1.11 34 */ 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 /* 41 * The device handle uniquely identifies a SUN4V device. 42 * It consists of the lower 28-bits of the hi-cell of the 43 * first entry of the SUN4V device's "reg" property as 44 * defined by the SUN4V Bus Binding to Open Firmware. 45 */ 46 #define DEVHDLE_MASK 0xFFFFFFF 47 48 /* PX BDF Shift in a Phyiscal Address - used FMA Fabric only */ 49 #define PX_RA_BDF_SHIFT 8 50 51 #define PX_ADDR2PFN(addr, index, flag, i) \ 52 ((flag == MMU_MAP_MP) ? \ 53 PX_GET_MP_PFN((ddi_dma_impl_t *)(addr), (index + i)) : \ 54 hat_getpfnum(kas.a_hat, ((caddr_t)addr + (MMU_PAGE_SIZE * i)))) 55 56 extern uint64_t hvio_config_get(devhandle_t dev_hdl, pci_device_t bdf, 57 pci_config_offset_t off, pci_config_size_t size, pci_cfg_data_t *data_p); 58 extern uint64_t hvio_config_put(devhandle_t dev_hdl, pci_device_t bdf, 59 pci_config_offset_t off, pci_config_size_t size, pci_cfg_data_t data); 60 61 extern uint64_t hvio_iommu_map(devhandle_t dev_hdl, tsbid_t tsbid, 62 pages_t pages, io_attributes_t io_attributes, 63 io_page_list_t *io_page_list_p, pages_t *pages_mapped); 64 extern uint64_t hvio_iommu_demap(devhandle_t dev_hdl, tsbid_t tsbid, 65 pages_t pages, pages_t *pages_demapped); 66 extern uint64_t hvio_iommu_getmap(devhandle_t dev_hdl, tsbid_t tsbid, 67 io_attributes_t *attributes_p, r_addr_t *r_addr_p); 68 extern uint64_t hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra, 69 io_attributes_t io_attributes, io_addr_t *io_addr_p); 70 extern uint64_t hvio_dma_sync(devhandle_t dev_hdl, r_addr_t ra, 71 size_t num_bytes, io_sync_direction_t io_sync_direction, 72 size_t *bytes_synched); 73 74 /* 75 * MSIQ Functions: 76 */ 77 extern uint64_t hvio_msiq_conf(devhandle_t dev_hdl, msiqid_t msiq_id, 78 r_addr_t ra, uint_t msiq_rec_cnt); 79 extern uint64_t hvio_msiq_info(devhandle_t dev_hdl, msiqid_t msiq_id, 80 r_addr_t *ra_p, uint_t *msiq_rec_cnt_p); 81 extern uint64_t hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 82 pci_msiq_valid_state_t *msiq_valid_state); 83 extern uint64_t hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 84 pci_msiq_valid_state_t msiq_valid_state); 85 extern uint64_t hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id, 86 pci_msiq_state_t *msiq_state); 87 extern uint64_t hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id, 88 pci_msiq_state_t msiq_state); 89 extern uint64_t hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id, 90 msiqhead_t *msiq_head); 91 extern uint64_t hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id, 92 msiqhead_t msiq_head); 93 extern uint64_t hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id, 94 msiqtail_t *msiq_tail); 95 96 /* 97 * MSI Functions: 98 */ 99 extern uint64_t hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num, 100 msiqid_t *msiq_id); 101 extern uint64_t hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num, 102 msiqid_t msiq_id, msi_type_t msitype); 103 extern uint64_t hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num, 104 pci_msi_valid_state_t *msi_valid_state); 105 extern uint64_t hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num, 106 pci_msi_valid_state_t msi_valid_state); 107 extern uint64_t hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num, 108 pci_msi_state_t *msi_state); 109 extern uint64_t hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num, 110 pci_msi_state_t msi_state); 111 112 /* 113 * MSG Functions: 114 */ 115 extern uint64_t hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 116 msiqid_t *msiq_id); 117 extern uint64_t hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 118 msiqid_t msiq_id); 119 extern uint64_t hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 120 pcie_msg_valid_state_t *msg_valid_state); 121 extern uint64_t hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 122 pcie_msg_valid_state_t msg_valid_state); 123 124 typedef struct px_config_acc_pvt { 125 dev_info_t *dip; 126 uint32_t raddr; 127 uint32_t vaddr; 128 } px_config_acc_pvt_t; 129 130 /* 131 * Peek/poke functionality: 132 */ 133 134 extern uint64_t hvio_peek(devhandle_t dev_hdl, r_addr_t ra, size_t size, 135 uint32_t *status, uint64_t *data_p); 136 extern uint64_t hvio_poke(devhandle_t dev_hdl, r_addr_t ra, size_t size, 137 uint64_t data, pci_device_t bdf, uint32_t *wrt_stat); 138 139 /* 140 * Priviledged physical access: 141 */ 142 extern uint64_t hv_ra2pa(uint64_t ra); 143 extern uint64_t hv_hpriv(void *func, uint64_t arg1, uint64_t arg2, 144 uint64_t arg3); 145 146 #ifdef __cplusplus 147 } 148 #endif 149 150 #endif /* _SYS_PX_LIB4V_H */ 151