1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <sys/types.h> 27 #include <sys/sysmacros.h> 28 #include <sys/ddi.h> 29 #include <sys/async.h> 30 #include <sys/sunddi.h> 31 #include <sys/ddifm.h> 32 #include <sys/fm/protocol.h> 33 #include <sys/vmem.h> 34 #include <sys/intr.h> 35 #include <sys/ivintr.h> 36 #include <sys/errno.h> 37 #include <sys/hypervisor_api.h> 38 #include <sys/hsvc.h> 39 #include <px_obj.h> 40 #include <sys/machsystm.h> 41 #include <sys/hotplug/pci/pcihp.h> 42 #include "px_lib4v.h" 43 #include "px_err.h" 44 #include <vm/vm_dep.h> 45 #include <vm/hat_sfmmu.h> 46 47 /* mask for the ranges property in calculating the real PFN range */ 48 uint_t px_ranges_phi_mask = ((1 << 28) -1); 49 50 /* 51 * Hypervisor VPCI services information for the px nexus driver. 52 */ 53 static uint64_t px_vpci_min_ver; /* Negotiated VPCI API minor version */ 54 static uint_t px_vpci_users = 0; /* VPCI API users */ 55 56 static hsvc_info_t px_hsvc = { 57 HSVC_REV_1, NULL, HSVC_GROUP_VPCI, PX_VPCI_MAJOR_VER, 58 PX_VPCI_MINOR_VER, "PX" 59 }; 60 61 int 62 px_lib_dev_init(dev_info_t *dip, devhandle_t *dev_hdl) 63 { 64 px_nexus_regspec_t *rp; 65 uint_t reglen; 66 int ret; 67 68 uint64_t mjrnum; 69 uint64_t mnrnum; 70 71 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dip 0x%p\n", dip); 72 73 /* 74 * Check HV intr group api versioning. 75 * This driver uses the old interrupt routines which are supported 76 * in old firmware in the CORE API group and in newer firmware in 77 * the INTR API group. Support for these calls will be dropped 78 * once the INTR API group major goes to 2. 79 */ 80 if ((hsvc_version(HSVC_GROUP_INTR, &mjrnum, &mnrnum) == 0) && 81 (mjrnum > 1)) { 82 cmn_err(CE_WARN, "niumx: unsupported intr api group: " 83 "maj:0x%lx, min:0x%lx", mjrnum, mnrnum); 84 return (ENOTSUP); 85 } 86 87 ret = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 88 "reg", (uchar_t **)&rp, ®len); 89 if (ret != DDI_PROP_SUCCESS) { 90 DBG(DBG_ATTACH, dip, "px_lib_dev_init failed ret=%d\n", ret); 91 return (DDI_FAILURE); 92 } 93 94 /* 95 * Initilize device handle. The device handle uniquely identifies 96 * a SUN4V device. It consists of the lower 28-bits of the hi-cell 97 * of the first entry of the SUN4V device's "reg" property as 98 * defined by the SUN4V Bus Binding to Open Firmware. 99 */ 100 *dev_hdl = (devhandle_t)((rp->phys_addr >> 32) & DEVHDLE_MASK); 101 ddi_prop_free(rp); 102 103 /* 104 * hotplug implementation requires this property to be associated with 105 * any indirect PCI config access services 106 */ 107 (void) ddi_prop_update_int(makedevice(ddi_driver_major(dip), 108 PCIHP_AP_MINOR_NUM(ddi_get_instance(dip), PCIHP_DEVCTL_MINOR)), dip, 109 PCI_BUS_CONF_MAP_PROP, 1); 110 111 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dev_hdl 0x%llx\n", *dev_hdl); 112 113 /* 114 * Negotiate the API version for VPCI hypervisor services. 115 */ 116 if (px_vpci_users++) 117 return (DDI_SUCCESS); 118 119 if ((ret = hsvc_register(&px_hsvc, &px_vpci_min_ver)) != 0) { 120 cmn_err(CE_WARN, "%s: cannot negotiate hypervisor services " 121 "group: 0x%lx major: 0x%lx minor: 0x%lx errno: %d\n", 122 px_hsvc.hsvc_modname, px_hsvc.hsvc_group, 123 px_hsvc.hsvc_major, px_hsvc.hsvc_minor, ret); 124 125 return (DDI_FAILURE); 126 } 127 128 DBG(DBG_ATTACH, dip, "px_lib_dev_init: negotiated VPCI API version, " 129 "major 0x%lx minor 0x%lx\n", px_hsvc.hsvc_major, px_vpci_min_ver); 130 131 return (DDI_SUCCESS); 132 } 133 134 /*ARGSUSED*/ 135 int 136 px_lib_dev_fini(dev_info_t *dip) 137 { 138 DBG(DBG_DETACH, dip, "px_lib_dev_fini: dip 0x%p\n", dip); 139 140 (void) ddi_prop_remove(makedevice(ddi_driver_major(dip), 141 PCIHP_AP_MINOR_NUM(ddi_get_instance(dip), PCIHP_DEVCTL_MINOR)), dip, 142 PCI_BUS_CONF_MAP_PROP); 143 144 if (--px_vpci_users == 0) 145 (void) hsvc_unregister(&px_hsvc); 146 147 return (DDI_SUCCESS); 148 } 149 150 /*ARGSUSED*/ 151 int 152 px_lib_intr_devino_to_sysino(dev_info_t *dip, devino_t devino, 153 sysino_t *sysino) 154 { 155 uint64_t ret; 156 157 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: dip 0x%p " 158 "devino 0x%x\n", dip, devino); 159 160 if ((ret = hvio_intr_devino_to_sysino(DIP_TO_HANDLE(dip), 161 devino, sysino)) != H_EOK) { 162 DBG(DBG_LIB_INT, dip, 163 "hvio_intr_devino_to_sysino failed, ret 0x%lx\n", ret); 164 return (DDI_FAILURE); 165 } 166 167 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: sysino 0x%llx\n", 168 *sysino); 169 170 return (DDI_SUCCESS); 171 } 172 173 /*ARGSUSED*/ 174 int 175 px_lib_intr_getvalid(dev_info_t *dip, sysino_t sysino, 176 intr_valid_state_t *intr_valid_state) 177 { 178 uint64_t ret; 179 180 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: dip 0x%p sysino 0x%llx\n", 181 dip, sysino); 182 183 if ((ret = hvio_intr_getvalid(sysino, 184 (int *)intr_valid_state)) != H_EOK) { 185 DBG(DBG_LIB_INT, dip, "hvio_intr_getvalid failed, ret 0x%lx\n", 186 ret); 187 return (DDI_FAILURE); 188 } 189 190 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: intr_valid_state 0x%x\n", 191 *intr_valid_state); 192 193 return (DDI_SUCCESS); 194 } 195 196 /*ARGSUSED*/ 197 int 198 px_lib_intr_setvalid(dev_info_t *dip, sysino_t sysino, 199 intr_valid_state_t intr_valid_state) 200 { 201 uint64_t ret; 202 203 DBG(DBG_LIB_INT, dip, "px_lib_intr_setvalid: dip 0x%p sysino 0x%llx " 204 "intr_valid_state 0x%x\n", dip, sysino, intr_valid_state); 205 206 if ((ret = hvio_intr_setvalid(sysino, intr_valid_state)) != H_EOK) { 207 DBG(DBG_LIB_INT, dip, "hvio_intr_setvalid failed, ret 0x%lx\n", 208 ret); 209 return (DDI_FAILURE); 210 } 211 212 return (DDI_SUCCESS); 213 } 214 215 /*ARGSUSED*/ 216 int 217 px_lib_intr_getstate(dev_info_t *dip, sysino_t sysino, 218 intr_state_t *intr_state) 219 { 220 uint64_t ret; 221 222 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: dip 0x%p sysino 0x%llx\n", 223 dip, sysino); 224 225 if ((ret = hvio_intr_getstate(sysino, (int *)intr_state)) != H_EOK) { 226 DBG(DBG_LIB_INT, dip, "hvio_intr_getstate failed, ret 0x%lx\n", 227 ret); 228 return (DDI_FAILURE); 229 } 230 231 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: intr_state 0x%x\n", 232 *intr_state); 233 234 return (DDI_SUCCESS); 235 } 236 237 /*ARGSUSED*/ 238 int 239 px_lib_intr_setstate(dev_info_t *dip, sysino_t sysino, 240 intr_state_t intr_state) 241 { 242 uint64_t ret; 243 244 DBG(DBG_LIB_INT, dip, "px_lib_intr_setstate: dip 0x%p sysino 0x%llx " 245 "intr_state 0x%x\n", dip, sysino, intr_state); 246 247 if ((ret = hvio_intr_setstate(sysino, intr_state)) != H_EOK) { 248 DBG(DBG_LIB_INT, dip, "hvio_intr_setstate failed, ret 0x%lx\n", 249 ret); 250 return (DDI_FAILURE); 251 } 252 253 return (DDI_SUCCESS); 254 } 255 256 /*ARGSUSED*/ 257 int 258 px_lib_intr_gettarget(dev_info_t *dip, sysino_t sysino, cpuid_t *cpuid) 259 { 260 uint64_t ret; 261 262 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: dip 0x%p sysino 0x%llx\n", 263 dip, sysino); 264 265 if ((ret = hvio_intr_gettarget(sysino, cpuid)) != H_EOK) { 266 DBG(DBG_LIB_INT, dip, 267 "hvio_intr_gettarget failed, ret 0x%lx\n", ret); 268 return (DDI_FAILURE); 269 } 270 271 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: cpuid 0x%x\n", cpuid); 272 273 return (DDI_SUCCESS); 274 } 275 276 /*ARGSUSED*/ 277 int 278 px_lib_intr_settarget(dev_info_t *dip, sysino_t sysino, cpuid_t cpuid) 279 { 280 uint64_t ret; 281 282 DBG(DBG_LIB_INT, dip, "px_lib_intr_settarget: dip 0x%p sysino 0x%llx " 283 "cpuid 0x%x\n", dip, sysino, cpuid); 284 285 ret = hvio_intr_settarget(sysino, cpuid); 286 if (ret == H_ECPUERROR) { 287 cmn_err(CE_PANIC, 288 "px_lib_intr_settarget: hvio_intr_settarget failed, " 289 "ret = 0x%lx, cpuid = 0x%x, sysino = 0x%lx\n", ret, 290 cpuid, sysino); 291 } else if (ret != H_EOK) { 292 DBG(DBG_LIB_INT, dip, 293 "hvio_intr_settarget failed, ret 0x%lx\n", ret); 294 return (DDI_FAILURE); 295 } 296 297 return (DDI_SUCCESS); 298 } 299 300 /*ARGSUSED*/ 301 int 302 px_lib_intr_reset(dev_info_t *dip) 303 { 304 px_t *px_p = DIP_TO_STATE(dip); 305 px_ib_t *ib_p = px_p->px_ib_p; 306 px_ino_t *ino_p; 307 308 DBG(DBG_LIB_INT, dip, "px_lib_intr_reset: dip 0x%p\n", dip); 309 310 mutex_enter(&ib_p->ib_ino_lst_mutex); 311 312 /* Reset all Interrupts */ 313 for (ino_p = ib_p->ib_ino_lst; ino_p; ino_p = ino_p->ino_next_p) { 314 if (px_lib_intr_setstate(dip, ino_p->ino_sysino, 315 INTR_IDLE_STATE) != DDI_SUCCESS) 316 return (BF_FATAL); 317 } 318 319 mutex_exit(&ib_p->ib_ino_lst_mutex); 320 321 return (BF_NONE); 322 } 323 324 /*ARGSUSED*/ 325 int 326 px_lib_iommu_map(dev_info_t *dip, tsbid_t tsbid, pages_t pages, 327 io_attributes_t attr, void *addr, size_t pfn_index, int flags) 328 { 329 tsbnum_t tsb_num = PCI_TSBID_TO_TSBNUM(tsbid); 330 tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); 331 io_page_list_t *pfns, *pfn_p; 332 pages_t ttes_mapped = 0; 333 int i, err = DDI_SUCCESS; 334 335 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: dip 0x%p tsbid 0x%llx " 336 "pages 0x%x attr 0x%x addr 0x%p pfn_index 0x%llx flags 0x%x\n", 337 dip, tsbid, pages, attr, addr, pfn_index, flags); 338 339 if ((pfns = pfn_p = kmem_zalloc((pages * sizeof (io_page_list_t)), 340 KM_NOSLEEP)) == NULL) { 341 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: kmem_zalloc failed\n"); 342 return (DDI_FAILURE); 343 } 344 345 for (i = 0; i < pages; i++) 346 pfns[i] = MMU_PTOB(PX_ADDR2PFN(addr, pfn_index, flags, i)); 347 348 /* 349 * If HV VPCI version is 1.1 and higher, pass BDF, phantom function, 350 * and relaxed ordering attributes. Otherwise, pass only read or write 351 * attribute. 352 */ 353 if (px_vpci_min_ver == PX_VPCI_MINOR_VER_0) 354 attr = attr & (PCI_MAP_ATTR_READ | PCI_MAP_ATTR_WRITE); 355 356 while ((ttes_mapped = pfn_p - pfns) < pages) { 357 uintptr_t ra = va_to_pa(pfn_p); 358 pages_t ttes2map; 359 uint64_t ret; 360 361 ttes2map = (MMU_PAGE_SIZE - P2PHASE(ra, MMU_PAGE_SIZE)) >> 3; 362 ra = MMU_PTOB(MMU_BTOP(ra)); 363 364 for (ttes2map = MIN(ttes2map, pages - ttes_mapped); ttes2map; 365 ttes2map -= ttes_mapped, pfn_p += ttes_mapped) { 366 367 ttes_mapped = 0; 368 if ((ret = hvio_iommu_map(DIP_TO_HANDLE(dip), 369 PCI_TSBID(tsb_num, tsb_index + (pfn_p - pfns)), 370 ttes2map, attr, (io_page_list_t *)(ra | 371 ((uintptr_t)pfn_p & MMU_PAGE_OFFSET)), 372 &ttes_mapped)) != H_EOK) { 373 DBG(DBG_LIB_DMA, dip, "hvio_iommu_map failed " 374 "ret 0x%lx\n", ret); 375 376 ttes_mapped = pfn_p - pfns; 377 err = DDI_FAILURE; 378 goto cleanup; 379 } 380 381 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: tsb_num 0x%x " 382 "tsb_index 0x%lx ttes_to_map 0x%lx attr 0x%x " 383 "ra 0x%p ttes_mapped 0x%x\n", tsb_num, 384 tsb_index + (pfn_p - pfns), ttes2map, attr, 385 ra | ((uintptr_t)pfn_p & MMU_PAGE_OFFSET), 386 ttes_mapped); 387 } 388 } 389 390 cleanup: 391 if ((err == DDI_FAILURE) && ttes_mapped) 392 (void) px_lib_iommu_demap(dip, tsbid, ttes_mapped); 393 394 kmem_free(pfns, pages * sizeof (io_page_list_t)); 395 return (err); 396 } 397 398 /*ARGSUSED*/ 399 int 400 px_lib_iommu_demap(dev_info_t *dip, tsbid_t tsbid, pages_t pages) 401 { 402 tsbnum_t tsb_num = PCI_TSBID_TO_TSBNUM(tsbid); 403 tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); 404 pages_t ttes2demap, ttes_demapped = 0; 405 uint64_t ret; 406 407 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: dip 0x%p tsbid 0x%llx " 408 "pages 0x%x\n", dip, tsbid, pages); 409 410 for (ttes2demap = pages; ttes2demap; 411 ttes2demap -= ttes_demapped, tsb_index += ttes_demapped) { 412 if ((ret = hvio_iommu_demap(DIP_TO_HANDLE(dip), 413 PCI_TSBID(tsb_num, tsb_index), ttes2demap, 414 &ttes_demapped)) != H_EOK) { 415 DBG(DBG_LIB_DMA, dip, "hvio_iommu_demap failed, " 416 "ret 0x%lx\n", ret); 417 418 return (DDI_FAILURE); 419 } 420 421 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: tsb_num 0x%x " 422 "tsb_index 0x%lx ttes_to_demap 0x%lx ttes_demapped 0x%x\n", 423 tsb_num, tsb_index, ttes2demap, ttes_demapped); 424 } 425 426 return (DDI_SUCCESS); 427 } 428 429 /*ARGSUSED*/ 430 int 431 px_lib_iommu_getmap(dev_info_t *dip, tsbid_t tsbid, io_attributes_t *attr_p, 432 r_addr_t *r_addr_p) 433 { 434 uint64_t ret; 435 436 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: dip 0x%p tsbid 0x%llx\n", 437 dip, tsbid); 438 439 if ((ret = hvio_iommu_getmap(DIP_TO_HANDLE(dip), tsbid, 440 attr_p, r_addr_p)) != H_EOK) { 441 DBG(DBG_LIB_DMA, dip, 442 "hvio_iommu_getmap failed, ret 0x%lx\n", ret); 443 444 return ((ret == H_ENOMAP) ? DDI_DMA_NOMAPPING:DDI_FAILURE); 445 } 446 447 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: attr 0x%x r_addr 0x%llx\n", 448 *attr_p, *r_addr_p); 449 450 return (DDI_SUCCESS); 451 } 452 453 /*ARGSUSED*/ 454 uint64_t 455 px_get_rng_parent_hi_mask(px_t *px_p) 456 { 457 return (PX_RANGE_PROP_MASK); 458 } 459 460 /* 461 * Checks dma attributes against system bypass ranges 462 * A sun4v device must be capable of generating the entire 64-bit 463 * address in order to perform bypass DMA. 464 */ 465 /*ARGSUSED*/ 466 int 467 px_lib_dma_bypass_rngchk(dev_info_t *dip, ddi_dma_attr_t *attr_p, 468 uint64_t *lo_p, uint64_t *hi_p) 469 { 470 if ((attr_p->dma_attr_addr_lo != 0ull) || 471 (attr_p->dma_attr_addr_hi != UINT64_MAX)) { 472 473 return (DDI_DMA_BADATTR); 474 } 475 476 *lo_p = 0ull; 477 *hi_p = UINT64_MAX; 478 479 return (DDI_SUCCESS); 480 } 481 482 483 /*ARGSUSED*/ 484 int 485 px_lib_iommu_getbypass(dev_info_t *dip, r_addr_t ra, io_attributes_t attr, 486 io_addr_t *io_addr_p) 487 { 488 uint64_t ret; 489 490 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: dip 0x%p ra 0x%llx " 491 "attr 0x%x\n", dip, ra, attr); 492 493 if ((ret = hvio_iommu_getbypass(DIP_TO_HANDLE(dip), ra, 494 attr, io_addr_p)) != H_EOK) { 495 DBG(DBG_LIB_DMA, dip, 496 "hvio_iommu_getbypass failed, ret 0x%lx\n", ret); 497 return (ret == H_ENOTSUPPORTED ? DDI_ENOTSUP : DDI_FAILURE); 498 } 499 500 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: io_addr 0x%llx\n", 501 *io_addr_p); 502 503 return (DDI_SUCCESS); 504 } 505 506 /*ARGSUSED*/ 507 int 508 px_lib_dma_sync(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 509 off_t off, size_t len, uint_t cache_flags) 510 { 511 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 512 uint64_t sync_dir; 513 size_t bytes_synced; 514 int end, idx; 515 off_t pg_off; 516 devhandle_t hdl = DIP_TO_HANDLE(dip); /* need to cache hdl */ 517 518 DBG(DBG_LIB_DMA, dip, "px_lib_dma_sync: dip 0x%p rdip 0x%p " 519 "handle 0x%llx off 0x%x len 0x%x flags 0x%x\n", 520 dip, rdip, handle, off, len, cache_flags); 521 522 if (!(mp->dmai_flags & PX_DMAI_FLAGS_INUSE)) { 523 cmn_err(CE_WARN, "%s%d: Unbound dma handle %p.", 524 ddi_driver_name(rdip), ddi_get_instance(rdip), (void *)mp); 525 return (DDI_FAILURE); 526 } 527 528 if (mp->dmai_flags & PX_DMAI_FLAGS_NOSYNC) 529 return (DDI_SUCCESS); 530 531 if (!len) 532 len = mp->dmai_size; 533 534 if (mp->dmai_rflags & DDI_DMA_READ) 535 sync_dir = HVIO_DMA_SYNC_DIR_FROM_DEV; 536 else 537 sync_dir = HVIO_DMA_SYNC_DIR_TO_DEV; 538 539 if (force_sync_icache_after_dma == 0 && !icache_is_coherent) 540 sync_dir |= HVIO_DMA_SYNC_DIR_NO_ICACHE_FLUSH; 541 542 off += mp->dmai_offset; 543 pg_off = off & MMU_PAGEOFFSET; 544 545 DBG(DBG_LIB_DMA, dip, "px_lib_dma_sync: page offset %x size %x\n", 546 pg_off, len); 547 548 /* sync on page basis */ 549 end = MMU_BTOPR(off + len - 1); 550 for (idx = MMU_BTOP(off); idx < end; idx++, 551 len -= bytes_synced, pg_off = 0) { 552 size_t bytes_to_sync = MIN(len, MMU_PAGESIZE - pg_off); 553 554 while (hvio_dma_sync(hdl, 555 MMU_PTOB(PX_GET_MP_PFN(mp, idx)) + pg_off, 556 bytes_to_sync, sync_dir, &bytes_synced) != H_EOK) { 557 558 if (!(sync_dir & HVIO_DMA_SYNC_DIR_NO_ICACHE_FLUSH)) { 559 bytes_synced = 0; 560 break; 561 } 562 563 /* 564 * Some versions of firmware do not support 565 * this sync_dir flag. If the call fails clear 566 * the flag and retry the call. Also, set the 567 * global so that we dont set the sync_dir 568 * flag again. 569 */ 570 sync_dir &= ~HVIO_DMA_SYNC_DIR_NO_ICACHE_FLUSH; 571 force_sync_icache_after_dma = 1; 572 } 573 574 DBG(DBG_LIB_DMA, dip, "px_lib_dma_sync: Called hvio_dma_sync " 575 "ra = %p bytes to sync = %x bytes synced %x\n", 576 MMU_PTOB(PX_GET_MP_PFN(mp, idx)) + pg_off, bytes_to_sync, 577 bytes_synced); 578 579 if (bytes_to_sync != bytes_synced) 580 break; 581 } 582 583 return (len ? DDI_FAILURE : DDI_SUCCESS); 584 } 585 586 587 /* 588 * MSIQ Functions: 589 */ 590 591 /*ARGSUSED*/ 592 int 593 px_lib_msiq_init(dev_info_t *dip) 594 { 595 px_t *px_p = DIP_TO_STATE(dip); 596 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 597 r_addr_t ra; 598 size_t msiq_size; 599 uint_t rec_cnt; 600 int i, err = DDI_SUCCESS; 601 uint64_t ret; 602 603 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_init: dip 0x%p\n", dip); 604 605 msiq_size = msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t); 606 607 /* sun4v requires all EQ allocation to be on q size boundary */ 608 if ((msiq_state_p->msiq_buf_p = contig_mem_alloc_align( 609 msiq_state_p->msiq_cnt * msiq_size, msiq_size)) == NULL) { 610 DBG(DBG_LIB_MSIQ, dip, 611 "px_lib_msiq_init: Contig alloc failed\n"); 612 613 return (DDI_FAILURE); 614 } 615 616 for (i = 0; i < msiq_state_p->msiq_cnt; i++) { 617 msiq_state_p->msiq_p[i].msiq_base_p = (msiqhead_t *) 618 ((caddr_t)msiq_state_p->msiq_buf_p + (i * msiq_size)); 619 620 ra = (r_addr_t)va_to_pa((caddr_t)msiq_state_p->msiq_buf_p + 621 (i * msiq_size)); 622 623 if ((ret = hvio_msiq_conf(DIP_TO_HANDLE(dip), 624 (i + msiq_state_p->msiq_1st_msiq_id), 625 ra, msiq_state_p->msiq_rec_cnt)) != H_EOK) { 626 DBG(DBG_LIB_MSIQ, dip, 627 "hvio_msiq_conf failed, ret 0x%lx\n", ret); 628 err = DDI_FAILURE; 629 break; 630 } 631 632 if ((err = px_lib_msiq_info(dip, 633 (i + msiq_state_p->msiq_1st_msiq_id), 634 &ra, &rec_cnt)) != DDI_SUCCESS) { 635 DBG(DBG_LIB_MSIQ, dip, 636 "px_lib_msiq_info failed, ret 0x%x\n", err); 637 err = DDI_FAILURE; 638 break; 639 } 640 641 DBG(DBG_LIB_MSIQ, dip, 642 "px_lib_msiq_init: ra 0x%p rec_cnt 0x%x\n", ra, rec_cnt); 643 } 644 645 return (err); 646 } 647 648 /*ARGSUSED*/ 649 int 650 px_lib_msiq_fini(dev_info_t *dip) 651 { 652 px_t *px_p = DIP_TO_STATE(dip); 653 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 654 size_t msiq_size; 655 656 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_fini: dip 0x%p\n", dip); 657 msiq_size = msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t); 658 659 if (msiq_state_p->msiq_buf_p != NULL) 660 contig_mem_free(msiq_state_p->msiq_buf_p, 661 msiq_state_p->msiq_cnt * msiq_size); 662 663 return (DDI_SUCCESS); 664 } 665 666 /*ARGSUSED*/ 667 int 668 px_lib_msiq_info(dev_info_t *dip, msiqid_t msiq_id, r_addr_t *ra_p, 669 uint_t *msiq_rec_cnt_p) 670 { 671 uint64_t ret; 672 673 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: dip 0x%p msiq_id 0x%x\n", 674 dip, msiq_id); 675 676 if ((ret = hvio_msiq_info(DIP_TO_HANDLE(dip), 677 msiq_id, ra_p, msiq_rec_cnt_p)) != H_EOK) { 678 DBG(DBG_LIB_MSIQ, dip, 679 "hvio_msiq_info failed, ret 0x%lx\n", ret); 680 return (DDI_FAILURE); 681 } 682 683 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: ra_p 0x%p msiq_rec_cnt 0x%x\n", 684 ra_p, *msiq_rec_cnt_p); 685 686 return (DDI_SUCCESS); 687 } 688 689 /*ARGSUSED*/ 690 int 691 px_lib_msiq_getvalid(dev_info_t *dip, msiqid_t msiq_id, 692 pci_msiq_valid_state_t *msiq_valid_state) 693 { 694 uint64_t ret; 695 696 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: dip 0x%p msiq_id 0x%x\n", 697 dip, msiq_id); 698 699 if ((ret = hvio_msiq_getvalid(DIP_TO_HANDLE(dip), 700 msiq_id, msiq_valid_state)) != H_EOK) { 701 DBG(DBG_LIB_MSIQ, dip, 702 "hvio_msiq_getvalid failed, ret 0x%lx\n", ret); 703 return (DDI_FAILURE); 704 } 705 706 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: msiq_valid_state 0x%x\n", 707 *msiq_valid_state); 708 709 return (DDI_SUCCESS); 710 } 711 712 /*ARGSUSED*/ 713 int 714 px_lib_msiq_setvalid(dev_info_t *dip, msiqid_t msiq_id, 715 pci_msiq_valid_state_t msiq_valid_state) 716 { 717 uint64_t ret; 718 719 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setvalid: dip 0x%p msiq_id 0x%x " 720 "msiq_valid_state 0x%x\n", dip, msiq_id, msiq_valid_state); 721 722 if ((ret = hvio_msiq_setvalid(DIP_TO_HANDLE(dip), 723 msiq_id, msiq_valid_state)) != H_EOK) { 724 DBG(DBG_LIB_MSIQ, dip, 725 "hvio_msiq_setvalid failed, ret 0x%lx\n", ret); 726 return (DDI_FAILURE); 727 } 728 729 return (DDI_SUCCESS); 730 } 731 732 /*ARGSUSED*/ 733 int 734 px_lib_msiq_getstate(dev_info_t *dip, msiqid_t msiq_id, 735 pci_msiq_state_t *msiq_state) 736 { 737 uint64_t ret; 738 739 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: dip 0x%p msiq_id 0x%x\n", 740 dip, msiq_id); 741 742 if ((ret = hvio_msiq_getstate(DIP_TO_HANDLE(dip), 743 msiq_id, msiq_state)) != H_EOK) { 744 DBG(DBG_LIB_MSIQ, dip, 745 "hvio_msiq_getstate failed, ret 0x%lx\n", ret); 746 return (DDI_FAILURE); 747 } 748 749 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: msiq_state 0x%x\n", 750 *msiq_state); 751 752 return (DDI_SUCCESS); 753 } 754 755 /*ARGSUSED*/ 756 int 757 px_lib_msiq_setstate(dev_info_t *dip, msiqid_t msiq_id, 758 pci_msiq_state_t msiq_state) 759 { 760 uint64_t ret; 761 762 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setstate: dip 0x%p msiq_id 0x%x " 763 "msiq_state 0x%x\n", dip, msiq_id, msiq_state); 764 765 if ((ret = hvio_msiq_setstate(DIP_TO_HANDLE(dip), 766 msiq_id, msiq_state)) != H_EOK) { 767 DBG(DBG_LIB_MSIQ, dip, 768 "hvio_msiq_setstate failed, ret 0x%lx\n", ret); 769 return (DDI_FAILURE); 770 } 771 772 return (DDI_SUCCESS); 773 } 774 775 /*ARGSUSED*/ 776 int 777 px_lib_msiq_gethead(dev_info_t *dip, msiqid_t msiq_id, 778 msiqhead_t *msiq_head_p) 779 { 780 uint64_t ret; 781 782 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gethead: dip 0x%p msiq_id 0x%x\n", 783 dip, msiq_id); 784 785 if ((ret = hvio_msiq_gethead(DIP_TO_HANDLE(dip), 786 msiq_id, msiq_head_p)) != H_EOK) { 787 DBG(DBG_LIB_MSIQ, dip, 788 "hvio_msiq_gethead failed, ret 0x%lx\n", ret); 789 return (DDI_FAILURE); 790 } 791 792 *msiq_head_p = (*msiq_head_p / sizeof (msiq_rec_t)); 793 794 DBG(DBG_LIB_MSIQ, dip, "px_msiq_gethead: msiq_head 0x%x\n", 795 *msiq_head_p); 796 797 return (DDI_SUCCESS); 798 } 799 800 /*ARGSUSED*/ 801 int 802 px_lib_msiq_sethead(dev_info_t *dip, msiqid_t msiq_id, 803 msiqhead_t msiq_head) 804 { 805 uint64_t ret; 806 807 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_sethead: dip 0x%p msiq_id 0x%x " 808 "msiq_head 0x%x\n", dip, msiq_id, msiq_head); 809 810 if ((ret = hvio_msiq_sethead(DIP_TO_HANDLE(dip), 811 msiq_id, msiq_head * sizeof (msiq_rec_t))) != H_EOK) { 812 DBG(DBG_LIB_MSIQ, dip, 813 "hvio_msiq_sethead failed, ret 0x%lx\n", ret); 814 return (DDI_FAILURE); 815 } 816 817 return (DDI_SUCCESS); 818 } 819 820 /*ARGSUSED*/ 821 int 822 px_lib_msiq_gettail(dev_info_t *dip, msiqid_t msiq_id, 823 msiqtail_t *msiq_tail_p) 824 { 825 uint64_t ret; 826 827 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: dip 0x%p msiq_id 0x%x\n", 828 dip, msiq_id); 829 830 if ((ret = hvio_msiq_gettail(DIP_TO_HANDLE(dip), 831 msiq_id, msiq_tail_p)) != H_EOK) { 832 DBG(DBG_LIB_MSIQ, dip, 833 "hvio_msiq_gettail failed, ret 0x%lx\n", ret); 834 return (DDI_FAILURE); 835 } 836 837 *msiq_tail_p = (*msiq_tail_p / sizeof (msiq_rec_t)); 838 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: msiq_tail 0x%x\n", 839 *msiq_tail_p); 840 841 return (DDI_SUCCESS); 842 } 843 844 /*ARGSUSED*/ 845 void 846 px_lib_get_msiq_rec(dev_info_t *dip, msiqhead_t *msiq_head_p, 847 msiq_rec_t *msiq_rec_p) 848 { 849 msiq_rec_t *curr_msiq_rec_p = (msiq_rec_t *)msiq_head_p; 850 851 DBG(DBG_LIB_MSIQ, dip, "px_lib_get_msiq_rec: dip 0x%p\n", dip); 852 853 if (!curr_msiq_rec_p->msiq_rec_type) { 854 /* Set msiq_rec_type to zero */ 855 msiq_rec_p->msiq_rec_type = 0; 856 857 return; 858 } 859 860 *msiq_rec_p = *curr_msiq_rec_p; 861 } 862 863 /*ARGSUSED*/ 864 void 865 px_lib_clr_msiq_rec(dev_info_t *dip, msiqhead_t *msiq_head_p) 866 { 867 msiq_rec_t *curr_msiq_rec_p = (msiq_rec_t *)msiq_head_p; 868 869 DBG(DBG_LIB_MSIQ, dip, "px_lib_clr_msiq_rec: dip 0x%p\n", dip); 870 871 /* Zero out msiq_rec_type field */ 872 curr_msiq_rec_p->msiq_rec_type = 0; 873 } 874 875 /* 876 * MSI Functions: 877 */ 878 879 /*ARGSUSED*/ 880 int 881 px_lib_msi_init(dev_info_t *dip) 882 { 883 DBG(DBG_LIB_MSI, dip, "px_lib_msi_init: dip 0x%p\n", dip); 884 885 /* Noop */ 886 return (DDI_SUCCESS); 887 } 888 889 /*ARGSUSED*/ 890 int 891 px_lib_msi_getmsiq(dev_info_t *dip, msinum_t msi_num, 892 msiqid_t *msiq_id) 893 { 894 uint64_t ret; 895 896 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: dip 0x%p msi_num 0x%x\n", 897 dip, msi_num); 898 899 if ((ret = hvio_msi_getmsiq(DIP_TO_HANDLE(dip), 900 msi_num, msiq_id)) != H_EOK) { 901 DBG(DBG_LIB_MSI, dip, 902 "hvio_msi_getmsiq failed, ret 0x%lx\n", ret); 903 return (DDI_FAILURE); 904 } 905 906 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: msiq_id 0x%x\n", 907 *msiq_id); 908 909 return (DDI_SUCCESS); 910 } 911 912 /*ARGSUSED*/ 913 int 914 px_lib_msi_setmsiq(dev_info_t *dip, msinum_t msi_num, 915 msiqid_t msiq_id, msi_type_t msitype) 916 { 917 uint64_t ret; 918 919 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setmsiq: dip 0x%p msi_num 0x%x " 920 "msq_id 0x%x\n", dip, msi_num, msiq_id); 921 922 if ((ret = hvio_msi_setmsiq(DIP_TO_HANDLE(dip), 923 msi_num, msiq_id, msitype)) != H_EOK) { 924 DBG(DBG_LIB_MSI, dip, 925 "hvio_msi_setmsiq failed, ret 0x%lx\n", ret); 926 return (DDI_FAILURE); 927 } 928 929 return (DDI_SUCCESS); 930 } 931 932 /*ARGSUSED*/ 933 int 934 px_lib_msi_getvalid(dev_info_t *dip, msinum_t msi_num, 935 pci_msi_valid_state_t *msi_valid_state) 936 { 937 uint64_t ret; 938 939 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: dip 0x%p msi_num 0x%x\n", 940 dip, msi_num); 941 942 if ((ret = hvio_msi_getvalid(DIP_TO_HANDLE(dip), 943 msi_num, msi_valid_state)) != H_EOK) { 944 DBG(DBG_LIB_MSI, dip, 945 "hvio_msi_getvalid failed, ret 0x%lx\n", ret); 946 return (DDI_FAILURE); 947 } 948 949 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: msiq_id 0x%x\n", 950 *msi_valid_state); 951 952 return (DDI_SUCCESS); 953 } 954 955 /*ARGSUSED*/ 956 int 957 px_lib_msi_setvalid(dev_info_t *dip, msinum_t msi_num, 958 pci_msi_valid_state_t msi_valid_state) 959 { 960 uint64_t ret; 961 962 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setvalid: dip 0x%p msi_num 0x%x " 963 "msi_valid_state 0x%x\n", dip, msi_num, msi_valid_state); 964 965 if ((ret = hvio_msi_setvalid(DIP_TO_HANDLE(dip), 966 msi_num, msi_valid_state)) != H_EOK) { 967 DBG(DBG_LIB_MSI, dip, 968 "hvio_msi_setvalid failed, ret 0x%lx\n", ret); 969 return (DDI_FAILURE); 970 } 971 972 return (DDI_SUCCESS); 973 } 974 975 /*ARGSUSED*/ 976 int 977 px_lib_msi_getstate(dev_info_t *dip, msinum_t msi_num, 978 pci_msi_state_t *msi_state) 979 { 980 uint64_t ret; 981 982 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: dip 0x%p msi_num 0x%x\n", 983 dip, msi_num); 984 985 if ((ret = hvio_msi_getstate(DIP_TO_HANDLE(dip), 986 msi_num, msi_state)) != H_EOK) { 987 DBG(DBG_LIB_MSI, dip, 988 "hvio_msi_getstate failed, ret 0x%lx\n", ret); 989 return (DDI_FAILURE); 990 } 991 992 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: msi_state 0x%x\n", 993 *msi_state); 994 995 return (DDI_SUCCESS); 996 } 997 998 /*ARGSUSED*/ 999 int 1000 px_lib_msi_setstate(dev_info_t *dip, msinum_t msi_num, 1001 pci_msi_state_t msi_state) 1002 { 1003 uint64_t ret; 1004 1005 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setstate: dip 0x%p msi_num 0x%x " 1006 "msi_state 0x%x\n", dip, msi_num, msi_state); 1007 1008 if ((ret = hvio_msi_setstate(DIP_TO_HANDLE(dip), 1009 msi_num, msi_state)) != H_EOK) { 1010 DBG(DBG_LIB_MSI, dip, 1011 "hvio_msi_setstate failed, ret 0x%lx\n", ret); 1012 return (DDI_FAILURE); 1013 } 1014 1015 return (DDI_SUCCESS); 1016 } 1017 1018 /* 1019 * MSG Functions: 1020 */ 1021 1022 /*ARGSUSED*/ 1023 int 1024 px_lib_msg_getmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 1025 msiqid_t *msiq_id) 1026 { 1027 uint64_t ret; 1028 1029 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getmsiq: dip 0x%p msg_type 0x%x\n", 1030 dip, msg_type); 1031 1032 if ((ret = hvio_msg_getmsiq(DIP_TO_HANDLE(dip), 1033 msg_type, msiq_id)) != H_EOK) { 1034 DBG(DBG_LIB_MSG, dip, 1035 "hvio_msg_getmsiq failed, ret 0x%lx\n", ret); 1036 return (DDI_FAILURE); 1037 } 1038 1039 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getmsiq: msiq_id 0x%x\n", 1040 *msiq_id); 1041 1042 return (DDI_SUCCESS); 1043 } 1044 1045 /*ARGSUSED*/ 1046 int 1047 px_lib_msg_setmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 1048 msiqid_t msiq_id) 1049 { 1050 uint64_t ret; 1051 1052 DBG(DBG_LIB_MSG, dip, "px_lib_msg_setmsiq: dip 0x%p msg_type 0x%x " 1053 "msq_id 0x%x\n", dip, msg_type, msiq_id); 1054 1055 if ((ret = hvio_msg_setmsiq(DIP_TO_HANDLE(dip), 1056 msg_type, msiq_id)) != H_EOK) { 1057 DBG(DBG_LIB_MSG, dip, 1058 "hvio_msg_setmsiq failed, ret 0x%lx\n", ret); 1059 return (DDI_FAILURE); 1060 } 1061 1062 return (DDI_SUCCESS); 1063 } 1064 1065 /*ARGSUSED*/ 1066 int 1067 px_lib_msg_getvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 1068 pcie_msg_valid_state_t *msg_valid_state) 1069 { 1070 uint64_t ret; 1071 1072 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getvalid: dip 0x%p msg_type 0x%x\n", 1073 dip, msg_type); 1074 1075 if ((ret = hvio_msg_getvalid(DIP_TO_HANDLE(dip), msg_type, 1076 msg_valid_state)) != H_EOK) { 1077 DBG(DBG_LIB_MSG, dip, 1078 "hvio_msg_getvalid failed, ret 0x%lx\n", ret); 1079 return (DDI_FAILURE); 1080 } 1081 1082 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getvalid: msg_valid_state 0x%x\n", 1083 *msg_valid_state); 1084 1085 return (DDI_SUCCESS); 1086 } 1087 1088 /*ARGSUSED*/ 1089 int 1090 px_lib_msg_setvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 1091 pcie_msg_valid_state_t msg_valid_state) 1092 { 1093 uint64_t ret; 1094 1095 DBG(DBG_LIB_MSG, dip, "px_lib_msg_setvalid: dip 0x%p msg_type 0x%x " 1096 "msg_valid_state 0x%x\n", dip, msg_type, msg_valid_state); 1097 1098 if ((ret = hvio_msg_setvalid(DIP_TO_HANDLE(dip), msg_type, 1099 msg_valid_state)) != H_EOK) { 1100 DBG(DBG_LIB_MSG, dip, 1101 "hvio_msg_setvalid failed, ret 0x%lx\n", ret); 1102 return (DDI_FAILURE); 1103 } 1104 1105 return (DDI_SUCCESS); 1106 } 1107 1108 /* 1109 * Suspend/Resume Functions: 1110 * Currently unsupported by hypervisor and all functions are noops. 1111 */ 1112 /*ARGSUSED*/ 1113 int 1114 px_lib_suspend(dev_info_t *dip) 1115 { 1116 DBG(DBG_ATTACH, dip, "px_lib_suspend: Not supported\n"); 1117 1118 /* Not supported */ 1119 return (DDI_FAILURE); 1120 } 1121 1122 /*ARGSUSED*/ 1123 void 1124 px_lib_resume(dev_info_t *dip) 1125 { 1126 DBG(DBG_ATTACH, dip, "px_lib_resume: Not supported\n"); 1127 1128 /* Noop */ 1129 } 1130 1131 /* 1132 * Misc Functions: 1133 * Currently unsupported by hypervisor and all functions are noops. 1134 */ 1135 /*ARGSUSED*/ 1136 static int 1137 px_lib_config_get(dev_info_t *dip, pci_device_t bdf, pci_config_offset_t off, 1138 uint8_t size, pci_cfg_data_t *data_p) 1139 { 1140 uint64_t ret; 1141 1142 DBG(DBG_LIB_CFG, dip, "px_lib_config_get: dip 0x%p, bdf 0x%llx " 1143 "off 0x%x size 0x%x\n", dip, bdf, off, size); 1144 1145 if ((ret = hvio_config_get(DIP_TO_HANDLE(dip), bdf, off, 1146 size, data_p)) != H_EOK) { 1147 DBG(DBG_LIB_CFG, dip, 1148 "hvio_config_get failed, ret 0x%lx\n", ret); 1149 return (DDI_FAILURE); 1150 } 1151 DBG(DBG_LIB_CFG, dip, "px_config_get: data 0x%x\n", data_p->dw); 1152 1153 return (DDI_SUCCESS); 1154 } 1155 1156 /*ARGSUSED*/ 1157 static int 1158 px_lib_config_put(dev_info_t *dip, pci_device_t bdf, pci_config_offset_t off, 1159 uint8_t size, pci_cfg_data_t data) 1160 { 1161 uint64_t ret; 1162 1163 DBG(DBG_LIB_CFG, dip, "px_lib_config_put: dip 0x%p, bdf 0x%llx " 1164 "off 0x%x size 0x%x data 0x%llx\n", dip, bdf, off, size, data.qw); 1165 1166 if ((ret = hvio_config_put(DIP_TO_HANDLE(dip), bdf, off, 1167 size, data)) != H_EOK) { 1168 DBG(DBG_LIB_CFG, dip, 1169 "hvio_config_put failed, ret 0x%lx\n", ret); 1170 return (DDI_FAILURE); 1171 } 1172 1173 return (DDI_SUCCESS); 1174 } 1175 1176 static uint32_t 1177 px_pci_config_get(ddi_acc_impl_t *handle, uint32_t *addr, int size) 1178 { 1179 px_config_acc_pvt_t *px_pvt = (px_config_acc_pvt_t *) 1180 handle->ahi_common.ah_bus_private; 1181 uint32_t pci_dev_addr = px_pvt->raddr; 1182 uint32_t vaddr = px_pvt->vaddr; 1183 uint16_t off = (uint16_t)(uintptr_t)(addr - vaddr) & 0xfff; 1184 uint32_t rdata = 0; 1185 1186 if (px_lib_config_get(px_pvt->dip, pci_dev_addr, off, 1187 size, (pci_cfg_data_t *)&rdata) != DDI_SUCCESS) 1188 /* XXX update error kstats */ 1189 return (0xffffffff); 1190 return (rdata); 1191 } 1192 1193 static void 1194 px_pci_config_put(ddi_acc_impl_t *handle, uint32_t *addr, 1195 int size, pci_cfg_data_t wdata) 1196 { 1197 px_config_acc_pvt_t *px_pvt = (px_config_acc_pvt_t *) 1198 handle->ahi_common.ah_bus_private; 1199 uint32_t pci_dev_addr = px_pvt->raddr; 1200 uint32_t vaddr = px_pvt->vaddr; 1201 uint16_t off = (uint16_t)(uintptr_t)(addr - vaddr) & 0xfff; 1202 1203 if (px_lib_config_put(px_pvt->dip, pci_dev_addr, off, 1204 size, wdata) != DDI_SUCCESS) { 1205 /*EMPTY*/ 1206 /* XXX update error kstats */ 1207 } 1208 } 1209 1210 static uint8_t 1211 px_pci_config_get8(ddi_acc_impl_t *handle, uint8_t *addr) 1212 { 1213 return ((uint8_t)px_pci_config_get(handle, (uint32_t *)addr, 1)); 1214 } 1215 1216 static uint16_t 1217 px_pci_config_get16(ddi_acc_impl_t *handle, uint16_t *addr) 1218 { 1219 return ((uint16_t)px_pci_config_get(handle, (uint32_t *)addr, 2)); 1220 } 1221 1222 static uint32_t 1223 px_pci_config_get32(ddi_acc_impl_t *handle, uint32_t *addr) 1224 { 1225 return ((uint32_t)px_pci_config_get(handle, (uint32_t *)addr, 4)); 1226 } 1227 1228 static uint64_t 1229 px_pci_config_get64(ddi_acc_impl_t *handle, uint64_t *addr) 1230 { 1231 uint32_t rdatah, rdatal; 1232 1233 rdatal = (uint32_t)px_pci_config_get(handle, (uint32_t *)addr, 4); 1234 rdatah = (uint32_t)px_pci_config_get(handle, 1235 (uint32_t *)((char *)addr+4), 4); 1236 return (((uint64_t)rdatah << 32) | rdatal); 1237 } 1238 1239 static void 1240 px_pci_config_put8(ddi_acc_impl_t *handle, uint8_t *addr, uint8_t data) 1241 { 1242 pci_cfg_data_t wdata = { 0 }; 1243 1244 wdata.qw = (uint8_t)data; 1245 px_pci_config_put(handle, (uint32_t *)addr, 1, wdata); 1246 } 1247 1248 static void 1249 px_pci_config_put16(ddi_acc_impl_t *handle, uint16_t *addr, uint16_t data) 1250 { 1251 pci_cfg_data_t wdata = { 0 }; 1252 1253 wdata.qw = (uint16_t)data; 1254 px_pci_config_put(handle, (uint32_t *)addr, 2, wdata); 1255 } 1256 1257 static void 1258 px_pci_config_put32(ddi_acc_impl_t *handle, uint32_t *addr, uint32_t data) 1259 { 1260 pci_cfg_data_t wdata = { 0 }; 1261 1262 wdata.qw = (uint32_t)data; 1263 px_pci_config_put(handle, (uint32_t *)addr, 4, wdata); 1264 } 1265 1266 static void 1267 px_pci_config_put64(ddi_acc_impl_t *handle, uint64_t *addr, uint64_t data) 1268 { 1269 pci_cfg_data_t wdata = { 0 }; 1270 1271 wdata.qw = (uint32_t)(data & 0xffffffff); 1272 px_pci_config_put(handle, (uint32_t *)addr, 4, wdata); 1273 wdata.qw = (uint32_t)((data >> 32) & 0xffffffff); 1274 px_pci_config_put(handle, (uint32_t *)((char *)addr+4), 4, wdata); 1275 } 1276 1277 static void 1278 px_pci_config_rep_get8(ddi_acc_impl_t *handle, uint8_t *host_addr, 1279 uint8_t *dev_addr, size_t repcount, uint_t flags) 1280 { 1281 if (flags == DDI_DEV_AUTOINCR) 1282 for (; repcount; repcount--) 1283 *host_addr++ = px_pci_config_get8(handle, dev_addr++); 1284 else 1285 for (; repcount; repcount--) 1286 *host_addr++ = px_pci_config_get8(handle, dev_addr); 1287 } 1288 1289 /* 1290 * Function to rep read 16 bit data off the PCI configuration space behind 1291 * the 21554's host interface. 1292 */ 1293 static void 1294 px_pci_config_rep_get16(ddi_acc_impl_t *handle, uint16_t *host_addr, 1295 uint16_t *dev_addr, size_t repcount, uint_t flags) 1296 { 1297 if (flags == DDI_DEV_AUTOINCR) 1298 for (; repcount; repcount--) 1299 *host_addr++ = px_pci_config_get16(handle, dev_addr++); 1300 else 1301 for (; repcount; repcount--) 1302 *host_addr++ = px_pci_config_get16(handle, dev_addr); 1303 } 1304 1305 /* 1306 * Function to rep read 32 bit data off the PCI configuration space behind 1307 * the 21554's host interface. 1308 */ 1309 static void 1310 px_pci_config_rep_get32(ddi_acc_impl_t *handle, uint32_t *host_addr, 1311 uint32_t *dev_addr, size_t repcount, uint_t flags) 1312 { 1313 if (flags == DDI_DEV_AUTOINCR) 1314 for (; repcount; repcount--) 1315 *host_addr++ = px_pci_config_get32(handle, dev_addr++); 1316 else 1317 for (; repcount; repcount--) 1318 *host_addr++ = px_pci_config_get32(handle, dev_addr); 1319 } 1320 1321 /* 1322 * Function to rep read 64 bit data off the PCI configuration space behind 1323 * the 21554's host interface. 1324 */ 1325 static void 1326 px_pci_config_rep_get64(ddi_acc_impl_t *handle, uint64_t *host_addr, 1327 uint64_t *dev_addr, size_t repcount, uint_t flags) 1328 { 1329 if (flags == DDI_DEV_AUTOINCR) 1330 for (; repcount; repcount--) 1331 *host_addr++ = px_pci_config_get64(handle, dev_addr++); 1332 else 1333 for (; repcount; repcount--) 1334 *host_addr++ = px_pci_config_get64(handle, dev_addr); 1335 } 1336 1337 /* 1338 * Function to rep write 8 bit data into the PCI configuration space behind 1339 * the 21554's host interface. 1340 */ 1341 static void 1342 px_pci_config_rep_put8(ddi_acc_impl_t *handle, uint8_t *host_addr, 1343 uint8_t *dev_addr, size_t repcount, uint_t flags) 1344 { 1345 if (flags == DDI_DEV_AUTOINCR) 1346 for (; repcount; repcount--) 1347 px_pci_config_put8(handle, dev_addr++, *host_addr++); 1348 else 1349 for (; repcount; repcount--) 1350 px_pci_config_put8(handle, dev_addr, *host_addr++); 1351 } 1352 1353 /* 1354 * Function to rep write 16 bit data into the PCI configuration space behind 1355 * the 21554's host interface. 1356 */ 1357 static void 1358 px_pci_config_rep_put16(ddi_acc_impl_t *handle, uint16_t *host_addr, 1359 uint16_t *dev_addr, size_t repcount, uint_t flags) 1360 { 1361 if (flags == DDI_DEV_AUTOINCR) 1362 for (; repcount; repcount--) 1363 px_pci_config_put16(handle, dev_addr++, *host_addr++); 1364 else 1365 for (; repcount; repcount--) 1366 px_pci_config_put16(handle, dev_addr, *host_addr++); 1367 } 1368 1369 /* 1370 * Function to rep write 32 bit data into the PCI configuration space behind 1371 * the 21554's host interface. 1372 */ 1373 static void 1374 px_pci_config_rep_put32(ddi_acc_impl_t *handle, uint32_t *host_addr, 1375 uint32_t *dev_addr, size_t repcount, uint_t flags) 1376 { 1377 if (flags == DDI_DEV_AUTOINCR) 1378 for (; repcount; repcount--) 1379 px_pci_config_put32(handle, dev_addr++, *host_addr++); 1380 else 1381 for (; repcount; repcount--) 1382 px_pci_config_put32(handle, dev_addr, *host_addr++); 1383 } 1384 1385 /* 1386 * Function to rep write 64 bit data into the PCI configuration space behind 1387 * the 21554's host interface. 1388 */ 1389 static void 1390 px_pci_config_rep_put64(ddi_acc_impl_t *handle, uint64_t *host_addr, 1391 uint64_t *dev_addr, size_t repcount, uint_t flags) 1392 { 1393 if (flags == DDI_DEV_AUTOINCR) 1394 for (; repcount; repcount--) 1395 px_pci_config_put64(handle, dev_addr++, *host_addr++); 1396 else 1397 for (; repcount; repcount--) 1398 px_pci_config_put64(handle, dev_addr, *host_addr++); 1399 } 1400 1401 /* 1402 * Provide a private access handle to route config access calls to Hypervisor. 1403 * Beware: Do all error checking for config space accesses before calling 1404 * this function. ie. do error checking from the calling function. 1405 * Due to a lack of meaningful error code in DDI, the gauranteed return of 1406 * DDI_SUCCESS from here makes the code organization readable/easier from 1407 * the generic code. 1408 */ 1409 /*ARGSUSED*/ 1410 int 1411 px_lib_map_vconfig(dev_info_t *dip, 1412 ddi_map_req_t *mp, pci_config_offset_t off, 1413 pci_regspec_t *rp, caddr_t *addrp) 1414 { 1415 int fmcap; 1416 ndi_err_t *errp; 1417 on_trap_data_t *otp; 1418 ddi_acc_hdl_t *hp; 1419 ddi_acc_impl_t *ap; 1420 uchar_t busnum; /* bus number */ 1421 uchar_t devnum; /* device number */ 1422 uchar_t funcnum; /* function number */ 1423 px_config_acc_pvt_t *px_pvt; 1424 1425 hp = (ddi_acc_hdl_t *)mp->map_handlep; 1426 ap = (ddi_acc_impl_t *)hp->ah_platform_private; 1427 1428 /* Check for mapping teardown operation */ 1429 if ((mp->map_op == DDI_MO_UNMAP) || 1430 (mp->map_op == DDI_MO_UNLOCK)) { 1431 /* free up memory allocated for the private access handle. */ 1432 px_pvt = (px_config_acc_pvt_t *)hp->ah_bus_private; 1433 kmem_free((void *)px_pvt, sizeof (px_config_acc_pvt_t)); 1434 1435 /* unmap operation of PCI IO/config space. */ 1436 return (DDI_SUCCESS); 1437 } 1438 1439 fmcap = ddi_fm_capable(dip); 1440 if (DDI_FM_ACC_ERR_CAP(fmcap)) { 1441 errp = ((ddi_acc_impl_t *)hp)->ahi_err; 1442 otp = (on_trap_data_t *)errp->err_ontrap; 1443 otp->ot_handle = (void *)(hp); 1444 otp->ot_prot = OT_DATA_ACCESS; 1445 errp->err_status = DDI_FM_OK; 1446 errp->err_expected = DDI_FM_ERR_UNEXPECTED; 1447 errp->err_cf = px_err_cfg_hdl_check; 1448 } 1449 1450 ap->ahi_get8 = px_pci_config_get8; 1451 ap->ahi_get16 = px_pci_config_get16; 1452 ap->ahi_get32 = px_pci_config_get32; 1453 ap->ahi_get64 = px_pci_config_get64; 1454 ap->ahi_put8 = px_pci_config_put8; 1455 ap->ahi_put16 = px_pci_config_put16; 1456 ap->ahi_put32 = px_pci_config_put32; 1457 ap->ahi_put64 = px_pci_config_put64; 1458 ap->ahi_rep_get8 = px_pci_config_rep_get8; 1459 ap->ahi_rep_get16 = px_pci_config_rep_get16; 1460 ap->ahi_rep_get32 = px_pci_config_rep_get32; 1461 ap->ahi_rep_get64 = px_pci_config_rep_get64; 1462 ap->ahi_rep_put8 = px_pci_config_rep_put8; 1463 ap->ahi_rep_put16 = px_pci_config_rep_put16; 1464 ap->ahi_rep_put32 = px_pci_config_rep_put32; 1465 ap->ahi_rep_put64 = px_pci_config_rep_put64; 1466 1467 /* Initialize to default check/notify functions */ 1468 ap->ahi_fault = 0; 1469 ap->ahi_fault_check = i_ddi_acc_fault_check; 1470 ap->ahi_fault_notify = i_ddi_acc_fault_notify; 1471 1472 /* allocate memory for our private handle */ 1473 px_pvt = (px_config_acc_pvt_t *) 1474 kmem_zalloc(sizeof (px_config_acc_pvt_t), KM_SLEEP); 1475 hp->ah_bus_private = (void *)px_pvt; 1476 1477 busnum = PCI_REG_BUS_G(rp->pci_phys_hi); 1478 devnum = PCI_REG_DEV_G(rp->pci_phys_hi); 1479 funcnum = PCI_REG_FUNC_G(rp->pci_phys_hi); 1480 1481 /* set up private data for use during IO routines */ 1482 1483 /* addr needed by the HV APIs */ 1484 px_pvt->raddr = busnum << 16 | devnum << 11 | funcnum << 8; 1485 /* 1486 * Address that specifies the actual offset into the 256MB 1487 * memory mapped configuration space, 4K per device. 1488 * First 12bits form the offset into 4K config space. 1489 * This address is only used during the IO routines to calculate 1490 * the offset at which the transaction must be performed. 1491 * Drivers bypassing DDI functions to access PCI config space will 1492 * panic the system since the following is a bogus virtual address. 1493 */ 1494 px_pvt->vaddr = busnum << 20 | devnum << 15 | funcnum << 12 | off; 1495 px_pvt->dip = dip; 1496 1497 DBG(DBG_LIB_CFG, dip, "px_config_setup: raddr 0x%x, vaddr 0x%x\n", 1498 px_pvt->raddr, px_pvt->vaddr); 1499 *addrp = (caddr_t)(uintptr_t)px_pvt->vaddr; 1500 return (DDI_SUCCESS); 1501 } 1502 1503 /*ARGSUSED*/ 1504 void 1505 px_lib_map_attr_check(ddi_map_req_t *mp) 1506 { 1507 } 1508 1509 /* 1510 * px_lib_log_safeacc_err: 1511 * Imitate a cpu/mem trap call when a peek/poke fails. 1512 * This will initiate something similar to px_fm_callback. 1513 */ 1514 static void 1515 px_lib_log_safeacc_err(px_t *px_p, ddi_acc_handle_t handle, int fme_flag, 1516 r_addr_t addr) 1517 { 1518 uint32_t addr_high, addr_low; 1519 pcie_req_id_t bdf; 1520 px_ranges_t *ranges_p; 1521 int range_len, i; 1522 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)handle; 1523 ddi_fm_error_t derr; 1524 1525 derr.fme_status = DDI_FM_NONFATAL; 1526 derr.fme_version = DDI_FME_VERSION; 1527 derr.fme_flag = fme_flag; 1528 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 1529 derr.fme_acc_handle = handle; 1530 if (hp) 1531 hp->ahi_err->err_expected = DDI_FM_ERR_EXPECTED; 1532 1533 addr_high = (uint32_t)(addr >> 32); 1534 addr_low = (uint32_t)addr; 1535 1536 /* 1537 * Make sure this failed load came from this PCIe port. Check by 1538 * matching the upper 32 bits of the address with the ranges property. 1539 */ 1540 range_len = px_p->px_ranges_length / sizeof (px_ranges_t); 1541 i = 0; 1542 for (ranges_p = px_p->px_ranges_p; i < range_len; i++, ranges_p++) { 1543 if (ranges_p->parent_high == addr_high) { 1544 switch (ranges_p->child_high & PCI_ADDR_MASK) { 1545 case PCI_ADDR_CONFIG: 1546 bdf = (pcie_req_id_t)(addr_low >> 12); 1547 break; 1548 default: 1549 bdf = NULL; 1550 break; 1551 } 1552 break; 1553 } 1554 } 1555 1556 px_rp_en_q(px_p, bdf, addr, NULL); 1557 1558 if (px_fm_enter(px_p) == DDI_SUCCESS) { 1559 (void) px_scan_fabric(px_p, px_p->px_dip, &derr); 1560 px_fm_exit(px_p); 1561 } 1562 } 1563 1564 1565 #ifdef DEBUG 1566 int px_peekfault_cnt = 0; 1567 int px_pokefault_cnt = 0; 1568 #endif /* DEBUG */ 1569 1570 /* 1571 * Do a safe write to a device. 1572 * 1573 * When this function is given a handle (cautious access), all errors are 1574 * suppressed. 1575 * 1576 * When this function is not given a handle (poke), only Unsupported Request 1577 * and Completer Abort errors are suppressed. 1578 * 1579 * In all cases, all errors are returned in the function return status. 1580 */ 1581 1582 int 1583 px_lib_ctlops_poke(dev_info_t *dip, dev_info_t *rdip, 1584 peekpoke_ctlops_t *in_args) 1585 { 1586 px_t *px_p = DIP_TO_STATE(dip); 1587 px_pec_t *pec_p = px_p->px_pec_p; 1588 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)in_args->handle; 1589 1590 size_t repcount = in_args->repcount; 1591 size_t size = in_args->size; 1592 uintptr_t dev_addr = in_args->dev_addr; 1593 uintptr_t host_addr = in_args->host_addr; 1594 1595 int err = DDI_SUCCESS; 1596 uint64_t hvio_poke_status; 1597 uint32_t wrt_stat; 1598 1599 r_addr_t ra; 1600 uint64_t pokeval; 1601 pcie_req_id_t bdf; 1602 1603 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1604 for (; repcount; repcount--) { 1605 1606 switch (size) { 1607 case sizeof (uint8_t): 1608 pokeval = *(uint8_t *)host_addr; 1609 break; 1610 case sizeof (uint16_t): 1611 pokeval = *(uint16_t *)host_addr; 1612 break; 1613 case sizeof (uint32_t): 1614 pokeval = *(uint32_t *)host_addr; 1615 break; 1616 case sizeof (uint64_t): 1617 pokeval = *(uint64_t *)host_addr; 1618 break; 1619 default: 1620 DBG(DBG_MAP, px_p->px_dip, 1621 "poke: invalid size %d passed\n", size); 1622 err = DDI_FAILURE; 1623 goto done; 1624 } 1625 1626 /* 1627 * Grab pokefault mutex since hypervisor does not guarantee 1628 * poke serialization. 1629 */ 1630 if (hp) { 1631 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, 1632 (ddi_acc_handle_t)hp); 1633 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1634 } else { 1635 mutex_enter(&pec_p->pec_pokefault_mutex); 1636 pec_p->pec_safeacc_type = DDI_FM_ERR_POKE; 1637 } 1638 1639 if (pcie_get_bdf_from_dip(rdip, &bdf) != DDI_SUCCESS) { 1640 err = DDI_FAILURE; 1641 goto done; 1642 } 1643 1644 hvio_poke_status = hvio_poke(px_p->px_dev_hdl, ra, size, 1645 pokeval, bdf << 8, &wrt_stat); 1646 1647 if ((hvio_poke_status != H_EOK) || (wrt_stat != H_EOK)) { 1648 err = DDI_FAILURE; 1649 #ifdef DEBUG 1650 px_pokefault_cnt++; 1651 #endif 1652 /* 1653 * For CAUTIOUS and POKE access, notify FMA to 1654 * cleanup. Imitate a cpu/mem trap call like in sun4u. 1655 */ 1656 px_lib_log_safeacc_err(px_p, (ddi_acc_handle_t)hp, 1657 (hp ? DDI_FM_ERR_EXPECTED : 1658 DDI_FM_ERR_POKE), ra); 1659 1660 pec_p->pec_ontrap_data = NULL; 1661 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1662 if (hp) { 1663 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1664 (ddi_acc_handle_t)hp); 1665 } else { 1666 mutex_exit(&pec_p->pec_pokefault_mutex); 1667 } 1668 goto done; 1669 } 1670 1671 pec_p->pec_ontrap_data = NULL; 1672 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1673 if (hp) { 1674 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1675 (ddi_acc_handle_t)hp); 1676 } else { 1677 mutex_exit(&pec_p->pec_pokefault_mutex); 1678 } 1679 1680 host_addr += size; 1681 1682 if (in_args->flags == DDI_DEV_AUTOINCR) { 1683 dev_addr += size; 1684 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1685 } 1686 } 1687 1688 done: 1689 return (err); 1690 } 1691 1692 1693 /*ARGSUSED*/ 1694 int 1695 px_lib_ctlops_peek(dev_info_t *dip, dev_info_t *rdip, 1696 peekpoke_ctlops_t *in_args, void *result) 1697 { 1698 px_t *px_p = DIP_TO_STATE(dip); 1699 px_pec_t *pec_p = px_p->px_pec_p; 1700 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)in_args->handle; 1701 1702 size_t repcount = in_args->repcount; 1703 uintptr_t dev_addr = in_args->dev_addr; 1704 uintptr_t host_addr = in_args->host_addr; 1705 1706 r_addr_t ra; 1707 uint32_t read_status; 1708 uint64_t hvio_peek_status; 1709 uint64_t peekval; 1710 int err = DDI_SUCCESS; 1711 1712 result = (void *)in_args->host_addr; 1713 1714 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1715 for (; repcount; repcount--) { 1716 1717 /* Lock pokefault mutex so read doesn't mask a poke fault. */ 1718 if (hp) { 1719 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, 1720 (ddi_acc_handle_t)hp); 1721 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1722 } else { 1723 mutex_enter(&pec_p->pec_pokefault_mutex); 1724 pec_p->pec_safeacc_type = DDI_FM_ERR_PEEK; 1725 } 1726 1727 hvio_peek_status = hvio_peek(px_p->px_dev_hdl, ra, 1728 in_args->size, &read_status, &peekval); 1729 1730 if ((hvio_peek_status != H_EOK) || (read_status != H_EOK)) { 1731 err = DDI_FAILURE; 1732 1733 /* 1734 * For CAUTIOUS and PEEK access, notify FMA to 1735 * cleanup. Imitate a cpu/mem trap call like in sun4u. 1736 */ 1737 px_lib_log_safeacc_err(px_p, (ddi_acc_handle_t)hp, 1738 (hp ? DDI_FM_ERR_EXPECTED : 1739 DDI_FM_ERR_PEEK), ra); 1740 1741 /* Stuff FFs in host addr if peek. */ 1742 if (hp == NULL) { 1743 int i; 1744 uint8_t *ff_addr = (uint8_t *)host_addr; 1745 for (i = 0; i < in_args->size; i++) 1746 *ff_addr++ = 0xff; 1747 } 1748 #ifdef DEBUG 1749 px_peekfault_cnt++; 1750 #endif 1751 pec_p->pec_ontrap_data = NULL; 1752 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1753 if (hp) { 1754 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1755 (ddi_acc_handle_t)hp); 1756 } else { 1757 mutex_exit(&pec_p->pec_pokefault_mutex); 1758 } 1759 goto done; 1760 1761 } 1762 pec_p->pec_ontrap_data = NULL; 1763 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1764 if (hp) { 1765 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1766 (ddi_acc_handle_t)hp); 1767 } else { 1768 mutex_exit(&pec_p->pec_pokefault_mutex); 1769 } 1770 1771 switch (in_args->size) { 1772 case sizeof (uint8_t): 1773 *(uint8_t *)host_addr = (uint8_t)peekval; 1774 break; 1775 case sizeof (uint16_t): 1776 *(uint16_t *)host_addr = (uint16_t)peekval; 1777 break; 1778 case sizeof (uint32_t): 1779 *(uint32_t *)host_addr = (uint32_t)peekval; 1780 break; 1781 case sizeof (uint64_t): 1782 *(uint64_t *)host_addr = (uint64_t)peekval; 1783 break; 1784 default: 1785 DBG(DBG_MAP, px_p->px_dip, 1786 "peek: invalid size %d passed\n", 1787 in_args->size); 1788 err = DDI_FAILURE; 1789 goto done; 1790 } 1791 1792 host_addr += in_args->size; 1793 1794 if (in_args->flags == DDI_DEV_AUTOINCR) { 1795 dev_addr += in_args->size; 1796 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1797 } 1798 } 1799 done: 1800 return (err); 1801 } 1802 1803 1804 /* add interrupt vector */ 1805 int 1806 px_err_add_intr(px_fault_t *px_fault_p) 1807 { 1808 px_t *px_p = DIP_TO_STATE(px_fault_p->px_fh_dip); 1809 1810 DBG(DBG_LIB_INT, px_p->px_dip, 1811 "px_err_add_intr: calling add_ivintr"); 1812 1813 VERIFY(add_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL, 1814 (intrfunc)px_fault_p->px_err_func, (caddr_t)px_fault_p, NULL, 1815 (caddr_t)&px_fault_p->px_intr_payload[0]) == 0); 1816 1817 DBG(DBG_LIB_INT, px_p->px_dip, 1818 "px_err_add_intr: ib_intr_enable "); 1819 1820 px_ib_intr_enable(px_p, intr_dist_cpuid(), px_fault_p->px_intr_ino); 1821 1822 return (DDI_SUCCESS); 1823 } 1824 1825 /* remove interrupt vector */ 1826 void 1827 px_err_rem_intr(px_fault_t *px_fault_p) 1828 { 1829 px_t *px_p = DIP_TO_STATE(px_fault_p->px_fh_dip); 1830 1831 px_ib_intr_disable(px_p->px_ib_p, px_fault_p->px_intr_ino, 1832 IB_INTR_WAIT); 1833 1834 VERIFY(rem_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL) == 0); 1835 } 1836 1837 void 1838 px_cb_intr_redist(void *arg) 1839 { 1840 px_t *px_p = (px_t *)arg; 1841 px_ib_intr_dist_en(px_p->px_dip, intr_dist_cpuid(), 1842 px_p->px_inos[PX_INTR_XBC], B_FALSE); 1843 } 1844 1845 int 1846 px_cb_add_intr(px_fault_t *f_p) 1847 { 1848 px_t *px_p = DIP_TO_STATE(f_p->px_fh_dip); 1849 1850 DBG(DBG_LIB_INT, px_p->px_dip, 1851 "px_err_add_intr: calling add_ivintr"); 1852 1853 VERIFY(add_ivintr(f_p->px_fh_sysino, PX_ERR_PIL, 1854 (intrfunc)f_p->px_err_func, (caddr_t)f_p, NULL, 1855 (caddr_t)&f_p->px_intr_payload[0]) == 0); 1856 1857 intr_dist_add(px_cb_intr_redist, px_p); 1858 1859 DBG(DBG_LIB_INT, px_p->px_dip, 1860 "px_err_add_intr: ib_intr_enable "); 1861 1862 px_ib_intr_enable(px_p, intr_dist_cpuid(), f_p->px_intr_ino); 1863 1864 return (DDI_SUCCESS); 1865 } 1866 1867 void 1868 px_cb_rem_intr(px_fault_t *f_p) 1869 { 1870 intr_dist_rem(px_cb_intr_redist, DIP_TO_STATE(f_p->px_fh_dip)); 1871 px_err_rem_intr(f_p); 1872 } 1873 1874 #ifdef FMA 1875 void 1876 px_fill_rc_status(px_fault_t *px_fault_p, pciex_rc_error_regs_t *rc_status) 1877 { 1878 px_pec_err_t *err_pkt; 1879 1880 err_pkt = (px_pec_err_t *)px_fault_p->px_intr_payload; 1881 1882 /* initialise all the structure members */ 1883 rc_status->status_valid = 0; 1884 1885 if (err_pkt->pec_descr.P) { 1886 /* PCI Status Register */ 1887 rc_status->pci_err_status = err_pkt->pci_err_status; 1888 rc_status->status_valid |= PCI_ERR_STATUS_VALID; 1889 } 1890 1891 if (err_pkt->pec_descr.E) { 1892 /* PCIe Status Register */ 1893 rc_status->pcie_err_status = err_pkt->pcie_err_status; 1894 rc_status->status_valid |= PCIE_ERR_STATUS_VALID; 1895 } 1896 1897 if (err_pkt->pec_descr.U) { 1898 rc_status->ue_status = err_pkt->ue_reg_status; 1899 rc_status->status_valid |= UE_STATUS_VALID; 1900 } 1901 1902 if (err_pkt->pec_descr.H) { 1903 rc_status->ue_hdr1 = err_pkt->hdr[0]; 1904 rc_status->status_valid |= UE_HDR1_VALID; 1905 } 1906 1907 if (err_pkt->pec_descr.I) { 1908 rc_status->ue_hdr2 = err_pkt->hdr[1]; 1909 rc_status->status_valid |= UE_HDR2_VALID; 1910 } 1911 1912 /* ue_fst_err_ptr - not available for sun4v?? */ 1913 1914 1915 if (err_pkt->pec_descr.S) { 1916 rc_status->source_id = err_pkt->err_src_reg; 1917 rc_status->status_valid |= SOURCE_ID_VALID; 1918 } 1919 1920 if (err_pkt->pec_descr.R) { 1921 rc_status->root_err_status = err_pkt->root_err_status; 1922 rc_status->status_valid |= CE_STATUS_VALID; 1923 } 1924 } 1925 #endif 1926 1927 /*ARGSUSED*/ 1928 int 1929 px_lib_pmctl(int cmd, px_t *px_p) 1930 { 1931 return (DDI_FAILURE); 1932 } 1933 1934 /*ARGSUSED*/ 1935 uint_t 1936 px_pmeq_intr(caddr_t arg) 1937 { 1938 return (DDI_INTR_CLAIMED); 1939 } 1940 1941 /* 1942 * Unprotected raw reads/writes of fabric device's config space. 1943 * Only used for temporary PCI-E Fabric Error Handling. 1944 */ 1945 uint32_t 1946 px_fab_get(px_t *px_p, pcie_req_id_t bdf, uint16_t offset) { 1947 uint32_t data = 0; 1948 1949 (void) hvio_config_get(px_p->px_dev_hdl, 1950 (bdf << PX_RA_BDF_SHIFT), offset, 4, 1951 (pci_cfg_data_t *)&data); 1952 1953 return (data); 1954 } 1955 1956 void 1957 px_fab_set(px_t *px_p, pcie_req_id_t bdf, uint16_t offset, 1958 uint32_t val) { 1959 pci_cfg_data_t wdata = { 0 }; 1960 1961 wdata.qw = (uint32_t)val; 1962 (void) hvio_config_put(px_p->px_dev_hdl, 1963 (bdf << PX_RA_BDF_SHIFT), offset, 4, wdata); 1964 } 1965 1966 /*ARGSUSED*/ 1967 int 1968 px_lib_hotplug_init(dev_info_t *dip, void *arg) 1969 { 1970 return (DDI_ENOTSUP); 1971 } 1972 1973 /*ARGSUSED*/ 1974 void 1975 px_lib_hotplug_uninit(dev_info_t *dip) 1976 { 1977 } 1978 1979 /*ARGSUSED*/ 1980 void 1981 px_hp_intr_redist(px_t *px_p) 1982 { 1983 } 1984 1985 /* Dummy cpr add callback */ 1986 /*ARGSUSED*/ 1987 void 1988 px_cpr_add_callb(px_t *px_p) 1989 { 1990 } 1991 1992 /* Dummy cpr rem callback */ 1993 /*ARGSUSED*/ 1994 void 1995 px_cpr_rem_callb(px_t *px_p) 1996 { 1997 } 1998 1999 /*ARGSUSED*/ 2000 boolean_t 2001 px_lib_is_in_drain_state(px_t *px_p) 2002 { 2003 return (B_FALSE); 2004 } 2005 2006 /* 2007 * There is no IOAPI to get the BDF of the pcie root port nexus at this moment. 2008 * Assume it is 0x0000, until otherwise noted. For now, all sun4v platforms 2009 * have programmed the BDF to be 0x0000. 2010 */ 2011 /*ARGSUSED*/ 2012 pcie_req_id_t 2013 px_lib_get_bdf(px_t *px_p) 2014 { 2015 return (0x0000); 2016 } 2017 2018 int 2019 px_lib_get_root_complex_mps(px_t *px_p, dev_info_t *dip, int *mps) 2020 { 2021 pci_device_t bdf = px_lib_get_bdf(px_p); 2022 2023 if (hvio_get_rp_mps_cap(DIP_TO_HANDLE(dip), bdf, mps) == H_EOK) 2024 return (DDI_SUCCESS); 2025 else 2026 return (DDI_FAILURE); 2027 } 2028 2029 int 2030 px_lib_set_root_complex_mps(px_t *px_p, dev_info_t *dip, int mps) 2031 { 2032 pci_device_t bdf = px_lib_get_bdf(px_p); 2033 2034 if (hvio_set_rp_mps(DIP_TO_HANDLE(dip), bdf, mps) == H_EOK) 2035 return (DDI_SUCCESS); 2036 else 2037 return (DDI_FAILURE); 2038 } 2039