1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/types.h> 30 #include <sys/sysmacros.h> 31 #include <sys/ddi.h> 32 #include <sys/sunddi.h> 33 #include <sys/ddifm.h> 34 #include <sys/fm/protocol.h> 35 #include <sys/vmem.h> 36 #include <sys/intr.h> 37 #include <sys/ivintr.h> 38 #include <sys/errno.h> 39 #include <sys/hypervisor_api.h> 40 #include <px_obj.h> 41 #include <sys/machsystm.h> 42 #include "px_lib4v.h" 43 #include "px_err.h" 44 45 /* mask for the ranges property in calculating the real PFN range */ 46 uint_t px_ranges_phi_mask = ((1 << 28) -1); 47 48 int 49 px_lib_dev_init(dev_info_t *dip, devhandle_t *dev_hdl) 50 { 51 px_nexus_regspec_t *rp; 52 uint_t reglen; 53 int ret; 54 55 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dip 0x%p\n", dip); 56 57 ret = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 58 "reg", (uchar_t **)&rp, ®len); 59 if (ret != DDI_PROP_SUCCESS) { 60 DBG(DBG_ATTACH, dip, "px_lib_dev_init failed ret=%d\n", ret); 61 return (DDI_FAILURE); 62 } 63 64 /* 65 * Initilize device handle. The device handle uniquely identifies 66 * a SUN4V device. It consists of the lower 28-bits of the hi-cell 67 * of the first entry of the SUN4V device's "reg" property as 68 * defined by the SUN4V Bus Binding to Open Firmware. 69 */ 70 *dev_hdl = (devhandle_t)((rp->phys_addr >> 32) & DEVHDLE_MASK); 71 72 ddi_prop_free(rp); 73 74 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dev_hdl 0x%llx\n", *dev_hdl); 75 76 return (DDI_SUCCESS); 77 } 78 79 /*ARGSUSED*/ 80 int 81 px_lib_dev_fini(dev_info_t *dip) 82 { 83 DBG(DBG_DETACH, dip, "px_lib_dev_fini: dip 0x%p\n", dip); 84 85 return (DDI_SUCCESS); 86 } 87 88 /*ARGSUSED*/ 89 int 90 px_lib_intr_devino_to_sysino(dev_info_t *dip, devino_t devino, 91 sysino_t *sysino) 92 { 93 uint64_t ret; 94 95 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: dip 0x%p " 96 "devino 0x%x\n", dip, devino); 97 98 if ((ret = hvio_intr_devino_to_sysino(DIP_TO_HANDLE(dip), 99 devino, sysino)) != H_EOK) { 100 DBG(DBG_LIB_INT, dip, 101 "hvio_intr_devino_to_sysino failed, ret 0x%lx\n", ret); 102 return (DDI_FAILURE); 103 } 104 105 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: sysino 0x%llx\n", 106 *sysino); 107 108 return (DDI_SUCCESS); 109 } 110 111 /*ARGSUSED*/ 112 int 113 px_lib_intr_getvalid(dev_info_t *dip, sysino_t sysino, 114 intr_valid_state_t *intr_valid_state) 115 { 116 uint64_t ret; 117 118 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: dip 0x%p sysino 0x%llx\n", 119 dip, sysino); 120 121 if ((ret = hvio_intr_getvalid(sysino, 122 (int *)intr_valid_state)) != H_EOK) { 123 DBG(DBG_LIB_INT, dip, "hvio_intr_getvalid failed, ret 0x%lx\n", 124 ret); 125 return (DDI_FAILURE); 126 } 127 128 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: intr_valid_state 0x%x\n", 129 *intr_valid_state); 130 131 return (DDI_SUCCESS); 132 } 133 134 /*ARGSUSED*/ 135 int 136 px_lib_intr_setvalid(dev_info_t *dip, sysino_t sysino, 137 intr_valid_state_t intr_valid_state) 138 { 139 uint64_t ret; 140 141 DBG(DBG_LIB_INT, dip, "px_lib_intr_setvalid: dip 0x%p sysino 0x%llx " 142 "intr_valid_state 0x%x\n", dip, sysino, intr_valid_state); 143 144 if ((ret = hvio_intr_setvalid(sysino, intr_valid_state)) != H_EOK) { 145 DBG(DBG_LIB_INT, dip, "hvio_intr_setvalid failed, ret 0x%lx\n", 146 ret); 147 return (DDI_FAILURE); 148 } 149 150 return (DDI_SUCCESS); 151 } 152 153 /*ARGSUSED*/ 154 int 155 px_lib_intr_getstate(dev_info_t *dip, sysino_t sysino, 156 intr_state_t *intr_state) 157 { 158 uint64_t ret; 159 160 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: dip 0x%p sysino 0x%llx\n", 161 dip, sysino); 162 163 if ((ret = hvio_intr_getstate(sysino, (int *)intr_state)) != H_EOK) { 164 DBG(DBG_LIB_INT, dip, "hvio_intr_getstate failed, ret 0x%lx\n", 165 ret); 166 return (DDI_FAILURE); 167 } 168 169 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: intr_state 0x%x\n", 170 *intr_state); 171 172 return (DDI_SUCCESS); 173 } 174 175 /*ARGSUSED*/ 176 int 177 px_lib_intr_setstate(dev_info_t *dip, sysino_t sysino, 178 intr_state_t intr_state) 179 { 180 uint64_t ret; 181 182 DBG(DBG_LIB_INT, dip, "px_lib_intr_setstate: dip 0x%p sysino 0x%llx " 183 "intr_state 0x%x\n", dip, sysino, intr_state); 184 185 if ((ret = hvio_intr_setstate(sysino, intr_state)) != H_EOK) { 186 DBG(DBG_LIB_INT, dip, "hvio_intr_setstate failed, ret 0x%lx\n", 187 ret); 188 return (DDI_FAILURE); 189 } 190 191 return (DDI_SUCCESS); 192 } 193 194 /*ARGSUSED*/ 195 int 196 px_lib_intr_gettarget(dev_info_t *dip, sysino_t sysino, cpuid_t *cpuid) 197 { 198 uint64_t ret; 199 200 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: dip 0x%p sysino 0x%llx\n", 201 dip, sysino); 202 203 if ((ret = hvio_intr_gettarget(sysino, cpuid)) != H_EOK) { 204 DBG(DBG_LIB_INT, dip, 205 "hvio_intr_gettarget failed, ret 0x%lx\n", ret); 206 return (DDI_FAILURE); 207 } 208 209 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: cpuid 0x%x\n", cpuid); 210 211 return (DDI_SUCCESS); 212 } 213 214 /*ARGSUSED*/ 215 int 216 px_lib_intr_settarget(dev_info_t *dip, sysino_t sysino, cpuid_t cpuid) 217 { 218 uint64_t ret; 219 220 DBG(DBG_LIB_INT, dip, "px_lib_intr_settarget: dip 0x%p sysino 0x%llx " 221 "cpuid 0x%x\n", dip, sysino, cpuid); 222 223 if ((ret = hvio_intr_settarget(sysino, cpuid)) != H_EOK) { 224 DBG(DBG_LIB_INT, dip, 225 "hvio_intr_settarget failed, ret 0x%lx\n", ret); 226 return (DDI_FAILURE); 227 } 228 229 return (DDI_SUCCESS); 230 } 231 232 /*ARGSUSED*/ 233 int 234 px_lib_intr_reset(dev_info_t *dip) 235 { 236 DBG(DBG_LIB_INT, dip, "px_lib_intr_reset: dip 0x%p\n", dip); 237 238 return (DDI_SUCCESS); 239 } 240 241 /*ARGSUSED*/ 242 int 243 px_lib_iommu_map(dev_info_t *dip, tsbid_t tsbid, pages_t pages, 244 io_attributes_t io_attributes, void *addr, size_t pfn_index, 245 int flag) 246 { 247 pages_t pgs_mapped = 0, pgs_cnt = 0; 248 pages_t pgs = pages; 249 tsbnum_t tsb_num = PCI_TSBID_TO_TSBNUM(tsbid); 250 tsbindex_t tsbindex = PCI_TSBID_TO_TSBINDEX(tsbid); 251 io_page_list_t *io_page_list_p, *ptr; 252 int i, err = DDI_SUCCESS; 253 uint64_t ret; 254 255 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: dip 0x%p tsbid 0x%llx " 256 "pages 0x%x atrr 0x%x addr 0x%p pfn_index 0x%llx, flag 0x%x\n", 257 dip, tsbid, pages, io_attributes, addr, pfn_index, flag); 258 259 if ((ptr = kmem_zalloc((pages * sizeof (io_page_list_t)), 260 KM_NOSLEEP)) == NULL) { 261 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: kmem_zalloc failed\n"); 262 return (DDI_FAILURE); 263 } 264 265 io_page_list_p = (io_page_list_t *)ptr; 266 267 if (flag == MMU_MAP_MP) { 268 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)addr; 269 270 for (i = 0; i < pages; i++, pfn_index++) { 271 px_iopfn_t pfn = PX_GET_MP_PFN(mp, pfn_index); 272 io_page_list_p[i] = MMU_PTOB(pfn); 273 } 274 } else { 275 caddr_t a = (caddr_t)addr; 276 277 for (i = 0; i < pages; i++, a += MMU_PAGE_SIZE) { 278 px_iopfn_t pfn = hat_getpfnum(kas.a_hat, a); 279 io_page_list_p[i] = MMU_PTOB(pfn); 280 } 281 } 282 283 io_page_list_p = (io_page_list_t *)va_to_pa(ptr); 284 pgs_mapped = 0; 285 286 while (pgs) { 287 if ((ret = hvio_iommu_map(DIP_TO_HANDLE(dip), 288 PCI_TSBID(tsb_num, tsbindex), pgs, io_attributes, 289 io_page_list_p, &pgs_cnt)) != H_EOK) { 290 DBG(DBG_LIB_DMA, dip, 291 "hvio_iommu_map failed, ret 0x%lx\n", ret); 292 err = DDI_FAILURE; 293 break; 294 } 295 296 pgs_mapped += pgs_cnt; 297 pgs -= pgs_cnt; 298 tsbindex += pgs_cnt; 299 io_page_list_p += pgs_cnt; 300 pgs_cnt = 0; 301 } 302 303 if ((err == DDI_FAILURE) && (pgs_mapped)) 304 (void) px_lib_iommu_demap(dip, tsbid, pgs_mapped); 305 306 kmem_free(ptr, (pages * sizeof (io_page_list_t))); 307 308 return (err); 309 } 310 311 /*ARGSUSED*/ 312 int 313 px_lib_iommu_demap(dev_info_t *dip, tsbid_t tsbid, pages_t pages) 314 { 315 tsbnum_t tsb_num = PCI_TSBID_TO_TSBNUM(tsbid); 316 tsbindex_t tsbindex = PCI_TSBID_TO_TSBINDEX(tsbid); 317 pages_t pgs_cnt = 0; 318 uint64_t ret; 319 320 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: dip 0x%p tsbid 0x%llx " 321 "pages 0x%x\n", dip, tsbid, pages); 322 323 while (pages) { 324 if ((ret = hvio_iommu_demap(DIP_TO_HANDLE(dip), 325 PCI_TSBID(tsb_num, tsbindex), pages, 326 &pgs_cnt)) != H_EOK) { 327 DBG(DBG_LIB_DMA, dip, 328 "hvio_iommu_demap failed, ret 0x%lx\n", ret); 329 return (DDI_FAILURE); 330 } 331 332 pages -= pgs_cnt; 333 tsbindex += pgs_cnt; 334 pgs_cnt = 0; 335 } 336 337 return (DDI_SUCCESS); 338 } 339 340 /*ARGSUSED*/ 341 int 342 px_lib_iommu_getmap(dev_info_t *dip, tsbid_t tsbid, 343 io_attributes_t *attributes_p, r_addr_t *r_addr_p) 344 { 345 uint64_t ret; 346 347 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: dip 0x%p tsbid 0x%llx\n", 348 dip, tsbid); 349 350 if ((ret = hvio_iommu_getmap(DIP_TO_HANDLE(dip), tsbid, 351 attributes_p, r_addr_p)) != H_EOK) { 352 DBG(DBG_LIB_DMA, dip, 353 "hvio_iommu_getmap failed, ret 0x%lx\n", ret); 354 355 return ((ret == H_ENOMAP) ? DDI_DMA_NOMAPPING:DDI_FAILURE); 356 } 357 358 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: attr 0x%x r_addr 0x%llx\n", 359 *attributes_p, *r_addr_p); 360 361 return (DDI_SUCCESS); 362 } 363 364 365 /* 366 * Checks dma attributes against system bypass ranges 367 * A sun4v device must be capable of generating the entire 64-bit 368 * address in order to perform bypass DMA. 369 */ 370 /*ARGSUSED*/ 371 int 372 px_lib_dma_bypass_rngchk(ddi_dma_attr_t *attrp, uint64_t *lo_p, uint64_t *hi_p) 373 { 374 if ((attrp->dma_attr_addr_lo != 0ull) || 375 (attrp->dma_attr_addr_hi != UINT64_MAX)) { 376 377 return (DDI_DMA_BADATTR); 378 } 379 380 *lo_p = 0ull; 381 *hi_p = UINT64_MAX; 382 383 return (DDI_SUCCESS); 384 } 385 386 387 /*ARGSUSED*/ 388 int 389 px_lib_iommu_getbypass(dev_info_t *dip, r_addr_t ra, 390 io_attributes_t io_attributes, io_addr_t *io_addr_p) 391 { 392 uint64_t ret; 393 394 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: dip 0x%p ra 0x%llx " 395 "attr 0x%x\n", dip, ra, io_attributes); 396 397 if ((ret = hvio_iommu_getbypass(DIP_TO_HANDLE(dip), ra, 398 io_attributes, io_addr_p)) != H_EOK) { 399 DBG(DBG_LIB_DMA, dip, 400 "hvio_iommu_getbypass failed, ret 0x%lx\n", ret); 401 return (ret == H_ENOTSUPPORTED ? DDI_ENOTSUP : DDI_FAILURE); 402 } 403 404 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: io_addr 0x%llx\n", 405 *io_addr_p); 406 407 return (DDI_SUCCESS); 408 } 409 410 /*ARGSUSED*/ 411 int 412 px_lib_dma_sync(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 413 off_t off, size_t len, uint_t cache_flags) 414 { 415 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 416 uint64_t sync_dir; 417 px_dvma_addr_t dvma_addr, pg_off; 418 size_t num_sync; 419 uint64_t status = H_EOK; 420 421 DBG(DBG_LIB_DMA, dip, "px_lib_dma_sync: dip 0x%p rdip 0x%p " 422 "handle 0x%llx off 0x%x len 0x%x flags 0x%x\n", 423 dip, rdip, handle, off, len, cache_flags); 424 425 if (!(mp->dmai_flags & DMAI_FLAGS_INUSE)) { 426 cmn_err(CE_WARN, "%s%d: Unbound dma handle %p.", 427 ddi_driver_name(rdip), ddi_get_instance(rdip), (void *)mp); 428 return (DDI_FAILURE); 429 } 430 431 if (mp->dmai_flags & DMAI_FLAGS_NOSYNC) 432 return (DDI_SUCCESS); 433 434 if (!len) 435 len = mp->dmai_size; 436 437 pg_off = mp->dmai_offset; /* start min */ 438 dvma_addr = MAX(off, pg_off); /* lo */ 439 pg_off += mp->dmai_size; /* end max */ 440 pg_off = MIN(off + len, pg_off); /* hi */ 441 if (dvma_addr >= pg_off) { /* lo >= hi ? */ 442 cmn_err(CE_WARN, "%s%d: %lx + %lx out of window [%lx,%lx]", 443 ddi_driver_name(rdip), ddi_get_instance(rdip), 444 off, len, mp->dmai_offset, 445 mp->dmai_offset + mp->dmai_size); 446 return (DDI_FAILURE); 447 } 448 449 len = pg_off - dvma_addr; /* sz = hi - lo */ 450 dvma_addr += mp->dmai_mapping; /* start addr */ 451 452 if (mp->dmai_rflags & DDI_DMA_READ) 453 sync_dir = HVIO_DMA_SYNC_DIR_FROM_DEV; 454 else 455 sync_dir = HVIO_DMA_SYNC_DIR_TO_DEV; 456 457 for (; ((len > 0) && (status == H_EOK)); len -= num_sync) { 458 status = hvio_dma_sync(DIP_TO_HANDLE(dip), dvma_addr, len, 459 sync_dir, &num_sync); 460 dvma_addr += num_sync; 461 } 462 463 return ((status == H_EOK) ? DDI_SUCCESS : DDI_FAILURE); 464 } 465 466 467 /* 468 * MSIQ Functions: 469 */ 470 471 /*ARGSUSED*/ 472 int 473 px_lib_msiq_init(dev_info_t *dip) 474 { 475 px_t *px_p = DIP_TO_STATE(dip); 476 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 477 uint64_t *msiq_addr, ra; 478 size_t msiq_size; 479 uint_t rec_cnt; 480 int i, err = DDI_SUCCESS; 481 uint64_t ret; 482 483 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_init: dip 0x%p\n", dip); 484 485 msiq_addr = (uint64_t *)(((uint64_t)msiq_state_p->msiq_buf_p + 486 (MMU_PAGE_SIZE - 1)) >> MMU_PAGE_SHIFT << MMU_PAGE_SHIFT); 487 488 msiq_size = msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t); 489 490 for (i = 0; i < msiq_state_p->msiq_cnt; i++) { 491 ra = (r_addr_t)va_to_pa((caddr_t)msiq_addr + (i * msiq_size)); 492 493 if ((ret = hvio_msiq_conf(DIP_TO_HANDLE(dip), 494 (i + msiq_state_p->msiq_1st_msiq_id), 495 ra, msiq_state_p->msiq_rec_cnt)) != H_EOK) { 496 DBG(DBG_LIB_MSIQ, dip, 497 "hvio_msiq_conf failed, ret 0x%lx\n", ret); 498 err = DDI_FAILURE; 499 break; 500 } 501 502 if ((err = px_lib_msiq_info(dip, 503 (i + msiq_state_p->msiq_1st_msiq_id), 504 &ra, &rec_cnt)) != DDI_SUCCESS) { 505 DBG(DBG_LIB_MSIQ, dip, 506 "px_lib_msiq_info failed, ret 0x%x\n", err); 507 err = DDI_FAILURE; 508 break; 509 } 510 511 DBG(DBG_LIB_MSIQ, dip, 512 "px_lib_msiq_init: ra 0x%p rec_cnt 0x%x\n", ra, rec_cnt); 513 } 514 515 return (err); 516 } 517 518 /*ARGSUSED*/ 519 int 520 px_lib_msiq_fini(dev_info_t *dip) 521 { 522 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_fini: dip 0x%p\n", dip); 523 524 return (DDI_SUCCESS); 525 } 526 527 /*ARGSUSED*/ 528 int 529 px_lib_msiq_info(dev_info_t *dip, msiqid_t msiq_id, r_addr_t *ra_p, 530 uint_t *msiq_rec_cnt_p) 531 { 532 uint64_t ret; 533 534 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: dip 0x%p msiq_id 0x%x\n", 535 dip, msiq_id); 536 537 if ((ret = hvio_msiq_info(DIP_TO_HANDLE(dip), 538 msiq_id, ra_p, msiq_rec_cnt_p)) != H_EOK) { 539 DBG(DBG_LIB_MSIQ, dip, 540 "hvio_msiq_info failed, ret 0x%lx\n", ret); 541 return (DDI_FAILURE); 542 } 543 544 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: ra_p 0x%p msiq_rec_cnt 0x%x\n", 545 ra_p, *msiq_rec_cnt_p); 546 547 return (DDI_SUCCESS); 548 } 549 550 /*ARGSUSED*/ 551 int 552 px_lib_msiq_getvalid(dev_info_t *dip, msiqid_t msiq_id, 553 pci_msiq_valid_state_t *msiq_valid_state) 554 { 555 uint64_t ret; 556 557 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: dip 0x%p msiq_id 0x%x\n", 558 dip, msiq_id); 559 560 if ((ret = hvio_msiq_getvalid(DIP_TO_HANDLE(dip), 561 msiq_id, msiq_valid_state)) != H_EOK) { 562 DBG(DBG_LIB_MSIQ, dip, 563 "hvio_msiq_getvalid failed, ret 0x%lx\n", ret); 564 return (DDI_FAILURE); 565 } 566 567 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: msiq_valid_state 0x%x\n", 568 *msiq_valid_state); 569 570 return (DDI_SUCCESS); 571 } 572 573 /*ARGSUSED*/ 574 int 575 px_lib_msiq_setvalid(dev_info_t *dip, msiqid_t msiq_id, 576 pci_msiq_valid_state_t msiq_valid_state) 577 { 578 uint64_t ret; 579 580 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setvalid: dip 0x%p msiq_id 0x%x " 581 "msiq_valid_state 0x%x\n", dip, msiq_id, msiq_valid_state); 582 583 if ((ret = hvio_msiq_setvalid(DIP_TO_HANDLE(dip), 584 msiq_id, msiq_valid_state)) != H_EOK) { 585 DBG(DBG_LIB_MSIQ, dip, 586 "hvio_msiq_setvalid failed, ret 0x%lx\n", ret); 587 return (DDI_FAILURE); 588 } 589 590 return (DDI_SUCCESS); 591 } 592 593 /*ARGSUSED*/ 594 int 595 px_lib_msiq_getstate(dev_info_t *dip, msiqid_t msiq_id, 596 pci_msiq_state_t *msiq_state) 597 { 598 uint64_t ret; 599 600 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: dip 0x%p msiq_id 0x%x\n", 601 dip, msiq_id); 602 603 if ((ret = hvio_msiq_getstate(DIP_TO_HANDLE(dip), 604 msiq_id, msiq_state)) != H_EOK) { 605 DBG(DBG_LIB_MSIQ, dip, 606 "hvio_msiq_getstate failed, ret 0x%lx\n", ret); 607 return (DDI_FAILURE); 608 } 609 610 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: msiq_state 0x%x\n", 611 *msiq_state); 612 613 return (DDI_SUCCESS); 614 } 615 616 /*ARGSUSED*/ 617 int 618 px_lib_msiq_setstate(dev_info_t *dip, msiqid_t msiq_id, 619 pci_msiq_state_t msiq_state) 620 { 621 uint64_t ret; 622 623 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setstate: dip 0x%p msiq_id 0x%x " 624 "msiq_state 0x%x\n", dip, msiq_id, msiq_state); 625 626 if ((ret = hvio_msiq_setstate(DIP_TO_HANDLE(dip), 627 msiq_id, msiq_state)) != H_EOK) { 628 DBG(DBG_LIB_MSIQ, dip, 629 "hvio_msiq_setstate failed, ret 0x%lx\n", ret); 630 return (DDI_FAILURE); 631 } 632 633 return (DDI_SUCCESS); 634 } 635 636 /*ARGSUSED*/ 637 int 638 px_lib_msiq_gethead(dev_info_t *dip, msiqid_t msiq_id, 639 msiqhead_t *msiq_head_p) 640 { 641 uint64_t ret; 642 643 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gethead: dip 0x%p msiq_id 0x%x\n", 644 dip, msiq_id); 645 646 if ((ret = hvio_msiq_gethead(DIP_TO_HANDLE(dip), 647 msiq_id, msiq_head_p)) != H_EOK) { 648 DBG(DBG_LIB_MSIQ, dip, 649 "hvio_msiq_gethead failed, ret 0x%lx\n", ret); 650 return (DDI_FAILURE); 651 } 652 653 *msiq_head_p = (*msiq_head_p / sizeof (msiq_rec_t)); 654 655 DBG(DBG_LIB_MSIQ, dip, "px_msiq_gethead: msiq_head 0x%x\n", 656 *msiq_head_p); 657 658 return (DDI_SUCCESS); 659 } 660 661 /*ARGSUSED*/ 662 int 663 px_lib_msiq_sethead(dev_info_t *dip, msiqid_t msiq_id, 664 msiqhead_t msiq_head) 665 { 666 uint64_t ret; 667 668 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_sethead: dip 0x%p msiq_id 0x%x " 669 "msiq_head 0x%x\n", dip, msiq_id, msiq_head); 670 671 if ((ret = hvio_msiq_sethead(DIP_TO_HANDLE(dip), 672 msiq_id, msiq_head * sizeof (msiq_rec_t))) != H_EOK) { 673 DBG(DBG_LIB_MSIQ, dip, 674 "hvio_msiq_sethead failed, ret 0x%lx\n", ret); 675 return (DDI_FAILURE); 676 } 677 678 return (DDI_SUCCESS); 679 } 680 681 /*ARGSUSED*/ 682 int 683 px_lib_msiq_gettail(dev_info_t *dip, msiqid_t msiq_id, 684 msiqtail_t *msiq_tail_p) 685 { 686 uint64_t ret; 687 688 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: dip 0x%p msiq_id 0x%x\n", 689 dip, msiq_id); 690 691 if ((ret = hvio_msiq_gettail(DIP_TO_HANDLE(dip), 692 msiq_id, msiq_tail_p)) != H_EOK) { 693 DBG(DBG_LIB_MSIQ, dip, 694 "hvio_msiq_gettail failed, ret 0x%lx\n", ret); 695 return (DDI_FAILURE); 696 } 697 698 *msiq_tail_p = (*msiq_tail_p / sizeof (msiq_rec_t)); 699 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: msiq_tail 0x%x\n", 700 *msiq_tail_p); 701 702 return (DDI_SUCCESS); 703 } 704 705 /*ARGSUSED*/ 706 void 707 px_lib_get_msiq_rec(dev_info_t *dip, px_msiq_t *msiq_p, msiq_rec_t *msiq_rec_p) 708 { 709 msiq_rec_t *curr_msiq_rec_p = (msiq_rec_t *)msiq_p->msiq_curr; 710 711 DBG(DBG_LIB_MSIQ, dip, "px_lib_get_msiq_rec: dip 0x%p\n", dip); 712 713 if (!curr_msiq_rec_p->msiq_rec_type) 714 return; 715 716 *msiq_rec_p = *curr_msiq_rec_p; 717 718 /* Zero out msiq_rec_type field */ 719 curr_msiq_rec_p->msiq_rec_type = 0; 720 } 721 722 /* 723 * MSI Functions: 724 */ 725 726 /*ARGSUSED*/ 727 int 728 px_lib_msi_init(dev_info_t *dip) 729 { 730 DBG(DBG_LIB_MSI, dip, "px_lib_msi_init: dip 0x%p\n", dip); 731 732 /* Noop */ 733 return (DDI_SUCCESS); 734 } 735 736 /*ARGSUSED*/ 737 int 738 px_lib_msi_getmsiq(dev_info_t *dip, msinum_t msi_num, 739 msiqid_t *msiq_id) 740 { 741 uint64_t ret; 742 743 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: dip 0x%p msi_num 0x%x\n", 744 dip, msi_num); 745 746 if ((ret = hvio_msi_getmsiq(DIP_TO_HANDLE(dip), 747 msi_num, msiq_id)) != H_EOK) { 748 DBG(DBG_LIB_MSI, dip, 749 "hvio_msi_getmsiq failed, ret 0x%lx\n", ret); 750 return (DDI_FAILURE); 751 } 752 753 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: msiq_id 0x%x\n", 754 *msiq_id); 755 756 return (DDI_SUCCESS); 757 } 758 759 /*ARGSUSED*/ 760 int 761 px_lib_msi_setmsiq(dev_info_t *dip, msinum_t msi_num, 762 msiqid_t msiq_id, msi_type_t msitype) 763 { 764 uint64_t ret; 765 766 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setmsiq: dip 0x%p msi_num 0x%x " 767 "msq_id 0x%x\n", dip, msi_num, msiq_id); 768 769 if ((ret = hvio_msi_setmsiq(DIP_TO_HANDLE(dip), 770 msi_num, msiq_id, msitype)) != H_EOK) { 771 DBG(DBG_LIB_MSI, dip, 772 "hvio_msi_setmsiq failed, ret 0x%lx\n", ret); 773 return (DDI_FAILURE); 774 } 775 776 return (DDI_SUCCESS); 777 } 778 779 /*ARGSUSED*/ 780 int 781 px_lib_msi_getvalid(dev_info_t *dip, msinum_t msi_num, 782 pci_msi_valid_state_t *msi_valid_state) 783 { 784 uint64_t ret; 785 786 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: dip 0x%p msi_num 0x%x\n", 787 dip, msi_num); 788 789 if ((ret = hvio_msi_getvalid(DIP_TO_HANDLE(dip), 790 msi_num, msi_valid_state)) != H_EOK) { 791 DBG(DBG_LIB_MSI, dip, 792 "hvio_msi_getvalid failed, ret 0x%lx\n", ret); 793 return (DDI_FAILURE); 794 } 795 796 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: msiq_id 0x%x\n", 797 *msi_valid_state); 798 799 return (DDI_SUCCESS); 800 } 801 802 /*ARGSUSED*/ 803 int 804 px_lib_msi_setvalid(dev_info_t *dip, msinum_t msi_num, 805 pci_msi_valid_state_t msi_valid_state) 806 { 807 uint64_t ret; 808 809 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setvalid: dip 0x%p msi_num 0x%x " 810 "msi_valid_state 0x%x\n", dip, msi_num, msi_valid_state); 811 812 if ((ret = hvio_msi_setvalid(DIP_TO_HANDLE(dip), 813 msi_num, msi_valid_state)) != H_EOK) { 814 DBG(DBG_LIB_MSI, dip, 815 "hvio_msi_setvalid failed, ret 0x%lx\n", ret); 816 return (DDI_FAILURE); 817 } 818 819 return (DDI_SUCCESS); 820 } 821 822 /*ARGSUSED*/ 823 int 824 px_lib_msi_getstate(dev_info_t *dip, msinum_t msi_num, 825 pci_msi_state_t *msi_state) 826 { 827 uint64_t ret; 828 829 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: dip 0x%p msi_num 0x%x\n", 830 dip, msi_num); 831 832 if ((ret = hvio_msi_getstate(DIP_TO_HANDLE(dip), 833 msi_num, msi_state)) != H_EOK) { 834 DBG(DBG_LIB_MSI, dip, 835 "hvio_msi_getstate failed, ret 0x%lx\n", ret); 836 return (DDI_FAILURE); 837 } 838 839 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: msi_state 0x%x\n", 840 *msi_state); 841 842 return (DDI_SUCCESS); 843 } 844 845 /*ARGSUSED*/ 846 int 847 px_lib_msi_setstate(dev_info_t *dip, msinum_t msi_num, 848 pci_msi_state_t msi_state) 849 { 850 uint64_t ret; 851 852 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setstate: dip 0x%p msi_num 0x%x " 853 "msi_state 0x%x\n", dip, msi_num, msi_state); 854 855 if ((ret = hvio_msi_setstate(DIP_TO_HANDLE(dip), 856 msi_num, msi_state)) != H_EOK) { 857 DBG(DBG_LIB_MSI, dip, 858 "hvio_msi_setstate failed, ret 0x%lx\n", ret); 859 return (DDI_FAILURE); 860 } 861 862 return (DDI_SUCCESS); 863 } 864 865 /* 866 * MSG Functions: 867 */ 868 869 /*ARGSUSED*/ 870 int 871 px_lib_msg_getmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 872 msiqid_t *msiq_id) 873 { 874 uint64_t ret; 875 876 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getmsiq: dip 0x%p msg_type 0x%x\n", 877 dip, msg_type); 878 879 if ((ret = hvio_msg_getmsiq(DIP_TO_HANDLE(dip), 880 msg_type, msiq_id)) != H_EOK) { 881 DBG(DBG_LIB_MSG, dip, 882 "hvio_msg_getmsiq failed, ret 0x%lx\n", ret); 883 return (DDI_FAILURE); 884 } 885 886 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getmsiq: msiq_id 0x%x\n", 887 *msiq_id); 888 889 return (DDI_SUCCESS); 890 } 891 892 /*ARGSUSED*/ 893 int 894 px_lib_msg_setmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 895 msiqid_t msiq_id) 896 { 897 uint64_t ret; 898 899 DBG(DBG_LIB_MSG, dip, "px_lib_msg_setmsiq: dip 0x%p msg_type 0x%x " 900 "msq_id 0x%x\n", dip, msg_type, msiq_id); 901 902 if ((ret = hvio_msg_setmsiq(DIP_TO_HANDLE(dip), 903 msg_type, msiq_id)) != H_EOK) { 904 DBG(DBG_LIB_MSG, dip, 905 "hvio_msg_setmsiq failed, ret 0x%lx\n", ret); 906 return (DDI_FAILURE); 907 } 908 909 return (DDI_SUCCESS); 910 } 911 912 /*ARGSUSED*/ 913 int 914 px_lib_msg_getvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 915 pcie_msg_valid_state_t *msg_valid_state) 916 { 917 uint64_t ret; 918 919 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getvalid: dip 0x%p msg_type 0x%x\n", 920 dip, msg_type); 921 922 if ((ret = hvio_msg_getvalid(DIP_TO_HANDLE(dip), msg_type, 923 msg_valid_state)) != H_EOK) { 924 DBG(DBG_LIB_MSG, dip, 925 "hvio_msg_getvalid failed, ret 0x%lx\n", ret); 926 return (DDI_FAILURE); 927 } 928 929 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getvalid: msg_valid_state 0x%x\n", 930 *msg_valid_state); 931 932 return (DDI_SUCCESS); 933 } 934 935 /*ARGSUSED*/ 936 int 937 px_lib_msg_setvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 938 pcie_msg_valid_state_t msg_valid_state) 939 { 940 uint64_t ret; 941 942 DBG(DBG_LIB_MSG, dip, "px_lib_msg_setvalid: dip 0x%p msg_type 0x%x " 943 "msg_valid_state 0x%x\n", dip, msg_type, msg_valid_state); 944 945 if ((ret = hvio_msg_setvalid(DIP_TO_HANDLE(dip), msg_type, 946 msg_valid_state)) != H_EOK) { 947 DBG(DBG_LIB_MSG, dip, 948 "hvio_msg_setvalid failed, ret 0x%lx\n", ret); 949 return (DDI_FAILURE); 950 } 951 952 return (DDI_SUCCESS); 953 } 954 955 /* 956 * Suspend/Resume Functions: 957 * Currently unsupported by hypervisor and all functions are noops. 958 */ 959 /*ARGSUSED*/ 960 int 961 px_lib_suspend(dev_info_t *dip) 962 { 963 DBG(DBG_ATTACH, dip, "px_lib_suspend: Not supported\n"); 964 965 /* Not supported */ 966 return (DDI_FAILURE); 967 } 968 969 /*ARGSUSED*/ 970 void 971 px_lib_resume(dev_info_t *dip) 972 { 973 DBG(DBG_ATTACH, dip, "px_lib_resume: Not supported\n"); 974 975 /* Noop */ 976 } 977 978 /* 979 * Misc Functions: 980 * Currently unsupported by hypervisor and all functions are noops. 981 */ 982 /*ARGSUSED*/ 983 uint64_t 984 px_lib_get_cb(dev_info_t *dip) 985 { 986 return (DDI_SUCCESS); 987 } 988 989 /*ARGSUSED*/ 990 void 991 px_lib_set_cb(dev_info_t *dip, uint64_t val) 992 { 993 /* Noop */ 994 } 995 996 /*ARGSUSED*/ 997 static int 998 px_lib_config_get(dev_info_t *dip, pci_device_t bdf, pci_config_offset_t off, 999 uint8_t size, pci_cfg_data_t *data_p) 1000 { 1001 uint64_t ret; 1002 1003 DBG(DBG_LIB_CFG, dip, "px_lib_config_get: dip 0x%p, bdf 0x%llx " 1004 "off 0x%x size 0x%x\n", dip, bdf, off, size); 1005 1006 if ((ret = hvio_config_get(DIP_TO_HANDLE(dip), bdf, off, 1007 size, data_p)) != H_EOK) { 1008 DBG(DBG_LIB_CFG, dip, 1009 "hvio_config_get failed, ret 0x%lx\n", ret); 1010 return (DDI_FAILURE); 1011 } 1012 DBG(DBG_LIB_CFG, dip, "px_config_get: data 0x%x\n", data_p->dw); 1013 1014 return (DDI_SUCCESS); 1015 } 1016 1017 /*ARGSUSED*/ 1018 static int 1019 px_lib_config_put(dev_info_t *dip, pci_device_t bdf, pci_config_offset_t off, 1020 uint8_t size, pci_cfg_data_t data) 1021 { 1022 uint64_t ret; 1023 1024 DBG(DBG_LIB_CFG, dip, "px_lib_config_put: dip 0x%p, bdf 0x%llx " 1025 "off 0x%x size 0x%x data 0x%llx\n", dip, bdf, off, size, data.qw); 1026 1027 if ((ret = hvio_config_put(DIP_TO_HANDLE(dip), bdf, off, 1028 size, data)) != H_EOK) { 1029 DBG(DBG_LIB_CFG, dip, 1030 "hvio_config_put failed, ret 0x%lx\n", ret); 1031 return (DDI_FAILURE); 1032 } 1033 1034 return (DDI_SUCCESS); 1035 } 1036 1037 static uint32_t 1038 px_pci_config_get(ddi_acc_impl_t *handle, uint32_t *addr, int size) 1039 { 1040 px_config_acc_pvt_t *px_pvt = (px_config_acc_pvt_t *) 1041 handle->ahi_common.ah_bus_private; 1042 uint32_t pci_dev_addr = px_pvt->raddr; 1043 uint32_t vaddr = px_pvt->vaddr; 1044 uint16_t off = (uint16_t)(uintptr_t)(addr - vaddr) & 0xfff; 1045 uint32_t rdata = 0; 1046 1047 if (px_lib_config_get(px_pvt->dip, pci_dev_addr, off, 1048 size, (pci_cfg_data_t *)&rdata) != DDI_SUCCESS) 1049 /* XXX update error kstats */ 1050 return (0xffffffff); 1051 return (rdata); 1052 } 1053 1054 static void 1055 px_pci_config_put(ddi_acc_impl_t *handle, uint32_t *addr, 1056 int size, pci_cfg_data_t wdata) 1057 { 1058 px_config_acc_pvt_t *px_pvt = (px_config_acc_pvt_t *) 1059 handle->ahi_common.ah_bus_private; 1060 uint32_t pci_dev_addr = px_pvt->raddr; 1061 uint32_t vaddr = px_pvt->vaddr; 1062 uint16_t off = (uint16_t)(uintptr_t)(addr - vaddr) & 0xfff; 1063 1064 if (px_lib_config_put(px_pvt->dip, pci_dev_addr, off, 1065 size, wdata) != DDI_SUCCESS) { 1066 /*EMPTY*/ 1067 /* XXX update error kstats */ 1068 } 1069 } 1070 1071 static uint8_t 1072 px_pci_config_get8(ddi_acc_impl_t *handle, uint8_t *addr) 1073 { 1074 return ((uint8_t)px_pci_config_get(handle, (uint32_t *)addr, 1)); 1075 } 1076 1077 static uint16_t 1078 px_pci_config_get16(ddi_acc_impl_t *handle, uint16_t *addr) 1079 { 1080 return ((uint16_t)px_pci_config_get(handle, (uint32_t *)addr, 2)); 1081 } 1082 1083 static uint32_t 1084 px_pci_config_get32(ddi_acc_impl_t *handle, uint32_t *addr) 1085 { 1086 return ((uint32_t)px_pci_config_get(handle, (uint32_t *)addr, 4)); 1087 } 1088 1089 static uint64_t 1090 px_pci_config_get64(ddi_acc_impl_t *handle, uint64_t *addr) 1091 { 1092 uint32_t rdatah, rdatal; 1093 1094 rdatal = (uint32_t)px_pci_config_get(handle, (uint32_t *)addr, 4); 1095 rdatah = (uint32_t)px_pci_config_get(handle, 1096 (uint32_t *)((char *)addr+4), 4); 1097 return (((uint64_t)rdatah << 32) | rdatal); 1098 } 1099 1100 static void 1101 px_pci_config_put8(ddi_acc_impl_t *handle, uint8_t *addr, uint8_t data) 1102 { 1103 pci_cfg_data_t wdata = { 0 }; 1104 1105 wdata.qw = (uint8_t)data; 1106 px_pci_config_put(handle, (uint32_t *)addr, 1, wdata); 1107 } 1108 1109 static void 1110 px_pci_config_put16(ddi_acc_impl_t *handle, uint16_t *addr, uint16_t data) 1111 { 1112 pci_cfg_data_t wdata = { 0 }; 1113 1114 wdata.qw = (uint16_t)data; 1115 px_pci_config_put(handle, (uint32_t *)addr, 2, wdata); 1116 } 1117 1118 static void 1119 px_pci_config_put32(ddi_acc_impl_t *handle, uint32_t *addr, uint32_t data) 1120 { 1121 pci_cfg_data_t wdata = { 0 }; 1122 1123 wdata.qw = (uint32_t)data; 1124 px_pci_config_put(handle, (uint32_t *)addr, 4, wdata); 1125 } 1126 1127 static void 1128 px_pci_config_put64(ddi_acc_impl_t *handle, uint64_t *addr, uint64_t data) 1129 { 1130 pci_cfg_data_t wdata = { 0 }; 1131 1132 wdata.qw = (uint32_t)(data & 0xffffffff); 1133 px_pci_config_put(handle, (uint32_t *)addr, 4, wdata); 1134 wdata.qw = (uint32_t)((data >> 32) & 0xffffffff); 1135 px_pci_config_put(handle, (uint32_t *)((char *)addr+4), 4, wdata); 1136 } 1137 1138 static void 1139 px_pci_config_rep_get8(ddi_acc_impl_t *handle, uint8_t *host_addr, 1140 uint8_t *dev_addr, size_t repcount, uint_t flags) 1141 { 1142 if (flags == DDI_DEV_AUTOINCR) 1143 for (; repcount; repcount--) 1144 *host_addr++ = px_pci_config_get8(handle, dev_addr++); 1145 else 1146 for (; repcount; repcount--) 1147 *host_addr++ = px_pci_config_get8(handle, dev_addr); 1148 } 1149 1150 /* 1151 * Function to rep read 16 bit data off the PCI configuration space behind 1152 * the 21554's host interface. 1153 */ 1154 static void 1155 px_pci_config_rep_get16(ddi_acc_impl_t *handle, uint16_t *host_addr, 1156 uint16_t *dev_addr, size_t repcount, uint_t flags) 1157 { 1158 if (flags == DDI_DEV_AUTOINCR) 1159 for (; repcount; repcount--) 1160 *host_addr++ = px_pci_config_get16(handle, dev_addr++); 1161 else 1162 for (; repcount; repcount--) 1163 *host_addr++ = px_pci_config_get16(handle, dev_addr); 1164 } 1165 1166 /* 1167 * Function to rep read 32 bit data off the PCI configuration space behind 1168 * the 21554's host interface. 1169 */ 1170 static void 1171 px_pci_config_rep_get32(ddi_acc_impl_t *handle, uint32_t *host_addr, 1172 uint32_t *dev_addr, size_t repcount, uint_t flags) 1173 { 1174 if (flags == DDI_DEV_AUTOINCR) 1175 for (; repcount; repcount--) 1176 *host_addr++ = px_pci_config_get32(handle, dev_addr++); 1177 else 1178 for (; repcount; repcount--) 1179 *host_addr++ = px_pci_config_get32(handle, dev_addr); 1180 } 1181 1182 /* 1183 * Function to rep read 64 bit data off the PCI configuration space behind 1184 * the 21554's host interface. 1185 */ 1186 static void 1187 px_pci_config_rep_get64(ddi_acc_impl_t *handle, uint64_t *host_addr, 1188 uint64_t *dev_addr, size_t repcount, uint_t flags) 1189 { 1190 if (flags == DDI_DEV_AUTOINCR) 1191 for (; repcount; repcount--) 1192 *host_addr++ = px_pci_config_get64(handle, dev_addr++); 1193 else 1194 for (; repcount; repcount--) 1195 *host_addr++ = px_pci_config_get64(handle, dev_addr); 1196 } 1197 1198 /* 1199 * Function to rep write 8 bit data into the PCI configuration space behind 1200 * the 21554's host interface. 1201 */ 1202 static void 1203 px_pci_config_rep_put8(ddi_acc_impl_t *handle, uint8_t *host_addr, 1204 uint8_t *dev_addr, size_t repcount, uint_t flags) 1205 { 1206 if (flags == DDI_DEV_AUTOINCR) 1207 for (; repcount; repcount--) 1208 px_pci_config_put8(handle, dev_addr++, *host_addr++); 1209 else 1210 for (; repcount; repcount--) 1211 px_pci_config_put8(handle, dev_addr, *host_addr++); 1212 } 1213 1214 /* 1215 * Function to rep write 16 bit data into the PCI configuration space behind 1216 * the 21554's host interface. 1217 */ 1218 static void 1219 px_pci_config_rep_put16(ddi_acc_impl_t *handle, uint16_t *host_addr, 1220 uint16_t *dev_addr, size_t repcount, uint_t flags) 1221 { 1222 if (flags == DDI_DEV_AUTOINCR) 1223 for (; repcount; repcount--) 1224 px_pci_config_put16(handle, dev_addr++, *host_addr++); 1225 else 1226 for (; repcount; repcount--) 1227 px_pci_config_put16(handle, dev_addr, *host_addr++); 1228 } 1229 1230 /* 1231 * Function to rep write 32 bit data into the PCI configuration space behind 1232 * the 21554's host interface. 1233 */ 1234 static void 1235 px_pci_config_rep_put32(ddi_acc_impl_t *handle, uint32_t *host_addr, 1236 uint32_t *dev_addr, size_t repcount, uint_t flags) 1237 { 1238 if (flags == DDI_DEV_AUTOINCR) 1239 for (; repcount; repcount--) 1240 px_pci_config_put32(handle, dev_addr++, *host_addr++); 1241 else 1242 for (; repcount; repcount--) 1243 px_pci_config_put32(handle, dev_addr, *host_addr++); 1244 } 1245 1246 /* 1247 * Function to rep write 64 bit data into the PCI configuration space behind 1248 * the 21554's host interface. 1249 */ 1250 static void 1251 px_pci_config_rep_put64(ddi_acc_impl_t *handle, uint64_t *host_addr, 1252 uint64_t *dev_addr, size_t repcount, uint_t flags) 1253 { 1254 if (flags == DDI_DEV_AUTOINCR) 1255 for (; repcount; repcount--) 1256 px_pci_config_put64(handle, dev_addr++, *host_addr++); 1257 else 1258 for (; repcount; repcount--) 1259 px_pci_config_put64(handle, dev_addr, *host_addr++); 1260 } 1261 1262 /* 1263 * Provide a private access handle to route config access calls to Hypervisor. 1264 * Beware: Do all error checking for config space accesses before calling 1265 * this function. ie. do error checking from the calling function. 1266 * Due to a lack of meaningful error code in DDI, the gauranteed return of 1267 * DDI_SUCCESS from here makes the code organization readable/easier from 1268 * the generic code. 1269 */ 1270 /*ARGSUSED*/ 1271 int 1272 px_lib_map_vconfig(dev_info_t *dip, 1273 ddi_map_req_t *mp, pci_config_offset_t off, 1274 pci_regspec_t *rp, caddr_t *addrp) 1275 { 1276 ddi_acc_hdl_t *hp; 1277 ddi_acc_impl_t *ap; 1278 uchar_t busnum; /* bus number */ 1279 uchar_t devnum; /* device number */ 1280 uchar_t funcnum; /* function number */ 1281 px_config_acc_pvt_t *px_pvt; 1282 1283 hp = (ddi_acc_hdl_t *)mp->map_handlep; 1284 ap = (ddi_acc_impl_t *)hp->ah_platform_private; 1285 1286 /* Check for mapping teardown operation */ 1287 if ((mp->map_op == DDI_MO_UNMAP) || 1288 (mp->map_op == DDI_MO_UNLOCK)) { 1289 /* free up memory allocated for the private access handle. */ 1290 px_pvt = (px_config_acc_pvt_t *)hp->ah_bus_private; 1291 kmem_free((void *)px_pvt, sizeof (px_config_acc_pvt_t)); 1292 1293 /* unmap operation of PCI IO/config space. */ 1294 return (DDI_SUCCESS); 1295 } 1296 1297 ap->ahi_get8 = px_pci_config_get8; 1298 ap->ahi_get16 = px_pci_config_get16; 1299 ap->ahi_get32 = px_pci_config_get32; 1300 ap->ahi_get64 = px_pci_config_get64; 1301 ap->ahi_put8 = px_pci_config_put8; 1302 ap->ahi_put16 = px_pci_config_put16; 1303 ap->ahi_put32 = px_pci_config_put32; 1304 ap->ahi_put64 = px_pci_config_put64; 1305 ap->ahi_rep_get8 = px_pci_config_rep_get8; 1306 ap->ahi_rep_get16 = px_pci_config_rep_get16; 1307 ap->ahi_rep_get32 = px_pci_config_rep_get32; 1308 ap->ahi_rep_get64 = px_pci_config_rep_get64; 1309 ap->ahi_rep_put8 = px_pci_config_rep_put8; 1310 ap->ahi_rep_put16 = px_pci_config_rep_put16; 1311 ap->ahi_rep_put32 = px_pci_config_rep_put32; 1312 ap->ahi_rep_put64 = px_pci_config_rep_put64; 1313 1314 /* Initialize to default check/notify functions */ 1315 ap->ahi_fault = 0; 1316 ap->ahi_fault_check = i_ddi_acc_fault_check; 1317 ap->ahi_fault_notify = i_ddi_acc_fault_notify; 1318 1319 /* allocate memory for our private handle */ 1320 px_pvt = (px_config_acc_pvt_t *) 1321 kmem_zalloc(sizeof (px_config_acc_pvt_t), KM_SLEEP); 1322 hp->ah_bus_private = (void *)px_pvt; 1323 1324 busnum = PCI_REG_BUS_G(rp->pci_phys_hi); 1325 devnum = PCI_REG_DEV_G(rp->pci_phys_hi); 1326 funcnum = PCI_REG_FUNC_G(rp->pci_phys_hi); 1327 1328 /* set up private data for use during IO routines */ 1329 1330 /* addr needed by the HV APIs */ 1331 px_pvt->raddr = busnum << 16 | devnum << 11 | funcnum << 8; 1332 /* 1333 * Address that specifies the actual offset into the 256MB 1334 * memory mapped configuration space, 4K per device. 1335 * First 12bits form the offset into 4K config space. 1336 * This address is only used during the IO routines to calculate 1337 * the offset at which the transaction must be performed. 1338 * Drivers bypassing DDI functions to access PCI config space will 1339 * panic the system since the following is a bogus virtual address. 1340 */ 1341 px_pvt->vaddr = busnum << 20 | devnum << 15 | funcnum << 12 | off; 1342 px_pvt->dip = dip; 1343 1344 DBG(DBG_LIB_CFG, dip, "px_config_setup: raddr 0x%x, vaddr 0x%x\n", 1345 px_pvt->raddr, px_pvt->vaddr); 1346 *addrp = (caddr_t)(uintptr_t)px_pvt->vaddr; 1347 return (DDI_SUCCESS); 1348 } 1349 1350 /*ARGSUSED*/ 1351 void 1352 px_lib_map_attr_check(ddi_map_req_t *mp) 1353 { 1354 } 1355 1356 /* 1357 * px_lib_log_safeacc_err: 1358 * Imitate a cpu/mem trap call when a peek/poke fails. 1359 * This will initiate something similar to px_fm_callback. 1360 */ 1361 static void 1362 px_lib_log_safeacc_err(px_t *px_p, ddi_acc_handle_t handle, int fme_flag) 1363 { 1364 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)handle; 1365 px_cb_t *cb_p = px_p->px_cb_p; 1366 ddi_fm_error_t derr; 1367 1368 derr.fme_status = DDI_FM_NONFATAL; 1369 derr.fme_version = DDI_FME_VERSION; 1370 derr.fme_flag = fme_flag; 1371 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 1372 derr.fme_acc_handle = handle; 1373 if (hp) 1374 hp->ahi_err->err_expected = DDI_FM_ERR_EXPECTED; 1375 1376 mutex_enter(&cb_p->xbc_fm_mutex); 1377 1378 (void) ndi_fm_handler_dispatch(px_p->px_dip, NULL, &derr); 1379 1380 mutex_exit(&cb_p->xbc_fm_mutex); 1381 } 1382 1383 1384 #ifdef DEBUG 1385 int px_peekfault_cnt = 0; 1386 int px_pokefault_cnt = 0; 1387 #endif /* DEBUG */ 1388 1389 static int 1390 px_lib_bdf_from_dip(dev_info_t *rdip, uint32_t *bdf) 1391 { 1392 /* Start with an array of 8 reg spaces for now to cover most devices. */ 1393 pci_regspec_t regspec_array[8]; 1394 pci_regspec_t *regspec = regspec_array; 1395 int buflen = sizeof (regspec_array); 1396 boolean_t kmalloced = B_FALSE; 1397 int status; 1398 1399 status = ddi_getlongprop_buf(DDI_DEV_T_ANY, rdip, 1400 DDI_PROP_DONTPASS, "reg", (caddr_t)regspec, &buflen); 1401 1402 /* If need more space, fallback to kmem_alloc. */ 1403 if (status == DDI_PROP_BUF_TOO_SMALL) { 1404 regspec = kmem_alloc(buflen, KM_SLEEP); 1405 1406 status = ddi_getlongprop_buf(DDI_DEV_T_ANY, rdip, 1407 DDI_PROP_DONTPASS, "reg", (caddr_t)regspec, &buflen); 1408 1409 kmalloced = B_TRUE; 1410 } 1411 1412 /* Get phys_hi from first element. All have same bdf. */ 1413 if (status == DDI_PROP_SUCCESS) 1414 *bdf = regspec->pci_phys_hi & (PCI_REG_BDFR_M ^ PCI_REG_REG_M); 1415 1416 if (kmalloced) 1417 kmem_free(regspec, buflen); 1418 1419 return ((status == DDI_PROP_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE); 1420 } 1421 1422 /* 1423 * Do a safe write to a device. 1424 * 1425 * When this function is given a handle (cautious access), all errors are 1426 * suppressed. 1427 * 1428 * When this function is not given a handle (poke), only Unsupported Request 1429 * and Completer Abort errors are suppressed. 1430 * 1431 * In all cases, all errors are returned in the function return status. 1432 */ 1433 1434 int 1435 px_lib_ctlops_poke(dev_info_t *dip, dev_info_t *rdip, 1436 peekpoke_ctlops_t *in_args) 1437 { 1438 px_t *px_p = DIP_TO_STATE(dip); 1439 px_pec_t *pec_p = px_p->px_pec_p; 1440 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)in_args->handle; 1441 1442 size_t repcount = in_args->repcount; 1443 size_t size = in_args->size; 1444 uintptr_t dev_addr = in_args->dev_addr; 1445 uintptr_t host_addr = in_args->host_addr; 1446 1447 int err = DDI_SUCCESS; 1448 uint64_t hvio_poke_status; 1449 uint32_t bdf; 1450 uint32_t wrt_stat; 1451 1452 r_addr_t ra; 1453 uint64_t pokeval; 1454 1455 /* 1456 * Used only to notify error handling peek/poke is occuring 1457 * One scenario is when a fabric err as a result of peek/poke. 1458 * However there is no way to guarantee that the fabric error 1459 * handler will occur in the window where otd is set. 1460 */ 1461 on_trap_data_t otd; 1462 1463 if (px_lib_bdf_from_dip(rdip, &bdf) != DDI_SUCCESS) { 1464 DBG(DBG_LIB_DMA, px_p->px_dip, 1465 "poke: px_lib_bdf_from_dip failed\n"); 1466 err = DDI_FAILURE; 1467 goto done; 1468 } 1469 1470 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1471 for (; repcount; repcount--) { 1472 1473 switch (size) { 1474 case sizeof (uint8_t): 1475 pokeval = *(uint8_t *)host_addr; 1476 break; 1477 case sizeof (uint16_t): 1478 pokeval = *(uint16_t *)host_addr; 1479 break; 1480 case sizeof (uint32_t): 1481 pokeval = *(uint32_t *)host_addr; 1482 break; 1483 case sizeof (uint64_t): 1484 pokeval = *(uint64_t *)host_addr; 1485 break; 1486 default: 1487 DBG(DBG_MAP, px_p->px_dip, 1488 "poke: invalid size %d passed\n", size); 1489 err = DDI_FAILURE; 1490 goto done; 1491 } 1492 1493 /* 1494 * Grab pokefault mutex since hypervisor does not guarantee 1495 * poke serialization. 1496 */ 1497 if (hp) { 1498 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, 1499 (ddi_acc_handle_t)hp); 1500 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1501 } else { 1502 mutex_enter(&pec_p->pec_pokefault_mutex); 1503 pec_p->pec_safeacc_type = DDI_FM_ERR_POKE; 1504 } 1505 pec_p->pec_ontrap_data = &otd; 1506 1507 hvio_poke_status = hvio_poke(px_p->px_dev_hdl, ra, size, 1508 pokeval, bdf, &wrt_stat); 1509 1510 if (otd.ot_trap & OT_DATA_ACCESS) 1511 err = DDI_FAILURE; 1512 1513 if ((hvio_poke_status != H_EOK) || (wrt_stat != H_EOK)) { 1514 err = DDI_FAILURE; 1515 #ifdef DEBUG 1516 px_pokefault_cnt++; 1517 #endif 1518 /* 1519 * For CAUTIOUS and POKE access, notify FMA to 1520 * cleanup. Imitate a cpu/mem trap call like in sun4u. 1521 */ 1522 px_lib_log_safeacc_err(px_p, (ddi_acc_handle_t)hp, 1523 (hp ? DDI_FM_ERR_EXPECTED : 1524 DDI_FM_ERR_POKE)); 1525 1526 pec_p->pec_ontrap_data = NULL; 1527 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1528 if (hp) { 1529 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1530 (ddi_acc_handle_t)hp); 1531 } else { 1532 mutex_exit(&pec_p->pec_pokefault_mutex); 1533 } 1534 goto done; 1535 } 1536 1537 pec_p->pec_ontrap_data = NULL; 1538 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1539 if (hp) { 1540 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1541 (ddi_acc_handle_t)hp); 1542 } else { 1543 mutex_exit(&pec_p->pec_pokefault_mutex); 1544 } 1545 1546 host_addr += size; 1547 1548 if (in_args->flags == DDI_DEV_AUTOINCR) { 1549 dev_addr += size; 1550 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1551 } 1552 } 1553 1554 done: 1555 return (err); 1556 } 1557 1558 1559 /*ARGSUSED*/ 1560 int 1561 px_lib_ctlops_peek(dev_info_t *dip, dev_info_t *rdip, 1562 peekpoke_ctlops_t *in_args, void *result) 1563 { 1564 px_t *px_p = DIP_TO_STATE(dip); 1565 px_pec_t *pec_p = px_p->px_pec_p; 1566 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)in_args->handle; 1567 1568 size_t repcount = in_args->repcount; 1569 uintptr_t dev_addr = in_args->dev_addr; 1570 uintptr_t host_addr = in_args->host_addr; 1571 1572 r_addr_t ra; 1573 uint32_t read_status; 1574 uint64_t hvio_peek_status; 1575 uint64_t peekval; 1576 int err = DDI_SUCCESS; 1577 1578 /* 1579 * Used only to notify error handling peek/poke is occuring 1580 * One scenario is when a fabric err as a result of peek/poke. 1581 * However there is no way to guarantee that the fabric error 1582 * handler will occur in the window where otd is set. 1583 */ 1584 on_trap_data_t otd; 1585 1586 result = (void *)in_args->host_addr; 1587 1588 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1589 for (; repcount; repcount--) { 1590 1591 /* Lock pokefault mutex so read doesn't mask a poke fault. */ 1592 if (hp) { 1593 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, 1594 (ddi_acc_handle_t)hp); 1595 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1596 } else { 1597 mutex_enter(&pec_p->pec_pokefault_mutex); 1598 pec_p->pec_safeacc_type = DDI_FM_ERR_PEEK; 1599 } 1600 pec_p->pec_ontrap_data = &otd; 1601 1602 hvio_peek_status = hvio_peek(px_p->px_dev_hdl, ra, 1603 in_args->size, &read_status, &peekval); 1604 1605 if ((hvio_peek_status != H_EOK) || (read_status != H_EOK)) { 1606 err = DDI_FAILURE; 1607 1608 /* 1609 * For CAUTIOUS and PEEK access, notify FMA to 1610 * cleanup. Imitate a cpu/mem trap call like in sun4u. 1611 */ 1612 px_lib_log_safeacc_err(px_p, (ddi_acc_handle_t)hp, 1613 (hp ? DDI_FM_ERR_EXPECTED : 1614 DDI_FM_ERR_PEEK)); 1615 1616 /* Stuff FFs in host addr if peek. */ 1617 if (hp == NULL) { 1618 int i; 1619 uint8_t *ff_addr = (uint8_t *)host_addr; 1620 for (i = 0; i < in_args->size; i++) 1621 *ff_addr++ = 0xff; 1622 } 1623 #ifdef DEBUG 1624 px_peekfault_cnt++; 1625 #endif 1626 pec_p->pec_ontrap_data = NULL; 1627 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1628 if (hp) { 1629 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1630 (ddi_acc_handle_t)hp); 1631 } else { 1632 mutex_exit(&pec_p->pec_pokefault_mutex); 1633 } 1634 goto done; 1635 1636 } 1637 pec_p->pec_ontrap_data = NULL; 1638 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1639 if (hp) { 1640 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1641 (ddi_acc_handle_t)hp); 1642 } else { 1643 mutex_exit(&pec_p->pec_pokefault_mutex); 1644 } 1645 1646 switch (in_args->size) { 1647 case sizeof (uint8_t): 1648 *(uint8_t *)host_addr = (uint8_t)peekval; 1649 break; 1650 case sizeof (uint16_t): 1651 *(uint16_t *)host_addr = (uint16_t)peekval; 1652 break; 1653 case sizeof (uint32_t): 1654 *(uint32_t *)host_addr = (uint32_t)peekval; 1655 break; 1656 case sizeof (uint64_t): 1657 *(uint64_t *)host_addr = (uint64_t)peekval; 1658 break; 1659 default: 1660 DBG(DBG_MAP, px_p->px_dip, 1661 "peek: invalid size %d passed\n", 1662 in_args->size); 1663 err = DDI_FAILURE; 1664 goto done; 1665 } 1666 1667 host_addr += in_args->size; 1668 1669 if (in_args->flags == DDI_DEV_AUTOINCR) { 1670 dev_addr += in_args->size; 1671 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1672 } 1673 } 1674 done: 1675 return (err); 1676 } 1677 1678 1679 /* add interrupt vector */ 1680 int 1681 px_err_add_intr(px_fault_t *px_fault_p) 1682 { 1683 int ret; 1684 px_t *px_p = DIP_TO_STATE(px_fault_p->px_fh_dip); 1685 1686 DBG(DBG_LIB_INT, px_p->px_dip, 1687 "px_err_add_intr: calling add_ivintr"); 1688 ret = add_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL, 1689 px_fault_p->px_err_func, (caddr_t)px_fault_p, 1690 (caddr_t)&px_fault_p->px_intr_payload[0]); 1691 1692 if (ret != DDI_SUCCESS) { 1693 DBG(DBG_LIB_INT, px_p->px_dip, 1694 "add_ivintr returns %d, faultp: %p", ret, px_fault_p); 1695 1696 return (ret); 1697 } 1698 DBG(DBG_LIB_INT, px_p->px_dip, 1699 "px_err_add_intr: ib_intr_enable "); 1700 1701 px_ib_intr_enable(px_p, intr_dist_cpuid(), px_fault_p->px_intr_ino); 1702 1703 return (ret); 1704 } 1705 1706 1707 /* remove interrupt vector */ 1708 void 1709 px_err_rem_intr(px_fault_t *px_fault_p) 1710 { 1711 px_t *px_p = DIP_TO_STATE(px_fault_p->px_fh_dip); 1712 1713 rem_ivintr(px_fault_p->px_fh_sysino, NULL); 1714 1715 px_ib_intr_disable(px_p->px_ib_p, px_fault_p->px_intr_ino, 1716 IB_INTR_WAIT); 1717 } 1718 1719 1720 #ifdef FMA 1721 void 1722 px_fill_rc_status(px_fault_t *px_fault_p, pciex_rc_error_regs_t *rc_status) 1723 { 1724 px_pec_err_t *err_pkt; 1725 1726 err_pkt = (px_pec_err_t *)px_fault_p->px_intr_payload; 1727 1728 /* initialise all the structure members */ 1729 rc_status->status_valid = 0; 1730 1731 if (err_pkt->pec_descr.P) { 1732 /* PCI Status Register */ 1733 rc_status->pci_err_status = err_pkt->pci_err_status; 1734 rc_status->status_valid |= PCI_ERR_STATUS_VALID; 1735 } 1736 1737 if (err_pkt->pec_descr.E) { 1738 /* PCIe Status Register */ 1739 rc_status->pcie_err_status = err_pkt->pcie_err_status; 1740 rc_status->status_valid |= PCIE_ERR_STATUS_VALID; 1741 } 1742 1743 if (err_pkt->pec_descr.U) { 1744 rc_status->ue_status = err_pkt->ue_reg_status; 1745 rc_status->status_valid |= UE_STATUS_VALID; 1746 } 1747 1748 if (err_pkt->pec_descr.H) { 1749 rc_status->ue_hdr1 = err_pkt->hdr[0]; 1750 rc_status->status_valid |= UE_HDR1_VALID; 1751 } 1752 1753 if (err_pkt->pec_descr.I) { 1754 rc_status->ue_hdr2 = err_pkt->hdr[1]; 1755 rc_status->status_valid |= UE_HDR2_VALID; 1756 } 1757 1758 /* ue_fst_err_ptr - not available for sun4v?? */ 1759 1760 1761 if (err_pkt->pec_descr.S) { 1762 rc_status->source_id = err_pkt->err_src_reg; 1763 rc_status->status_valid |= SOURCE_ID_VALID; 1764 } 1765 1766 if (err_pkt->pec_descr.R) { 1767 rc_status->root_err_status = err_pkt->root_err_status; 1768 rc_status->status_valid |= CE_STATUS_VALID; 1769 } 1770 } 1771 #endif 1772 1773 /*ARGSUSED*/ 1774 int 1775 px_lib_pmctl(int cmd, px_t *px_p) 1776 { 1777 return (DDI_FAILURE); 1778 } 1779 1780 /*ARGSUSED*/ 1781 uint_t 1782 px_lup_softintr(caddr_t arg) 1783 { 1784 return (DDI_INTR_CLAIMED); 1785 } 1786 1787 /*ARGSUSED*/ 1788 uint_t 1789 px_pmeq_intr(caddr_t arg) 1790 { 1791 return (DDI_INTR_CLAIMED); 1792 } 1793 1794 /* 1795 * Unprotected raw reads/writes of fabric device's config space. 1796 * Only used for temporary PCI-E Fabric Error Handling. 1797 */ 1798 uint32_t 1799 px_fab_get(px_t *px_p, pcie_req_id_t bdf, uint16_t offset) { 1800 uint32_t data = 0; 1801 1802 (void) hvio_config_get(px_p->px_dev_hdl, 1803 (bdf << PX_RA_BDF_SHIFT), offset, 4, 1804 (pci_cfg_data_t *)&data); 1805 1806 return (data); 1807 } 1808 1809 void 1810 px_fab_set(px_t *px_p, pcie_req_id_t bdf, uint16_t offset, 1811 uint32_t val) { 1812 pci_cfg_data_t wdata = { 0 }; 1813 1814 wdata.qw = (uint32_t)val; 1815 (void) hvio_config_put(px_p->px_dev_hdl, 1816 (bdf << PX_RA_BDF_SHIFT), offset, 4, wdata); 1817 } 1818 1819 /* Dummy cpr add callback */ 1820 /*ARGSUSED*/ 1821 void 1822 px_cpr_add_callb(px_t *px_p) 1823 { 1824 } 1825 1826 /* Dummy cpr rem callback */ 1827 /*ARGSUSED*/ 1828 void 1829 px_cpr_rem_callb(px_t *px_p) 1830 { 1831 } 1832