1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/types.h> 30 #include <sys/sysmacros.h> 31 #include <sys/ddi.h> 32 #include <sys/async.h> 33 #include <sys/sunddi.h> 34 #include <sys/ddifm.h> 35 #include <sys/fm/protocol.h> 36 #include <sys/vmem.h> 37 #include <sys/intr.h> 38 #include <sys/ivintr.h> 39 #include <sys/errno.h> 40 #include <sys/hypervisor_api.h> 41 #include <px_obj.h> 42 #include <sys/machsystm.h> 43 #include "px_lib4v.h" 44 #include "px_err.h" 45 46 /* mask for the ranges property in calculating the real PFN range */ 47 uint_t px_ranges_phi_mask = ((1 << 28) -1); 48 49 int 50 px_lib_dev_init(dev_info_t *dip, devhandle_t *dev_hdl) 51 { 52 px_nexus_regspec_t *rp; 53 uint_t reglen; 54 int ret; 55 56 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dip 0x%p\n", dip); 57 58 ret = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 59 "reg", (uchar_t **)&rp, ®len); 60 if (ret != DDI_PROP_SUCCESS) { 61 DBG(DBG_ATTACH, dip, "px_lib_dev_init failed ret=%d\n", ret); 62 return (DDI_FAILURE); 63 } 64 65 /* 66 * Initilize device handle. The device handle uniquely identifies 67 * a SUN4V device. It consists of the lower 28-bits of the hi-cell 68 * of the first entry of the SUN4V device's "reg" property as 69 * defined by the SUN4V Bus Binding to Open Firmware. 70 */ 71 *dev_hdl = (devhandle_t)((rp->phys_addr >> 32) & DEVHDLE_MASK); 72 73 ddi_prop_free(rp); 74 75 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dev_hdl 0x%llx\n", *dev_hdl); 76 77 return (DDI_SUCCESS); 78 } 79 80 /*ARGSUSED*/ 81 int 82 px_lib_dev_fini(dev_info_t *dip) 83 { 84 DBG(DBG_DETACH, dip, "px_lib_dev_fini: dip 0x%p\n", dip); 85 86 return (DDI_SUCCESS); 87 } 88 89 /*ARGSUSED*/ 90 int 91 px_lib_intr_devino_to_sysino(dev_info_t *dip, devino_t devino, 92 sysino_t *sysino) 93 { 94 uint64_t ret; 95 96 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: dip 0x%p " 97 "devino 0x%x\n", dip, devino); 98 99 if ((ret = hvio_intr_devino_to_sysino(DIP_TO_HANDLE(dip), 100 devino, sysino)) != H_EOK) { 101 DBG(DBG_LIB_INT, dip, 102 "hvio_intr_devino_to_sysino failed, ret 0x%lx\n", ret); 103 return (DDI_FAILURE); 104 } 105 106 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: sysino 0x%llx\n", 107 *sysino); 108 109 return (DDI_SUCCESS); 110 } 111 112 /*ARGSUSED*/ 113 int 114 px_lib_intr_getvalid(dev_info_t *dip, sysino_t sysino, 115 intr_valid_state_t *intr_valid_state) 116 { 117 uint64_t ret; 118 119 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: dip 0x%p sysino 0x%llx\n", 120 dip, sysino); 121 122 if ((ret = hvio_intr_getvalid(sysino, 123 (int *)intr_valid_state)) != H_EOK) { 124 DBG(DBG_LIB_INT, dip, "hvio_intr_getvalid failed, ret 0x%lx\n", 125 ret); 126 return (DDI_FAILURE); 127 } 128 129 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: intr_valid_state 0x%x\n", 130 *intr_valid_state); 131 132 return (DDI_SUCCESS); 133 } 134 135 /*ARGSUSED*/ 136 int 137 px_lib_intr_setvalid(dev_info_t *dip, sysino_t sysino, 138 intr_valid_state_t intr_valid_state) 139 { 140 uint64_t ret; 141 142 DBG(DBG_LIB_INT, dip, "px_lib_intr_setvalid: dip 0x%p sysino 0x%llx " 143 "intr_valid_state 0x%x\n", dip, sysino, intr_valid_state); 144 145 if ((ret = hvio_intr_setvalid(sysino, intr_valid_state)) != H_EOK) { 146 DBG(DBG_LIB_INT, dip, "hvio_intr_setvalid failed, ret 0x%lx\n", 147 ret); 148 return (DDI_FAILURE); 149 } 150 151 return (DDI_SUCCESS); 152 } 153 154 /*ARGSUSED*/ 155 int 156 px_lib_intr_getstate(dev_info_t *dip, sysino_t sysino, 157 intr_state_t *intr_state) 158 { 159 uint64_t ret; 160 161 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: dip 0x%p sysino 0x%llx\n", 162 dip, sysino); 163 164 if ((ret = hvio_intr_getstate(sysino, (int *)intr_state)) != H_EOK) { 165 DBG(DBG_LIB_INT, dip, "hvio_intr_getstate failed, ret 0x%lx\n", 166 ret); 167 return (DDI_FAILURE); 168 } 169 170 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: intr_state 0x%x\n", 171 *intr_state); 172 173 return (DDI_SUCCESS); 174 } 175 176 /*ARGSUSED*/ 177 int 178 px_lib_intr_setstate(dev_info_t *dip, sysino_t sysino, 179 intr_state_t intr_state) 180 { 181 uint64_t ret; 182 183 DBG(DBG_LIB_INT, dip, "px_lib_intr_setstate: dip 0x%p sysino 0x%llx " 184 "intr_state 0x%x\n", dip, sysino, intr_state); 185 186 if ((ret = hvio_intr_setstate(sysino, intr_state)) != H_EOK) { 187 DBG(DBG_LIB_INT, dip, "hvio_intr_setstate failed, ret 0x%lx\n", 188 ret); 189 return (DDI_FAILURE); 190 } 191 192 return (DDI_SUCCESS); 193 } 194 195 /*ARGSUSED*/ 196 int 197 px_lib_intr_gettarget(dev_info_t *dip, sysino_t sysino, cpuid_t *cpuid) 198 { 199 uint64_t ret; 200 201 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: dip 0x%p sysino 0x%llx\n", 202 dip, sysino); 203 204 if ((ret = hvio_intr_gettarget(sysino, cpuid)) != H_EOK) { 205 DBG(DBG_LIB_INT, dip, 206 "hvio_intr_gettarget failed, ret 0x%lx\n", ret); 207 return (DDI_FAILURE); 208 } 209 210 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: cpuid 0x%x\n", cpuid); 211 212 return (DDI_SUCCESS); 213 } 214 215 /*ARGSUSED*/ 216 int 217 px_lib_intr_settarget(dev_info_t *dip, sysino_t sysino, cpuid_t cpuid) 218 { 219 uint64_t ret; 220 221 DBG(DBG_LIB_INT, dip, "px_lib_intr_settarget: dip 0x%p sysino 0x%llx " 222 "cpuid 0x%x\n", dip, sysino, cpuid); 223 224 if ((ret = hvio_intr_settarget(sysino, cpuid)) != H_EOK) { 225 DBG(DBG_LIB_INT, dip, 226 "hvio_intr_settarget failed, ret 0x%lx\n", ret); 227 return (DDI_FAILURE); 228 } 229 230 return (DDI_SUCCESS); 231 } 232 233 /*ARGSUSED*/ 234 int 235 px_lib_intr_reset(dev_info_t *dip) 236 { 237 px_t *px_p = DIP_TO_STATE(dip); 238 px_ib_t *ib_p = px_p->px_ib_p; 239 px_ib_ino_info_t *ino_p; 240 241 DBG(DBG_LIB_INT, dip, "px_lib_intr_reset: dip 0x%p\n", dip); 242 243 mutex_enter(&ib_p->ib_ino_lst_mutex); 244 245 /* Reset all Interrupts */ 246 for (ino_p = ib_p->ib_ino_lst; ino_p; ino_p = ino_p->ino_next) { 247 if (px_lib_intr_setstate(dip, ino_p->ino_sysino, 248 INTR_IDLE_STATE) != DDI_SUCCESS) 249 return (BF_FATAL); 250 } 251 252 mutex_exit(&ib_p->ib_ino_lst_mutex); 253 254 return (BF_NONE); 255 } 256 257 /*ARGSUSED*/ 258 int 259 px_lib_iommu_map(dev_info_t *dip, tsbid_t tsbid, pages_t pages, 260 io_attributes_t io_attr, void *addr, size_t pfn_index, 261 int flag) 262 { 263 tsbnum_t tsb_num = PCI_TSBID_TO_TSBNUM(tsbid); 264 tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); 265 io_page_list_t *pfns, *pfn_p; 266 pages_t ttes_mapped = 0; 267 int i, err = DDI_SUCCESS; 268 269 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: dip 0x%p tsbid 0x%llx " 270 "pages 0x%x atrr 0x%x addr 0x%p pfn_index 0x%llx, flag 0x%x\n", 271 dip, tsbid, pages, io_attr, addr, pfn_index, flag); 272 273 if ((pfns = pfn_p = kmem_zalloc((pages * sizeof (io_page_list_t)), 274 KM_NOSLEEP)) == NULL) { 275 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: kmem_zalloc failed\n"); 276 return (DDI_FAILURE); 277 } 278 279 for (i = 0; i < pages; i++) 280 pfns[i] = MMU_PTOB(PX_ADDR2PFN(addr, pfn_index, flag, i)); 281 282 while ((ttes_mapped = pfn_p - pfns) < pages) { 283 uintptr_t ra = va_to_pa(pfn_p); 284 pages_t ttes2map; 285 uint64_t ret; 286 287 ttes2map = (MMU_PAGE_SIZE - P2PHASE(ra, MMU_PAGE_SIZE)) >> 3; 288 ra = MMU_PTOB(MMU_BTOP(ra)); 289 290 for (ttes2map = MIN(ttes2map, pages - ttes_mapped); ttes2map; 291 ttes2map -= ttes_mapped, pfn_p += ttes_mapped) { 292 293 ttes_mapped = 0; 294 if ((ret = hvio_iommu_map(DIP_TO_HANDLE(dip), 295 PCI_TSBID(tsb_num, tsb_index + (pfn_p - pfns)), 296 ttes2map, io_attr, (io_page_list_t *)(ra | 297 ((uintptr_t)pfn_p & MMU_PAGE_OFFSET)), 298 &ttes_mapped)) != H_EOK) { 299 DBG(DBG_LIB_DMA, dip, "hvio_iommu_map failed " 300 "ret 0x%lx\n", ret); 301 302 ttes_mapped = pfn_p - pfns; 303 err = DDI_FAILURE; 304 goto cleanup; 305 } 306 307 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: tsb_num 0x%x " 308 "tsb_index 0x%lx ttes_to_map 0x%lx attr 0x%x " 309 "ra 0x%p ttes_mapped 0x%x\n", tsb_num, 310 tsb_index + (pfn_p - pfns), ttes2map, io_attr, 311 ra | ((uintptr_t)pfn_p & MMU_PAGE_OFFSET), 312 ttes_mapped); 313 } 314 } 315 316 cleanup: 317 if ((err == DDI_FAILURE) && ttes_mapped) 318 (void) px_lib_iommu_demap(dip, tsbid, ttes_mapped); 319 320 kmem_free(pfns, pages * sizeof (io_page_list_t)); 321 return (err); 322 } 323 324 /*ARGSUSED*/ 325 int 326 px_lib_iommu_demap(dev_info_t *dip, tsbid_t tsbid, pages_t pages) 327 { 328 tsbnum_t tsb_num = PCI_TSBID_TO_TSBNUM(tsbid); 329 tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); 330 pages_t ttes2demap, ttes_demapped = 0; 331 uint64_t ret; 332 333 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: dip 0x%p tsbid 0x%llx " 334 "pages 0x%x\n", dip, tsbid, pages); 335 336 for (ttes2demap = pages; ttes2demap; 337 ttes2demap -= ttes_demapped, tsb_index += ttes_demapped) { 338 if ((ret = hvio_iommu_demap(DIP_TO_HANDLE(dip), 339 PCI_TSBID(tsb_num, tsb_index), ttes2demap, 340 &ttes_demapped)) != H_EOK) { 341 DBG(DBG_LIB_DMA, dip, "hvio_iommu_demap failed, " 342 "ret 0x%lx\n", ret); 343 344 return (DDI_FAILURE); 345 } 346 347 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: tsb_num 0x%x " 348 "tsb_index 0x%lx ttes_to_demap 0x%lx ttes_demapped 0x%x\n", 349 tsb_num, tsb_index, ttes2demap, ttes_demapped); 350 } 351 352 return (DDI_SUCCESS); 353 } 354 355 /*ARGSUSED*/ 356 int 357 px_lib_iommu_getmap(dev_info_t *dip, tsbid_t tsbid, 358 io_attributes_t *attributes_p, r_addr_t *r_addr_p) 359 { 360 uint64_t ret; 361 362 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: dip 0x%p tsbid 0x%llx\n", 363 dip, tsbid); 364 365 if ((ret = hvio_iommu_getmap(DIP_TO_HANDLE(dip), tsbid, 366 attributes_p, r_addr_p)) != H_EOK) { 367 DBG(DBG_LIB_DMA, dip, 368 "hvio_iommu_getmap failed, ret 0x%lx\n", ret); 369 370 return ((ret == H_ENOMAP) ? DDI_DMA_NOMAPPING:DDI_FAILURE); 371 } 372 373 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: attr 0x%x r_addr 0x%llx\n", 374 *attributes_p, *r_addr_p); 375 376 return (DDI_SUCCESS); 377 } 378 379 380 /* 381 * Checks dma attributes against system bypass ranges 382 * A sun4v device must be capable of generating the entire 64-bit 383 * address in order to perform bypass DMA. 384 */ 385 /*ARGSUSED*/ 386 int 387 px_lib_dma_bypass_rngchk(ddi_dma_attr_t *attrp, uint64_t *lo_p, uint64_t *hi_p) 388 { 389 if ((attrp->dma_attr_addr_lo != 0ull) || 390 (attrp->dma_attr_addr_hi != UINT64_MAX)) { 391 392 return (DDI_DMA_BADATTR); 393 } 394 395 *lo_p = 0ull; 396 *hi_p = UINT64_MAX; 397 398 return (DDI_SUCCESS); 399 } 400 401 402 /*ARGSUSED*/ 403 int 404 px_lib_iommu_getbypass(dev_info_t *dip, r_addr_t ra, 405 io_attributes_t io_attributes, io_addr_t *io_addr_p) 406 { 407 uint64_t ret; 408 409 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: dip 0x%p ra 0x%llx " 410 "attr 0x%x\n", dip, ra, io_attributes); 411 412 if ((ret = hvio_iommu_getbypass(DIP_TO_HANDLE(dip), ra, 413 io_attributes, io_addr_p)) != H_EOK) { 414 DBG(DBG_LIB_DMA, dip, 415 "hvio_iommu_getbypass failed, ret 0x%lx\n", ret); 416 return (ret == H_ENOTSUPPORTED ? DDI_ENOTSUP : DDI_FAILURE); 417 } 418 419 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: io_addr 0x%llx\n", 420 *io_addr_p); 421 422 return (DDI_SUCCESS); 423 } 424 425 /*ARGSUSED*/ 426 int 427 px_lib_dma_sync(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 428 off_t off, size_t len, uint_t cache_flags) 429 { 430 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 431 uint64_t sync_dir; 432 px_dvma_addr_t dvma_addr, pg_off; 433 size_t num_sync; 434 uint64_t status = H_EOK; 435 436 DBG(DBG_LIB_DMA, dip, "px_lib_dma_sync: dip 0x%p rdip 0x%p " 437 "handle 0x%llx off 0x%x len 0x%x flags 0x%x\n", 438 dip, rdip, handle, off, len, cache_flags); 439 440 if (!(mp->dmai_flags & PX_DMAI_FLAGS_INUSE)) { 441 cmn_err(CE_WARN, "%s%d: Unbound dma handle %p.", 442 ddi_driver_name(rdip), ddi_get_instance(rdip), (void *)mp); 443 return (DDI_FAILURE); 444 } 445 446 if (mp->dmai_flags & PX_DMAI_FLAGS_NOSYNC) 447 return (DDI_SUCCESS); 448 449 if (!len) 450 len = mp->dmai_size; 451 452 pg_off = mp->dmai_offset; /* start min */ 453 dvma_addr = MAX(off, pg_off); /* lo */ 454 pg_off += mp->dmai_size; /* end max */ 455 pg_off = MIN(off + len, pg_off); /* hi */ 456 if (dvma_addr >= pg_off) { /* lo >= hi ? */ 457 cmn_err(CE_WARN, "%s%d: %lx + %lx out of window [%lx,%lx]", 458 ddi_driver_name(rdip), ddi_get_instance(rdip), 459 off, len, mp->dmai_offset, 460 mp->dmai_offset + mp->dmai_size); 461 return (DDI_FAILURE); 462 } 463 464 len = pg_off - dvma_addr; /* sz = hi - lo */ 465 dvma_addr += mp->dmai_mapping; /* start addr */ 466 467 if (mp->dmai_rflags & DDI_DMA_READ) 468 sync_dir = HVIO_DMA_SYNC_DIR_FROM_DEV; 469 else 470 sync_dir = HVIO_DMA_SYNC_DIR_TO_DEV; 471 472 for (; ((len > 0) && (status == H_EOK)); len -= num_sync) { 473 status = hvio_dma_sync(DIP_TO_HANDLE(dip), dvma_addr, len, 474 sync_dir, &num_sync); 475 dvma_addr += num_sync; 476 } 477 478 return ((status == H_EOK) ? DDI_SUCCESS : DDI_FAILURE); 479 } 480 481 482 /* 483 * MSIQ Functions: 484 */ 485 486 /*ARGSUSED*/ 487 int 488 px_lib_msiq_init(dev_info_t *dip) 489 { 490 px_t *px_p = DIP_TO_STATE(dip); 491 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 492 uint64_t *msiq_addr, ra; 493 size_t msiq_size; 494 uint_t rec_cnt; 495 int i, err = DDI_SUCCESS; 496 uint64_t ret; 497 498 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_init: dip 0x%p\n", dip); 499 500 msiq_addr = (uint64_t *)(((uint64_t)msiq_state_p->msiq_buf_p + 501 (MMU_PAGE_SIZE - 1)) >> MMU_PAGE_SHIFT << MMU_PAGE_SHIFT); 502 503 msiq_size = msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t); 504 505 for (i = 0; i < msiq_state_p->msiq_cnt; i++) { 506 ra = (r_addr_t)va_to_pa((caddr_t)msiq_addr + (i * msiq_size)); 507 508 if ((ret = hvio_msiq_conf(DIP_TO_HANDLE(dip), 509 (i + msiq_state_p->msiq_1st_msiq_id), 510 ra, msiq_state_p->msiq_rec_cnt)) != H_EOK) { 511 DBG(DBG_LIB_MSIQ, dip, 512 "hvio_msiq_conf failed, ret 0x%lx\n", ret); 513 err = DDI_FAILURE; 514 break; 515 } 516 517 if ((err = px_lib_msiq_info(dip, 518 (i + msiq_state_p->msiq_1st_msiq_id), 519 &ra, &rec_cnt)) != DDI_SUCCESS) { 520 DBG(DBG_LIB_MSIQ, dip, 521 "px_lib_msiq_info failed, ret 0x%x\n", err); 522 err = DDI_FAILURE; 523 break; 524 } 525 526 DBG(DBG_LIB_MSIQ, dip, 527 "px_lib_msiq_init: ra 0x%p rec_cnt 0x%x\n", ra, rec_cnt); 528 } 529 530 return (err); 531 } 532 533 /*ARGSUSED*/ 534 int 535 px_lib_msiq_fini(dev_info_t *dip) 536 { 537 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_fini: dip 0x%p\n", dip); 538 539 return (DDI_SUCCESS); 540 } 541 542 /*ARGSUSED*/ 543 int 544 px_lib_msiq_info(dev_info_t *dip, msiqid_t msiq_id, r_addr_t *ra_p, 545 uint_t *msiq_rec_cnt_p) 546 { 547 uint64_t ret; 548 549 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: dip 0x%p msiq_id 0x%x\n", 550 dip, msiq_id); 551 552 if ((ret = hvio_msiq_info(DIP_TO_HANDLE(dip), 553 msiq_id, ra_p, msiq_rec_cnt_p)) != H_EOK) { 554 DBG(DBG_LIB_MSIQ, dip, 555 "hvio_msiq_info failed, ret 0x%lx\n", ret); 556 return (DDI_FAILURE); 557 } 558 559 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: ra_p 0x%p msiq_rec_cnt 0x%x\n", 560 ra_p, *msiq_rec_cnt_p); 561 562 return (DDI_SUCCESS); 563 } 564 565 /*ARGSUSED*/ 566 int 567 px_lib_msiq_getvalid(dev_info_t *dip, msiqid_t msiq_id, 568 pci_msiq_valid_state_t *msiq_valid_state) 569 { 570 uint64_t ret; 571 572 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: dip 0x%p msiq_id 0x%x\n", 573 dip, msiq_id); 574 575 if ((ret = hvio_msiq_getvalid(DIP_TO_HANDLE(dip), 576 msiq_id, msiq_valid_state)) != H_EOK) { 577 DBG(DBG_LIB_MSIQ, dip, 578 "hvio_msiq_getvalid failed, ret 0x%lx\n", ret); 579 return (DDI_FAILURE); 580 } 581 582 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: msiq_valid_state 0x%x\n", 583 *msiq_valid_state); 584 585 return (DDI_SUCCESS); 586 } 587 588 /*ARGSUSED*/ 589 int 590 px_lib_msiq_setvalid(dev_info_t *dip, msiqid_t msiq_id, 591 pci_msiq_valid_state_t msiq_valid_state) 592 { 593 uint64_t ret; 594 595 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setvalid: dip 0x%p msiq_id 0x%x " 596 "msiq_valid_state 0x%x\n", dip, msiq_id, msiq_valid_state); 597 598 if ((ret = hvio_msiq_setvalid(DIP_TO_HANDLE(dip), 599 msiq_id, msiq_valid_state)) != H_EOK) { 600 DBG(DBG_LIB_MSIQ, dip, 601 "hvio_msiq_setvalid failed, ret 0x%lx\n", ret); 602 return (DDI_FAILURE); 603 } 604 605 return (DDI_SUCCESS); 606 } 607 608 /*ARGSUSED*/ 609 int 610 px_lib_msiq_getstate(dev_info_t *dip, msiqid_t msiq_id, 611 pci_msiq_state_t *msiq_state) 612 { 613 uint64_t ret; 614 615 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: dip 0x%p msiq_id 0x%x\n", 616 dip, msiq_id); 617 618 if ((ret = hvio_msiq_getstate(DIP_TO_HANDLE(dip), 619 msiq_id, msiq_state)) != H_EOK) { 620 DBG(DBG_LIB_MSIQ, dip, 621 "hvio_msiq_getstate failed, ret 0x%lx\n", ret); 622 return (DDI_FAILURE); 623 } 624 625 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: msiq_state 0x%x\n", 626 *msiq_state); 627 628 return (DDI_SUCCESS); 629 } 630 631 /*ARGSUSED*/ 632 int 633 px_lib_msiq_setstate(dev_info_t *dip, msiqid_t msiq_id, 634 pci_msiq_state_t msiq_state) 635 { 636 uint64_t ret; 637 638 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setstate: dip 0x%p msiq_id 0x%x " 639 "msiq_state 0x%x\n", dip, msiq_id, msiq_state); 640 641 if ((ret = hvio_msiq_setstate(DIP_TO_HANDLE(dip), 642 msiq_id, msiq_state)) != H_EOK) { 643 DBG(DBG_LIB_MSIQ, dip, 644 "hvio_msiq_setstate failed, ret 0x%lx\n", ret); 645 return (DDI_FAILURE); 646 } 647 648 return (DDI_SUCCESS); 649 } 650 651 /*ARGSUSED*/ 652 int 653 px_lib_msiq_gethead(dev_info_t *dip, msiqid_t msiq_id, 654 msiqhead_t *msiq_head_p) 655 { 656 uint64_t ret; 657 658 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gethead: dip 0x%p msiq_id 0x%x\n", 659 dip, msiq_id); 660 661 if ((ret = hvio_msiq_gethead(DIP_TO_HANDLE(dip), 662 msiq_id, msiq_head_p)) != H_EOK) { 663 DBG(DBG_LIB_MSIQ, dip, 664 "hvio_msiq_gethead failed, ret 0x%lx\n", ret); 665 return (DDI_FAILURE); 666 } 667 668 *msiq_head_p = (*msiq_head_p / sizeof (msiq_rec_t)); 669 670 DBG(DBG_LIB_MSIQ, dip, "px_msiq_gethead: msiq_head 0x%x\n", 671 *msiq_head_p); 672 673 return (DDI_SUCCESS); 674 } 675 676 /*ARGSUSED*/ 677 int 678 px_lib_msiq_sethead(dev_info_t *dip, msiqid_t msiq_id, 679 msiqhead_t msiq_head) 680 { 681 uint64_t ret; 682 683 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_sethead: dip 0x%p msiq_id 0x%x " 684 "msiq_head 0x%x\n", dip, msiq_id, msiq_head); 685 686 if ((ret = hvio_msiq_sethead(DIP_TO_HANDLE(dip), 687 msiq_id, msiq_head * sizeof (msiq_rec_t))) != H_EOK) { 688 DBG(DBG_LIB_MSIQ, dip, 689 "hvio_msiq_sethead failed, ret 0x%lx\n", ret); 690 return (DDI_FAILURE); 691 } 692 693 return (DDI_SUCCESS); 694 } 695 696 /*ARGSUSED*/ 697 int 698 px_lib_msiq_gettail(dev_info_t *dip, msiqid_t msiq_id, 699 msiqtail_t *msiq_tail_p) 700 { 701 uint64_t ret; 702 703 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: dip 0x%p msiq_id 0x%x\n", 704 dip, msiq_id); 705 706 if ((ret = hvio_msiq_gettail(DIP_TO_HANDLE(dip), 707 msiq_id, msiq_tail_p)) != H_EOK) { 708 DBG(DBG_LIB_MSIQ, dip, 709 "hvio_msiq_gettail failed, ret 0x%lx\n", ret); 710 return (DDI_FAILURE); 711 } 712 713 *msiq_tail_p = (*msiq_tail_p / sizeof (msiq_rec_t)); 714 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: msiq_tail 0x%x\n", 715 *msiq_tail_p); 716 717 return (DDI_SUCCESS); 718 } 719 720 /*ARGSUSED*/ 721 void 722 px_lib_get_msiq_rec(dev_info_t *dip, px_msiq_t *msiq_p, msiq_rec_t *msiq_rec_p) 723 { 724 msiq_rec_t *curr_msiq_rec_p = (msiq_rec_t *)msiq_p->msiq_curr; 725 726 DBG(DBG_LIB_MSIQ, dip, "px_lib_get_msiq_rec: dip 0x%p\n", dip); 727 728 if (!curr_msiq_rec_p->msiq_rec_type) 729 return; 730 731 *msiq_rec_p = *curr_msiq_rec_p; 732 733 /* Zero out msiq_rec_type field */ 734 curr_msiq_rec_p->msiq_rec_type = 0; 735 } 736 737 /* 738 * MSI Functions: 739 */ 740 741 /*ARGSUSED*/ 742 int 743 px_lib_msi_init(dev_info_t *dip) 744 { 745 DBG(DBG_LIB_MSI, dip, "px_lib_msi_init: dip 0x%p\n", dip); 746 747 /* Noop */ 748 return (DDI_SUCCESS); 749 } 750 751 /*ARGSUSED*/ 752 int 753 px_lib_msi_getmsiq(dev_info_t *dip, msinum_t msi_num, 754 msiqid_t *msiq_id) 755 { 756 uint64_t ret; 757 758 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: dip 0x%p msi_num 0x%x\n", 759 dip, msi_num); 760 761 if ((ret = hvio_msi_getmsiq(DIP_TO_HANDLE(dip), 762 msi_num, msiq_id)) != H_EOK) { 763 DBG(DBG_LIB_MSI, dip, 764 "hvio_msi_getmsiq failed, ret 0x%lx\n", ret); 765 return (DDI_FAILURE); 766 } 767 768 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: msiq_id 0x%x\n", 769 *msiq_id); 770 771 return (DDI_SUCCESS); 772 } 773 774 /*ARGSUSED*/ 775 int 776 px_lib_msi_setmsiq(dev_info_t *dip, msinum_t msi_num, 777 msiqid_t msiq_id, msi_type_t msitype) 778 { 779 uint64_t ret; 780 781 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setmsiq: dip 0x%p msi_num 0x%x " 782 "msq_id 0x%x\n", dip, msi_num, msiq_id); 783 784 if ((ret = hvio_msi_setmsiq(DIP_TO_HANDLE(dip), 785 msi_num, msiq_id, msitype)) != H_EOK) { 786 DBG(DBG_LIB_MSI, dip, 787 "hvio_msi_setmsiq failed, ret 0x%lx\n", ret); 788 return (DDI_FAILURE); 789 } 790 791 return (DDI_SUCCESS); 792 } 793 794 /*ARGSUSED*/ 795 int 796 px_lib_msi_getvalid(dev_info_t *dip, msinum_t msi_num, 797 pci_msi_valid_state_t *msi_valid_state) 798 { 799 uint64_t ret; 800 801 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: dip 0x%p msi_num 0x%x\n", 802 dip, msi_num); 803 804 if ((ret = hvio_msi_getvalid(DIP_TO_HANDLE(dip), 805 msi_num, msi_valid_state)) != H_EOK) { 806 DBG(DBG_LIB_MSI, dip, 807 "hvio_msi_getvalid failed, ret 0x%lx\n", ret); 808 return (DDI_FAILURE); 809 } 810 811 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: msiq_id 0x%x\n", 812 *msi_valid_state); 813 814 return (DDI_SUCCESS); 815 } 816 817 /*ARGSUSED*/ 818 int 819 px_lib_msi_setvalid(dev_info_t *dip, msinum_t msi_num, 820 pci_msi_valid_state_t msi_valid_state) 821 { 822 uint64_t ret; 823 824 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setvalid: dip 0x%p msi_num 0x%x " 825 "msi_valid_state 0x%x\n", dip, msi_num, msi_valid_state); 826 827 if ((ret = hvio_msi_setvalid(DIP_TO_HANDLE(dip), 828 msi_num, msi_valid_state)) != H_EOK) { 829 DBG(DBG_LIB_MSI, dip, 830 "hvio_msi_setvalid failed, ret 0x%lx\n", ret); 831 return (DDI_FAILURE); 832 } 833 834 return (DDI_SUCCESS); 835 } 836 837 /*ARGSUSED*/ 838 int 839 px_lib_msi_getstate(dev_info_t *dip, msinum_t msi_num, 840 pci_msi_state_t *msi_state) 841 { 842 uint64_t ret; 843 844 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: dip 0x%p msi_num 0x%x\n", 845 dip, msi_num); 846 847 if ((ret = hvio_msi_getstate(DIP_TO_HANDLE(dip), 848 msi_num, msi_state)) != H_EOK) { 849 DBG(DBG_LIB_MSI, dip, 850 "hvio_msi_getstate failed, ret 0x%lx\n", ret); 851 return (DDI_FAILURE); 852 } 853 854 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: msi_state 0x%x\n", 855 *msi_state); 856 857 return (DDI_SUCCESS); 858 } 859 860 /*ARGSUSED*/ 861 int 862 px_lib_msi_setstate(dev_info_t *dip, msinum_t msi_num, 863 pci_msi_state_t msi_state) 864 { 865 uint64_t ret; 866 867 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setstate: dip 0x%p msi_num 0x%x " 868 "msi_state 0x%x\n", dip, msi_num, msi_state); 869 870 if ((ret = hvio_msi_setstate(DIP_TO_HANDLE(dip), 871 msi_num, msi_state)) != H_EOK) { 872 DBG(DBG_LIB_MSI, dip, 873 "hvio_msi_setstate failed, ret 0x%lx\n", ret); 874 return (DDI_FAILURE); 875 } 876 877 return (DDI_SUCCESS); 878 } 879 880 /* 881 * MSG Functions: 882 */ 883 884 /*ARGSUSED*/ 885 int 886 px_lib_msg_getmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 887 msiqid_t *msiq_id) 888 { 889 uint64_t ret; 890 891 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getmsiq: dip 0x%p msg_type 0x%x\n", 892 dip, msg_type); 893 894 if ((ret = hvio_msg_getmsiq(DIP_TO_HANDLE(dip), 895 msg_type, msiq_id)) != H_EOK) { 896 DBG(DBG_LIB_MSG, dip, 897 "hvio_msg_getmsiq failed, ret 0x%lx\n", ret); 898 return (DDI_FAILURE); 899 } 900 901 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getmsiq: msiq_id 0x%x\n", 902 *msiq_id); 903 904 return (DDI_SUCCESS); 905 } 906 907 /*ARGSUSED*/ 908 int 909 px_lib_msg_setmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 910 msiqid_t msiq_id) 911 { 912 uint64_t ret; 913 914 DBG(DBG_LIB_MSG, dip, "px_lib_msg_setmsiq: dip 0x%p msg_type 0x%x " 915 "msq_id 0x%x\n", dip, msg_type, msiq_id); 916 917 if ((ret = hvio_msg_setmsiq(DIP_TO_HANDLE(dip), 918 msg_type, msiq_id)) != H_EOK) { 919 DBG(DBG_LIB_MSG, dip, 920 "hvio_msg_setmsiq failed, ret 0x%lx\n", ret); 921 return (DDI_FAILURE); 922 } 923 924 return (DDI_SUCCESS); 925 } 926 927 /*ARGSUSED*/ 928 int 929 px_lib_msg_getvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 930 pcie_msg_valid_state_t *msg_valid_state) 931 { 932 uint64_t ret; 933 934 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getvalid: dip 0x%p msg_type 0x%x\n", 935 dip, msg_type); 936 937 if ((ret = hvio_msg_getvalid(DIP_TO_HANDLE(dip), msg_type, 938 msg_valid_state)) != H_EOK) { 939 DBG(DBG_LIB_MSG, dip, 940 "hvio_msg_getvalid failed, ret 0x%lx\n", ret); 941 return (DDI_FAILURE); 942 } 943 944 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getvalid: msg_valid_state 0x%x\n", 945 *msg_valid_state); 946 947 return (DDI_SUCCESS); 948 } 949 950 /*ARGSUSED*/ 951 int 952 px_lib_msg_setvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 953 pcie_msg_valid_state_t msg_valid_state) 954 { 955 uint64_t ret; 956 957 DBG(DBG_LIB_MSG, dip, "px_lib_msg_setvalid: dip 0x%p msg_type 0x%x " 958 "msg_valid_state 0x%x\n", dip, msg_type, msg_valid_state); 959 960 if ((ret = hvio_msg_setvalid(DIP_TO_HANDLE(dip), msg_type, 961 msg_valid_state)) != H_EOK) { 962 DBG(DBG_LIB_MSG, dip, 963 "hvio_msg_setvalid failed, ret 0x%lx\n", ret); 964 return (DDI_FAILURE); 965 } 966 967 return (DDI_SUCCESS); 968 } 969 970 /* 971 * Suspend/Resume Functions: 972 * Currently unsupported by hypervisor and all functions are noops. 973 */ 974 /*ARGSUSED*/ 975 int 976 px_lib_suspend(dev_info_t *dip) 977 { 978 DBG(DBG_ATTACH, dip, "px_lib_suspend: Not supported\n"); 979 980 /* Not supported */ 981 return (DDI_FAILURE); 982 } 983 984 /*ARGSUSED*/ 985 void 986 px_lib_resume(dev_info_t *dip) 987 { 988 DBG(DBG_ATTACH, dip, "px_lib_resume: Not supported\n"); 989 990 /* Noop */ 991 } 992 993 /* 994 * Misc Functions: 995 * Currently unsupported by hypervisor and all functions are noops. 996 */ 997 /*ARGSUSED*/ 998 uint64_t 999 px_lib_get_cb(dev_info_t *dip) 1000 { 1001 return (DDI_SUCCESS); 1002 } 1003 1004 /*ARGSUSED*/ 1005 void 1006 px_lib_set_cb(dev_info_t *dip, uint64_t val) 1007 { 1008 /* Noop */ 1009 } 1010 1011 /*ARGSUSED*/ 1012 static int 1013 px_lib_config_get(dev_info_t *dip, pci_device_t bdf, pci_config_offset_t off, 1014 uint8_t size, pci_cfg_data_t *data_p) 1015 { 1016 uint64_t ret; 1017 1018 DBG(DBG_LIB_CFG, dip, "px_lib_config_get: dip 0x%p, bdf 0x%llx " 1019 "off 0x%x size 0x%x\n", dip, bdf, off, size); 1020 1021 if ((ret = hvio_config_get(DIP_TO_HANDLE(dip), bdf, off, 1022 size, data_p)) != H_EOK) { 1023 DBG(DBG_LIB_CFG, dip, 1024 "hvio_config_get failed, ret 0x%lx\n", ret); 1025 return (DDI_FAILURE); 1026 } 1027 DBG(DBG_LIB_CFG, dip, "px_config_get: data 0x%x\n", data_p->dw); 1028 1029 return (DDI_SUCCESS); 1030 } 1031 1032 /*ARGSUSED*/ 1033 static int 1034 px_lib_config_put(dev_info_t *dip, pci_device_t bdf, pci_config_offset_t off, 1035 uint8_t size, pci_cfg_data_t data) 1036 { 1037 uint64_t ret; 1038 1039 DBG(DBG_LIB_CFG, dip, "px_lib_config_put: dip 0x%p, bdf 0x%llx " 1040 "off 0x%x size 0x%x data 0x%llx\n", dip, bdf, off, size, data.qw); 1041 1042 if ((ret = hvio_config_put(DIP_TO_HANDLE(dip), bdf, off, 1043 size, data)) != H_EOK) { 1044 DBG(DBG_LIB_CFG, dip, 1045 "hvio_config_put failed, ret 0x%lx\n", ret); 1046 return (DDI_FAILURE); 1047 } 1048 1049 return (DDI_SUCCESS); 1050 } 1051 1052 static uint32_t 1053 px_pci_config_get(ddi_acc_impl_t *handle, uint32_t *addr, int size) 1054 { 1055 px_config_acc_pvt_t *px_pvt = (px_config_acc_pvt_t *) 1056 handle->ahi_common.ah_bus_private; 1057 uint32_t pci_dev_addr = px_pvt->raddr; 1058 uint32_t vaddr = px_pvt->vaddr; 1059 uint16_t off = (uint16_t)(uintptr_t)(addr - vaddr) & 0xfff; 1060 uint32_t rdata = 0; 1061 1062 if (px_lib_config_get(px_pvt->dip, pci_dev_addr, off, 1063 size, (pci_cfg_data_t *)&rdata) != DDI_SUCCESS) 1064 /* XXX update error kstats */ 1065 return (0xffffffff); 1066 return (rdata); 1067 } 1068 1069 static void 1070 px_pci_config_put(ddi_acc_impl_t *handle, uint32_t *addr, 1071 int size, pci_cfg_data_t wdata) 1072 { 1073 px_config_acc_pvt_t *px_pvt = (px_config_acc_pvt_t *) 1074 handle->ahi_common.ah_bus_private; 1075 uint32_t pci_dev_addr = px_pvt->raddr; 1076 uint32_t vaddr = px_pvt->vaddr; 1077 uint16_t off = (uint16_t)(uintptr_t)(addr - vaddr) & 0xfff; 1078 1079 if (px_lib_config_put(px_pvt->dip, pci_dev_addr, off, 1080 size, wdata) != DDI_SUCCESS) { 1081 /*EMPTY*/ 1082 /* XXX update error kstats */ 1083 } 1084 } 1085 1086 static uint8_t 1087 px_pci_config_get8(ddi_acc_impl_t *handle, uint8_t *addr) 1088 { 1089 return ((uint8_t)px_pci_config_get(handle, (uint32_t *)addr, 1)); 1090 } 1091 1092 static uint16_t 1093 px_pci_config_get16(ddi_acc_impl_t *handle, uint16_t *addr) 1094 { 1095 return ((uint16_t)px_pci_config_get(handle, (uint32_t *)addr, 2)); 1096 } 1097 1098 static uint32_t 1099 px_pci_config_get32(ddi_acc_impl_t *handle, uint32_t *addr) 1100 { 1101 return ((uint32_t)px_pci_config_get(handle, (uint32_t *)addr, 4)); 1102 } 1103 1104 static uint64_t 1105 px_pci_config_get64(ddi_acc_impl_t *handle, uint64_t *addr) 1106 { 1107 uint32_t rdatah, rdatal; 1108 1109 rdatal = (uint32_t)px_pci_config_get(handle, (uint32_t *)addr, 4); 1110 rdatah = (uint32_t)px_pci_config_get(handle, 1111 (uint32_t *)((char *)addr+4), 4); 1112 return (((uint64_t)rdatah << 32) | rdatal); 1113 } 1114 1115 static void 1116 px_pci_config_put8(ddi_acc_impl_t *handle, uint8_t *addr, uint8_t data) 1117 { 1118 pci_cfg_data_t wdata = { 0 }; 1119 1120 wdata.qw = (uint8_t)data; 1121 px_pci_config_put(handle, (uint32_t *)addr, 1, wdata); 1122 } 1123 1124 static void 1125 px_pci_config_put16(ddi_acc_impl_t *handle, uint16_t *addr, uint16_t data) 1126 { 1127 pci_cfg_data_t wdata = { 0 }; 1128 1129 wdata.qw = (uint16_t)data; 1130 px_pci_config_put(handle, (uint32_t *)addr, 2, wdata); 1131 } 1132 1133 static void 1134 px_pci_config_put32(ddi_acc_impl_t *handle, uint32_t *addr, uint32_t data) 1135 { 1136 pci_cfg_data_t wdata = { 0 }; 1137 1138 wdata.qw = (uint32_t)data; 1139 px_pci_config_put(handle, (uint32_t *)addr, 4, wdata); 1140 } 1141 1142 static void 1143 px_pci_config_put64(ddi_acc_impl_t *handle, uint64_t *addr, uint64_t data) 1144 { 1145 pci_cfg_data_t wdata = { 0 }; 1146 1147 wdata.qw = (uint32_t)(data & 0xffffffff); 1148 px_pci_config_put(handle, (uint32_t *)addr, 4, wdata); 1149 wdata.qw = (uint32_t)((data >> 32) & 0xffffffff); 1150 px_pci_config_put(handle, (uint32_t *)((char *)addr+4), 4, wdata); 1151 } 1152 1153 static void 1154 px_pci_config_rep_get8(ddi_acc_impl_t *handle, uint8_t *host_addr, 1155 uint8_t *dev_addr, size_t repcount, uint_t flags) 1156 { 1157 if (flags == DDI_DEV_AUTOINCR) 1158 for (; repcount; repcount--) 1159 *host_addr++ = px_pci_config_get8(handle, dev_addr++); 1160 else 1161 for (; repcount; repcount--) 1162 *host_addr++ = px_pci_config_get8(handle, dev_addr); 1163 } 1164 1165 /* 1166 * Function to rep read 16 bit data off the PCI configuration space behind 1167 * the 21554's host interface. 1168 */ 1169 static void 1170 px_pci_config_rep_get16(ddi_acc_impl_t *handle, uint16_t *host_addr, 1171 uint16_t *dev_addr, size_t repcount, uint_t flags) 1172 { 1173 if (flags == DDI_DEV_AUTOINCR) 1174 for (; repcount; repcount--) 1175 *host_addr++ = px_pci_config_get16(handle, dev_addr++); 1176 else 1177 for (; repcount; repcount--) 1178 *host_addr++ = px_pci_config_get16(handle, dev_addr); 1179 } 1180 1181 /* 1182 * Function to rep read 32 bit data off the PCI configuration space behind 1183 * the 21554's host interface. 1184 */ 1185 static void 1186 px_pci_config_rep_get32(ddi_acc_impl_t *handle, uint32_t *host_addr, 1187 uint32_t *dev_addr, size_t repcount, uint_t flags) 1188 { 1189 if (flags == DDI_DEV_AUTOINCR) 1190 for (; repcount; repcount--) 1191 *host_addr++ = px_pci_config_get32(handle, dev_addr++); 1192 else 1193 for (; repcount; repcount--) 1194 *host_addr++ = px_pci_config_get32(handle, dev_addr); 1195 } 1196 1197 /* 1198 * Function to rep read 64 bit data off the PCI configuration space behind 1199 * the 21554's host interface. 1200 */ 1201 static void 1202 px_pci_config_rep_get64(ddi_acc_impl_t *handle, uint64_t *host_addr, 1203 uint64_t *dev_addr, size_t repcount, uint_t flags) 1204 { 1205 if (flags == DDI_DEV_AUTOINCR) 1206 for (; repcount; repcount--) 1207 *host_addr++ = px_pci_config_get64(handle, dev_addr++); 1208 else 1209 for (; repcount; repcount--) 1210 *host_addr++ = px_pci_config_get64(handle, dev_addr); 1211 } 1212 1213 /* 1214 * Function to rep write 8 bit data into the PCI configuration space behind 1215 * the 21554's host interface. 1216 */ 1217 static void 1218 px_pci_config_rep_put8(ddi_acc_impl_t *handle, uint8_t *host_addr, 1219 uint8_t *dev_addr, size_t repcount, uint_t flags) 1220 { 1221 if (flags == DDI_DEV_AUTOINCR) 1222 for (; repcount; repcount--) 1223 px_pci_config_put8(handle, dev_addr++, *host_addr++); 1224 else 1225 for (; repcount; repcount--) 1226 px_pci_config_put8(handle, dev_addr, *host_addr++); 1227 } 1228 1229 /* 1230 * Function to rep write 16 bit data into the PCI configuration space behind 1231 * the 21554's host interface. 1232 */ 1233 static void 1234 px_pci_config_rep_put16(ddi_acc_impl_t *handle, uint16_t *host_addr, 1235 uint16_t *dev_addr, size_t repcount, uint_t flags) 1236 { 1237 if (flags == DDI_DEV_AUTOINCR) 1238 for (; repcount; repcount--) 1239 px_pci_config_put16(handle, dev_addr++, *host_addr++); 1240 else 1241 for (; repcount; repcount--) 1242 px_pci_config_put16(handle, dev_addr, *host_addr++); 1243 } 1244 1245 /* 1246 * Function to rep write 32 bit data into the PCI configuration space behind 1247 * the 21554's host interface. 1248 */ 1249 static void 1250 px_pci_config_rep_put32(ddi_acc_impl_t *handle, uint32_t *host_addr, 1251 uint32_t *dev_addr, size_t repcount, uint_t flags) 1252 { 1253 if (flags == DDI_DEV_AUTOINCR) 1254 for (; repcount; repcount--) 1255 px_pci_config_put32(handle, dev_addr++, *host_addr++); 1256 else 1257 for (; repcount; repcount--) 1258 px_pci_config_put32(handle, dev_addr, *host_addr++); 1259 } 1260 1261 /* 1262 * Function to rep write 64 bit data into the PCI configuration space behind 1263 * the 21554's host interface. 1264 */ 1265 static void 1266 px_pci_config_rep_put64(ddi_acc_impl_t *handle, uint64_t *host_addr, 1267 uint64_t *dev_addr, size_t repcount, uint_t flags) 1268 { 1269 if (flags == DDI_DEV_AUTOINCR) 1270 for (; repcount; repcount--) 1271 px_pci_config_put64(handle, dev_addr++, *host_addr++); 1272 else 1273 for (; repcount; repcount--) 1274 px_pci_config_put64(handle, dev_addr, *host_addr++); 1275 } 1276 1277 /* 1278 * Provide a private access handle to route config access calls to Hypervisor. 1279 * Beware: Do all error checking for config space accesses before calling 1280 * this function. ie. do error checking from the calling function. 1281 * Due to a lack of meaningful error code in DDI, the gauranteed return of 1282 * DDI_SUCCESS from here makes the code organization readable/easier from 1283 * the generic code. 1284 */ 1285 /*ARGSUSED*/ 1286 int 1287 px_lib_map_vconfig(dev_info_t *dip, 1288 ddi_map_req_t *mp, pci_config_offset_t off, 1289 pci_regspec_t *rp, caddr_t *addrp) 1290 { 1291 ddi_acc_hdl_t *hp; 1292 ddi_acc_impl_t *ap; 1293 uchar_t busnum; /* bus number */ 1294 uchar_t devnum; /* device number */ 1295 uchar_t funcnum; /* function number */ 1296 px_config_acc_pvt_t *px_pvt; 1297 1298 hp = (ddi_acc_hdl_t *)mp->map_handlep; 1299 ap = (ddi_acc_impl_t *)hp->ah_platform_private; 1300 1301 /* Check for mapping teardown operation */ 1302 if ((mp->map_op == DDI_MO_UNMAP) || 1303 (mp->map_op == DDI_MO_UNLOCK)) { 1304 /* free up memory allocated for the private access handle. */ 1305 px_pvt = (px_config_acc_pvt_t *)hp->ah_bus_private; 1306 kmem_free((void *)px_pvt, sizeof (px_config_acc_pvt_t)); 1307 1308 /* unmap operation of PCI IO/config space. */ 1309 return (DDI_SUCCESS); 1310 } 1311 1312 ap->ahi_get8 = px_pci_config_get8; 1313 ap->ahi_get16 = px_pci_config_get16; 1314 ap->ahi_get32 = px_pci_config_get32; 1315 ap->ahi_get64 = px_pci_config_get64; 1316 ap->ahi_put8 = px_pci_config_put8; 1317 ap->ahi_put16 = px_pci_config_put16; 1318 ap->ahi_put32 = px_pci_config_put32; 1319 ap->ahi_put64 = px_pci_config_put64; 1320 ap->ahi_rep_get8 = px_pci_config_rep_get8; 1321 ap->ahi_rep_get16 = px_pci_config_rep_get16; 1322 ap->ahi_rep_get32 = px_pci_config_rep_get32; 1323 ap->ahi_rep_get64 = px_pci_config_rep_get64; 1324 ap->ahi_rep_put8 = px_pci_config_rep_put8; 1325 ap->ahi_rep_put16 = px_pci_config_rep_put16; 1326 ap->ahi_rep_put32 = px_pci_config_rep_put32; 1327 ap->ahi_rep_put64 = px_pci_config_rep_put64; 1328 1329 /* Initialize to default check/notify functions */ 1330 ap->ahi_fault = 0; 1331 ap->ahi_fault_check = i_ddi_acc_fault_check; 1332 ap->ahi_fault_notify = i_ddi_acc_fault_notify; 1333 1334 /* allocate memory for our private handle */ 1335 px_pvt = (px_config_acc_pvt_t *) 1336 kmem_zalloc(sizeof (px_config_acc_pvt_t), KM_SLEEP); 1337 hp->ah_bus_private = (void *)px_pvt; 1338 1339 busnum = PCI_REG_BUS_G(rp->pci_phys_hi); 1340 devnum = PCI_REG_DEV_G(rp->pci_phys_hi); 1341 funcnum = PCI_REG_FUNC_G(rp->pci_phys_hi); 1342 1343 /* set up private data for use during IO routines */ 1344 1345 /* addr needed by the HV APIs */ 1346 px_pvt->raddr = busnum << 16 | devnum << 11 | funcnum << 8; 1347 /* 1348 * Address that specifies the actual offset into the 256MB 1349 * memory mapped configuration space, 4K per device. 1350 * First 12bits form the offset into 4K config space. 1351 * This address is only used during the IO routines to calculate 1352 * the offset at which the transaction must be performed. 1353 * Drivers bypassing DDI functions to access PCI config space will 1354 * panic the system since the following is a bogus virtual address. 1355 */ 1356 px_pvt->vaddr = busnum << 20 | devnum << 15 | funcnum << 12 | off; 1357 px_pvt->dip = dip; 1358 1359 DBG(DBG_LIB_CFG, dip, "px_config_setup: raddr 0x%x, vaddr 0x%x\n", 1360 px_pvt->raddr, px_pvt->vaddr); 1361 *addrp = (caddr_t)(uintptr_t)px_pvt->vaddr; 1362 return (DDI_SUCCESS); 1363 } 1364 1365 /*ARGSUSED*/ 1366 void 1367 px_lib_map_attr_check(ddi_map_req_t *mp) 1368 { 1369 } 1370 1371 /* 1372 * px_lib_log_safeacc_err: 1373 * Imitate a cpu/mem trap call when a peek/poke fails. 1374 * This will initiate something similar to px_fm_callback. 1375 */ 1376 static void 1377 px_lib_log_safeacc_err(px_t *px_p, ddi_acc_handle_t handle, int fme_flag) 1378 { 1379 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)handle; 1380 px_cb_t *cb_p = px_p->px_cb_p; 1381 ddi_fm_error_t derr; 1382 1383 derr.fme_status = DDI_FM_NONFATAL; 1384 derr.fme_version = DDI_FME_VERSION; 1385 derr.fme_flag = fme_flag; 1386 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 1387 derr.fme_acc_handle = handle; 1388 if (hp) 1389 hp->ahi_err->err_expected = DDI_FM_ERR_EXPECTED; 1390 1391 mutex_enter(&cb_p->xbc_fm_mutex); 1392 1393 (void) ndi_fm_handler_dispatch(px_p->px_dip, NULL, &derr); 1394 1395 mutex_exit(&cb_p->xbc_fm_mutex); 1396 } 1397 1398 1399 #ifdef DEBUG 1400 int px_peekfault_cnt = 0; 1401 int px_pokefault_cnt = 0; 1402 #endif /* DEBUG */ 1403 1404 static int 1405 px_lib_bdf_from_dip(dev_info_t *rdip, uint32_t *bdf) 1406 { 1407 /* Start with an array of 8 reg spaces for now to cover most devices. */ 1408 pci_regspec_t regspec_array[8]; 1409 pci_regspec_t *regspec = regspec_array; 1410 int buflen = sizeof (regspec_array); 1411 boolean_t kmalloced = B_FALSE; 1412 int status; 1413 1414 status = ddi_getlongprop_buf(DDI_DEV_T_ANY, rdip, 1415 DDI_PROP_DONTPASS, "reg", (caddr_t)regspec, &buflen); 1416 1417 /* If need more space, fallback to kmem_alloc. */ 1418 if (status == DDI_PROP_BUF_TOO_SMALL) { 1419 regspec = kmem_alloc(buflen, KM_SLEEP); 1420 1421 status = ddi_getlongprop_buf(DDI_DEV_T_ANY, rdip, 1422 DDI_PROP_DONTPASS, "reg", (caddr_t)regspec, &buflen); 1423 1424 kmalloced = B_TRUE; 1425 } 1426 1427 /* Get phys_hi from first element. All have same bdf. */ 1428 if (status == DDI_PROP_SUCCESS) 1429 *bdf = regspec->pci_phys_hi & (PCI_REG_BDFR_M ^ PCI_REG_REG_M); 1430 1431 if (kmalloced) 1432 kmem_free(regspec, buflen); 1433 1434 return ((status == DDI_PROP_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE); 1435 } 1436 1437 /* 1438 * Do a safe write to a device. 1439 * 1440 * When this function is given a handle (cautious access), all errors are 1441 * suppressed. 1442 * 1443 * When this function is not given a handle (poke), only Unsupported Request 1444 * and Completer Abort errors are suppressed. 1445 * 1446 * In all cases, all errors are returned in the function return status. 1447 */ 1448 1449 int 1450 px_lib_ctlops_poke(dev_info_t *dip, dev_info_t *rdip, 1451 peekpoke_ctlops_t *in_args) 1452 { 1453 px_t *px_p = DIP_TO_STATE(dip); 1454 px_pec_t *pec_p = px_p->px_pec_p; 1455 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)in_args->handle; 1456 1457 size_t repcount = in_args->repcount; 1458 size_t size = in_args->size; 1459 uintptr_t dev_addr = in_args->dev_addr; 1460 uintptr_t host_addr = in_args->host_addr; 1461 1462 int err = DDI_SUCCESS; 1463 uint64_t hvio_poke_status; 1464 uint32_t bdf; 1465 uint32_t wrt_stat; 1466 1467 r_addr_t ra; 1468 uint64_t pokeval; 1469 1470 /* 1471 * Used only to notify error handling peek/poke is occuring 1472 * One scenario is when a fabric err as a result of peek/poke. 1473 * However there is no way to guarantee that the fabric error 1474 * handler will occur in the window where otd is set. 1475 */ 1476 on_trap_data_t otd; 1477 1478 if (px_lib_bdf_from_dip(rdip, &bdf) != DDI_SUCCESS) { 1479 DBG(DBG_LIB_DMA, px_p->px_dip, 1480 "poke: px_lib_bdf_from_dip failed\n"); 1481 err = DDI_FAILURE; 1482 goto done; 1483 } 1484 1485 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1486 for (; repcount; repcount--) { 1487 1488 switch (size) { 1489 case sizeof (uint8_t): 1490 pokeval = *(uint8_t *)host_addr; 1491 break; 1492 case sizeof (uint16_t): 1493 pokeval = *(uint16_t *)host_addr; 1494 break; 1495 case sizeof (uint32_t): 1496 pokeval = *(uint32_t *)host_addr; 1497 break; 1498 case sizeof (uint64_t): 1499 pokeval = *(uint64_t *)host_addr; 1500 break; 1501 default: 1502 DBG(DBG_MAP, px_p->px_dip, 1503 "poke: invalid size %d passed\n", size); 1504 err = DDI_FAILURE; 1505 goto done; 1506 } 1507 1508 /* 1509 * Grab pokefault mutex since hypervisor does not guarantee 1510 * poke serialization. 1511 */ 1512 if (hp) { 1513 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, 1514 (ddi_acc_handle_t)hp); 1515 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1516 } else { 1517 mutex_enter(&pec_p->pec_pokefault_mutex); 1518 pec_p->pec_safeacc_type = DDI_FM_ERR_POKE; 1519 } 1520 pec_p->pec_ontrap_data = &otd; 1521 1522 hvio_poke_status = hvio_poke(px_p->px_dev_hdl, ra, size, 1523 pokeval, bdf, &wrt_stat); 1524 1525 if (otd.ot_trap & OT_DATA_ACCESS) 1526 err = DDI_FAILURE; 1527 1528 if ((hvio_poke_status != H_EOK) || (wrt_stat != H_EOK)) { 1529 err = DDI_FAILURE; 1530 #ifdef DEBUG 1531 px_pokefault_cnt++; 1532 #endif 1533 /* 1534 * For CAUTIOUS and POKE access, notify FMA to 1535 * cleanup. Imitate a cpu/mem trap call like in sun4u. 1536 */ 1537 px_lib_log_safeacc_err(px_p, (ddi_acc_handle_t)hp, 1538 (hp ? DDI_FM_ERR_EXPECTED : 1539 DDI_FM_ERR_POKE)); 1540 1541 pec_p->pec_ontrap_data = NULL; 1542 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1543 if (hp) { 1544 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1545 (ddi_acc_handle_t)hp); 1546 } else { 1547 mutex_exit(&pec_p->pec_pokefault_mutex); 1548 } 1549 goto done; 1550 } 1551 1552 pec_p->pec_ontrap_data = NULL; 1553 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1554 if (hp) { 1555 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1556 (ddi_acc_handle_t)hp); 1557 } else { 1558 mutex_exit(&pec_p->pec_pokefault_mutex); 1559 } 1560 1561 host_addr += size; 1562 1563 if (in_args->flags == DDI_DEV_AUTOINCR) { 1564 dev_addr += size; 1565 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1566 } 1567 } 1568 1569 done: 1570 return (err); 1571 } 1572 1573 1574 /*ARGSUSED*/ 1575 int 1576 px_lib_ctlops_peek(dev_info_t *dip, dev_info_t *rdip, 1577 peekpoke_ctlops_t *in_args, void *result) 1578 { 1579 px_t *px_p = DIP_TO_STATE(dip); 1580 px_pec_t *pec_p = px_p->px_pec_p; 1581 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)in_args->handle; 1582 1583 size_t repcount = in_args->repcount; 1584 uintptr_t dev_addr = in_args->dev_addr; 1585 uintptr_t host_addr = in_args->host_addr; 1586 1587 r_addr_t ra; 1588 uint32_t read_status; 1589 uint64_t hvio_peek_status; 1590 uint64_t peekval; 1591 int err = DDI_SUCCESS; 1592 1593 /* 1594 * Used only to notify error handling peek/poke is occuring 1595 * One scenario is when a fabric err as a result of peek/poke. 1596 * However there is no way to guarantee that the fabric error 1597 * handler will occur in the window where otd is set. 1598 */ 1599 on_trap_data_t otd; 1600 1601 result = (void *)in_args->host_addr; 1602 1603 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1604 for (; repcount; repcount--) { 1605 1606 /* Lock pokefault mutex so read doesn't mask a poke fault. */ 1607 if (hp) { 1608 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, 1609 (ddi_acc_handle_t)hp); 1610 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1611 } else { 1612 mutex_enter(&pec_p->pec_pokefault_mutex); 1613 pec_p->pec_safeacc_type = DDI_FM_ERR_PEEK; 1614 } 1615 pec_p->pec_ontrap_data = &otd; 1616 1617 hvio_peek_status = hvio_peek(px_p->px_dev_hdl, ra, 1618 in_args->size, &read_status, &peekval); 1619 1620 if ((hvio_peek_status != H_EOK) || (read_status != H_EOK)) { 1621 err = DDI_FAILURE; 1622 1623 /* 1624 * For CAUTIOUS and PEEK access, notify FMA to 1625 * cleanup. Imitate a cpu/mem trap call like in sun4u. 1626 */ 1627 px_lib_log_safeacc_err(px_p, (ddi_acc_handle_t)hp, 1628 (hp ? DDI_FM_ERR_EXPECTED : 1629 DDI_FM_ERR_PEEK)); 1630 1631 /* Stuff FFs in host addr if peek. */ 1632 if (hp == NULL) { 1633 int i; 1634 uint8_t *ff_addr = (uint8_t *)host_addr; 1635 for (i = 0; i < in_args->size; i++) 1636 *ff_addr++ = 0xff; 1637 } 1638 #ifdef DEBUG 1639 px_peekfault_cnt++; 1640 #endif 1641 pec_p->pec_ontrap_data = NULL; 1642 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1643 if (hp) { 1644 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1645 (ddi_acc_handle_t)hp); 1646 } else { 1647 mutex_exit(&pec_p->pec_pokefault_mutex); 1648 } 1649 goto done; 1650 1651 } 1652 pec_p->pec_ontrap_data = NULL; 1653 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1654 if (hp) { 1655 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1656 (ddi_acc_handle_t)hp); 1657 } else { 1658 mutex_exit(&pec_p->pec_pokefault_mutex); 1659 } 1660 1661 switch (in_args->size) { 1662 case sizeof (uint8_t): 1663 *(uint8_t *)host_addr = (uint8_t)peekval; 1664 break; 1665 case sizeof (uint16_t): 1666 *(uint16_t *)host_addr = (uint16_t)peekval; 1667 break; 1668 case sizeof (uint32_t): 1669 *(uint32_t *)host_addr = (uint32_t)peekval; 1670 break; 1671 case sizeof (uint64_t): 1672 *(uint64_t *)host_addr = (uint64_t)peekval; 1673 break; 1674 default: 1675 DBG(DBG_MAP, px_p->px_dip, 1676 "peek: invalid size %d passed\n", 1677 in_args->size); 1678 err = DDI_FAILURE; 1679 goto done; 1680 } 1681 1682 host_addr += in_args->size; 1683 1684 if (in_args->flags == DDI_DEV_AUTOINCR) { 1685 dev_addr += in_args->size; 1686 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1687 } 1688 } 1689 done: 1690 return (err); 1691 } 1692 1693 1694 /* add interrupt vector */ 1695 int 1696 px_err_add_intr(px_fault_t *px_fault_p) 1697 { 1698 int ret; 1699 px_t *px_p = DIP_TO_STATE(px_fault_p->px_fh_dip); 1700 1701 DBG(DBG_LIB_INT, px_p->px_dip, 1702 "px_err_add_intr: calling add_ivintr"); 1703 ret = add_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL, 1704 px_fault_p->px_err_func, (caddr_t)px_fault_p, 1705 (caddr_t)&px_fault_p->px_intr_payload[0]); 1706 1707 if (ret != DDI_SUCCESS) { 1708 DBG(DBG_LIB_INT, px_p->px_dip, 1709 "add_ivintr returns %d, faultp: %p", ret, px_fault_p); 1710 1711 return (ret); 1712 } 1713 DBG(DBG_LIB_INT, px_p->px_dip, 1714 "px_err_add_intr: ib_intr_enable "); 1715 1716 px_ib_intr_enable(px_p, intr_dist_cpuid(), px_fault_p->px_intr_ino); 1717 1718 return (ret); 1719 } 1720 1721 1722 /* remove interrupt vector */ 1723 void 1724 px_err_rem_intr(px_fault_t *px_fault_p) 1725 { 1726 px_t *px_p = DIP_TO_STATE(px_fault_p->px_fh_dip); 1727 1728 px_ib_intr_disable(px_p->px_ib_p, px_fault_p->px_intr_ino, 1729 IB_INTR_WAIT); 1730 1731 rem_ivintr(px_fault_p->px_fh_sysino, NULL); 1732 } 1733 1734 1735 #ifdef FMA 1736 void 1737 px_fill_rc_status(px_fault_t *px_fault_p, pciex_rc_error_regs_t *rc_status) 1738 { 1739 px_pec_err_t *err_pkt; 1740 1741 err_pkt = (px_pec_err_t *)px_fault_p->px_intr_payload; 1742 1743 /* initialise all the structure members */ 1744 rc_status->status_valid = 0; 1745 1746 if (err_pkt->pec_descr.P) { 1747 /* PCI Status Register */ 1748 rc_status->pci_err_status = err_pkt->pci_err_status; 1749 rc_status->status_valid |= PCI_ERR_STATUS_VALID; 1750 } 1751 1752 if (err_pkt->pec_descr.E) { 1753 /* PCIe Status Register */ 1754 rc_status->pcie_err_status = err_pkt->pcie_err_status; 1755 rc_status->status_valid |= PCIE_ERR_STATUS_VALID; 1756 } 1757 1758 if (err_pkt->pec_descr.U) { 1759 rc_status->ue_status = err_pkt->ue_reg_status; 1760 rc_status->status_valid |= UE_STATUS_VALID; 1761 } 1762 1763 if (err_pkt->pec_descr.H) { 1764 rc_status->ue_hdr1 = err_pkt->hdr[0]; 1765 rc_status->status_valid |= UE_HDR1_VALID; 1766 } 1767 1768 if (err_pkt->pec_descr.I) { 1769 rc_status->ue_hdr2 = err_pkt->hdr[1]; 1770 rc_status->status_valid |= UE_HDR2_VALID; 1771 } 1772 1773 /* ue_fst_err_ptr - not available for sun4v?? */ 1774 1775 1776 if (err_pkt->pec_descr.S) { 1777 rc_status->source_id = err_pkt->err_src_reg; 1778 rc_status->status_valid |= SOURCE_ID_VALID; 1779 } 1780 1781 if (err_pkt->pec_descr.R) { 1782 rc_status->root_err_status = err_pkt->root_err_status; 1783 rc_status->status_valid |= CE_STATUS_VALID; 1784 } 1785 } 1786 #endif 1787 1788 /*ARGSUSED*/ 1789 int 1790 px_lib_pmctl(int cmd, px_t *px_p) 1791 { 1792 return (DDI_FAILURE); 1793 } 1794 1795 /*ARGSUSED*/ 1796 uint_t 1797 px_lup_softintr(caddr_t arg) 1798 { 1799 return (DDI_INTR_CLAIMED); 1800 } 1801 1802 /*ARGSUSED*/ 1803 uint_t 1804 px_pmeq_intr(caddr_t arg) 1805 { 1806 return (DDI_INTR_CLAIMED); 1807 } 1808 1809 /* 1810 * Unprotected raw reads/writes of fabric device's config space. 1811 * Only used for temporary PCI-E Fabric Error Handling. 1812 */ 1813 uint32_t 1814 px_fab_get(px_t *px_p, pcie_req_id_t bdf, uint16_t offset) { 1815 uint32_t data = 0; 1816 1817 (void) hvio_config_get(px_p->px_dev_hdl, 1818 (bdf << PX_RA_BDF_SHIFT), offset, 4, 1819 (pci_cfg_data_t *)&data); 1820 1821 return (data); 1822 } 1823 1824 void 1825 px_fab_set(px_t *px_p, pcie_req_id_t bdf, uint16_t offset, 1826 uint32_t val) { 1827 pci_cfg_data_t wdata = { 0 }; 1828 1829 wdata.qw = (uint32_t)val; 1830 (void) hvio_config_put(px_p->px_dev_hdl, 1831 (bdf << PX_RA_BDF_SHIFT), offset, 4, wdata); 1832 } 1833 1834 /* Dummy cpr add callback */ 1835 /*ARGSUSED*/ 1836 void 1837 px_cpr_add_callb(px_t *px_p) 1838 { 1839 } 1840 1841 /* Dummy cpr rem callback */ 1842 /*ARGSUSED*/ 1843 void 1844 px_cpr_rem_callb(px_t *px_p) 1845 { 1846 } 1847