1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/types.h> 30 #include <sys/sysmacros.h> 31 #include <sys/ddi.h> 32 #include <sys/sunddi.h> 33 #include <sys/ddifm.h> 34 #include <sys/fm/protocol.h> 35 #include <sys/vmem.h> 36 #include <sys/intr.h> 37 #include <sys/ivintr.h> 38 #include <sys/errno.h> 39 #include <sys/hypervisor_api.h> 40 #include <px_obj.h> 41 #include <sys/machsystm.h> 42 #include "px_lib4v.h" 43 #include "px_err.h" 44 45 /* mask for the ranges property in calculating the real PFN range */ 46 uint_t px_ranges_phi_mask = ((1 << 28) -1); 47 48 int 49 px_lib_dev_init(dev_info_t *dip, devhandle_t *dev_hdl) 50 { 51 px_nexus_regspec_t *rp; 52 int reglen; 53 54 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dip 0x%p\n", dip); 55 56 if (ddi_getlongprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 57 "reg", (caddr_t)&rp, ®len) != DDI_SUCCESS) { 58 DBG(DBG_ATTACH, dip, "px_lib_dev_init failed\n"); 59 return (DDI_FAILURE); 60 } 61 62 /* 63 * Initilize device handle. The device handle uniquely identifies 64 * a SUN4V device. It consists of the lower 28-bits of the hi-cell 65 * of the first entry of the SUN4V device's "reg" property as 66 * defined by the SUN4V Bus Binding to Open Firmware. 67 */ 68 *dev_hdl = (devhandle_t)((rp->phys_addr >> 32) & DEVHDLE_MASK); 69 70 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dev_hdl 0x%llx\n", *dev_hdl); 71 72 return (DDI_SUCCESS); 73 } 74 75 /*ARGSUSED*/ 76 int 77 px_lib_dev_fini(dev_info_t *dip) 78 { 79 DBG(DBG_DETACH, dip, "px_lib_dev_fini: dip 0x%p\n", dip); 80 81 return (DDI_SUCCESS); 82 } 83 84 /*ARGSUSED*/ 85 int 86 px_lib_intr_devino_to_sysino(dev_info_t *dip, devino_t devino, 87 sysino_t *sysino) 88 { 89 uint64_t ret; 90 91 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: dip 0x%p " 92 "devino 0x%x\n", dip, devino); 93 94 if ((ret = hvio_intr_devino_to_sysino(DIP_TO_HANDLE(dip), 95 devino, sysino)) != H_EOK) { 96 DBG(DBG_LIB_INT, dip, 97 "hvio_intr_devino_to_sysino failed, ret 0x%lx\n", ret); 98 return (DDI_FAILURE); 99 } 100 101 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: sysino 0x%llx\n", 102 *sysino); 103 104 return (DDI_SUCCESS); 105 } 106 107 /*ARGSUSED*/ 108 int 109 px_lib_intr_getvalid(dev_info_t *dip, sysino_t sysino, 110 intr_valid_state_t *intr_valid_state) 111 { 112 uint64_t ret; 113 114 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: dip 0x%p sysino 0x%llx\n", 115 dip, sysino); 116 117 if ((ret = hvio_intr_getvalid(sysino, 118 (int *)intr_valid_state)) != H_EOK) { 119 DBG(DBG_LIB_INT, dip, "hvio_intr_getvalid failed, ret 0x%lx\n", 120 ret); 121 return (DDI_FAILURE); 122 } 123 124 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: intr_valid_state 0x%x\n", 125 *intr_valid_state); 126 127 return (DDI_SUCCESS); 128 } 129 130 /*ARGSUSED*/ 131 int 132 px_lib_intr_setvalid(dev_info_t *dip, sysino_t sysino, 133 intr_valid_state_t intr_valid_state) 134 { 135 uint64_t ret; 136 137 DBG(DBG_LIB_INT, dip, "px_lib_intr_setvalid: dip 0x%p sysino 0x%llx " 138 "intr_valid_state 0x%x\n", dip, sysino, intr_valid_state); 139 140 if ((ret = hvio_intr_setvalid(sysino, intr_valid_state)) != H_EOK) { 141 DBG(DBG_LIB_INT, dip, "hvio_intr_setvalid failed, ret 0x%lx\n", 142 ret); 143 return (DDI_FAILURE); 144 } 145 146 return (DDI_SUCCESS); 147 } 148 149 /*ARGSUSED*/ 150 int 151 px_lib_intr_getstate(dev_info_t *dip, sysino_t sysino, 152 intr_state_t *intr_state) 153 { 154 uint64_t ret; 155 156 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: dip 0x%p sysino 0x%llx\n", 157 dip, sysino); 158 159 if ((ret = hvio_intr_getstate(sysino, (int *)intr_state)) != H_EOK) { 160 DBG(DBG_LIB_INT, dip, "hvio_intr_getstate failed, ret 0x%lx\n", 161 ret); 162 return (DDI_FAILURE); 163 } 164 165 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: intr_state 0x%x\n", 166 *intr_state); 167 168 return (DDI_SUCCESS); 169 } 170 171 /*ARGSUSED*/ 172 int 173 px_lib_intr_setstate(dev_info_t *dip, sysino_t sysino, 174 intr_state_t intr_state) 175 { 176 uint64_t ret; 177 178 DBG(DBG_LIB_INT, dip, "px_lib_intr_setstate: dip 0x%p sysino 0x%llx " 179 "intr_state 0x%x\n", dip, sysino, intr_state); 180 181 if ((ret = hvio_intr_setstate(sysino, intr_state)) != H_EOK) { 182 DBG(DBG_LIB_INT, dip, "hvio_intr_setstate failed, ret 0x%lx\n", 183 ret); 184 return (DDI_FAILURE); 185 } 186 187 return (DDI_SUCCESS); 188 } 189 190 /*ARGSUSED*/ 191 int 192 px_lib_intr_gettarget(dev_info_t *dip, sysino_t sysino, cpuid_t *cpuid) 193 { 194 uint64_t ret; 195 196 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: dip 0x%p sysino 0x%llx\n", 197 dip, sysino); 198 199 if ((ret = hvio_intr_gettarget(sysino, cpuid)) != H_EOK) { 200 DBG(DBG_LIB_INT, dip, 201 "hvio_intr_gettarget failed, ret 0x%lx\n", ret); 202 return (DDI_FAILURE); 203 } 204 205 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: cpuid 0x%x\n", cpuid); 206 207 return (DDI_SUCCESS); 208 } 209 210 /*ARGSUSED*/ 211 int 212 px_lib_intr_settarget(dev_info_t *dip, sysino_t sysino, cpuid_t cpuid) 213 { 214 uint64_t ret; 215 216 DBG(DBG_LIB_INT, dip, "px_lib_intr_settarget: dip 0x%p sysino 0x%llx " 217 "cpuid 0x%x\n", dip, sysino, cpuid); 218 219 if ((ret = hvio_intr_settarget(sysino, cpuid)) != H_EOK) { 220 DBG(DBG_LIB_INT, dip, 221 "hvio_intr_settarget failed, ret 0x%lx\n", ret); 222 return (DDI_FAILURE); 223 } 224 225 return (DDI_SUCCESS); 226 } 227 228 /*ARGSUSED*/ 229 int 230 px_lib_intr_reset(dev_info_t *dip) 231 { 232 DBG(DBG_LIB_INT, dip, "px_lib_intr_reset: dip 0x%p\n", dip); 233 234 return (DDI_SUCCESS); 235 } 236 237 /*ARGSUSED*/ 238 int 239 px_lib_iommu_map(dev_info_t *dip, tsbid_t tsbid, pages_t pages, 240 io_attributes_t io_attributes, void *addr, size_t pfn_index, 241 int flag) 242 { 243 pages_t pgs_mapped = 0, pgs_cnt = 0; 244 pages_t pgs = pages; 245 tsbnum_t tsb_num = PCI_TSBID_TO_TSBNUM(tsbid); 246 tsbindex_t tsbindex = PCI_TSBID_TO_TSBINDEX(tsbid); 247 io_page_list_t *io_page_list_p, *ptr; 248 int i, err = DDI_SUCCESS; 249 uint64_t ret; 250 251 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: dip 0x%p tsbid 0x%llx " 252 "pages 0x%x atrr 0x%x addr 0x%p pfn_index 0x%llx, flag 0x%x\n", 253 dip, tsbid, pages, io_attributes, addr, pfn_index, flag); 254 255 if ((ptr = kmem_zalloc((pages * sizeof (io_page_list_t)), 256 KM_NOSLEEP)) == NULL) { 257 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: kmem_zalloc failed\n"); 258 return (DDI_FAILURE); 259 } 260 261 io_page_list_p = (io_page_list_t *)ptr; 262 263 if (flag == MMU_MAP_MP) { 264 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)addr; 265 266 for (i = 0; i < pages; i++, pfn_index++) { 267 px_iopfn_t pfn = PX_GET_MP_PFN(mp, pfn_index); 268 io_page_list_p[i] = MMU_PTOB(pfn); 269 } 270 } else { 271 caddr_t a = (caddr_t)addr; 272 273 for (i = 0; i < pages; i++, a += MMU_PAGE_SIZE) { 274 px_iopfn_t pfn = hat_getpfnum(kas.a_hat, a); 275 io_page_list_p[i] = MMU_PTOB(pfn); 276 } 277 } 278 279 io_page_list_p = (io_page_list_t *)va_to_pa(ptr); 280 pgs_mapped = 0; 281 282 while (pgs) { 283 if ((ret = hvio_iommu_map(DIP_TO_HANDLE(dip), 284 PCI_TSBID(tsb_num, tsbindex), pgs, io_attributes, 285 io_page_list_p, &pgs_cnt)) != H_EOK) { 286 DBG(DBG_LIB_DMA, dip, 287 "hvio_iommu_map failed, ret 0x%lx\n", ret); 288 err = DDI_FAILURE; 289 break; 290 } 291 292 pgs_mapped += pgs_cnt; 293 pgs -= pgs_cnt; 294 tsbindex += pgs_cnt; 295 io_page_list_p += pgs_cnt; 296 pgs_cnt = 0; 297 } 298 299 if ((err == DDI_FAILURE) && (pgs_mapped)) 300 (void) px_lib_iommu_demap(dip, tsbid, pgs_mapped); 301 302 kmem_free(ptr, (pages * sizeof (io_page_list_t))); 303 304 return (err); 305 } 306 307 /*ARGSUSED*/ 308 int 309 px_lib_iommu_demap(dev_info_t *dip, tsbid_t tsbid, pages_t pages) 310 { 311 tsbnum_t tsb_num = PCI_TSBID_TO_TSBNUM(tsbid); 312 tsbindex_t tsbindex = PCI_TSBID_TO_TSBINDEX(tsbid); 313 pages_t pgs_cnt = 0; 314 uint64_t ret; 315 316 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: dip 0x%p tsbid 0x%llx " 317 "pages 0x%x\n", dip, tsbid, pages); 318 319 while (pages) { 320 if ((ret = hvio_iommu_demap(DIP_TO_HANDLE(dip), 321 PCI_TSBID(tsb_num, tsbindex), pages, 322 &pgs_cnt)) != H_EOK) { 323 DBG(DBG_LIB_DMA, dip, 324 "hvio_iommu_demap failed, ret 0x%lx\n", ret); 325 return (DDI_FAILURE); 326 } 327 328 pages -= pgs_cnt; 329 tsbindex += pgs_cnt; 330 pgs_cnt = 0; 331 } 332 333 return (DDI_SUCCESS); 334 } 335 336 /*ARGSUSED*/ 337 int 338 px_lib_iommu_getmap(dev_info_t *dip, tsbid_t tsbid, 339 io_attributes_t *attributes_p, r_addr_t *r_addr_p) 340 { 341 uint64_t ret; 342 343 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: dip 0x%p tsbid 0x%llx\n", 344 dip, tsbid); 345 346 if ((ret = hvio_iommu_getmap(DIP_TO_HANDLE(dip), tsbid, 347 attributes_p, r_addr_p)) != H_EOK) { 348 DBG(DBG_LIB_DMA, dip, 349 "hvio_iommu_getmap failed, ret 0x%lx\n", ret); 350 351 return ((ret == H_ENOMAP) ? DDI_DMA_NOMAPPING:DDI_FAILURE); 352 } 353 354 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: attr 0x%x r_addr 0x%llx\n", 355 *attributes_p, *r_addr_p); 356 357 return (DDI_SUCCESS); 358 } 359 360 361 /* 362 * Checks dma attributes against system bypass ranges 363 * A sun4v device must be capable of generating the entire 64-bit 364 * address in order to perform bypass DMA. 365 */ 366 /*ARGSUSED*/ 367 int 368 px_lib_dma_bypass_rngchk(ddi_dma_attr_t *attrp, uint64_t *lo_p, uint64_t *hi_p) 369 { 370 if ((attrp->dma_attr_addr_lo != 0ull) || 371 (attrp->dma_attr_addr_hi != UINT64_MAX)) { 372 373 return (DDI_DMA_BADATTR); 374 } 375 376 *lo_p = 0ull; 377 *hi_p = UINT64_MAX; 378 379 return (DDI_SUCCESS); 380 } 381 382 383 /*ARGSUSED*/ 384 int 385 px_lib_iommu_getbypass(dev_info_t *dip, r_addr_t ra, 386 io_attributes_t io_attributes, io_addr_t *io_addr_p) 387 { 388 uint64_t ret; 389 390 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: dip 0x%p ra 0x%llx " 391 "attr 0x%x\n", dip, ra, io_attributes); 392 393 if ((ret = hvio_iommu_getbypass(DIP_TO_HANDLE(dip), ra, 394 io_attributes, io_addr_p)) != H_EOK) { 395 DBG(DBG_LIB_DMA, dip, 396 "hvio_iommu_getbypass failed, ret 0x%lx\n", ret); 397 return (ret == H_ENOTSUPPORTED ? DDI_ENOTSUP : DDI_FAILURE); 398 } 399 400 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: io_addr 0x%llx\n", 401 *io_addr_p); 402 403 return (DDI_SUCCESS); 404 } 405 406 /*ARGSUSED*/ 407 int 408 px_lib_dma_sync(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 409 off_t off, size_t len, uint_t cache_flags) 410 { 411 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 412 uint64_t sync_dir; 413 px_dvma_addr_t dvma_addr, pg_off; 414 size_t num_sync; 415 uint64_t status = H_EOK; 416 417 DBG(DBG_LIB_DMA, dip, "px_lib_dma_sync: dip 0x%p rdip 0x%p " 418 "handle 0x%llx off 0x%x len 0x%x flags 0x%x\n", 419 dip, rdip, handle, off, len, cache_flags); 420 421 if (!(mp->dmai_flags & DMAI_FLAGS_INUSE)) { 422 cmn_err(CE_WARN, "%s%d: Unbound dma handle %p.", 423 ddi_driver_name(rdip), ddi_get_instance(rdip), (void *)mp); 424 return (DDI_FAILURE); 425 } 426 427 if (mp->dmai_flags & DMAI_FLAGS_NOSYNC) 428 return (DDI_SUCCESS); 429 430 if (!len) 431 len = mp->dmai_size; 432 433 pg_off = mp->dmai_offset; /* start min */ 434 dvma_addr = MAX(off, pg_off); /* lo */ 435 pg_off += mp->dmai_size; /* end max */ 436 pg_off = MIN(off + len, pg_off); /* hi */ 437 if (dvma_addr >= pg_off) { /* lo >= hi ? */ 438 cmn_err(CE_WARN, "%s%d: %lx + %lx out of window [%lx,%lx]", 439 ddi_driver_name(rdip), ddi_get_instance(rdip), 440 off, len, mp->dmai_offset, 441 mp->dmai_offset + mp->dmai_size); 442 return (DDI_FAILURE); 443 } 444 445 len = pg_off - dvma_addr; /* sz = hi - lo */ 446 dvma_addr += mp->dmai_mapping; /* start addr */ 447 448 if (mp->dmai_rflags & DDI_DMA_READ) 449 sync_dir = HVIO_DMA_SYNC_DIR_FROM_DEV; 450 else 451 sync_dir = HVIO_DMA_SYNC_DIR_TO_DEV; 452 453 for (; ((len > 0) && (status == H_EOK)); len -= num_sync) { 454 status = hvio_dma_sync(DIP_TO_HANDLE(dip), dvma_addr, len, 455 sync_dir, &num_sync); 456 dvma_addr += num_sync; 457 } 458 459 return ((status == H_EOK) ? DDI_SUCCESS : DDI_FAILURE); 460 } 461 462 463 /* 464 * MSIQ Functions: 465 */ 466 467 /*ARGSUSED*/ 468 int 469 px_lib_msiq_init(dev_info_t *dip) 470 { 471 px_t *px_p = DIP_TO_STATE(dip); 472 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 473 uint64_t *msiq_addr, ra; 474 size_t msiq_size; 475 uint_t rec_cnt; 476 int i, err = DDI_SUCCESS; 477 uint64_t ret; 478 479 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_init: dip 0x%p\n", dip); 480 481 msiq_addr = (uint64_t *)(((uint64_t)msiq_state_p->msiq_buf_p + 482 (MMU_PAGE_SIZE - 1)) >> MMU_PAGE_SHIFT << MMU_PAGE_SHIFT); 483 484 msiq_size = msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t); 485 486 for (i = 0; i < msiq_state_p->msiq_cnt; i++) { 487 ra = (r_addr_t)va_to_pa((caddr_t)msiq_addr + (i * msiq_size)); 488 489 if ((ret = hvio_msiq_conf(DIP_TO_HANDLE(dip), 490 (i + msiq_state_p->msiq_1st_msiq_id), 491 ra, msiq_state_p->msiq_rec_cnt)) != H_EOK) { 492 DBG(DBG_LIB_MSIQ, dip, 493 "hvio_msiq_conf failed, ret 0x%lx\n", ret); 494 err = DDI_FAILURE; 495 break; 496 } 497 498 if ((err = px_lib_msiq_info(dip, 499 (i + msiq_state_p->msiq_1st_msiq_id), 500 &ra, &rec_cnt)) != DDI_SUCCESS) { 501 DBG(DBG_LIB_MSIQ, dip, 502 "px_lib_msiq_info failed, ret 0x%x\n", err); 503 err = DDI_FAILURE; 504 break; 505 } 506 507 DBG(DBG_LIB_MSIQ, dip, 508 "px_lib_msiq_init: ra 0x%p rec_cnt 0x%x\n", ra, rec_cnt); 509 } 510 511 return (err); 512 } 513 514 /*ARGSUSED*/ 515 int 516 px_lib_msiq_fini(dev_info_t *dip) 517 { 518 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_fini: dip 0x%p\n", dip); 519 520 return (DDI_SUCCESS); 521 } 522 523 /*ARGSUSED*/ 524 int 525 px_lib_msiq_info(dev_info_t *dip, msiqid_t msiq_id, r_addr_t *ra_p, 526 uint_t *msiq_rec_cnt_p) 527 { 528 uint64_t ret; 529 530 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: dip 0x%p msiq_id 0x%x\n", 531 dip, msiq_id); 532 533 if ((ret = hvio_msiq_info(DIP_TO_HANDLE(dip), 534 msiq_id, ra_p, msiq_rec_cnt_p)) != H_EOK) { 535 DBG(DBG_LIB_MSIQ, dip, 536 "hvio_msiq_info failed, ret 0x%lx\n", ret); 537 return (DDI_FAILURE); 538 } 539 540 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: ra_p 0x%p msiq_rec_cnt 0x%x\n", 541 ra_p, *msiq_rec_cnt_p); 542 543 return (DDI_SUCCESS); 544 } 545 546 /*ARGSUSED*/ 547 int 548 px_lib_msiq_getvalid(dev_info_t *dip, msiqid_t msiq_id, 549 pci_msiq_valid_state_t *msiq_valid_state) 550 { 551 uint64_t ret; 552 553 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: dip 0x%p msiq_id 0x%x\n", 554 dip, msiq_id); 555 556 if ((ret = hvio_msiq_getvalid(DIP_TO_HANDLE(dip), 557 msiq_id, msiq_valid_state)) != H_EOK) { 558 DBG(DBG_LIB_MSIQ, dip, 559 "hvio_msiq_getvalid failed, ret 0x%lx\n", ret); 560 return (DDI_FAILURE); 561 } 562 563 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: msiq_valid_state 0x%x\n", 564 *msiq_valid_state); 565 566 return (DDI_SUCCESS); 567 } 568 569 /*ARGSUSED*/ 570 int 571 px_lib_msiq_setvalid(dev_info_t *dip, msiqid_t msiq_id, 572 pci_msiq_valid_state_t msiq_valid_state) 573 { 574 uint64_t ret; 575 576 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setvalid: dip 0x%p msiq_id 0x%x " 577 "msiq_valid_state 0x%x\n", dip, msiq_id, msiq_valid_state); 578 579 if ((ret = hvio_msiq_setvalid(DIP_TO_HANDLE(dip), 580 msiq_id, msiq_valid_state)) != H_EOK) { 581 DBG(DBG_LIB_MSIQ, dip, 582 "hvio_msiq_setvalid failed, ret 0x%lx\n", ret); 583 return (DDI_FAILURE); 584 } 585 586 return (DDI_SUCCESS); 587 } 588 589 /*ARGSUSED*/ 590 int 591 px_lib_msiq_getstate(dev_info_t *dip, msiqid_t msiq_id, 592 pci_msiq_state_t *msiq_state) 593 { 594 uint64_t ret; 595 596 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: dip 0x%p msiq_id 0x%x\n", 597 dip, msiq_id); 598 599 if ((ret = hvio_msiq_getstate(DIP_TO_HANDLE(dip), 600 msiq_id, msiq_state)) != H_EOK) { 601 DBG(DBG_LIB_MSIQ, dip, 602 "hvio_msiq_getstate failed, ret 0x%lx\n", ret); 603 return (DDI_FAILURE); 604 } 605 606 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: msiq_state 0x%x\n", 607 *msiq_state); 608 609 return (DDI_SUCCESS); 610 } 611 612 /*ARGSUSED*/ 613 int 614 px_lib_msiq_setstate(dev_info_t *dip, msiqid_t msiq_id, 615 pci_msiq_state_t msiq_state) 616 { 617 uint64_t ret; 618 619 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setstate: dip 0x%p msiq_id 0x%x " 620 "msiq_state 0x%x\n", dip, msiq_id, msiq_state); 621 622 if ((ret = hvio_msiq_setstate(DIP_TO_HANDLE(dip), 623 msiq_id, msiq_state)) != H_EOK) { 624 DBG(DBG_LIB_MSIQ, dip, 625 "hvio_msiq_setstate failed, ret 0x%lx\n", ret); 626 return (DDI_FAILURE); 627 } 628 629 return (DDI_SUCCESS); 630 } 631 632 /*ARGSUSED*/ 633 int 634 px_lib_msiq_gethead(dev_info_t *dip, msiqid_t msiq_id, 635 msiqhead_t *msiq_head_p) 636 { 637 uint64_t ret; 638 639 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gethead: dip 0x%p msiq_id 0x%x\n", 640 dip, msiq_id); 641 642 if ((ret = hvio_msiq_gethead(DIP_TO_HANDLE(dip), 643 msiq_id, msiq_head_p)) != H_EOK) { 644 DBG(DBG_LIB_MSIQ, dip, 645 "hvio_msiq_gethead failed, ret 0x%lx\n", ret); 646 return (DDI_FAILURE); 647 } 648 649 *msiq_head_p = (*msiq_head_p / sizeof (msiq_rec_t)); 650 651 DBG(DBG_LIB_MSIQ, dip, "px_msiq_gethead: msiq_head 0x%x\n", 652 *msiq_head_p); 653 654 return (DDI_SUCCESS); 655 } 656 657 /*ARGSUSED*/ 658 int 659 px_lib_msiq_sethead(dev_info_t *dip, msiqid_t msiq_id, 660 msiqhead_t msiq_head) 661 { 662 uint64_t ret; 663 664 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_sethead: dip 0x%p msiq_id 0x%x " 665 "msiq_head 0x%x\n", dip, msiq_id, msiq_head); 666 667 if ((ret = hvio_msiq_sethead(DIP_TO_HANDLE(dip), 668 msiq_id, msiq_head * sizeof (msiq_rec_t))) != H_EOK) { 669 DBG(DBG_LIB_MSIQ, dip, 670 "hvio_msiq_sethead failed, ret 0x%lx\n", ret); 671 return (DDI_FAILURE); 672 } 673 674 return (DDI_SUCCESS); 675 } 676 677 /*ARGSUSED*/ 678 int 679 px_lib_msiq_gettail(dev_info_t *dip, msiqid_t msiq_id, 680 msiqtail_t *msiq_tail_p) 681 { 682 uint64_t ret; 683 684 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: dip 0x%p msiq_id 0x%x\n", 685 dip, msiq_id); 686 687 if ((ret = hvio_msiq_gettail(DIP_TO_HANDLE(dip), 688 msiq_id, msiq_tail_p)) != H_EOK) { 689 DBG(DBG_LIB_MSIQ, dip, 690 "hvio_msiq_gettail failed, ret 0x%lx\n", ret); 691 return (DDI_FAILURE); 692 } 693 694 *msiq_tail_p = (*msiq_tail_p / sizeof (msiq_rec_t)); 695 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: msiq_tail 0x%x\n", 696 *msiq_tail_p); 697 698 return (DDI_SUCCESS); 699 } 700 701 /*ARGSUSED*/ 702 void 703 px_lib_get_msiq_rec(dev_info_t *dip, px_msiq_t *msiq_p, msiq_rec_t *msiq_rec_p) 704 { 705 msiq_rec_t *curr_msiq_rec_p = (msiq_rec_t *)msiq_p->msiq_curr; 706 707 DBG(DBG_LIB_MSIQ, dip, "px_lib_get_msiq_rec: dip 0x%p\n", dip); 708 709 if (!curr_msiq_rec_p->msiq_rec_rid) 710 return; 711 712 *msiq_rec_p = *curr_msiq_rec_p; 713 714 /* Zero out msiq_rec_rid field */ 715 curr_msiq_rec_p->msiq_rec_rid = 0; 716 } 717 718 /* 719 * MSI Functions: 720 */ 721 722 /*ARGSUSED*/ 723 int 724 px_lib_msi_init(dev_info_t *dip) 725 { 726 DBG(DBG_LIB_MSI, dip, "px_lib_msi_init: dip 0x%p\n", dip); 727 728 /* Noop */ 729 return (DDI_SUCCESS); 730 } 731 732 /*ARGSUSED*/ 733 int 734 px_lib_msi_getmsiq(dev_info_t *dip, msinum_t msi_num, 735 msiqid_t *msiq_id) 736 { 737 uint64_t ret; 738 739 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: dip 0x%p msi_num 0x%x\n", 740 dip, msi_num); 741 742 if ((ret = hvio_msi_getmsiq(DIP_TO_HANDLE(dip), 743 msi_num, msiq_id)) != H_EOK) { 744 DBG(DBG_LIB_MSI, dip, 745 "hvio_msi_getmsiq failed, ret 0x%lx\n", ret); 746 return (DDI_FAILURE); 747 } 748 749 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: msiq_id 0x%x\n", 750 *msiq_id); 751 752 return (DDI_SUCCESS); 753 } 754 755 /*ARGSUSED*/ 756 int 757 px_lib_msi_setmsiq(dev_info_t *dip, msinum_t msi_num, 758 msiqid_t msiq_id, msi_type_t msitype) 759 { 760 uint64_t ret; 761 762 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setmsiq: dip 0x%p msi_num 0x%x " 763 "msq_id 0x%x\n", dip, msi_num, msiq_id); 764 765 if ((ret = hvio_msi_setmsiq(DIP_TO_HANDLE(dip), 766 msi_num, msiq_id, msitype)) != H_EOK) { 767 DBG(DBG_LIB_MSI, dip, 768 "hvio_msi_setmsiq failed, ret 0x%lx\n", ret); 769 return (DDI_FAILURE); 770 } 771 772 return (DDI_SUCCESS); 773 } 774 775 /*ARGSUSED*/ 776 int 777 px_lib_msi_getvalid(dev_info_t *dip, msinum_t msi_num, 778 pci_msi_valid_state_t *msi_valid_state) 779 { 780 uint64_t ret; 781 782 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: dip 0x%p msi_num 0x%x\n", 783 dip, msi_num); 784 785 if ((ret = hvio_msi_getvalid(DIP_TO_HANDLE(dip), 786 msi_num, msi_valid_state)) != H_EOK) { 787 DBG(DBG_LIB_MSI, dip, 788 "hvio_msi_getvalid failed, ret 0x%lx\n", ret); 789 return (DDI_FAILURE); 790 } 791 792 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: msiq_id 0x%x\n", 793 *msi_valid_state); 794 795 return (DDI_SUCCESS); 796 } 797 798 /*ARGSUSED*/ 799 int 800 px_lib_msi_setvalid(dev_info_t *dip, msinum_t msi_num, 801 pci_msi_valid_state_t msi_valid_state) 802 { 803 uint64_t ret; 804 805 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setvalid: dip 0x%p msi_num 0x%x " 806 "msi_valid_state 0x%x\n", dip, msi_num, msi_valid_state); 807 808 if ((ret = hvio_msi_setvalid(DIP_TO_HANDLE(dip), 809 msi_num, msi_valid_state)) != H_EOK) { 810 DBG(DBG_LIB_MSI, dip, 811 "hvio_msi_setvalid failed, ret 0x%lx\n", ret); 812 return (DDI_FAILURE); 813 } 814 815 return (DDI_SUCCESS); 816 } 817 818 /*ARGSUSED*/ 819 int 820 px_lib_msi_getstate(dev_info_t *dip, msinum_t msi_num, 821 pci_msi_state_t *msi_state) 822 { 823 uint64_t ret; 824 825 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: dip 0x%p msi_num 0x%x\n", 826 dip, msi_num); 827 828 if ((ret = hvio_msi_getstate(DIP_TO_HANDLE(dip), 829 msi_num, msi_state)) != H_EOK) { 830 DBG(DBG_LIB_MSI, dip, 831 "hvio_msi_getstate failed, ret 0x%lx\n", ret); 832 return (DDI_FAILURE); 833 } 834 835 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: msi_state 0x%x\n", 836 *msi_state); 837 838 return (DDI_SUCCESS); 839 } 840 841 /*ARGSUSED*/ 842 int 843 px_lib_msi_setstate(dev_info_t *dip, msinum_t msi_num, 844 pci_msi_state_t msi_state) 845 { 846 uint64_t ret; 847 848 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setstate: dip 0x%p msi_num 0x%x " 849 "msi_state 0x%x\n", dip, msi_num, msi_state); 850 851 if ((ret = hvio_msi_setstate(DIP_TO_HANDLE(dip), 852 msi_num, msi_state)) != H_EOK) { 853 DBG(DBG_LIB_MSI, dip, 854 "hvio_msi_setstate failed, ret 0x%lx\n", ret); 855 return (DDI_FAILURE); 856 } 857 858 return (DDI_SUCCESS); 859 } 860 861 /* 862 * MSG Functions: 863 */ 864 865 /*ARGSUSED*/ 866 int 867 px_lib_msg_getmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 868 msiqid_t *msiq_id) 869 { 870 uint64_t ret; 871 872 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getmsiq: dip 0x%p msg_type 0x%x\n", 873 dip, msg_type); 874 875 if ((ret = hvio_msg_getmsiq(DIP_TO_HANDLE(dip), 876 msg_type, msiq_id)) != H_EOK) { 877 DBG(DBG_LIB_MSG, dip, 878 "hvio_msg_getmsiq failed, ret 0x%lx\n", ret); 879 return (DDI_FAILURE); 880 } 881 882 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getmsiq: msiq_id 0x%x\n", 883 *msiq_id); 884 885 return (DDI_SUCCESS); 886 } 887 888 /*ARGSUSED*/ 889 int 890 px_lib_msg_setmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 891 msiqid_t msiq_id) 892 { 893 uint64_t ret; 894 895 DBG(DBG_LIB_MSG, dip, "px_lib_msg_setmsiq: dip 0x%p msg_type 0x%x " 896 "msq_id 0x%x\n", dip, msg_type, msiq_id); 897 898 if ((ret = hvio_msg_setmsiq(DIP_TO_HANDLE(dip), 899 msg_type, msiq_id)) != H_EOK) { 900 DBG(DBG_LIB_MSG, dip, 901 "hvio_msg_setmsiq failed, ret 0x%lx\n", ret); 902 return (DDI_FAILURE); 903 } 904 905 return (DDI_SUCCESS); 906 } 907 908 /*ARGSUSED*/ 909 int 910 px_lib_msg_getvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 911 pcie_msg_valid_state_t *msg_valid_state) 912 { 913 uint64_t ret; 914 915 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getvalid: dip 0x%p msg_type 0x%x\n", 916 dip, msg_type); 917 918 if ((ret = hvio_msg_getvalid(DIP_TO_HANDLE(dip), msg_type, 919 msg_valid_state)) != H_EOK) { 920 DBG(DBG_LIB_MSG, dip, 921 "hvio_msg_getvalid failed, ret 0x%lx\n", ret); 922 return (DDI_FAILURE); 923 } 924 925 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getvalid: msg_valid_state 0x%x\n", 926 *msg_valid_state); 927 928 return (DDI_SUCCESS); 929 } 930 931 /*ARGSUSED*/ 932 int 933 px_lib_msg_setvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 934 pcie_msg_valid_state_t msg_valid_state) 935 { 936 uint64_t ret; 937 938 DBG(DBG_LIB_MSG, dip, "px_lib_msg_setvalid: dip 0x%p msg_type 0x%x " 939 "msg_valid_state 0x%x\n", dip, msg_type, msg_valid_state); 940 941 if ((ret = hvio_msg_setvalid(DIP_TO_HANDLE(dip), msg_type, 942 msg_valid_state)) != H_EOK) { 943 DBG(DBG_LIB_MSG, dip, 944 "hvio_msg_setvalid failed, ret 0x%lx\n", ret); 945 return (DDI_FAILURE); 946 } 947 948 return (DDI_SUCCESS); 949 } 950 951 /* 952 * Suspend/Resume Functions: 953 * Currently unsupported by hypervisor and all functions are noops. 954 */ 955 /*ARGSUSED*/ 956 int 957 px_lib_suspend(dev_info_t *dip) 958 { 959 DBG(DBG_ATTACH, dip, "px_lib_suspend: Not supported\n"); 960 961 /* Not supported */ 962 return (DDI_FAILURE); 963 } 964 965 /*ARGSUSED*/ 966 void 967 px_lib_resume(dev_info_t *dip) 968 { 969 DBG(DBG_ATTACH, dip, "px_lib_resume: Not supported\n"); 970 971 /* Noop */ 972 } 973 974 /* 975 * PCI tool Functions: 976 * Currently unsupported by hypervisor and all functions are noops. 977 */ 978 /*ARGSUSED*/ 979 int 980 px_lib_tools_dev_reg_ops(dev_info_t *dip, void *arg, int cmd, int mode) 981 { 982 DBG(DBG_TOOLS, dip, "px_lib_tools_dev_reg_ops: Not supported\n"); 983 984 return (DDI_FAILURE); 985 } 986 987 /*ARGSUSED*/ 988 int 989 px_lib_tools_bus_reg_ops(dev_info_t *dip, void *arg, int cmd, int mode) 990 { 991 DBG(DBG_TOOLS, dip, "px_lib_tools_bus_reg_ops: Not supported\n"); 992 993 return (DDI_FAILURE); 994 } 995 996 /*ARGSUSED*/ 997 int 998 px_lib_tools_intr_admn(dev_info_t *dip, void *arg, int cmd, int mode) 999 { 1000 DBG(DBG_TOOLS, dip, "px_lib_tools_intr_admn: Not supported\n"); 1001 1002 return (DDI_FAILURE); 1003 } 1004 1005 /* 1006 * Misc Functions: 1007 * Currently unsupported by hypervisor and all functions are noops. 1008 */ 1009 /*ARGSUSED*/ 1010 uint64_t 1011 px_lib_get_cb(dev_info_t *dip) 1012 { 1013 return (DDI_SUCCESS); 1014 } 1015 1016 /*ARGSUSED*/ 1017 void 1018 px_lib_set_cb(dev_info_t *dip, uint64_t val) 1019 { 1020 /* Noop */ 1021 } 1022 1023 /*ARGSUSED*/ 1024 static int 1025 px_lib_config_get(dev_info_t *dip, pci_device_t bdf, pci_config_offset_t off, 1026 uint8_t size, pci_cfg_data_t *data_p) 1027 { 1028 uint64_t ret; 1029 1030 DBG(DBG_LIB_CFG, dip, "px_lib_config_get: dip 0x%p, bdf 0x%llx " 1031 "off 0x%x size 0x%x\n", dip, bdf, off, size); 1032 1033 if ((ret = hvio_config_get(DIP_TO_HANDLE(dip), bdf, off, 1034 size, data_p)) != H_EOK) { 1035 DBG(DBG_LIB_CFG, dip, 1036 "hvio_config_get failed, ret 0x%lx\n", ret); 1037 return (DDI_FAILURE); 1038 } 1039 DBG(DBG_LIB_CFG, dip, "px_config_get: data 0x%x\n", data_p->dw); 1040 1041 return (DDI_SUCCESS); 1042 } 1043 1044 /*ARGSUSED*/ 1045 static int 1046 px_lib_config_put(dev_info_t *dip, pci_device_t bdf, pci_config_offset_t off, 1047 uint8_t size, pci_cfg_data_t data) 1048 { 1049 uint64_t ret; 1050 1051 DBG(DBG_LIB_CFG, dip, "px_lib_config_put: dip 0x%p, bdf 0x%llx " 1052 "off 0x%x size 0x%x data 0x%llx\n", dip, bdf, off, size, data.qw); 1053 1054 if ((ret = hvio_config_put(DIP_TO_HANDLE(dip), bdf, off, 1055 size, data)) != H_EOK) { 1056 DBG(DBG_LIB_CFG, dip, 1057 "hvio_config_put failed, ret 0x%lx\n", ret); 1058 return (DDI_FAILURE); 1059 } 1060 1061 return (DDI_SUCCESS); 1062 } 1063 1064 static uint32_t 1065 px_pci_config_get(ddi_acc_impl_t *handle, uint32_t *addr, int size) 1066 { 1067 px_config_acc_pvt_t *px_pvt = (px_config_acc_pvt_t *) 1068 handle->ahi_common.ah_bus_private; 1069 uint32_t pci_dev_addr = px_pvt->raddr; 1070 uint32_t vaddr = px_pvt->vaddr; 1071 uint16_t off = (uint16_t)(addr - vaddr) & 0xfff; 1072 uint32_t rdata = 0; 1073 1074 if (px_lib_config_get(px_pvt->dip, pci_dev_addr, off, 1075 size, (pci_cfg_data_t *)&rdata) != DDI_SUCCESS) 1076 /* XXX update error kstats */ 1077 return (0xffffffff); 1078 return (rdata); 1079 } 1080 1081 static void 1082 px_pci_config_put(ddi_acc_impl_t *handle, uint32_t *addr, 1083 int size, pci_cfg_data_t wdata) 1084 { 1085 px_config_acc_pvt_t *px_pvt = (px_config_acc_pvt_t *) 1086 handle->ahi_common.ah_bus_private; 1087 uint32_t pci_dev_addr = px_pvt->raddr; 1088 uint32_t vaddr = px_pvt->vaddr; 1089 uint16_t off = (uint16_t)(addr - vaddr) & 0xfff; 1090 1091 if (px_lib_config_put(px_pvt->dip, pci_dev_addr, off, 1092 size, wdata) != DDI_SUCCESS) { 1093 /*EMPTY*/ 1094 /* XXX update error kstats */ 1095 } 1096 } 1097 1098 static uint8_t 1099 px_pci_config_get8(ddi_acc_impl_t *handle, uint8_t *addr) 1100 { 1101 return ((uint8_t)px_pci_config_get(handle, (uint32_t *)addr, 1)); 1102 } 1103 1104 static uint16_t 1105 px_pci_config_get16(ddi_acc_impl_t *handle, uint16_t *addr) 1106 { 1107 return ((uint16_t)px_pci_config_get(handle, (uint32_t *)addr, 2)); 1108 } 1109 1110 static uint32_t 1111 px_pci_config_get32(ddi_acc_impl_t *handle, uint32_t *addr) 1112 { 1113 return ((uint32_t)px_pci_config_get(handle, (uint32_t *)addr, 4)); 1114 } 1115 1116 static uint64_t 1117 px_pci_config_get64(ddi_acc_impl_t *handle, uint64_t *addr) 1118 { 1119 uint32_t rdatah, rdatal; 1120 1121 rdatal = (uint32_t)px_pci_config_get(handle, (uint32_t *)addr, 4); 1122 rdatah = (uint32_t)px_pci_config_get(handle, 1123 (uint32_t *)((char *)addr+4), 4); 1124 return (((uint64_t)rdatah << 32) | rdatal); 1125 } 1126 1127 static void 1128 px_pci_config_put8(ddi_acc_impl_t *handle, uint8_t *addr, uint8_t data) 1129 { 1130 pci_cfg_data_t wdata = { 0 }; 1131 1132 wdata.qw = (uint8_t)data; 1133 px_pci_config_put(handle, (uint32_t *)addr, 1, wdata); 1134 } 1135 1136 static void 1137 px_pci_config_put16(ddi_acc_impl_t *handle, uint16_t *addr, uint16_t data) 1138 { 1139 pci_cfg_data_t wdata = { 0 }; 1140 1141 wdata.qw = (uint16_t)data; 1142 px_pci_config_put(handle, (uint32_t *)addr, 2, wdata); 1143 } 1144 1145 static void 1146 px_pci_config_put32(ddi_acc_impl_t *handle, uint32_t *addr, uint32_t data) 1147 { 1148 pci_cfg_data_t wdata = { 0 }; 1149 1150 wdata.qw = (uint32_t)data; 1151 px_pci_config_put(handle, (uint32_t *)addr, 4, wdata); 1152 } 1153 1154 static void 1155 px_pci_config_put64(ddi_acc_impl_t *handle, uint64_t *addr, uint64_t data) 1156 { 1157 pci_cfg_data_t wdata = { 0 }; 1158 1159 wdata.qw = (uint32_t)(data & 0xffffffff); 1160 px_pci_config_put(handle, (uint32_t *)addr, 4, wdata); 1161 wdata.qw = (uint32_t)((data >> 32) & 0xffffffff); 1162 px_pci_config_put(handle, (uint32_t *)((char *)addr+4), 4, wdata); 1163 } 1164 1165 static void 1166 px_pci_config_rep_get8(ddi_acc_impl_t *handle, uint8_t *host_addr, 1167 uint8_t *dev_addr, size_t repcount, uint_t flags) 1168 { 1169 if (flags == DDI_DEV_AUTOINCR) 1170 for (; repcount; repcount--) 1171 *host_addr++ = px_pci_config_get8(handle, dev_addr++); 1172 else 1173 for (; repcount; repcount--) 1174 *host_addr++ = px_pci_config_get8(handle, dev_addr); 1175 } 1176 1177 /* 1178 * Function to rep read 16 bit data off the PCI configuration space behind 1179 * the 21554's host interface. 1180 */ 1181 static void 1182 px_pci_config_rep_get16(ddi_acc_impl_t *handle, uint16_t *host_addr, 1183 uint16_t *dev_addr, size_t repcount, uint_t flags) 1184 { 1185 if (flags == DDI_DEV_AUTOINCR) 1186 for (; repcount; repcount--) 1187 *host_addr++ = px_pci_config_get16(handle, dev_addr++); 1188 else 1189 for (; repcount; repcount--) 1190 *host_addr++ = px_pci_config_get16(handle, dev_addr); 1191 } 1192 1193 /* 1194 * Function to rep read 32 bit data off the PCI configuration space behind 1195 * the 21554's host interface. 1196 */ 1197 static void 1198 px_pci_config_rep_get32(ddi_acc_impl_t *handle, uint32_t *host_addr, 1199 uint32_t *dev_addr, size_t repcount, uint_t flags) 1200 { 1201 if (flags == DDI_DEV_AUTOINCR) 1202 for (; repcount; repcount--) 1203 *host_addr++ = px_pci_config_get32(handle, dev_addr++); 1204 else 1205 for (; repcount; repcount--) 1206 *host_addr++ = px_pci_config_get32(handle, dev_addr); 1207 } 1208 1209 /* 1210 * Function to rep read 64 bit data off the PCI configuration space behind 1211 * the 21554's host interface. 1212 */ 1213 static void 1214 px_pci_config_rep_get64(ddi_acc_impl_t *handle, uint64_t *host_addr, 1215 uint64_t *dev_addr, size_t repcount, uint_t flags) 1216 { 1217 if (flags == DDI_DEV_AUTOINCR) 1218 for (; repcount; repcount--) 1219 *host_addr++ = px_pci_config_get64(handle, dev_addr++); 1220 else 1221 for (; repcount; repcount--) 1222 *host_addr++ = px_pci_config_get64(handle, dev_addr); 1223 } 1224 1225 /* 1226 * Function to rep write 8 bit data into the PCI configuration space behind 1227 * the 21554's host interface. 1228 */ 1229 static void 1230 px_pci_config_rep_put8(ddi_acc_impl_t *handle, uint8_t *host_addr, 1231 uint8_t *dev_addr, size_t repcount, uint_t flags) 1232 { 1233 if (flags == DDI_DEV_AUTOINCR) 1234 for (; repcount; repcount--) 1235 px_pci_config_put8(handle, dev_addr++, *host_addr++); 1236 else 1237 for (; repcount; repcount--) 1238 px_pci_config_put8(handle, dev_addr, *host_addr++); 1239 } 1240 1241 /* 1242 * Function to rep write 16 bit data into the PCI configuration space behind 1243 * the 21554's host interface. 1244 */ 1245 static void 1246 px_pci_config_rep_put16(ddi_acc_impl_t *handle, uint16_t *host_addr, 1247 uint16_t *dev_addr, size_t repcount, uint_t flags) 1248 { 1249 if (flags == DDI_DEV_AUTOINCR) 1250 for (; repcount; repcount--) 1251 px_pci_config_put16(handle, dev_addr++, *host_addr++); 1252 else 1253 for (; repcount; repcount--) 1254 px_pci_config_put16(handle, dev_addr, *host_addr++); 1255 } 1256 1257 /* 1258 * Function to rep write 32 bit data into the PCI configuration space behind 1259 * the 21554's host interface. 1260 */ 1261 static void 1262 px_pci_config_rep_put32(ddi_acc_impl_t *handle, uint32_t *host_addr, 1263 uint32_t *dev_addr, size_t repcount, uint_t flags) 1264 { 1265 if (flags == DDI_DEV_AUTOINCR) 1266 for (; repcount; repcount--) 1267 px_pci_config_put32(handle, dev_addr++, *host_addr++); 1268 else 1269 for (; repcount; repcount--) 1270 px_pci_config_put32(handle, dev_addr, *host_addr++); 1271 } 1272 1273 /* 1274 * Function to rep write 64 bit data into the PCI configuration space behind 1275 * the 21554's host interface. 1276 */ 1277 static void 1278 px_pci_config_rep_put64(ddi_acc_impl_t *handle, uint64_t *host_addr, 1279 uint64_t *dev_addr, size_t repcount, uint_t flags) 1280 { 1281 if (flags == DDI_DEV_AUTOINCR) 1282 for (; repcount; repcount--) 1283 px_pci_config_put64(handle, dev_addr++, *host_addr++); 1284 else 1285 for (; repcount; repcount--) 1286 px_pci_config_put64(handle, dev_addr, *host_addr++); 1287 } 1288 1289 /* 1290 * Provide a private access handle to route config access calls to Hypervisor. 1291 * Beware: Do all error checking for config space accesses before calling 1292 * this function. ie. do error checking from the calling function. 1293 * Due to a lack of meaningful error code in DDI, the gauranteed return of 1294 * DDI_SUCCESS from here makes the code organization readable/easier from 1295 * the generic code. 1296 */ 1297 /*ARGSUSED*/ 1298 int 1299 px_lib_map_vconfig(dev_info_t *dip, 1300 ddi_map_req_t *mp, pci_config_offset_t off, 1301 pci_regspec_t *rp, caddr_t *addrp) 1302 { 1303 ddi_acc_hdl_t *hp; 1304 ddi_acc_impl_t *ap; 1305 uchar_t busnum; /* bus number */ 1306 uchar_t devnum; /* device number */ 1307 uchar_t funcnum; /* function number */ 1308 px_config_acc_pvt_t *px_pvt; 1309 1310 hp = (ddi_acc_hdl_t *)mp->map_handlep; 1311 ap = (ddi_acc_impl_t *)hp->ah_platform_private; 1312 1313 /* Check for mapping teardown operation */ 1314 if ((mp->map_op == DDI_MO_UNMAP) || 1315 (mp->map_op == DDI_MO_UNLOCK)) { 1316 /* free up memory allocated for the private access handle. */ 1317 px_pvt = (px_config_acc_pvt_t *)hp->ah_bus_private; 1318 kmem_free((void *)px_pvt, sizeof (px_config_acc_pvt_t)); 1319 1320 /* unmap operation of PCI IO/config space. */ 1321 return (DDI_SUCCESS); 1322 } 1323 1324 ap->ahi_get8 = px_pci_config_get8; 1325 ap->ahi_get16 = px_pci_config_get16; 1326 ap->ahi_get32 = px_pci_config_get32; 1327 ap->ahi_get64 = px_pci_config_get64; 1328 ap->ahi_put8 = px_pci_config_put8; 1329 ap->ahi_put16 = px_pci_config_put16; 1330 ap->ahi_put32 = px_pci_config_put32; 1331 ap->ahi_put64 = px_pci_config_put64; 1332 ap->ahi_rep_get8 = px_pci_config_rep_get8; 1333 ap->ahi_rep_get16 = px_pci_config_rep_get16; 1334 ap->ahi_rep_get32 = px_pci_config_rep_get32; 1335 ap->ahi_rep_get64 = px_pci_config_rep_get64; 1336 ap->ahi_rep_put8 = px_pci_config_rep_put8; 1337 ap->ahi_rep_put16 = px_pci_config_rep_put16; 1338 ap->ahi_rep_put32 = px_pci_config_rep_put32; 1339 ap->ahi_rep_put64 = px_pci_config_rep_put64; 1340 1341 /* Initialize to default check/notify functions */ 1342 ap->ahi_fault = 0; 1343 ap->ahi_fault_check = i_ddi_acc_fault_check; 1344 ap->ahi_fault_notify = i_ddi_acc_fault_notify; 1345 1346 /* allocate memory for our private handle */ 1347 px_pvt = (px_config_acc_pvt_t *) 1348 kmem_zalloc(sizeof (px_config_acc_pvt_t), KM_SLEEP); 1349 hp->ah_bus_private = (void *)px_pvt; 1350 1351 busnum = PCI_REG_BUS_G(rp->pci_phys_hi); 1352 devnum = PCI_REG_DEV_G(rp->pci_phys_hi); 1353 funcnum = PCI_REG_FUNC_G(rp->pci_phys_hi); 1354 1355 /* set up private data for use during IO routines */ 1356 1357 /* addr needed by the HV APIs */ 1358 px_pvt->raddr = busnum << 16 | devnum << 11 | funcnum << 8; 1359 /* 1360 * Address that specifies the actual offset into the 256MB 1361 * memory mapped configuration space, 4K per device. 1362 * First 12bits form the offset into 4K config space. 1363 * This address is only used during the IO routines to calculate 1364 * the offset at which the transaction must be performed. 1365 * Drivers bypassing DDI functions to access PCI config space will 1366 * panic the system since the following is a bogus virtual address. 1367 */ 1368 px_pvt->vaddr = busnum << 20 | devnum << 15 | funcnum << 12 | off; 1369 px_pvt->dip = dip; 1370 1371 DBG(DBG_LIB_CFG, dip, "px_config_setup: raddr 0x%x, vaddr 0x%x\n", 1372 px_pvt->raddr, px_pvt->vaddr); 1373 *addrp = (caddr_t)px_pvt->vaddr; 1374 return (DDI_SUCCESS); 1375 } 1376 1377 /* 1378 * px_lib_log_safeacc_err: 1379 * Imitate a cpu/mem trap call when a peek/poke fails. 1380 * This will initiate something similar to px_fm_callback. 1381 */ 1382 static void 1383 px_lib_log_safeacc_err(px_t *px_p, ddi_acc_handle_t handle, int fme_flag) 1384 { 1385 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)handle; 1386 px_cb_t *cb_p = px_p->px_cb_p; 1387 ddi_fm_error_t derr; 1388 1389 derr.fme_status = DDI_FM_NONFATAL; 1390 derr.fme_version = DDI_FME_VERSION; 1391 derr.fme_flag = fme_flag; 1392 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 1393 derr.fme_acc_handle = handle; 1394 if (hp) 1395 hp->ahi_err->err_expected = DDI_FM_ERR_EXPECTED; 1396 1397 mutex_enter(&cb_p->xbc_fm_mutex); 1398 1399 (void) ndi_fm_handler_dispatch(px_p->px_dip, NULL, &derr); 1400 1401 mutex_exit(&cb_p->xbc_fm_mutex); 1402 } 1403 1404 1405 #ifdef DEBUG 1406 int px_peekfault_cnt = 0; 1407 int px_pokefault_cnt = 0; 1408 #endif /* DEBUG */ 1409 1410 static int 1411 px_lib_bdf_from_dip(dev_info_t *rdip, uint32_t *bdf) 1412 { 1413 /* Start with an array of 8 reg spaces for now to cover most devices. */ 1414 pci_regspec_t regspec_array[8]; 1415 pci_regspec_t *regspec = regspec_array; 1416 int buflen = sizeof (regspec_array); 1417 boolean_t kmalloced = B_FALSE; 1418 int status; 1419 1420 status = ddi_getlongprop_buf(DDI_DEV_T_NONE, rdip, 1421 DDI_PROP_DONTPASS, "reg", (caddr_t)regspec, &buflen); 1422 1423 /* If need more space, fallback to kmem_alloc. */ 1424 if (status == DDI_PROP_BUF_TOO_SMALL) { 1425 regspec = kmem_alloc(buflen, KM_SLEEP); 1426 1427 status = ddi_getlongprop_buf(DDI_DEV_T_NONE, rdip, 1428 DDI_PROP_DONTPASS, "reg", (caddr_t)regspec, &buflen); 1429 1430 kmalloced = B_TRUE; 1431 } 1432 1433 /* Get phys_hi from first element. All have same bdf. */ 1434 if (status == DDI_PROP_SUCCESS) 1435 *bdf = regspec->pci_phys_hi & (PCI_REG_BDFR_M ^ PCI_REG_REG_M); 1436 1437 if (kmalloced) 1438 kmem_free(regspec, buflen); 1439 1440 return ((status == DDI_PROP_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE); 1441 } 1442 1443 /* 1444 * Do a safe write to a device. 1445 * 1446 * When this function is given a handle (cautious access), all errors are 1447 * suppressed. 1448 * 1449 * When this function is not given a handle (poke), only Unsupported Request 1450 * and Completer Abort errors are suppressed. 1451 * 1452 * In all cases, all errors are returned in the function return status. 1453 */ 1454 1455 int 1456 px_lib_ctlops_poke(dev_info_t *dip, dev_info_t *rdip, 1457 peekpoke_ctlops_t *in_args) 1458 { 1459 px_t *px_p = DIP_TO_STATE(dip); 1460 px_pec_t *pec_p = px_p->px_pec_p; 1461 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)in_args->handle; 1462 1463 size_t repcount = in_args->repcount; 1464 size_t size = in_args->size; 1465 uintptr_t dev_addr = in_args->dev_addr; 1466 uintptr_t host_addr = in_args->host_addr; 1467 1468 int err = DDI_SUCCESS; 1469 uint64_t hvio_poke_status; 1470 uint32_t bdf; 1471 uint32_t wrt_stat; 1472 1473 r_addr_t ra; 1474 uint64_t pokeval; 1475 1476 /* 1477 * Used only to notify error handling peek/poke is occuring 1478 * One scenario is when a fabric err as a result of peek/poke. 1479 * However there is no way to guarantee that the fabric error 1480 * handler will occur in the window where otd is set. 1481 */ 1482 on_trap_data_t otd; 1483 1484 if (px_lib_bdf_from_dip(rdip, &bdf) != DDI_SUCCESS) { 1485 DBG(DBG_LIB_DMA, px_p->px_dip, 1486 "poke: px_lib_bdf_from_dip failed\n"); 1487 err = DDI_FAILURE; 1488 goto done; 1489 } 1490 1491 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1492 for (; repcount; repcount--) { 1493 1494 switch (size) { 1495 case sizeof (uint8_t): 1496 pokeval = *(uint8_t *)host_addr; 1497 break; 1498 case sizeof (uint16_t): 1499 pokeval = *(uint16_t *)host_addr; 1500 break; 1501 case sizeof (uint32_t): 1502 pokeval = *(uint32_t *)host_addr; 1503 break; 1504 case sizeof (uint64_t): 1505 pokeval = *(uint64_t *)host_addr; 1506 break; 1507 default: 1508 DBG(DBG_MAP, px_p->px_dip, 1509 "poke: invalid size %d passed\n", size); 1510 err = DDI_FAILURE; 1511 goto done; 1512 } 1513 1514 /* 1515 * Grab pokefault mutex since hypervisor does not guarantee 1516 * poke serialization. 1517 */ 1518 if (hp) { 1519 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, 1520 (ddi_acc_handle_t)hp); 1521 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1522 } else { 1523 mutex_enter(&pec_p->pec_pokefault_mutex); 1524 pec_p->pec_safeacc_type = DDI_FM_ERR_POKE; 1525 } 1526 pec_p->pec_ontrap_data = &otd; 1527 1528 hvio_poke_status = hvio_poke(px_p->px_dev_hdl, ra, size, 1529 pokeval, bdf, &wrt_stat); 1530 1531 if (otd.ot_trap & OT_DATA_ACCESS) 1532 err = DDI_FAILURE; 1533 1534 if ((hvio_poke_status != H_EOK) || (wrt_stat != H_EOK)) { 1535 err = DDI_FAILURE; 1536 #ifdef DEBUG 1537 px_pokefault_cnt++; 1538 #endif 1539 /* 1540 * For CAUTIOUS and POKE access, notify FMA to 1541 * cleanup. Imitate a cpu/mem trap call like in sun4u. 1542 */ 1543 px_lib_log_safeacc_err(px_p, (ddi_acc_handle_t)hp, 1544 (hp ? DDI_FM_ERR_EXPECTED : 1545 DDI_FM_ERR_POKE)); 1546 1547 pec_p->pec_ontrap_data = NULL; 1548 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1549 if (hp) { 1550 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1551 (ddi_acc_handle_t)hp); 1552 } else { 1553 mutex_exit(&pec_p->pec_pokefault_mutex); 1554 } 1555 goto done; 1556 } 1557 1558 pec_p->pec_ontrap_data = NULL; 1559 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1560 if (hp) { 1561 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1562 (ddi_acc_handle_t)hp); 1563 } else { 1564 mutex_exit(&pec_p->pec_pokefault_mutex); 1565 } 1566 1567 host_addr += size; 1568 1569 if (in_args->flags == DDI_DEV_AUTOINCR) { 1570 dev_addr += size; 1571 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1572 } 1573 } 1574 1575 done: 1576 return (err); 1577 } 1578 1579 1580 /*ARGSUSED*/ 1581 int 1582 px_lib_ctlops_peek(dev_info_t *dip, dev_info_t *rdip, 1583 peekpoke_ctlops_t *in_args, void *result) 1584 { 1585 px_t *px_p = DIP_TO_STATE(dip); 1586 px_pec_t *pec_p = px_p->px_pec_p; 1587 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)in_args->handle; 1588 1589 size_t repcount = in_args->repcount; 1590 uintptr_t dev_addr = in_args->dev_addr; 1591 uintptr_t host_addr = in_args->host_addr; 1592 1593 r_addr_t ra; 1594 uint32_t read_status; 1595 uint64_t hvio_peek_status; 1596 uint64_t peekval; 1597 int err = DDI_SUCCESS; 1598 1599 /* 1600 * Used only to notify error handling peek/poke is occuring 1601 * One scenario is when a fabric err as a result of peek/poke. 1602 * However there is no way to guarantee that the fabric error 1603 * handler will occur in the window where otd is set. 1604 */ 1605 on_trap_data_t otd; 1606 1607 result = (void *)in_args->host_addr; 1608 1609 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1610 for (; repcount; repcount--) { 1611 1612 /* Lock pokefault mutex so read doesn't mask a poke fault. */ 1613 if (hp) { 1614 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, 1615 (ddi_acc_handle_t)hp); 1616 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1617 } else { 1618 mutex_enter(&pec_p->pec_pokefault_mutex); 1619 pec_p->pec_safeacc_type = DDI_FM_ERR_PEEK; 1620 } 1621 pec_p->pec_ontrap_data = &otd; 1622 1623 hvio_peek_status = hvio_peek(px_p->px_dev_hdl, ra, 1624 in_args->size, &read_status, &peekval); 1625 1626 if ((hvio_peek_status != H_EOK) || (read_status != H_EOK)) { 1627 err = DDI_FAILURE; 1628 1629 /* 1630 * For CAUTIOUS and PEEK access, notify FMA to 1631 * cleanup. Imitate a cpu/mem trap call like in sun4u. 1632 */ 1633 px_lib_log_safeacc_err(px_p, (ddi_acc_handle_t)hp, 1634 (hp ? DDI_FM_ERR_EXPECTED : 1635 DDI_FM_ERR_PEEK)); 1636 1637 /* Stuff FFs in host addr if peek. */ 1638 if (hp == NULL) { 1639 int i; 1640 uint8_t *ff_addr = (uint8_t *)host_addr; 1641 for (i = 0; i < in_args->size; i++) 1642 *ff_addr++ = 0xff; 1643 } 1644 #ifdef DEBUG 1645 px_peekfault_cnt++; 1646 #endif 1647 pec_p->pec_ontrap_data = NULL; 1648 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1649 if (hp) { 1650 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1651 (ddi_acc_handle_t)hp); 1652 } else { 1653 mutex_exit(&pec_p->pec_pokefault_mutex); 1654 } 1655 goto done; 1656 1657 } 1658 pec_p->pec_ontrap_data = NULL; 1659 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1660 if (hp) { 1661 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1662 (ddi_acc_handle_t)hp); 1663 } else { 1664 mutex_exit(&pec_p->pec_pokefault_mutex); 1665 } 1666 1667 switch (in_args->size) { 1668 case sizeof (uint8_t): 1669 *(uint8_t *)host_addr = (uint8_t)peekval; 1670 break; 1671 case sizeof (uint16_t): 1672 *(uint16_t *)host_addr = (uint16_t)peekval; 1673 break; 1674 case sizeof (uint32_t): 1675 *(uint32_t *)host_addr = (uint32_t)peekval; 1676 break; 1677 case sizeof (uint64_t): 1678 *(uint64_t *)host_addr = (uint64_t)peekval; 1679 break; 1680 default: 1681 DBG(DBG_MAP, px_p->px_dip, 1682 "peek: invalid size %d passed\n", 1683 in_args->size); 1684 err = DDI_FAILURE; 1685 goto done; 1686 } 1687 1688 host_addr += in_args->size; 1689 1690 if (in_args->flags == DDI_DEV_AUTOINCR) { 1691 dev_addr += in_args->size; 1692 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1693 } 1694 } 1695 done: 1696 return (err); 1697 } 1698 1699 1700 /* add interrupt vector */ 1701 int 1702 px_err_add_intr(px_fault_t *px_fault_p) 1703 { 1704 int ret; 1705 px_t *px_p = DIP_TO_STATE(px_fault_p->px_fh_dip); 1706 1707 DBG(DBG_LIB_INT, px_p->px_dip, 1708 "px_err_add_intr: calling add_ivintr"); 1709 ret = add_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL, 1710 px_fault_p->px_err_func, (caddr_t)px_fault_p, 1711 (caddr_t)&px_fault_p->px_intr_payload[0]); 1712 1713 if (ret != DDI_SUCCESS) { 1714 DBG(DBG_LIB_INT, px_p->px_dip, 1715 "add_ivintr returns %d, faultp: %p", ret, px_fault_p); 1716 1717 return (ret); 1718 } 1719 DBG(DBG_LIB_INT, px_p->px_dip, 1720 "px_err_add_intr: ib_intr_enable "); 1721 1722 px_ib_intr_enable(px_p, intr_dist_cpuid(), px_fault_p->px_intr_ino); 1723 1724 return (ret); 1725 } 1726 1727 1728 /* remove interrupt vector */ 1729 void 1730 px_err_rem_intr(px_fault_t *px_fault_p) 1731 { 1732 px_t *px_p = DIP_TO_STATE(px_fault_p->px_fh_dip); 1733 1734 rem_ivintr(px_fault_p->px_fh_sysino, NULL); 1735 1736 px_ib_intr_disable(px_p->px_ib_p, px_fault_p->px_intr_ino, 1737 IB_INTR_WAIT); 1738 } 1739 1740 1741 #ifdef FMA 1742 void 1743 px_fill_rc_status(px_fault_t *px_fault_p, pciex_rc_error_regs_t *rc_status) 1744 { 1745 px_pec_err_t *err_pkt; 1746 1747 err_pkt = (px_pec_err_t *)px_fault_p->px_intr_payload; 1748 1749 /* initialise all the structure members */ 1750 rc_status->status_valid = 0; 1751 1752 if (err_pkt->pec_descr.P) { 1753 /* PCI Status Register */ 1754 rc_status->pci_err_status = err_pkt->pci_err_status; 1755 rc_status->status_valid |= PCI_ERR_STATUS_VALID; 1756 } 1757 1758 if (err_pkt->pec_descr.E) { 1759 /* PCIe Status Register */ 1760 rc_status->pcie_err_status = err_pkt->pcie_err_status; 1761 rc_status->status_valid |= PCIE_ERR_STATUS_VALID; 1762 } 1763 1764 if (err_pkt->pec_descr.U) { 1765 rc_status->ue_status = err_pkt->ue_reg_status; 1766 rc_status->status_valid |= UE_STATUS_VALID; 1767 } 1768 1769 if (err_pkt->pec_descr.H) { 1770 rc_status->ue_hdr1 = err_pkt->hdr[0]; 1771 rc_status->status_valid |= UE_HDR1_VALID; 1772 } 1773 1774 if (err_pkt->pec_descr.I) { 1775 rc_status->ue_hdr2 = err_pkt->hdr[1]; 1776 rc_status->status_valid |= UE_HDR2_VALID; 1777 } 1778 1779 /* ue_fst_err_ptr - not available for sun4v?? */ 1780 1781 1782 if (err_pkt->pec_descr.S) { 1783 rc_status->source_id = err_pkt->err_src_reg; 1784 rc_status->status_valid |= SOURCE_ID_VALID; 1785 } 1786 1787 if (err_pkt->pec_descr.R) { 1788 rc_status->root_err_status = err_pkt->root_err_status; 1789 rc_status->status_valid |= CE_STATUS_VALID; 1790 } 1791 } 1792 #endif 1793 1794 /*ARGSUSED*/ 1795 int 1796 px_lib_pmctl(int cmd, px_t *px_p) 1797 { 1798 return (DDI_FAILURE); 1799 } 1800 1801 /*ARGSUSED*/ 1802 uint_t 1803 px_lup_softintr(caddr_t arg) 1804 { 1805 return (DDI_INTR_CLAIMED); 1806 } 1807 1808 /*ARGSUSED*/ 1809 uint_t 1810 px_pmeq_intr(caddr_t arg) 1811 { 1812 return (DDI_INTR_CLAIMED); 1813 } 1814