1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/sysmacros.h> 30 #include <sys/ddi.h> 31 #include <sys/async.h> 32 #include <sys/sunddi.h> 33 #include <sys/ddifm.h> 34 #include <sys/fm/protocol.h> 35 #include <sys/vmem.h> 36 #include <sys/intr.h> 37 #include <sys/ivintr.h> 38 #include <sys/errno.h> 39 #include <sys/hypervisor_api.h> 40 #include <sys/hsvc.h> 41 #include <px_obj.h> 42 #include <sys/machsystm.h> 43 #include <sys/hotplug/pci/pcihp.h> 44 #include "px_lib4v.h" 45 #include "px_err.h" 46 47 /* mask for the ranges property in calculating the real PFN range */ 48 uint_t px_ranges_phi_mask = ((1 << 28) -1); 49 50 /* 51 * Hypervisor VPCI services information for the px nexus driver. 52 */ 53 static uint64_t px_vpci_min_ver; /* Negotiated VPCI API minor version */ 54 static uint_t px_vpci_users = 0; /* VPCI API users */ 55 56 static hsvc_info_t px_hsvc = { 57 HSVC_REV_1, NULL, HSVC_GROUP_VPCI, PX_VPCI_MAJOR_VER, 58 PX_VPCI_MINOR_VER, "PX" 59 }; 60 61 int 62 px_lib_dev_init(dev_info_t *dip, devhandle_t *dev_hdl) 63 { 64 px_nexus_regspec_t *rp; 65 uint_t reglen; 66 int ret; 67 68 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dip 0x%p\n", dip); 69 70 ret = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 71 "reg", (uchar_t **)&rp, ®len); 72 if (ret != DDI_PROP_SUCCESS) { 73 DBG(DBG_ATTACH, dip, "px_lib_dev_init failed ret=%d\n", ret); 74 return (DDI_FAILURE); 75 } 76 77 /* 78 * Initilize device handle. The device handle uniquely identifies 79 * a SUN4V device. It consists of the lower 28-bits of the hi-cell 80 * of the first entry of the SUN4V device's "reg" property as 81 * defined by the SUN4V Bus Binding to Open Firmware. 82 */ 83 *dev_hdl = (devhandle_t)((rp->phys_addr >> 32) & DEVHDLE_MASK); 84 ddi_prop_free(rp); 85 86 /* 87 * hotplug implementation requires this property to be associated with 88 * any indirect PCI config access services 89 */ 90 (void) ddi_prop_update_int(makedevice(ddi_driver_major(dip), 91 PCIHP_AP_MINOR_NUM(ddi_get_instance(dip), PCIHP_DEVCTL_MINOR)), dip, 92 PCI_BUS_CONF_MAP_PROP, 1); 93 94 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dev_hdl 0x%llx\n", *dev_hdl); 95 96 /* 97 * Negotiate the API version for VPCI hypervisor services. 98 */ 99 if (px_vpci_users++) 100 return (DDI_SUCCESS); 101 102 if ((ret = hsvc_register(&px_hsvc, &px_vpci_min_ver)) != 0) { 103 cmn_err(CE_WARN, "%s: cannot negotiate hypervisor services " 104 "group: 0x%lx major: 0x%lx minor: 0x%lx errno: %d\n", 105 px_hsvc.hsvc_modname, px_hsvc.hsvc_group, 106 px_hsvc.hsvc_major, px_hsvc.hsvc_minor, ret); 107 108 return (DDI_FAILURE); 109 } 110 111 DBG(DBG_ATTACH, dip, "px_lib_dev_init: negotiated VPCI API version, " 112 "major 0x%lx minor 0x%lx\n", px_hsvc.hsvc_major, px_vpci_min_ver); 113 114 return (DDI_SUCCESS); 115 } 116 117 /*ARGSUSED*/ 118 int 119 px_lib_dev_fini(dev_info_t *dip) 120 { 121 DBG(DBG_DETACH, dip, "px_lib_dev_fini: dip 0x%p\n", dip); 122 123 (void) ddi_prop_remove(makedevice(ddi_driver_major(dip), 124 PCIHP_AP_MINOR_NUM(ddi_get_instance(dip), PCIHP_DEVCTL_MINOR)), dip, 125 PCI_BUS_CONF_MAP_PROP); 126 127 if (--px_vpci_users == 0) 128 (void) hsvc_unregister(&px_hsvc); 129 130 return (DDI_SUCCESS); 131 } 132 133 /*ARGSUSED*/ 134 int 135 px_lib_intr_devino_to_sysino(dev_info_t *dip, devino_t devino, 136 sysino_t *sysino) 137 { 138 uint64_t ret; 139 140 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: dip 0x%p " 141 "devino 0x%x\n", dip, devino); 142 143 if ((ret = hvio_intr_devino_to_sysino(DIP_TO_HANDLE(dip), 144 devino, sysino)) != H_EOK) { 145 DBG(DBG_LIB_INT, dip, 146 "hvio_intr_devino_to_sysino failed, ret 0x%lx\n", ret); 147 return (DDI_FAILURE); 148 } 149 150 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: sysino 0x%llx\n", 151 *sysino); 152 153 return (DDI_SUCCESS); 154 } 155 156 /*ARGSUSED*/ 157 int 158 px_lib_intr_getvalid(dev_info_t *dip, sysino_t sysino, 159 intr_valid_state_t *intr_valid_state) 160 { 161 uint64_t ret; 162 163 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: dip 0x%p sysino 0x%llx\n", 164 dip, sysino); 165 166 if ((ret = hvio_intr_getvalid(sysino, 167 (int *)intr_valid_state)) != H_EOK) { 168 DBG(DBG_LIB_INT, dip, "hvio_intr_getvalid failed, ret 0x%lx\n", 169 ret); 170 return (DDI_FAILURE); 171 } 172 173 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: intr_valid_state 0x%x\n", 174 *intr_valid_state); 175 176 return (DDI_SUCCESS); 177 } 178 179 /*ARGSUSED*/ 180 int 181 px_lib_intr_setvalid(dev_info_t *dip, sysino_t sysino, 182 intr_valid_state_t intr_valid_state) 183 { 184 uint64_t ret; 185 186 DBG(DBG_LIB_INT, dip, "px_lib_intr_setvalid: dip 0x%p sysino 0x%llx " 187 "intr_valid_state 0x%x\n", dip, sysino, intr_valid_state); 188 189 if ((ret = hvio_intr_setvalid(sysino, intr_valid_state)) != H_EOK) { 190 DBG(DBG_LIB_INT, dip, "hvio_intr_setvalid failed, ret 0x%lx\n", 191 ret); 192 return (DDI_FAILURE); 193 } 194 195 return (DDI_SUCCESS); 196 } 197 198 /*ARGSUSED*/ 199 int 200 px_lib_intr_getstate(dev_info_t *dip, sysino_t sysino, 201 intr_state_t *intr_state) 202 { 203 uint64_t ret; 204 205 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: dip 0x%p sysino 0x%llx\n", 206 dip, sysino); 207 208 if ((ret = hvio_intr_getstate(sysino, (int *)intr_state)) != H_EOK) { 209 DBG(DBG_LIB_INT, dip, "hvio_intr_getstate failed, ret 0x%lx\n", 210 ret); 211 return (DDI_FAILURE); 212 } 213 214 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: intr_state 0x%x\n", 215 *intr_state); 216 217 return (DDI_SUCCESS); 218 } 219 220 /*ARGSUSED*/ 221 int 222 px_lib_intr_setstate(dev_info_t *dip, sysino_t sysino, 223 intr_state_t intr_state) 224 { 225 uint64_t ret; 226 227 DBG(DBG_LIB_INT, dip, "px_lib_intr_setstate: dip 0x%p sysino 0x%llx " 228 "intr_state 0x%x\n", dip, sysino, intr_state); 229 230 if ((ret = hvio_intr_setstate(sysino, intr_state)) != H_EOK) { 231 DBG(DBG_LIB_INT, dip, "hvio_intr_setstate failed, ret 0x%lx\n", 232 ret); 233 return (DDI_FAILURE); 234 } 235 236 return (DDI_SUCCESS); 237 } 238 239 /*ARGSUSED*/ 240 int 241 px_lib_intr_gettarget(dev_info_t *dip, sysino_t sysino, cpuid_t *cpuid) 242 { 243 uint64_t ret; 244 245 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: dip 0x%p sysino 0x%llx\n", 246 dip, sysino); 247 248 if ((ret = hvio_intr_gettarget(sysino, cpuid)) != H_EOK) { 249 DBG(DBG_LIB_INT, dip, 250 "hvio_intr_gettarget failed, ret 0x%lx\n", ret); 251 return (DDI_FAILURE); 252 } 253 254 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: cpuid 0x%x\n", cpuid); 255 256 return (DDI_SUCCESS); 257 } 258 259 /*ARGSUSED*/ 260 int 261 px_lib_intr_settarget(dev_info_t *dip, sysino_t sysino, cpuid_t cpuid) 262 { 263 uint64_t ret; 264 265 DBG(DBG_LIB_INT, dip, "px_lib_intr_settarget: dip 0x%p sysino 0x%llx " 266 "cpuid 0x%x\n", dip, sysino, cpuid); 267 268 if ((ret = hvio_intr_settarget(sysino, cpuid)) != H_EOK) { 269 DBG(DBG_LIB_INT, dip, 270 "hvio_intr_settarget failed, ret 0x%lx\n", ret); 271 return (DDI_FAILURE); 272 } 273 274 return (DDI_SUCCESS); 275 } 276 277 /*ARGSUSED*/ 278 int 279 px_lib_intr_reset(dev_info_t *dip) 280 { 281 px_t *px_p = DIP_TO_STATE(dip); 282 px_ib_t *ib_p = px_p->px_ib_p; 283 px_ib_ino_info_t *ino_p; 284 285 DBG(DBG_LIB_INT, dip, "px_lib_intr_reset: dip 0x%p\n", dip); 286 287 mutex_enter(&ib_p->ib_ino_lst_mutex); 288 289 /* Reset all Interrupts */ 290 for (ino_p = ib_p->ib_ino_lst; ino_p; ino_p = ino_p->ino_next) { 291 if (px_lib_intr_setstate(dip, ino_p->ino_sysino, 292 INTR_IDLE_STATE) != DDI_SUCCESS) 293 return (BF_FATAL); 294 } 295 296 mutex_exit(&ib_p->ib_ino_lst_mutex); 297 298 return (BF_NONE); 299 } 300 301 /*ARGSUSED*/ 302 int 303 px_lib_iommu_map(dev_info_t *dip, tsbid_t tsbid, pages_t pages, 304 io_attributes_t attr, void *addr, size_t pfn_index, int flags) 305 { 306 tsbnum_t tsb_num = PCI_TSBID_TO_TSBNUM(tsbid); 307 tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); 308 io_page_list_t *pfns, *pfn_p; 309 pages_t ttes_mapped = 0; 310 int i, err = DDI_SUCCESS; 311 312 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: dip 0x%p tsbid 0x%llx " 313 "pages 0x%x attr 0x%x addr 0x%p pfn_index 0x%llx flags 0x%x\n", 314 dip, tsbid, pages, attr, addr, pfn_index, flags); 315 316 if ((pfns = pfn_p = kmem_zalloc((pages * sizeof (io_page_list_t)), 317 KM_NOSLEEP)) == NULL) { 318 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: kmem_zalloc failed\n"); 319 return (DDI_FAILURE); 320 } 321 322 for (i = 0; i < pages; i++) 323 pfns[i] = MMU_PTOB(PX_ADDR2PFN(addr, pfn_index, flags, i)); 324 325 while ((ttes_mapped = pfn_p - pfns) < pages) { 326 uintptr_t ra = va_to_pa(pfn_p); 327 pages_t ttes2map; 328 uint64_t ret; 329 330 ttes2map = (MMU_PAGE_SIZE - P2PHASE(ra, MMU_PAGE_SIZE)) >> 3; 331 ra = MMU_PTOB(MMU_BTOP(ra)); 332 333 for (ttes2map = MIN(ttes2map, pages - ttes_mapped); ttes2map; 334 ttes2map -= ttes_mapped, pfn_p += ttes_mapped) { 335 336 ttes_mapped = 0; 337 if ((ret = hvio_iommu_map(DIP_TO_HANDLE(dip), 338 PCI_TSBID(tsb_num, tsb_index + (pfn_p - pfns)), 339 ttes2map, attr, (io_page_list_t *)(ra | 340 ((uintptr_t)pfn_p & MMU_PAGE_OFFSET)), 341 &ttes_mapped)) != H_EOK) { 342 DBG(DBG_LIB_DMA, dip, "hvio_iommu_map failed " 343 "ret 0x%lx\n", ret); 344 345 ttes_mapped = pfn_p - pfns; 346 err = DDI_FAILURE; 347 goto cleanup; 348 } 349 350 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: tsb_num 0x%x " 351 "tsb_index 0x%lx ttes_to_map 0x%lx attr 0x%x " 352 "ra 0x%p ttes_mapped 0x%x\n", tsb_num, 353 tsb_index + (pfn_p - pfns), ttes2map, attr, 354 ra | ((uintptr_t)pfn_p & MMU_PAGE_OFFSET), 355 ttes_mapped); 356 } 357 } 358 359 cleanup: 360 if ((err == DDI_FAILURE) && ttes_mapped) 361 (void) px_lib_iommu_demap(dip, tsbid, ttes_mapped); 362 363 kmem_free(pfns, pages * sizeof (io_page_list_t)); 364 return (err); 365 } 366 367 /*ARGSUSED*/ 368 int 369 px_lib_iommu_demap(dev_info_t *dip, tsbid_t tsbid, pages_t pages) 370 { 371 tsbnum_t tsb_num = PCI_TSBID_TO_TSBNUM(tsbid); 372 tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); 373 pages_t ttes2demap, ttes_demapped = 0; 374 uint64_t ret; 375 376 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: dip 0x%p tsbid 0x%llx " 377 "pages 0x%x\n", dip, tsbid, pages); 378 379 for (ttes2demap = pages; ttes2demap; 380 ttes2demap -= ttes_demapped, tsb_index += ttes_demapped) { 381 if ((ret = hvio_iommu_demap(DIP_TO_HANDLE(dip), 382 PCI_TSBID(tsb_num, tsb_index), ttes2demap, 383 &ttes_demapped)) != H_EOK) { 384 DBG(DBG_LIB_DMA, dip, "hvio_iommu_demap failed, " 385 "ret 0x%lx\n", ret); 386 387 return (DDI_FAILURE); 388 } 389 390 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: tsb_num 0x%x " 391 "tsb_index 0x%lx ttes_to_demap 0x%lx ttes_demapped 0x%x\n", 392 tsb_num, tsb_index, ttes2demap, ttes_demapped); 393 } 394 395 return (DDI_SUCCESS); 396 } 397 398 /*ARGSUSED*/ 399 int 400 px_lib_iommu_getmap(dev_info_t *dip, tsbid_t tsbid, io_attributes_t *attr_p, 401 r_addr_t *r_addr_p) 402 { 403 uint64_t ret; 404 405 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: dip 0x%p tsbid 0x%llx\n", 406 dip, tsbid); 407 408 if ((ret = hvio_iommu_getmap(DIP_TO_HANDLE(dip), tsbid, 409 attr_p, r_addr_p)) != H_EOK) { 410 DBG(DBG_LIB_DMA, dip, 411 "hvio_iommu_getmap failed, ret 0x%lx\n", ret); 412 413 return ((ret == H_ENOMAP) ? DDI_DMA_NOMAPPING:DDI_FAILURE); 414 } 415 416 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: attr 0x%x r_addr 0x%llx\n", 417 *attr_p, *r_addr_p); 418 419 return (DDI_SUCCESS); 420 } 421 422 423 /* 424 * Checks dma attributes against system bypass ranges 425 * A sun4v device must be capable of generating the entire 64-bit 426 * address in order to perform bypass DMA. 427 */ 428 /*ARGSUSED*/ 429 int 430 px_lib_dma_bypass_rngchk(ddi_dma_attr_t *attr_p, uint64_t *lo_p, uint64_t *hi_p) 431 { 432 if ((attr_p->dma_attr_addr_lo != 0ull) || 433 (attr_p->dma_attr_addr_hi != UINT64_MAX)) { 434 435 return (DDI_DMA_BADATTR); 436 } 437 438 *lo_p = 0ull; 439 *hi_p = UINT64_MAX; 440 441 return (DDI_SUCCESS); 442 } 443 444 445 /*ARGSUSED*/ 446 int 447 px_lib_iommu_getbypass(dev_info_t *dip, r_addr_t ra, io_attributes_t attr, 448 io_addr_t *io_addr_p) 449 { 450 uint64_t ret; 451 452 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: dip 0x%p ra 0x%llx " 453 "attr 0x%x\n", dip, ra, attr); 454 455 if ((ret = hvio_iommu_getbypass(DIP_TO_HANDLE(dip), ra, 456 attr, io_addr_p)) != H_EOK) { 457 DBG(DBG_LIB_DMA, dip, 458 "hvio_iommu_getbypass failed, ret 0x%lx\n", ret); 459 return (ret == H_ENOTSUPPORTED ? DDI_ENOTSUP : DDI_FAILURE); 460 } 461 462 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: io_addr 0x%llx\n", 463 *io_addr_p); 464 465 return (DDI_SUCCESS); 466 } 467 468 /*ARGSUSED*/ 469 int 470 px_lib_dma_sync(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 471 off_t off, size_t len, uint_t cache_flags) 472 { 473 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 474 uint64_t sync_dir; 475 px_dvma_addr_t dvma_addr, pg_off; 476 size_t num_sync; 477 uint64_t status = H_EOK; 478 479 DBG(DBG_LIB_DMA, dip, "px_lib_dma_sync: dip 0x%p rdip 0x%p " 480 "handle 0x%llx off 0x%x len 0x%x flags 0x%x\n", 481 dip, rdip, handle, off, len, cache_flags); 482 483 if (!(mp->dmai_flags & PX_DMAI_FLAGS_INUSE)) { 484 cmn_err(CE_WARN, "%s%d: Unbound dma handle %p.", 485 ddi_driver_name(rdip), ddi_get_instance(rdip), (void *)mp); 486 return (DDI_FAILURE); 487 } 488 489 if (mp->dmai_flags & PX_DMAI_FLAGS_NOSYNC) 490 return (DDI_SUCCESS); 491 492 if (!len) 493 len = mp->dmai_size; 494 495 pg_off = mp->dmai_offset; /* start min */ 496 dvma_addr = MAX(off, pg_off); /* lo */ 497 pg_off += mp->dmai_size; /* end max */ 498 pg_off = MIN(off + len, pg_off); /* hi */ 499 if (dvma_addr >= pg_off) { /* lo >= hi ? */ 500 cmn_err(CE_WARN, "%s%d: %lx + %lx out of window [%lx,%lx]", 501 ddi_driver_name(rdip), ddi_get_instance(rdip), 502 off, len, mp->dmai_offset, 503 mp->dmai_offset + mp->dmai_size); 504 return (DDI_FAILURE); 505 } 506 507 len = pg_off - dvma_addr; /* sz = hi - lo */ 508 dvma_addr += mp->dmai_mapping; /* start addr */ 509 510 if (mp->dmai_rflags & DDI_DMA_READ) 511 sync_dir = HVIO_DMA_SYNC_DIR_FROM_DEV; 512 else 513 sync_dir = HVIO_DMA_SYNC_DIR_TO_DEV; 514 515 for (; ((len > 0) && (status == H_EOK)); len -= num_sync) { 516 status = hvio_dma_sync(DIP_TO_HANDLE(dip), dvma_addr, len, 517 sync_dir, &num_sync); 518 dvma_addr += num_sync; 519 } 520 521 return ((status == H_EOK) ? DDI_SUCCESS : DDI_FAILURE); 522 } 523 524 525 /* 526 * MSIQ Functions: 527 */ 528 529 /*ARGSUSED*/ 530 int 531 px_lib_msiq_init(dev_info_t *dip) 532 { 533 px_t *px_p = DIP_TO_STATE(dip); 534 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 535 uint64_t *msiq_addr, ra; 536 size_t msiq_size; 537 uint_t rec_cnt; 538 int i, err = DDI_SUCCESS; 539 uint64_t ret; 540 541 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_init: dip 0x%p\n", dip); 542 543 msiq_addr = (uint64_t *)(((uint64_t)msiq_state_p->msiq_buf_p + 544 (MMU_PAGE_SIZE - 1)) >> MMU_PAGE_SHIFT << MMU_PAGE_SHIFT); 545 546 msiq_size = msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t); 547 548 for (i = 0; i < msiq_state_p->msiq_cnt; i++) { 549 ra = (r_addr_t)va_to_pa((caddr_t)msiq_addr + (i * msiq_size)); 550 551 if ((ret = hvio_msiq_conf(DIP_TO_HANDLE(dip), 552 (i + msiq_state_p->msiq_1st_msiq_id), 553 ra, msiq_state_p->msiq_rec_cnt)) != H_EOK) { 554 DBG(DBG_LIB_MSIQ, dip, 555 "hvio_msiq_conf failed, ret 0x%lx\n", ret); 556 err = DDI_FAILURE; 557 break; 558 } 559 560 if ((err = px_lib_msiq_info(dip, 561 (i + msiq_state_p->msiq_1st_msiq_id), 562 &ra, &rec_cnt)) != DDI_SUCCESS) { 563 DBG(DBG_LIB_MSIQ, dip, 564 "px_lib_msiq_info failed, ret 0x%x\n", err); 565 err = DDI_FAILURE; 566 break; 567 } 568 569 DBG(DBG_LIB_MSIQ, dip, 570 "px_lib_msiq_init: ra 0x%p rec_cnt 0x%x\n", ra, rec_cnt); 571 } 572 573 return (err); 574 } 575 576 /*ARGSUSED*/ 577 int 578 px_lib_msiq_fini(dev_info_t *dip) 579 { 580 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_fini: dip 0x%p\n", dip); 581 582 return (DDI_SUCCESS); 583 } 584 585 /*ARGSUSED*/ 586 int 587 px_lib_msiq_info(dev_info_t *dip, msiqid_t msiq_id, r_addr_t *ra_p, 588 uint_t *msiq_rec_cnt_p) 589 { 590 uint64_t ret; 591 592 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: dip 0x%p msiq_id 0x%x\n", 593 dip, msiq_id); 594 595 if ((ret = hvio_msiq_info(DIP_TO_HANDLE(dip), 596 msiq_id, ra_p, msiq_rec_cnt_p)) != H_EOK) { 597 DBG(DBG_LIB_MSIQ, dip, 598 "hvio_msiq_info failed, ret 0x%lx\n", ret); 599 return (DDI_FAILURE); 600 } 601 602 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: ra_p 0x%p msiq_rec_cnt 0x%x\n", 603 ra_p, *msiq_rec_cnt_p); 604 605 return (DDI_SUCCESS); 606 } 607 608 /*ARGSUSED*/ 609 int 610 px_lib_msiq_getvalid(dev_info_t *dip, msiqid_t msiq_id, 611 pci_msiq_valid_state_t *msiq_valid_state) 612 { 613 uint64_t ret; 614 615 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: dip 0x%p msiq_id 0x%x\n", 616 dip, msiq_id); 617 618 if ((ret = hvio_msiq_getvalid(DIP_TO_HANDLE(dip), 619 msiq_id, msiq_valid_state)) != H_EOK) { 620 DBG(DBG_LIB_MSIQ, dip, 621 "hvio_msiq_getvalid failed, ret 0x%lx\n", ret); 622 return (DDI_FAILURE); 623 } 624 625 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: msiq_valid_state 0x%x\n", 626 *msiq_valid_state); 627 628 return (DDI_SUCCESS); 629 } 630 631 /*ARGSUSED*/ 632 int 633 px_lib_msiq_setvalid(dev_info_t *dip, msiqid_t msiq_id, 634 pci_msiq_valid_state_t msiq_valid_state) 635 { 636 uint64_t ret; 637 638 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setvalid: dip 0x%p msiq_id 0x%x " 639 "msiq_valid_state 0x%x\n", dip, msiq_id, msiq_valid_state); 640 641 if ((ret = hvio_msiq_setvalid(DIP_TO_HANDLE(dip), 642 msiq_id, msiq_valid_state)) != H_EOK) { 643 DBG(DBG_LIB_MSIQ, dip, 644 "hvio_msiq_setvalid failed, ret 0x%lx\n", ret); 645 return (DDI_FAILURE); 646 } 647 648 return (DDI_SUCCESS); 649 } 650 651 /*ARGSUSED*/ 652 int 653 px_lib_msiq_getstate(dev_info_t *dip, msiqid_t msiq_id, 654 pci_msiq_state_t *msiq_state) 655 { 656 uint64_t ret; 657 658 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: dip 0x%p msiq_id 0x%x\n", 659 dip, msiq_id); 660 661 if ((ret = hvio_msiq_getstate(DIP_TO_HANDLE(dip), 662 msiq_id, msiq_state)) != H_EOK) { 663 DBG(DBG_LIB_MSIQ, dip, 664 "hvio_msiq_getstate failed, ret 0x%lx\n", ret); 665 return (DDI_FAILURE); 666 } 667 668 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: msiq_state 0x%x\n", 669 *msiq_state); 670 671 return (DDI_SUCCESS); 672 } 673 674 /*ARGSUSED*/ 675 int 676 px_lib_msiq_setstate(dev_info_t *dip, msiqid_t msiq_id, 677 pci_msiq_state_t msiq_state) 678 { 679 uint64_t ret; 680 681 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setstate: dip 0x%p msiq_id 0x%x " 682 "msiq_state 0x%x\n", dip, msiq_id, msiq_state); 683 684 if ((ret = hvio_msiq_setstate(DIP_TO_HANDLE(dip), 685 msiq_id, msiq_state)) != H_EOK) { 686 DBG(DBG_LIB_MSIQ, dip, 687 "hvio_msiq_setstate failed, ret 0x%lx\n", ret); 688 return (DDI_FAILURE); 689 } 690 691 return (DDI_SUCCESS); 692 } 693 694 /*ARGSUSED*/ 695 int 696 px_lib_msiq_gethead(dev_info_t *dip, msiqid_t msiq_id, 697 msiqhead_t *msiq_head_p) 698 { 699 uint64_t ret; 700 701 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gethead: dip 0x%p msiq_id 0x%x\n", 702 dip, msiq_id); 703 704 if ((ret = hvio_msiq_gethead(DIP_TO_HANDLE(dip), 705 msiq_id, msiq_head_p)) != H_EOK) { 706 DBG(DBG_LIB_MSIQ, dip, 707 "hvio_msiq_gethead failed, ret 0x%lx\n", ret); 708 return (DDI_FAILURE); 709 } 710 711 *msiq_head_p = (*msiq_head_p / sizeof (msiq_rec_t)); 712 713 DBG(DBG_LIB_MSIQ, dip, "px_msiq_gethead: msiq_head 0x%x\n", 714 *msiq_head_p); 715 716 return (DDI_SUCCESS); 717 } 718 719 /*ARGSUSED*/ 720 int 721 px_lib_msiq_sethead(dev_info_t *dip, msiqid_t msiq_id, 722 msiqhead_t msiq_head) 723 { 724 uint64_t ret; 725 726 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_sethead: dip 0x%p msiq_id 0x%x " 727 "msiq_head 0x%x\n", dip, msiq_id, msiq_head); 728 729 if ((ret = hvio_msiq_sethead(DIP_TO_HANDLE(dip), 730 msiq_id, msiq_head * sizeof (msiq_rec_t))) != H_EOK) { 731 DBG(DBG_LIB_MSIQ, dip, 732 "hvio_msiq_sethead failed, ret 0x%lx\n", ret); 733 return (DDI_FAILURE); 734 } 735 736 return (DDI_SUCCESS); 737 } 738 739 /*ARGSUSED*/ 740 int 741 px_lib_msiq_gettail(dev_info_t *dip, msiqid_t msiq_id, 742 msiqtail_t *msiq_tail_p) 743 { 744 uint64_t ret; 745 746 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: dip 0x%p msiq_id 0x%x\n", 747 dip, msiq_id); 748 749 if ((ret = hvio_msiq_gettail(DIP_TO_HANDLE(dip), 750 msiq_id, msiq_tail_p)) != H_EOK) { 751 DBG(DBG_LIB_MSIQ, dip, 752 "hvio_msiq_gettail failed, ret 0x%lx\n", ret); 753 return (DDI_FAILURE); 754 } 755 756 *msiq_tail_p = (*msiq_tail_p / sizeof (msiq_rec_t)); 757 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: msiq_tail 0x%x\n", 758 *msiq_tail_p); 759 760 return (DDI_SUCCESS); 761 } 762 763 /*ARGSUSED*/ 764 void 765 px_lib_get_msiq_rec(dev_info_t *dip, px_msiq_t *msiq_p, msiq_rec_t *msiq_rec_p) 766 { 767 msiq_rec_t *curr_msiq_rec_p = (msiq_rec_t *)msiq_p->msiq_curr; 768 769 DBG(DBG_LIB_MSIQ, dip, "px_lib_get_msiq_rec: dip 0x%p\n", dip); 770 771 if (!curr_msiq_rec_p->msiq_rec_type) 772 return; 773 774 *msiq_rec_p = *curr_msiq_rec_p; 775 776 /* Zero out msiq_rec_type field */ 777 curr_msiq_rec_p->msiq_rec_type = 0; 778 } 779 780 /* 781 * MSI Functions: 782 */ 783 784 /*ARGSUSED*/ 785 int 786 px_lib_msi_init(dev_info_t *dip) 787 { 788 DBG(DBG_LIB_MSI, dip, "px_lib_msi_init: dip 0x%p\n", dip); 789 790 /* Noop */ 791 return (DDI_SUCCESS); 792 } 793 794 /*ARGSUSED*/ 795 int 796 px_lib_msi_getmsiq(dev_info_t *dip, msinum_t msi_num, 797 msiqid_t *msiq_id) 798 { 799 uint64_t ret; 800 801 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: dip 0x%p msi_num 0x%x\n", 802 dip, msi_num); 803 804 if ((ret = hvio_msi_getmsiq(DIP_TO_HANDLE(dip), 805 msi_num, msiq_id)) != H_EOK) { 806 DBG(DBG_LIB_MSI, dip, 807 "hvio_msi_getmsiq failed, ret 0x%lx\n", ret); 808 return (DDI_FAILURE); 809 } 810 811 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: msiq_id 0x%x\n", 812 *msiq_id); 813 814 return (DDI_SUCCESS); 815 } 816 817 /*ARGSUSED*/ 818 int 819 px_lib_msi_setmsiq(dev_info_t *dip, msinum_t msi_num, 820 msiqid_t msiq_id, msi_type_t msitype) 821 { 822 uint64_t ret; 823 824 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setmsiq: dip 0x%p msi_num 0x%x " 825 "msq_id 0x%x\n", dip, msi_num, msiq_id); 826 827 if ((ret = hvio_msi_setmsiq(DIP_TO_HANDLE(dip), 828 msi_num, msiq_id, msitype)) != H_EOK) { 829 DBG(DBG_LIB_MSI, dip, 830 "hvio_msi_setmsiq failed, ret 0x%lx\n", ret); 831 return (DDI_FAILURE); 832 } 833 834 return (DDI_SUCCESS); 835 } 836 837 /*ARGSUSED*/ 838 int 839 px_lib_msi_getvalid(dev_info_t *dip, msinum_t msi_num, 840 pci_msi_valid_state_t *msi_valid_state) 841 { 842 uint64_t ret; 843 844 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: dip 0x%p msi_num 0x%x\n", 845 dip, msi_num); 846 847 if ((ret = hvio_msi_getvalid(DIP_TO_HANDLE(dip), 848 msi_num, msi_valid_state)) != H_EOK) { 849 DBG(DBG_LIB_MSI, dip, 850 "hvio_msi_getvalid failed, ret 0x%lx\n", ret); 851 return (DDI_FAILURE); 852 } 853 854 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: msiq_id 0x%x\n", 855 *msi_valid_state); 856 857 return (DDI_SUCCESS); 858 } 859 860 /*ARGSUSED*/ 861 int 862 px_lib_msi_setvalid(dev_info_t *dip, msinum_t msi_num, 863 pci_msi_valid_state_t msi_valid_state) 864 { 865 uint64_t ret; 866 867 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setvalid: dip 0x%p msi_num 0x%x " 868 "msi_valid_state 0x%x\n", dip, msi_num, msi_valid_state); 869 870 if ((ret = hvio_msi_setvalid(DIP_TO_HANDLE(dip), 871 msi_num, msi_valid_state)) != H_EOK) { 872 DBG(DBG_LIB_MSI, dip, 873 "hvio_msi_setvalid failed, ret 0x%lx\n", ret); 874 return (DDI_FAILURE); 875 } 876 877 return (DDI_SUCCESS); 878 } 879 880 /*ARGSUSED*/ 881 int 882 px_lib_msi_getstate(dev_info_t *dip, msinum_t msi_num, 883 pci_msi_state_t *msi_state) 884 { 885 uint64_t ret; 886 887 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: dip 0x%p msi_num 0x%x\n", 888 dip, msi_num); 889 890 if ((ret = hvio_msi_getstate(DIP_TO_HANDLE(dip), 891 msi_num, msi_state)) != H_EOK) { 892 DBG(DBG_LIB_MSI, dip, 893 "hvio_msi_getstate failed, ret 0x%lx\n", ret); 894 return (DDI_FAILURE); 895 } 896 897 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: msi_state 0x%x\n", 898 *msi_state); 899 900 return (DDI_SUCCESS); 901 } 902 903 /*ARGSUSED*/ 904 int 905 px_lib_msi_setstate(dev_info_t *dip, msinum_t msi_num, 906 pci_msi_state_t msi_state) 907 { 908 uint64_t ret; 909 910 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setstate: dip 0x%p msi_num 0x%x " 911 "msi_state 0x%x\n", dip, msi_num, msi_state); 912 913 if ((ret = hvio_msi_setstate(DIP_TO_HANDLE(dip), 914 msi_num, msi_state)) != H_EOK) { 915 DBG(DBG_LIB_MSI, dip, 916 "hvio_msi_setstate failed, ret 0x%lx\n", ret); 917 return (DDI_FAILURE); 918 } 919 920 return (DDI_SUCCESS); 921 } 922 923 /* 924 * MSG Functions: 925 */ 926 927 /*ARGSUSED*/ 928 int 929 px_lib_msg_getmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 930 msiqid_t *msiq_id) 931 { 932 uint64_t ret; 933 934 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getmsiq: dip 0x%p msg_type 0x%x\n", 935 dip, msg_type); 936 937 if ((ret = hvio_msg_getmsiq(DIP_TO_HANDLE(dip), 938 msg_type, msiq_id)) != H_EOK) { 939 DBG(DBG_LIB_MSG, dip, 940 "hvio_msg_getmsiq failed, ret 0x%lx\n", ret); 941 return (DDI_FAILURE); 942 } 943 944 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getmsiq: msiq_id 0x%x\n", 945 *msiq_id); 946 947 return (DDI_SUCCESS); 948 } 949 950 /*ARGSUSED*/ 951 int 952 px_lib_msg_setmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 953 msiqid_t msiq_id) 954 { 955 uint64_t ret; 956 957 DBG(DBG_LIB_MSG, dip, "px_lib_msg_setmsiq: dip 0x%p msg_type 0x%x " 958 "msq_id 0x%x\n", dip, msg_type, msiq_id); 959 960 if ((ret = hvio_msg_setmsiq(DIP_TO_HANDLE(dip), 961 msg_type, msiq_id)) != H_EOK) { 962 DBG(DBG_LIB_MSG, dip, 963 "hvio_msg_setmsiq failed, ret 0x%lx\n", ret); 964 return (DDI_FAILURE); 965 } 966 967 return (DDI_SUCCESS); 968 } 969 970 /*ARGSUSED*/ 971 int 972 px_lib_msg_getvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 973 pcie_msg_valid_state_t *msg_valid_state) 974 { 975 uint64_t ret; 976 977 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getvalid: dip 0x%p msg_type 0x%x\n", 978 dip, msg_type); 979 980 if ((ret = hvio_msg_getvalid(DIP_TO_HANDLE(dip), msg_type, 981 msg_valid_state)) != H_EOK) { 982 DBG(DBG_LIB_MSG, dip, 983 "hvio_msg_getvalid failed, ret 0x%lx\n", ret); 984 return (DDI_FAILURE); 985 } 986 987 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getvalid: msg_valid_state 0x%x\n", 988 *msg_valid_state); 989 990 return (DDI_SUCCESS); 991 } 992 993 /*ARGSUSED*/ 994 int 995 px_lib_msg_setvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 996 pcie_msg_valid_state_t msg_valid_state) 997 { 998 uint64_t ret; 999 1000 DBG(DBG_LIB_MSG, dip, "px_lib_msg_setvalid: dip 0x%p msg_type 0x%x " 1001 "msg_valid_state 0x%x\n", dip, msg_type, msg_valid_state); 1002 1003 if ((ret = hvio_msg_setvalid(DIP_TO_HANDLE(dip), msg_type, 1004 msg_valid_state)) != H_EOK) { 1005 DBG(DBG_LIB_MSG, dip, 1006 "hvio_msg_setvalid failed, ret 0x%lx\n", ret); 1007 return (DDI_FAILURE); 1008 } 1009 1010 return (DDI_SUCCESS); 1011 } 1012 1013 /* 1014 * Suspend/Resume Functions: 1015 * Currently unsupported by hypervisor and all functions are noops. 1016 */ 1017 /*ARGSUSED*/ 1018 int 1019 px_lib_suspend(dev_info_t *dip) 1020 { 1021 DBG(DBG_ATTACH, dip, "px_lib_suspend: Not supported\n"); 1022 1023 /* Not supported */ 1024 return (DDI_FAILURE); 1025 } 1026 1027 /*ARGSUSED*/ 1028 void 1029 px_lib_resume(dev_info_t *dip) 1030 { 1031 DBG(DBG_ATTACH, dip, "px_lib_resume: Not supported\n"); 1032 1033 /* Noop */ 1034 } 1035 1036 /* 1037 * Misc Functions: 1038 * Currently unsupported by hypervisor and all functions are noops. 1039 */ 1040 /*ARGSUSED*/ 1041 uint64_t 1042 px_lib_get_cb(dev_info_t *dip) 1043 { 1044 return (DDI_SUCCESS); 1045 } 1046 1047 /*ARGSUSED*/ 1048 void 1049 px_lib_set_cb(dev_info_t *dip, uint64_t val) 1050 { 1051 /* Noop */ 1052 } 1053 1054 /*ARGSUSED*/ 1055 static int 1056 px_lib_config_get(dev_info_t *dip, pci_device_t bdf, pci_config_offset_t off, 1057 uint8_t size, pci_cfg_data_t *data_p) 1058 { 1059 uint64_t ret; 1060 1061 DBG(DBG_LIB_CFG, dip, "px_lib_config_get: dip 0x%p, bdf 0x%llx " 1062 "off 0x%x size 0x%x\n", dip, bdf, off, size); 1063 1064 if ((ret = hvio_config_get(DIP_TO_HANDLE(dip), bdf, off, 1065 size, data_p)) != H_EOK) { 1066 DBG(DBG_LIB_CFG, dip, 1067 "hvio_config_get failed, ret 0x%lx\n", ret); 1068 return (DDI_FAILURE); 1069 } 1070 DBG(DBG_LIB_CFG, dip, "px_config_get: data 0x%x\n", data_p->dw); 1071 1072 return (DDI_SUCCESS); 1073 } 1074 1075 /*ARGSUSED*/ 1076 static int 1077 px_lib_config_put(dev_info_t *dip, pci_device_t bdf, pci_config_offset_t off, 1078 uint8_t size, pci_cfg_data_t data) 1079 { 1080 uint64_t ret; 1081 1082 DBG(DBG_LIB_CFG, dip, "px_lib_config_put: dip 0x%p, bdf 0x%llx " 1083 "off 0x%x size 0x%x data 0x%llx\n", dip, bdf, off, size, data.qw); 1084 1085 if ((ret = hvio_config_put(DIP_TO_HANDLE(dip), bdf, off, 1086 size, data)) != H_EOK) { 1087 DBG(DBG_LIB_CFG, dip, 1088 "hvio_config_put failed, ret 0x%lx\n", ret); 1089 return (DDI_FAILURE); 1090 } 1091 1092 return (DDI_SUCCESS); 1093 } 1094 1095 static uint32_t 1096 px_pci_config_get(ddi_acc_impl_t *handle, uint32_t *addr, int size) 1097 { 1098 px_config_acc_pvt_t *px_pvt = (px_config_acc_pvt_t *) 1099 handle->ahi_common.ah_bus_private; 1100 uint32_t pci_dev_addr = px_pvt->raddr; 1101 uint32_t vaddr = px_pvt->vaddr; 1102 uint16_t off = (uint16_t)(uintptr_t)(addr - vaddr) & 0xfff; 1103 uint32_t rdata = 0; 1104 1105 if (px_lib_config_get(px_pvt->dip, pci_dev_addr, off, 1106 size, (pci_cfg_data_t *)&rdata) != DDI_SUCCESS) 1107 /* XXX update error kstats */ 1108 return (0xffffffff); 1109 return (rdata); 1110 } 1111 1112 static void 1113 px_pci_config_put(ddi_acc_impl_t *handle, uint32_t *addr, 1114 int size, pci_cfg_data_t wdata) 1115 { 1116 px_config_acc_pvt_t *px_pvt = (px_config_acc_pvt_t *) 1117 handle->ahi_common.ah_bus_private; 1118 uint32_t pci_dev_addr = px_pvt->raddr; 1119 uint32_t vaddr = px_pvt->vaddr; 1120 uint16_t off = (uint16_t)(uintptr_t)(addr - vaddr) & 0xfff; 1121 1122 if (px_lib_config_put(px_pvt->dip, pci_dev_addr, off, 1123 size, wdata) != DDI_SUCCESS) { 1124 /*EMPTY*/ 1125 /* XXX update error kstats */ 1126 } 1127 } 1128 1129 static uint8_t 1130 px_pci_config_get8(ddi_acc_impl_t *handle, uint8_t *addr) 1131 { 1132 return ((uint8_t)px_pci_config_get(handle, (uint32_t *)addr, 1)); 1133 } 1134 1135 static uint16_t 1136 px_pci_config_get16(ddi_acc_impl_t *handle, uint16_t *addr) 1137 { 1138 return ((uint16_t)px_pci_config_get(handle, (uint32_t *)addr, 2)); 1139 } 1140 1141 static uint32_t 1142 px_pci_config_get32(ddi_acc_impl_t *handle, uint32_t *addr) 1143 { 1144 return ((uint32_t)px_pci_config_get(handle, (uint32_t *)addr, 4)); 1145 } 1146 1147 static uint64_t 1148 px_pci_config_get64(ddi_acc_impl_t *handle, uint64_t *addr) 1149 { 1150 uint32_t rdatah, rdatal; 1151 1152 rdatal = (uint32_t)px_pci_config_get(handle, (uint32_t *)addr, 4); 1153 rdatah = (uint32_t)px_pci_config_get(handle, 1154 (uint32_t *)((char *)addr+4), 4); 1155 return (((uint64_t)rdatah << 32) | rdatal); 1156 } 1157 1158 static void 1159 px_pci_config_put8(ddi_acc_impl_t *handle, uint8_t *addr, uint8_t data) 1160 { 1161 pci_cfg_data_t wdata = { 0 }; 1162 1163 wdata.qw = (uint8_t)data; 1164 px_pci_config_put(handle, (uint32_t *)addr, 1, wdata); 1165 } 1166 1167 static void 1168 px_pci_config_put16(ddi_acc_impl_t *handle, uint16_t *addr, uint16_t data) 1169 { 1170 pci_cfg_data_t wdata = { 0 }; 1171 1172 wdata.qw = (uint16_t)data; 1173 px_pci_config_put(handle, (uint32_t *)addr, 2, wdata); 1174 } 1175 1176 static void 1177 px_pci_config_put32(ddi_acc_impl_t *handle, uint32_t *addr, uint32_t data) 1178 { 1179 pci_cfg_data_t wdata = { 0 }; 1180 1181 wdata.qw = (uint32_t)data; 1182 px_pci_config_put(handle, (uint32_t *)addr, 4, wdata); 1183 } 1184 1185 static void 1186 px_pci_config_put64(ddi_acc_impl_t *handle, uint64_t *addr, uint64_t data) 1187 { 1188 pci_cfg_data_t wdata = { 0 }; 1189 1190 wdata.qw = (uint32_t)(data & 0xffffffff); 1191 px_pci_config_put(handle, (uint32_t *)addr, 4, wdata); 1192 wdata.qw = (uint32_t)((data >> 32) & 0xffffffff); 1193 px_pci_config_put(handle, (uint32_t *)((char *)addr+4), 4, wdata); 1194 } 1195 1196 static void 1197 px_pci_config_rep_get8(ddi_acc_impl_t *handle, uint8_t *host_addr, 1198 uint8_t *dev_addr, size_t repcount, uint_t flags) 1199 { 1200 if (flags == DDI_DEV_AUTOINCR) 1201 for (; repcount; repcount--) 1202 *host_addr++ = px_pci_config_get8(handle, dev_addr++); 1203 else 1204 for (; repcount; repcount--) 1205 *host_addr++ = px_pci_config_get8(handle, dev_addr); 1206 } 1207 1208 /* 1209 * Function to rep read 16 bit data off the PCI configuration space behind 1210 * the 21554's host interface. 1211 */ 1212 static void 1213 px_pci_config_rep_get16(ddi_acc_impl_t *handle, uint16_t *host_addr, 1214 uint16_t *dev_addr, size_t repcount, uint_t flags) 1215 { 1216 if (flags == DDI_DEV_AUTOINCR) 1217 for (; repcount; repcount--) 1218 *host_addr++ = px_pci_config_get16(handle, dev_addr++); 1219 else 1220 for (; repcount; repcount--) 1221 *host_addr++ = px_pci_config_get16(handle, dev_addr); 1222 } 1223 1224 /* 1225 * Function to rep read 32 bit data off the PCI configuration space behind 1226 * the 21554's host interface. 1227 */ 1228 static void 1229 px_pci_config_rep_get32(ddi_acc_impl_t *handle, uint32_t *host_addr, 1230 uint32_t *dev_addr, size_t repcount, uint_t flags) 1231 { 1232 if (flags == DDI_DEV_AUTOINCR) 1233 for (; repcount; repcount--) 1234 *host_addr++ = px_pci_config_get32(handle, dev_addr++); 1235 else 1236 for (; repcount; repcount--) 1237 *host_addr++ = px_pci_config_get32(handle, dev_addr); 1238 } 1239 1240 /* 1241 * Function to rep read 64 bit data off the PCI configuration space behind 1242 * the 21554's host interface. 1243 */ 1244 static void 1245 px_pci_config_rep_get64(ddi_acc_impl_t *handle, uint64_t *host_addr, 1246 uint64_t *dev_addr, size_t repcount, uint_t flags) 1247 { 1248 if (flags == DDI_DEV_AUTOINCR) 1249 for (; repcount; repcount--) 1250 *host_addr++ = px_pci_config_get64(handle, dev_addr++); 1251 else 1252 for (; repcount; repcount--) 1253 *host_addr++ = px_pci_config_get64(handle, dev_addr); 1254 } 1255 1256 /* 1257 * Function to rep write 8 bit data into the PCI configuration space behind 1258 * the 21554's host interface. 1259 */ 1260 static void 1261 px_pci_config_rep_put8(ddi_acc_impl_t *handle, uint8_t *host_addr, 1262 uint8_t *dev_addr, size_t repcount, uint_t flags) 1263 { 1264 if (flags == DDI_DEV_AUTOINCR) 1265 for (; repcount; repcount--) 1266 px_pci_config_put8(handle, dev_addr++, *host_addr++); 1267 else 1268 for (; repcount; repcount--) 1269 px_pci_config_put8(handle, dev_addr, *host_addr++); 1270 } 1271 1272 /* 1273 * Function to rep write 16 bit data into the PCI configuration space behind 1274 * the 21554's host interface. 1275 */ 1276 static void 1277 px_pci_config_rep_put16(ddi_acc_impl_t *handle, uint16_t *host_addr, 1278 uint16_t *dev_addr, size_t repcount, uint_t flags) 1279 { 1280 if (flags == DDI_DEV_AUTOINCR) 1281 for (; repcount; repcount--) 1282 px_pci_config_put16(handle, dev_addr++, *host_addr++); 1283 else 1284 for (; repcount; repcount--) 1285 px_pci_config_put16(handle, dev_addr, *host_addr++); 1286 } 1287 1288 /* 1289 * Function to rep write 32 bit data into the PCI configuration space behind 1290 * the 21554's host interface. 1291 */ 1292 static void 1293 px_pci_config_rep_put32(ddi_acc_impl_t *handle, uint32_t *host_addr, 1294 uint32_t *dev_addr, size_t repcount, uint_t flags) 1295 { 1296 if (flags == DDI_DEV_AUTOINCR) 1297 for (; repcount; repcount--) 1298 px_pci_config_put32(handle, dev_addr++, *host_addr++); 1299 else 1300 for (; repcount; repcount--) 1301 px_pci_config_put32(handle, dev_addr, *host_addr++); 1302 } 1303 1304 /* 1305 * Function to rep write 64 bit data into the PCI configuration space behind 1306 * the 21554's host interface. 1307 */ 1308 static void 1309 px_pci_config_rep_put64(ddi_acc_impl_t *handle, uint64_t *host_addr, 1310 uint64_t *dev_addr, size_t repcount, uint_t flags) 1311 { 1312 if (flags == DDI_DEV_AUTOINCR) 1313 for (; repcount; repcount--) 1314 px_pci_config_put64(handle, dev_addr++, *host_addr++); 1315 else 1316 for (; repcount; repcount--) 1317 px_pci_config_put64(handle, dev_addr, *host_addr++); 1318 } 1319 1320 /* 1321 * Provide a private access handle to route config access calls to Hypervisor. 1322 * Beware: Do all error checking for config space accesses before calling 1323 * this function. ie. do error checking from the calling function. 1324 * Due to a lack of meaningful error code in DDI, the gauranteed return of 1325 * DDI_SUCCESS from here makes the code organization readable/easier from 1326 * the generic code. 1327 */ 1328 /*ARGSUSED*/ 1329 int 1330 px_lib_map_vconfig(dev_info_t *dip, 1331 ddi_map_req_t *mp, pci_config_offset_t off, 1332 pci_regspec_t *rp, caddr_t *addrp) 1333 { 1334 ddi_acc_hdl_t *hp; 1335 ddi_acc_impl_t *ap; 1336 uchar_t busnum; /* bus number */ 1337 uchar_t devnum; /* device number */ 1338 uchar_t funcnum; /* function number */ 1339 px_config_acc_pvt_t *px_pvt; 1340 1341 hp = (ddi_acc_hdl_t *)mp->map_handlep; 1342 ap = (ddi_acc_impl_t *)hp->ah_platform_private; 1343 1344 /* Check for mapping teardown operation */ 1345 if ((mp->map_op == DDI_MO_UNMAP) || 1346 (mp->map_op == DDI_MO_UNLOCK)) { 1347 /* free up memory allocated for the private access handle. */ 1348 px_pvt = (px_config_acc_pvt_t *)hp->ah_bus_private; 1349 kmem_free((void *)px_pvt, sizeof (px_config_acc_pvt_t)); 1350 1351 /* unmap operation of PCI IO/config space. */ 1352 return (DDI_SUCCESS); 1353 } 1354 1355 ap->ahi_get8 = px_pci_config_get8; 1356 ap->ahi_get16 = px_pci_config_get16; 1357 ap->ahi_get32 = px_pci_config_get32; 1358 ap->ahi_get64 = px_pci_config_get64; 1359 ap->ahi_put8 = px_pci_config_put8; 1360 ap->ahi_put16 = px_pci_config_put16; 1361 ap->ahi_put32 = px_pci_config_put32; 1362 ap->ahi_put64 = px_pci_config_put64; 1363 ap->ahi_rep_get8 = px_pci_config_rep_get8; 1364 ap->ahi_rep_get16 = px_pci_config_rep_get16; 1365 ap->ahi_rep_get32 = px_pci_config_rep_get32; 1366 ap->ahi_rep_get64 = px_pci_config_rep_get64; 1367 ap->ahi_rep_put8 = px_pci_config_rep_put8; 1368 ap->ahi_rep_put16 = px_pci_config_rep_put16; 1369 ap->ahi_rep_put32 = px_pci_config_rep_put32; 1370 ap->ahi_rep_put64 = px_pci_config_rep_put64; 1371 1372 /* Initialize to default check/notify functions */ 1373 ap->ahi_fault = 0; 1374 ap->ahi_fault_check = i_ddi_acc_fault_check; 1375 ap->ahi_fault_notify = i_ddi_acc_fault_notify; 1376 1377 /* allocate memory for our private handle */ 1378 px_pvt = (px_config_acc_pvt_t *) 1379 kmem_zalloc(sizeof (px_config_acc_pvt_t), KM_SLEEP); 1380 hp->ah_bus_private = (void *)px_pvt; 1381 1382 busnum = PCI_REG_BUS_G(rp->pci_phys_hi); 1383 devnum = PCI_REG_DEV_G(rp->pci_phys_hi); 1384 funcnum = PCI_REG_FUNC_G(rp->pci_phys_hi); 1385 1386 /* set up private data for use during IO routines */ 1387 1388 /* addr needed by the HV APIs */ 1389 px_pvt->raddr = busnum << 16 | devnum << 11 | funcnum << 8; 1390 /* 1391 * Address that specifies the actual offset into the 256MB 1392 * memory mapped configuration space, 4K per device. 1393 * First 12bits form the offset into 4K config space. 1394 * This address is only used during the IO routines to calculate 1395 * the offset at which the transaction must be performed. 1396 * Drivers bypassing DDI functions to access PCI config space will 1397 * panic the system since the following is a bogus virtual address. 1398 */ 1399 px_pvt->vaddr = busnum << 20 | devnum << 15 | funcnum << 12 | off; 1400 px_pvt->dip = dip; 1401 1402 DBG(DBG_LIB_CFG, dip, "px_config_setup: raddr 0x%x, vaddr 0x%x\n", 1403 px_pvt->raddr, px_pvt->vaddr); 1404 *addrp = (caddr_t)(uintptr_t)px_pvt->vaddr; 1405 return (DDI_SUCCESS); 1406 } 1407 1408 /*ARGSUSED*/ 1409 void 1410 px_lib_map_attr_check(ddi_map_req_t *mp) 1411 { 1412 } 1413 1414 /* 1415 * px_lib_log_safeacc_err: 1416 * Imitate a cpu/mem trap call when a peek/poke fails. 1417 * This will initiate something similar to px_fm_callback. 1418 */ 1419 static void 1420 px_lib_log_safeacc_err(px_t *px_p, ddi_acc_handle_t handle, int fme_flag) 1421 { 1422 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)handle; 1423 px_cb_t *cb_p = px_p->px_cb_p; 1424 ddi_fm_error_t derr; 1425 1426 derr.fme_status = DDI_FM_NONFATAL; 1427 derr.fme_version = DDI_FME_VERSION; 1428 derr.fme_flag = fme_flag; 1429 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 1430 derr.fme_acc_handle = handle; 1431 if (hp) 1432 hp->ahi_err->err_expected = DDI_FM_ERR_EXPECTED; 1433 1434 mutex_enter(&cb_p->xbc_fm_mutex); 1435 1436 (void) ndi_fm_handler_dispatch(px_p->px_dip, NULL, &derr); 1437 1438 mutex_exit(&cb_p->xbc_fm_mutex); 1439 } 1440 1441 1442 #ifdef DEBUG 1443 int px_peekfault_cnt = 0; 1444 int px_pokefault_cnt = 0; 1445 #endif /* DEBUG */ 1446 1447 static int 1448 px_lib_bdf_from_dip(dev_info_t *rdip, uint32_t *bdf) 1449 { 1450 /* Start with an array of 8 reg spaces for now to cover most devices. */ 1451 pci_regspec_t regspec_array[8]; 1452 pci_regspec_t *regspec = regspec_array; 1453 int buflen = sizeof (regspec_array); 1454 boolean_t kmalloced = B_FALSE; 1455 int status; 1456 1457 status = ddi_getlongprop_buf(DDI_DEV_T_ANY, rdip, 1458 DDI_PROP_DONTPASS, "reg", (caddr_t)regspec, &buflen); 1459 1460 /* If need more space, fallback to kmem_alloc. */ 1461 if (status == DDI_PROP_BUF_TOO_SMALL) { 1462 regspec = kmem_alloc(buflen, KM_SLEEP); 1463 1464 status = ddi_getlongprop_buf(DDI_DEV_T_ANY, rdip, 1465 DDI_PROP_DONTPASS, "reg", (caddr_t)regspec, &buflen); 1466 1467 kmalloced = B_TRUE; 1468 } 1469 1470 /* Get phys_hi from first element. All have same bdf. */ 1471 if (status == DDI_PROP_SUCCESS) 1472 *bdf = regspec->pci_phys_hi & (PCI_REG_BDFR_M ^ PCI_REG_REG_M); 1473 1474 if (kmalloced) 1475 kmem_free(regspec, buflen); 1476 1477 return ((status == DDI_PROP_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE); 1478 } 1479 1480 /* 1481 * Do a safe write to a device. 1482 * 1483 * When this function is given a handle (cautious access), all errors are 1484 * suppressed. 1485 * 1486 * When this function is not given a handle (poke), only Unsupported Request 1487 * and Completer Abort errors are suppressed. 1488 * 1489 * In all cases, all errors are returned in the function return status. 1490 */ 1491 1492 int 1493 px_lib_ctlops_poke(dev_info_t *dip, dev_info_t *rdip, 1494 peekpoke_ctlops_t *in_args) 1495 { 1496 px_t *px_p = DIP_TO_STATE(dip); 1497 px_pec_t *pec_p = px_p->px_pec_p; 1498 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)in_args->handle; 1499 1500 size_t repcount = in_args->repcount; 1501 size_t size = in_args->size; 1502 uintptr_t dev_addr = in_args->dev_addr; 1503 uintptr_t host_addr = in_args->host_addr; 1504 1505 int err = DDI_SUCCESS; 1506 uint64_t hvio_poke_status; 1507 uint32_t bdf; 1508 uint32_t wrt_stat; 1509 1510 r_addr_t ra; 1511 uint64_t pokeval; 1512 1513 /* 1514 * Used only to notify error handling peek/poke is occuring 1515 * One scenario is when a fabric err as a result of peek/poke. 1516 * However there is no way to guarantee that the fabric error 1517 * handler will occur in the window where otd is set. 1518 */ 1519 on_trap_data_t otd; 1520 1521 if (px_lib_bdf_from_dip(rdip, &bdf) != DDI_SUCCESS) { 1522 DBG(DBG_LIB_DMA, px_p->px_dip, 1523 "poke: px_lib_bdf_from_dip failed\n"); 1524 err = DDI_FAILURE; 1525 goto done; 1526 } 1527 1528 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1529 for (; repcount; repcount--) { 1530 1531 switch (size) { 1532 case sizeof (uint8_t): 1533 pokeval = *(uint8_t *)host_addr; 1534 break; 1535 case sizeof (uint16_t): 1536 pokeval = *(uint16_t *)host_addr; 1537 break; 1538 case sizeof (uint32_t): 1539 pokeval = *(uint32_t *)host_addr; 1540 break; 1541 case sizeof (uint64_t): 1542 pokeval = *(uint64_t *)host_addr; 1543 break; 1544 default: 1545 DBG(DBG_MAP, px_p->px_dip, 1546 "poke: invalid size %d passed\n", size); 1547 err = DDI_FAILURE; 1548 goto done; 1549 } 1550 1551 /* 1552 * Grab pokefault mutex since hypervisor does not guarantee 1553 * poke serialization. 1554 */ 1555 if (hp) { 1556 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, 1557 (ddi_acc_handle_t)hp); 1558 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1559 } else { 1560 mutex_enter(&pec_p->pec_pokefault_mutex); 1561 pec_p->pec_safeacc_type = DDI_FM_ERR_POKE; 1562 } 1563 pec_p->pec_ontrap_data = &otd; 1564 1565 hvio_poke_status = hvio_poke(px_p->px_dev_hdl, ra, size, 1566 pokeval, bdf, &wrt_stat); 1567 1568 if (otd.ot_trap & OT_DATA_ACCESS) 1569 err = DDI_FAILURE; 1570 1571 if ((hvio_poke_status != H_EOK) || (wrt_stat != H_EOK)) { 1572 err = DDI_FAILURE; 1573 #ifdef DEBUG 1574 px_pokefault_cnt++; 1575 #endif 1576 /* 1577 * For CAUTIOUS and POKE access, notify FMA to 1578 * cleanup. Imitate a cpu/mem trap call like in sun4u. 1579 */ 1580 px_lib_log_safeacc_err(px_p, (ddi_acc_handle_t)hp, 1581 (hp ? DDI_FM_ERR_EXPECTED : 1582 DDI_FM_ERR_POKE)); 1583 1584 pec_p->pec_ontrap_data = NULL; 1585 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1586 if (hp) { 1587 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1588 (ddi_acc_handle_t)hp); 1589 } else { 1590 mutex_exit(&pec_p->pec_pokefault_mutex); 1591 } 1592 goto done; 1593 } 1594 1595 pec_p->pec_ontrap_data = NULL; 1596 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1597 if (hp) { 1598 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1599 (ddi_acc_handle_t)hp); 1600 } else { 1601 mutex_exit(&pec_p->pec_pokefault_mutex); 1602 } 1603 1604 host_addr += size; 1605 1606 if (in_args->flags == DDI_DEV_AUTOINCR) { 1607 dev_addr += size; 1608 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1609 } 1610 } 1611 1612 done: 1613 return (err); 1614 } 1615 1616 1617 /*ARGSUSED*/ 1618 int 1619 px_lib_ctlops_peek(dev_info_t *dip, dev_info_t *rdip, 1620 peekpoke_ctlops_t *in_args, void *result) 1621 { 1622 px_t *px_p = DIP_TO_STATE(dip); 1623 px_pec_t *pec_p = px_p->px_pec_p; 1624 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)in_args->handle; 1625 1626 size_t repcount = in_args->repcount; 1627 uintptr_t dev_addr = in_args->dev_addr; 1628 uintptr_t host_addr = in_args->host_addr; 1629 1630 r_addr_t ra; 1631 uint32_t read_status; 1632 uint64_t hvio_peek_status; 1633 uint64_t peekval; 1634 int err = DDI_SUCCESS; 1635 1636 /* 1637 * Used only to notify error handling peek/poke is occuring 1638 * One scenario is when a fabric err as a result of peek/poke. 1639 * However there is no way to guarantee that the fabric error 1640 * handler will occur in the window where otd is set. 1641 */ 1642 on_trap_data_t otd; 1643 1644 result = (void *)in_args->host_addr; 1645 1646 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1647 for (; repcount; repcount--) { 1648 1649 /* Lock pokefault mutex so read doesn't mask a poke fault. */ 1650 if (hp) { 1651 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, 1652 (ddi_acc_handle_t)hp); 1653 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1654 } else { 1655 mutex_enter(&pec_p->pec_pokefault_mutex); 1656 pec_p->pec_safeacc_type = DDI_FM_ERR_PEEK; 1657 } 1658 pec_p->pec_ontrap_data = &otd; 1659 1660 hvio_peek_status = hvio_peek(px_p->px_dev_hdl, ra, 1661 in_args->size, &read_status, &peekval); 1662 1663 if ((hvio_peek_status != H_EOK) || (read_status != H_EOK)) { 1664 err = DDI_FAILURE; 1665 1666 /* 1667 * For CAUTIOUS and PEEK access, notify FMA to 1668 * cleanup. Imitate a cpu/mem trap call like in sun4u. 1669 */ 1670 px_lib_log_safeacc_err(px_p, (ddi_acc_handle_t)hp, 1671 (hp ? DDI_FM_ERR_EXPECTED : 1672 DDI_FM_ERR_PEEK)); 1673 1674 /* Stuff FFs in host addr if peek. */ 1675 if (hp == NULL) { 1676 int i; 1677 uint8_t *ff_addr = (uint8_t *)host_addr; 1678 for (i = 0; i < in_args->size; i++) 1679 *ff_addr++ = 0xff; 1680 } 1681 #ifdef DEBUG 1682 px_peekfault_cnt++; 1683 #endif 1684 pec_p->pec_ontrap_data = NULL; 1685 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1686 if (hp) { 1687 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1688 (ddi_acc_handle_t)hp); 1689 } else { 1690 mutex_exit(&pec_p->pec_pokefault_mutex); 1691 } 1692 goto done; 1693 1694 } 1695 pec_p->pec_ontrap_data = NULL; 1696 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1697 if (hp) { 1698 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1699 (ddi_acc_handle_t)hp); 1700 } else { 1701 mutex_exit(&pec_p->pec_pokefault_mutex); 1702 } 1703 1704 switch (in_args->size) { 1705 case sizeof (uint8_t): 1706 *(uint8_t *)host_addr = (uint8_t)peekval; 1707 break; 1708 case sizeof (uint16_t): 1709 *(uint16_t *)host_addr = (uint16_t)peekval; 1710 break; 1711 case sizeof (uint32_t): 1712 *(uint32_t *)host_addr = (uint32_t)peekval; 1713 break; 1714 case sizeof (uint64_t): 1715 *(uint64_t *)host_addr = (uint64_t)peekval; 1716 break; 1717 default: 1718 DBG(DBG_MAP, px_p->px_dip, 1719 "peek: invalid size %d passed\n", 1720 in_args->size); 1721 err = DDI_FAILURE; 1722 goto done; 1723 } 1724 1725 host_addr += in_args->size; 1726 1727 if (in_args->flags == DDI_DEV_AUTOINCR) { 1728 dev_addr += in_args->size; 1729 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1730 } 1731 } 1732 done: 1733 return (err); 1734 } 1735 1736 1737 /* add interrupt vector */ 1738 int 1739 px_err_add_intr(px_fault_t *px_fault_p) 1740 { 1741 int ret; 1742 px_t *px_p = DIP_TO_STATE(px_fault_p->px_fh_dip); 1743 1744 DBG(DBG_LIB_INT, px_p->px_dip, 1745 "px_err_add_intr: calling add_ivintr"); 1746 ret = add_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL, 1747 px_fault_p->px_err_func, (caddr_t)px_fault_p, 1748 (caddr_t)&px_fault_p->px_intr_payload[0]); 1749 1750 if (ret != DDI_SUCCESS) { 1751 DBG(DBG_LIB_INT, px_p->px_dip, 1752 "add_ivintr returns %d, faultp: %p", ret, px_fault_p); 1753 1754 return (ret); 1755 } 1756 DBG(DBG_LIB_INT, px_p->px_dip, 1757 "px_err_add_intr: ib_intr_enable "); 1758 1759 px_ib_intr_enable(px_p, intr_dist_cpuid(), px_fault_p->px_intr_ino); 1760 1761 return (ret); 1762 } 1763 1764 1765 /* remove interrupt vector */ 1766 void 1767 px_err_rem_intr(px_fault_t *px_fault_p) 1768 { 1769 px_t *px_p = DIP_TO_STATE(px_fault_p->px_fh_dip); 1770 1771 px_ib_intr_disable(px_p->px_ib_p, px_fault_p->px_intr_ino, 1772 IB_INTR_WAIT); 1773 1774 rem_ivintr(px_fault_p->px_fh_sysino, NULL); 1775 } 1776 1777 1778 #ifdef FMA 1779 void 1780 px_fill_rc_status(px_fault_t *px_fault_p, pciex_rc_error_regs_t *rc_status) 1781 { 1782 px_pec_err_t *err_pkt; 1783 1784 err_pkt = (px_pec_err_t *)px_fault_p->px_intr_payload; 1785 1786 /* initialise all the structure members */ 1787 rc_status->status_valid = 0; 1788 1789 if (err_pkt->pec_descr.P) { 1790 /* PCI Status Register */ 1791 rc_status->pci_err_status = err_pkt->pci_err_status; 1792 rc_status->status_valid |= PCI_ERR_STATUS_VALID; 1793 } 1794 1795 if (err_pkt->pec_descr.E) { 1796 /* PCIe Status Register */ 1797 rc_status->pcie_err_status = err_pkt->pcie_err_status; 1798 rc_status->status_valid |= PCIE_ERR_STATUS_VALID; 1799 } 1800 1801 if (err_pkt->pec_descr.U) { 1802 rc_status->ue_status = err_pkt->ue_reg_status; 1803 rc_status->status_valid |= UE_STATUS_VALID; 1804 } 1805 1806 if (err_pkt->pec_descr.H) { 1807 rc_status->ue_hdr1 = err_pkt->hdr[0]; 1808 rc_status->status_valid |= UE_HDR1_VALID; 1809 } 1810 1811 if (err_pkt->pec_descr.I) { 1812 rc_status->ue_hdr2 = err_pkt->hdr[1]; 1813 rc_status->status_valid |= UE_HDR2_VALID; 1814 } 1815 1816 /* ue_fst_err_ptr - not available for sun4v?? */ 1817 1818 1819 if (err_pkt->pec_descr.S) { 1820 rc_status->source_id = err_pkt->err_src_reg; 1821 rc_status->status_valid |= SOURCE_ID_VALID; 1822 } 1823 1824 if (err_pkt->pec_descr.R) { 1825 rc_status->root_err_status = err_pkt->root_err_status; 1826 rc_status->status_valid |= CE_STATUS_VALID; 1827 } 1828 } 1829 #endif 1830 1831 /*ARGSUSED*/ 1832 int 1833 px_lib_pmctl(int cmd, px_t *px_p) 1834 { 1835 return (DDI_FAILURE); 1836 } 1837 1838 /*ARGSUSED*/ 1839 uint_t 1840 px_pmeq_intr(caddr_t arg) 1841 { 1842 return (DDI_INTR_CLAIMED); 1843 } 1844 1845 /* 1846 * Unprotected raw reads/writes of fabric device's config space. 1847 * Only used for temporary PCI-E Fabric Error Handling. 1848 */ 1849 uint32_t 1850 px_fab_get(px_t *px_p, pcie_req_id_t bdf, uint16_t offset) { 1851 uint32_t data = 0; 1852 1853 (void) hvio_config_get(px_p->px_dev_hdl, 1854 (bdf << PX_RA_BDF_SHIFT), offset, 4, 1855 (pci_cfg_data_t *)&data); 1856 1857 return (data); 1858 } 1859 1860 void 1861 px_fab_set(px_t *px_p, pcie_req_id_t bdf, uint16_t offset, 1862 uint32_t val) { 1863 pci_cfg_data_t wdata = { 0 }; 1864 1865 wdata.qw = (uint32_t)val; 1866 (void) hvio_config_put(px_p->px_dev_hdl, 1867 (bdf << PX_RA_BDF_SHIFT), offset, 4, wdata); 1868 } 1869 1870 /*ARGSUSED*/ 1871 int 1872 px_lib_hotplug_init(dev_info_t *dip, void *arg) 1873 { 1874 return (DDI_ENOTSUP); 1875 } 1876 1877 /*ARGSUSED*/ 1878 void 1879 px_lib_hotplug_uninit(dev_info_t *dip) 1880 { 1881 } 1882 1883 /* Dummy cpr add callback */ 1884 /*ARGSUSED*/ 1885 void 1886 px_cpr_add_callb(px_t *px_p) 1887 { 1888 } 1889 1890 /* Dummy cpr rem callback */ 1891 /*ARGSUSED*/ 1892 void 1893 px_cpr_rem_callb(px_t *px_p) 1894 { 1895 } 1896