1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved.
23 */
24
25 /*
26 * The file has been code generated. Do NOT modify this file directly. Please
27 * use the sun4v PCIe FMA code generation tool.
28 *
29 * This file was generated for the following platforms:
30 * - Fire
31 * - N2PIU
32 * - Rainbow Falls
33 * - Victoria Falls
34 */
35
36 #include <sys/pcie_impl.h>
37
38 /* ARGSUSED */
39 static int
px_cb_epkt_severity(dev_info_t * dip,ddi_fm_error_t * derr,px_rc_err_t * epkt,pf_data_t * pfd_p)40 px_cb_epkt_severity(dev_info_t *dip, ddi_fm_error_t *derr, px_rc_err_t *epkt,
41 pf_data_t *pfd_p)
42 {
43 int err = 0;
44
45 /* STOP bit indicates a secondary error. Panic if it is set */
46 if (epkt->rc_descr.STOP == 1)
47 return (PX_PANIC);
48
49 switch (epkt->rc_descr.op) {
50 case OP_DMA:
51 switch (epkt->rc_descr.phase) {
52 case PH_ADDR:
53 switch (epkt->rc_descr.cond) {
54 case CND_ILL:
55 switch (epkt->rc_descr.dir) {
56 case DIR_WRITE:
57 err = PX_PANIC;
58 break;
59 } /* DIR */
60 break;
61 } /* CND */
62 break;
63 case PH_DATA:
64 switch (epkt->rc_descr.cond) {
65 case CND_INT:
66 switch (epkt->rc_descr.dir) {
67 case DIR_READ:
68 err = PX_PANIC;
69 break;
70 case DIR_RDWR:
71 err = PX_PANIC;
72 break;
73 case DIR_UNKNOWN:
74 err = PX_PANIC;
75 break;
76 case DIR_WRITE:
77 err = PX_PANIC;
78 break;
79 } /* DIR */
80 break;
81 case CND_TO:
82 switch (epkt->rc_descr.dir) {
83 case DIR_READ:
84 err = PX_PANIC;
85 break;
86 case DIR_WRITE:
87 err = PX_PANIC;
88 break;
89 } /* DIR */
90 break;
91 case CND_UE:
92 switch (epkt->rc_descr.dir) {
93 case DIR_READ:
94 err = PX_PANIC;
95 break;
96 } /* DIR */
97 break;
98 } /* CND */
99 break;
100 case PH_UNKNOWN:
101 switch (epkt->rc_descr.cond) {
102 case CND_ILL:
103 switch (epkt->rc_descr.dir) {
104 case DIR_READ:
105 err = PX_PANIC;
106 break;
107 } /* DIR */
108 break;
109 case CND_UNKNOWN:
110 switch (epkt->rc_descr.dir) {
111 case DIR_READ:
112 err = PX_PANIC;
113 break;
114 } /* DIR */
115 break;
116 } /* CND */
117 break;
118 } /* PH */
119 break;
120 case OP_PIO:
121 switch (epkt->rc_descr.phase) {
122 case PH_ADDR:
123 switch (epkt->rc_descr.cond) {
124 case CND_UNMAP:
125 switch (epkt->rc_descr.dir) {
126 case DIR_READ:
127 err = PX_PANIC;
128 break;
129 case DIR_WRITE:
130 err = PX_PANIC;
131 break;
132 } /* DIR */
133 break;
134 } /* CND */
135 break;
136 case PH_DATA:
137 switch (epkt->rc_descr.cond) {
138 case CND_INT:
139 switch (epkt->rc_descr.dir) {
140 case DIR_RDWR:
141 err = PX_PANIC;
142 break;
143 case DIR_UNKNOWN:
144 err = PX_PANIC;
145 break;
146 case DIR_WRITE:
147 err = PX_PANIC;
148 break;
149 } /* DIR */
150 break;
151 case CND_ILL:
152 switch (epkt->rc_descr.dir) {
153 case DIR_WRITE:
154 err = PX_PANIC;
155 break;
156 } /* DIR */
157 break;
158 } /* CND */
159 break;
160 case PH_UNKNOWN:
161 switch (epkt->rc_descr.cond) {
162 case CND_ILL:
163 switch (epkt->rc_descr.dir) {
164 case DIR_READ:
165 err = PX_PANIC;
166 break;
167 case DIR_WRITE:
168 err = PX_PANIC;
169 break;
170 } /* DIR */
171 break;
172 case CND_TO:
173 switch (epkt->rc_descr.dir) {
174 case DIR_RDWR:
175 err = PX_PANIC;
176 break;
177 } /* DIR */
178 break;
179 } /* CND */
180 break;
181 } /* PH */
182 break;
183 case OP_UNKNOWN:
184 switch (epkt->rc_descr.phase) {
185 case PH_ADDR:
186 switch (epkt->rc_descr.cond) {
187 case CND_UNMAP:
188 switch (epkt->rc_descr.dir) {
189 case DIR_RDWR:
190 err = PX_PANIC;
191 break;
192 } /* DIR */
193 break;
194 } /* CND */
195 break;
196 case PH_DATA:
197 switch (epkt->rc_descr.cond) {
198 case CND_INT:
199 switch (epkt->rc_descr.dir) {
200 case DIR_UNKNOWN:
201 err = PX_PANIC;
202 break;
203 } /* DIR */
204 break;
205 case CND_UE:
206 switch (epkt->rc_descr.dir) {
207 case DIR_IRR:
208 err = PX_PANIC;
209 break;
210 } /* DIR */
211 break;
212 } /* CND */
213 break;
214 case PH_UNKNOWN:
215 switch (epkt->rc_descr.cond) {
216 case CND_ILL:
217 switch (epkt->rc_descr.dir) {
218 case DIR_IRR:
219 err = PX_PANIC;
220 break;
221 } /* DIR */
222 } /* CND */
223 } /* PH */
224 } /* OP */
225
226 return (err);
227 }
228
229
230 /* ARGSUSED */
231 static int
px_mmu_epkt_severity(dev_info_t * dip,ddi_fm_error_t * derr,px_rc_err_t * epkt,pf_data_t * pfd_p)232 px_mmu_epkt_severity(dev_info_t *dip, ddi_fm_error_t *derr, px_rc_err_t *epkt,
233 pf_data_t *pfd_p)
234 {
235 int err = 0;
236
237 /* STOP bit indicates a secondary error. Panic if it is set */
238 if (epkt->rc_descr.STOP == 1)
239 return (PX_PANIC);
240
241 switch (epkt->rc_descr.op) {
242 case OP_BYPASS:
243 switch (epkt->rc_descr.phase) {
244 case PH_ADDR:
245 switch (epkt->rc_descr.cond) {
246 case CND_ILL:
247 switch (epkt->rc_descr.dir) {
248 case DIR_RDWR:
249 err = PX_NO_PANIC;
250 break;
251 } /* DIR */
252 break;
253 } /* CND */
254 break;
255 case PH_UNKNOWN:
256 switch (epkt->rc_descr.cond) {
257 case CND_ILL:
258 switch (epkt->rc_descr.dir) {
259 case DIR_UNKNOWN:
260 err = PX_NO_PANIC;
261 break;
262 } /* DIR */
263 break;
264 } /* CND */
265 break;
266 } /* PH */
267 break;
268 case OP_TBW:
269 switch (epkt->rc_descr.phase) {
270 case PH_ADDR:
271 switch (epkt->rc_descr.cond) {
272 case CND_UNKNOWN:
273 switch (epkt->rc_descr.dir) {
274 case DIR_UNKNOWN:
275 err = PX_PANIC;
276 break;
277 } /* DIR */
278 break;
279 case CND_UNMAP:
280 switch (epkt->rc_descr.dir) {
281 case DIR_UNKNOWN:
282 err = PX_PANIC;
283 break;
284 } /* DIR */
285 break;
286 } /* CND */
287 break;
288 case PH_DATA:
289 switch (epkt->rc_descr.cond) {
290 case CND_INT:
291 switch (epkt->rc_descr.dir) {
292 case DIR_IRR:
293 err = PX_PANIC;
294 break;
295 } /* DIR */
296 break;
297 } /* CND */
298 break;
299 case PH_UNKNOWN:
300 switch (epkt->rc_descr.cond) {
301 case CND_ILL:
302 switch (epkt->rc_descr.dir) {
303 case DIR_IRR:
304 err = PX_PANIC;
305 break;
306 } /* DIR */
307 break;
308 case CND_UNKNOWN:
309 switch (epkt->rc_descr.dir) {
310 case DIR_IRR:
311 err = PX_PANIC;
312 break;
313 case DIR_UNKNOWN:
314 err = PX_PANIC;
315 break;
316 } /* DIR */
317 break;
318 } /* CND */
319 break;
320 } /* PH */
321 break;
322 case OP_XLAT:
323 switch (epkt->rc_descr.phase) {
324 case PH_ADDR:
325 switch (epkt->rc_descr.cond) {
326 case CND_ILL:
327 switch (epkt->rc_descr.dir) {
328 case DIR_RDWR:
329 err = PX_NO_PANIC;
330 break;
331 } /* DIR */
332 break;
333 case CND_IRR:
334 switch (epkt->rc_descr.dir) {
335 case DIR_IRR:
336 err = PX_PANIC;
337 break;
338 } /* DIR */
339 break;
340 case CND_PROT:
341 switch (epkt->rc_descr.dir) {
342 case DIR_RDWR:
343 err = PX_NO_PANIC;
344 break;
345 } /* DIR */
346 break;
347 case CND_UNMAP:
348 switch (epkt->rc_descr.dir) {
349 case DIR_RDWR:
350 err = PX_NO_PANIC;
351 break;
352 } /* DIR */
353 break;
354 } /* CND */
355 break;
356 case PH_DATA:
357 switch (epkt->rc_descr.cond) {
358 case CND_INT:
359 switch (epkt->rc_descr.dir) {
360 case DIR_UNKNOWN:
361 err = PX_PANIC;
362 break;
363 } /* DIR */
364 break;
365 case CND_INV:
366 switch (epkt->rc_descr.dir) {
367 case DIR_RDWR:
368 err = PX_NO_PANIC;
369 break;
370 case DIR_UNKNOWN:
371 err = PX_NO_PANIC;
372 break;
373 } /* DIR */
374 break;
375 case CND_IRR:
376 switch (epkt->rc_descr.dir) {
377 case DIR_IRR:
378 err = PX_PANIC;
379 break;
380 } /* DIR */
381 break;
382 case CND_PROT:
383 switch (epkt->rc_descr.dir) {
384 case DIR_RDWR:
385 err = PX_NO_PANIC;
386 break;
387 case DIR_WRITE:
388 err = PX_NO_PANIC;
389 break;
390 } /* DIR */
391 break;
392 } /* CND */
393 break;
394 case PH_UNKNOWN:
395 switch (epkt->rc_descr.cond) {
396 case CND_ILL:
397 switch (epkt->rc_descr.dir) {
398 case DIR_IRR:
399 err = PX_PANIC;
400 break;
401 } /* DIR */
402 } /* CND */
403 } /* PH */
404 } /* OP */
405
406 if (epkt->rc_descr.D && (err & (PX_PANIC | PX_PROTECTED)) &&
407 px_mmu_handle_lookup(dip, derr, epkt) == PF_HDL_FOUND)
408 err = PX_NO_PANIC;
409
410 return (err);
411 }
412
413
414 /* ARGSUSED */
415 static int
px_intr_epkt_severity(dev_info_t * dip,ddi_fm_error_t * derr,px_rc_err_t * epkt,pf_data_t * pfd_p)416 px_intr_epkt_severity(dev_info_t *dip, ddi_fm_error_t *derr, px_rc_err_t *epkt,
417 pf_data_t *pfd_p)
418 {
419 int err = 0;
420
421 /* STOP bit indicates a secondary error. Panic if it is set */
422 if (epkt->rc_descr.STOP == 1)
423 return (PX_PANIC);
424
425 switch (epkt->rc_descr.op) {
426 case OP_FIXED:
427 switch (epkt->rc_descr.phase) {
428 case PH_UNKNOWN:
429 switch (epkt->rc_descr.cond) {
430 case CND_ILL:
431 switch (epkt->rc_descr.dir) {
432 case DIR_INGRESS:
433 err = PX_PANIC;
434 break;
435 } /* DIR */
436 break;
437 } /* CND */
438 break;
439 } /* PH */
440 break;
441 case OP_MSI32:
442 switch (epkt->rc_descr.phase) {
443 case PH_DATA:
444 switch (epkt->rc_descr.cond) {
445 case CND_INT:
446 switch (epkt->rc_descr.dir) {
447 case DIR_UNKNOWN:
448 err = PX_PANIC;
449 break;
450 } /* DIR */
451 break;
452 case CND_ILL:
453 switch (epkt->rc_descr.dir) {
454 case DIR_IRR:
455 err = PX_PANIC;
456 break;
457 } /* DIR */
458 break;
459 } /* CND */
460 break;
461 case PH_UNKNOWN:
462 switch (epkt->rc_descr.cond) {
463 case CND_ILL:
464 switch (epkt->rc_descr.dir) {
465 case DIR_IRR:
466 err = PX_PANIC;
467 break;
468 } /* DIR */
469 break;
470 } /* CND */
471 break;
472 } /* PH */
473 break;
474 case OP_MSI64:
475 switch (epkt->rc_descr.phase) {
476 case PH_DATA:
477 switch (epkt->rc_descr.cond) {
478 case CND_INT:
479 switch (epkt->rc_descr.dir) {
480 case DIR_UNKNOWN:
481 err = PX_PANIC;
482 break;
483 } /* DIR */
484 break;
485 case CND_ILL:
486 switch (epkt->rc_descr.dir) {
487 case DIR_IRR:
488 err = PX_PANIC;
489 break;
490 } /* DIR */
491 break;
492 } /* CND */
493 break;
494 case PH_UNKNOWN:
495 switch (epkt->rc_descr.cond) {
496 case CND_ILL:
497 switch (epkt->rc_descr.dir) {
498 case DIR_IRR:
499 err = PX_PANIC;
500 break;
501 } /* DIR */
502 break;
503 } /* CND */
504 break;
505 } /* PH */
506 break;
507 case OP_MSIQ:
508 switch (epkt->rc_descr.phase) {
509 case PH_DATA:
510 switch (epkt->rc_descr.cond) {
511 case CND_INT:
512 switch (epkt->rc_descr.dir) {
513 case DIR_UNKNOWN:
514 err = PX_PANIC;
515 break;
516 } /* DIR */
517 break;
518 } /* CND */
519 break;
520 case PH_UNKNOWN:
521 switch (epkt->rc_descr.cond) {
522 case CND_ILL:
523 switch (epkt->rc_descr.dir) {
524 case DIR_IRR:
525 err = PX_PANIC;
526 break;
527 } /* DIR */
528 break;
529 case CND_OV:
530 switch (epkt->rc_descr.dir) {
531 case DIR_IRR:
532 err = px_intr_handle_errors(dip, derr,
533 epkt, pfd_p);
534 break;
535 } /* DIR */
536 break;
537 } /* CND */
538 break;
539 } /* PH */
540 break;
541 case OP_PCIEMSG:
542 switch (epkt->rc_descr.phase) {
543 case PH_UNKNOWN:
544 switch (epkt->rc_descr.cond) {
545 case CND_ILL:
546 switch (epkt->rc_descr.dir) {
547 case DIR_INGRESS:
548 err = PX_PANIC;
549 break;
550 } /* DIR */
551 break;
552 } /* CND */
553 break;
554 } /* PH */
555 break;
556 case OP_UNKNOWN:
557 switch (epkt->rc_descr.phase) {
558 case PH_DATA:
559 switch (epkt->rc_descr.cond) {
560 case CND_INT:
561 switch (epkt->rc_descr.dir) {
562 case DIR_UNKNOWN:
563 err = PX_PANIC;
564 break;
565 } /* DIR */
566 break;
567 case CND_ILL:
568 switch (epkt->rc_descr.dir) {
569 case DIR_IRR:
570 err = PX_PANIC;
571 break;
572 } /* DIR */
573 break;
574 } /* CND */
575 break;
576 case PH_UNKNOWN:
577 switch (epkt->rc_descr.cond) {
578 case CND_ILL:
579 switch (epkt->rc_descr.dir) {
580 case DIR_IRR:
581 err = PX_PANIC;
582 break;
583 } /* DIR */
584 } /* CND */
585 } /* PH */
586 } /* OP */
587
588 return (err);
589 }
590
591
592 /* ARGSUSED */
593 static int
px_port_epkt_severity(dev_info_t * dip,ddi_fm_error_t * derr,px_rc_err_t * epkt,pf_data_t * pfd_p)594 px_port_epkt_severity(dev_info_t *dip, ddi_fm_error_t *derr, px_rc_err_t *epkt,
595 pf_data_t *pfd_p)
596 {
597 int err = 0;
598
599 /* STOP bit indicates a secondary error. Panic if it is set */
600 if (epkt->rc_descr.STOP == 1)
601 return (PX_PANIC);
602
603 switch (epkt->rc_descr.op) {
604 case OP_DMA:
605 switch (epkt->rc_descr.phase) {
606 case PH_DATA:
607 switch (epkt->rc_descr.cond) {
608 case CND_INT:
609 switch (epkt->rc_descr.dir) {
610 case DIR_READ:
611 err = PX_PANIC;
612 PFD_SET_AFFECTED_FLAG(pfd_p,
613 PF_AFFECTED_BDF);
614 PFD_SET_AFFECTED_BDF(pfd_p,
615 (uint16_t)epkt->reserved);
616 break;
617 } /* DIR */
618 break;
619 } /* CND */
620 break;
621 } /* PH */
622 break;
623 case OP_LINK:
624 switch (epkt->rc_descr.phase) {
625 case PH_FC:
626 switch (epkt->rc_descr.cond) {
627 case CND_TO:
628 switch (epkt->rc_descr.dir) {
629 case DIR_IRR:
630 err = PX_PANIC;
631 PFD_SET_AFFECTED_FLAG(pfd_p,
632 PF_AFFECTED_BDF);
633 PFD_SET_AFFECTED_BDF(pfd_p,
634 (uint16_t)epkt->reserved);
635 break;
636 } /* DIR */
637 break;
638 } /* CND */
639 break;
640 } /* PH */
641 break;
642 case OP_PIO:
643 switch (epkt->rc_descr.phase) {
644 case PH_DATA:
645 switch (epkt->rc_descr.cond) {
646 case CND_INT:
647 switch (epkt->rc_descr.dir) {
648 case DIR_READ:
649 err = PX_PANIC;
650 PFD_SET_AFFECTED_FLAG(pfd_p,
651 PF_AFFECTED_BDF);
652 PFD_SET_AFFECTED_BDF(pfd_p,
653 (uint16_t)epkt->reserved);
654 break;
655 case DIR_UNKNOWN:
656 err = PX_PANIC;
657 PFD_SET_AFFECTED_FLAG(pfd_p,
658 PF_AFFECTED_BDF);
659 PFD_SET_AFFECTED_BDF(pfd_p,
660 (uint16_t)epkt->reserved);
661 break;
662 } /* DIR */
663 break;
664 } /* CND */
665 break;
666 case PH_IRR:
667 switch (epkt->rc_descr.cond) {
668 case CND_INV:
669 switch (epkt->rc_descr.dir) {
670 case DIR_RDWR:
671 err = PX_PANIC;
672 break;
673 } /* DIR */
674 break;
675 case CND_RCA:
676 switch (epkt->rc_descr.dir) {
677 case DIR_WRITE:
678 err = px_port_handle_errors(dip, derr,
679 epkt, pfd_p);
680 break;
681 } /* DIR */
682 break;
683 case CND_RUR:
684 switch (epkt->rc_descr.dir) {
685 case DIR_WRITE:
686 err = px_port_handle_errors(dip, derr,
687 epkt, pfd_p);
688 break;
689 } /* DIR */
690 break;
691 case CND_TO:
692 switch (epkt->rc_descr.dir) {
693 case DIR_WRITE:
694 err = PX_PANIC;
695 break;
696 } /* DIR */
697 break;
698 case CND_UC:
699 switch (epkt->rc_descr.dir) {
700 case DIR_IRR:
701 err = PX_NO_PANIC;
702 break;
703 } /* DIR */
704 break;
705 } /* CND */
706 break;
707 } /* PH */
708 break;
709 case OP_UNKNOWN:
710 switch (epkt->rc_descr.phase) {
711 case PH_DATA:
712 switch (epkt->rc_descr.cond) {
713 case CND_INT:
714 switch (epkt->rc_descr.dir) {
715 case DIR_UNKNOWN:
716 err = PX_PANIC;
717 PFD_SET_AFFECTED_FLAG(pfd_p,
718 PF_AFFECTED_BDF);
719 PFD_SET_AFFECTED_BDF(pfd_p,
720 (uint16_t)epkt->reserved);
721 break;
722 } /* DIR */
723 } /* CND */
724 } /* PH */
725 } /* OP */
726
727 return (err);
728 }
729