1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * The file has been code generated. Do NOT modify this file directly. Please 30 * use the sun4v PCIe FMA code generation tool. 31 * 32 * This file was generated for the following platforms: 33 * - Fire 34 * - N2PIU 35 */ 36 37 /* ARGSUSED */ 38 static int 39 px_cb_epkt_severity(dev_info_t *dip, ddi_fm_error_t *derr, px_rc_err_t *epkt) 40 { 41 int err = 0; 42 43 /* STOP bit indicates a secondary error. Panic if it is set */ 44 if (epkt->rc_descr.STOP == 1) 45 return (PX_PANIC); 46 47 switch (epkt->rc_descr.op) { 48 case OP_DMA: 49 switch (epkt->rc_descr.phase) { 50 case PH_ADDR: 51 switch (epkt->rc_descr.cond) { 52 case CND_ILL: 53 switch (epkt->rc_descr.dir) { 54 case DIR_WRITE: 55 err = PX_PANIC; 56 break; 57 } /* DIR */ 58 break; 59 } /* CND */ 60 break; 61 case PH_DATA: 62 switch (epkt->rc_descr.cond) { 63 case CND_INT: 64 switch (epkt->rc_descr.dir) { 65 case DIR_READ: 66 err = PX_PANIC; 67 break; 68 case DIR_RDWR: 69 err = PX_PANIC; 70 break; 71 case DIR_WRITE: 72 err = PX_PANIC; 73 break; 74 } /* DIR */ 75 break; 76 case CND_UE: 77 switch (epkt->rc_descr.dir) { 78 case DIR_READ: 79 err = PX_PANIC; 80 break; 81 } /* DIR */ 82 break; 83 } /* CND */ 84 break; 85 case PH_UNKNOWN: 86 switch (epkt->rc_descr.cond) { 87 case CND_ILL: 88 switch (epkt->rc_descr.dir) { 89 case DIR_READ: 90 err = PX_PANIC; 91 break; 92 } /* DIR */ 93 break; 94 case CND_UNKNOWN: 95 switch (epkt->rc_descr.dir) { 96 case DIR_READ: 97 err = PX_PANIC; 98 break; 99 } /* DIR */ 100 break; 101 } /* CND */ 102 break; 103 } /* PH */ 104 break; 105 case OP_PIO: 106 switch (epkt->rc_descr.phase) { 107 case PH_ADDR: 108 switch (epkt->rc_descr.cond) { 109 case CND_UNMAP: 110 switch (epkt->rc_descr.dir) { 111 case DIR_READ: 112 err = PX_PANIC; 113 break; 114 case DIR_WRITE: 115 err = PX_PANIC; 116 break; 117 } /* DIR */ 118 break; 119 } /* CND */ 120 break; 121 case PH_DATA: 122 switch (epkt->rc_descr.cond) { 123 case CND_INT: 124 switch (epkt->rc_descr.dir) { 125 case DIR_READ: 126 err = PX_PANIC; 127 break; 128 case DIR_RDWR: 129 err = PX_PANIC; 130 break; 131 case DIR_WRITE: 132 err = PX_PANIC; 133 break; 134 } /* DIR */ 135 break; 136 case CND_ILL: 137 switch (epkt->rc_descr.dir) { 138 case DIR_WRITE: 139 err = PX_PANIC; 140 break; 141 } /* DIR */ 142 break; 143 } /* CND */ 144 break; 145 case PH_UNKNOWN: 146 switch (epkt->rc_descr.cond) { 147 case CND_ILL: 148 switch (epkt->rc_descr.dir) { 149 case DIR_READ: 150 err = PX_PANIC; 151 break; 152 case DIR_WRITE: 153 err = PX_PANIC; 154 break; 155 } /* DIR */ 156 break; 157 case CND_TO: 158 switch (epkt->rc_descr.dir) { 159 case DIR_RDWR: 160 err = PX_PANIC; 161 break; 162 } /* DIR */ 163 break; 164 } /* CND */ 165 break; 166 } /* PH */ 167 break; 168 case OP_UNKNOWN: 169 switch (epkt->rc_descr.phase) { 170 case PH_ADDR: 171 switch (epkt->rc_descr.cond) { 172 case CND_UNMAP: 173 switch (epkt->rc_descr.dir) { 174 case DIR_RDWR: 175 err = PX_PANIC; 176 break; 177 } /* DIR */ 178 break; 179 } /* CND */ 180 break; 181 case PH_DATA: 182 switch (epkt->rc_descr.cond) { 183 case CND_UE: 184 switch (epkt->rc_descr.dir) { 185 case DIR_IRR: 186 err = PX_PANIC; 187 break; 188 } /* DIR */ 189 break; 190 } /* CND */ 191 break; 192 case PH_UNKNOWN: 193 switch (epkt->rc_descr.cond) { 194 case CND_ILL: 195 switch (epkt->rc_descr.dir) { 196 case DIR_IRR: 197 err = PX_PANIC; 198 break; 199 } /* DIR */ 200 } /* CND */ 201 } /* PH */ 202 } /* OP */ 203 204 return (err); 205 } 206 207 208 /* ARGSUSED */ 209 static int 210 px_mmu_epkt_severity(dev_info_t *dip, ddi_fm_error_t *derr, px_rc_err_t *epkt) 211 { 212 int err = 0; 213 214 /* STOP bit indicates a secondary error. Panic if it is set */ 215 if (epkt->rc_descr.STOP == 1) 216 return (PX_PANIC); 217 218 switch (epkt->rc_descr.op) { 219 case OP_BYPASS: 220 switch (epkt->rc_descr.phase) { 221 case PH_ADDR: 222 switch (epkt->rc_descr.cond) { 223 case CND_ILL: 224 switch (epkt->rc_descr.dir) { 225 case DIR_RDWR: 226 err = PX_NO_PANIC; 227 break; 228 } /* DIR */ 229 break; 230 } /* CND */ 231 break; 232 case PH_UNKNOWN: 233 switch (epkt->rc_descr.cond) { 234 case CND_ILL: 235 switch (epkt->rc_descr.dir) { 236 case DIR_UNKNOWN: 237 err = PX_NO_PANIC; 238 break; 239 } /* DIR */ 240 break; 241 } /* CND */ 242 break; 243 } /* PH */ 244 break; 245 case OP_TBW: 246 switch (epkt->rc_descr.phase) { 247 case PH_DATA: 248 switch (epkt->rc_descr.cond) { 249 case CND_INT: 250 switch (epkt->rc_descr.dir) { 251 case DIR_IRR: 252 err = PX_PANIC; 253 break; 254 } /* DIR */ 255 break; 256 } /* CND */ 257 break; 258 case PH_UNKNOWN: 259 switch (epkt->rc_descr.cond) { 260 case CND_ILL: 261 switch (epkt->rc_descr.dir) { 262 case DIR_IRR: 263 err = PX_PANIC; 264 break; 265 } /* DIR */ 266 break; 267 case CND_UNKNOWN: 268 switch (epkt->rc_descr.dir) { 269 case DIR_IRR: 270 err = PX_PANIC; 271 break; 272 } /* DIR */ 273 break; 274 } /* CND */ 275 break; 276 } /* PH */ 277 break; 278 case OP_XLAT: 279 switch (epkt->rc_descr.phase) { 280 case PH_ADDR: 281 switch (epkt->rc_descr.cond) { 282 case CND_ILL: 283 switch (epkt->rc_descr.dir) { 284 case DIR_RDWR: 285 err = PX_NO_PANIC; 286 break; 287 } /* DIR */ 288 break; 289 case CND_IRR: 290 switch (epkt->rc_descr.dir) { 291 case DIR_IRR: 292 err = PX_PANIC; 293 break; 294 } /* DIR */ 295 break; 296 case CND_PROT: 297 switch (epkt->rc_descr.dir) { 298 case DIR_RDWR: 299 err = PX_NO_PANIC; 300 break; 301 } /* DIR */ 302 break; 303 case CND_UNMAP: 304 switch (epkt->rc_descr.dir) { 305 case DIR_RDWR: 306 err = PX_NO_PANIC; 307 break; 308 } /* DIR */ 309 break; 310 } /* CND */ 311 break; 312 case PH_DATA: 313 switch (epkt->rc_descr.cond) { 314 case CND_INV: 315 switch (epkt->rc_descr.dir) { 316 case DIR_RDWR: 317 err = PX_NO_PANIC; 318 break; 319 case DIR_UNKNOWN: 320 err = PX_NO_PANIC; 321 break; 322 } /* DIR */ 323 break; 324 case CND_IRR: 325 switch (epkt->rc_descr.dir) { 326 case DIR_IRR: 327 err = PX_PANIC; 328 break; 329 } /* DIR */ 330 break; 331 case CND_PROT: 332 switch (epkt->rc_descr.dir) { 333 case DIR_WRITE: 334 err = PX_NO_PANIC; 335 break; 336 } /* DIR */ 337 break; 338 } /* CND */ 339 break; 340 case PH_UNKNOWN: 341 switch (epkt->rc_descr.cond) { 342 case CND_ILL: 343 switch (epkt->rc_descr.dir) { 344 case DIR_IRR: 345 err = PX_PANIC; 346 break; 347 } /* DIR */ 348 } /* CND */ 349 } /* PH */ 350 } /* OP */ 351 352 if (epkt->rc_descr.D && (err & (PX_PANIC | PX_PROTECTED)) && 353 px_mmu_handle_lookup(dip, derr, epkt) == PF_HDL_FOUND) 354 err = PX_NO_PANIC; 355 356 return (err); 357 } 358 359 360 /* ARGSUSED */ 361 static int 362 px_intr_epkt_severity(dev_info_t *dip, ddi_fm_error_t *derr, px_rc_err_t *epkt) 363 { 364 int err = 0; 365 366 /* STOP bit indicates a secondary error. Panic if it is set */ 367 if (epkt->rc_descr.STOP == 1) 368 return (PX_PANIC); 369 370 switch (epkt->rc_descr.op) { 371 case OP_MSI32: 372 switch (epkt->rc_descr.phase) { 373 case PH_DATA: 374 switch (epkt->rc_descr.cond) { 375 case CND_INT: 376 switch (epkt->rc_descr.dir) { 377 case DIR_UNKNOWN: 378 err = PX_PANIC; 379 break; 380 } /* DIR */ 381 break; 382 case CND_ILL: 383 switch (epkt->rc_descr.dir) { 384 case DIR_IRR: 385 err = PX_PANIC; 386 break; 387 } /* DIR */ 388 break; 389 } /* CND */ 390 break; 391 case PH_UNKNOWN: 392 switch (epkt->rc_descr.cond) { 393 case CND_ILL: 394 switch (epkt->rc_descr.dir) { 395 case DIR_IRR: 396 err = PX_PANIC; 397 break; 398 } /* DIR */ 399 break; 400 } /* CND */ 401 break; 402 } /* PH */ 403 break; 404 case OP_MSI64: 405 switch (epkt->rc_descr.phase) { 406 case PH_DATA: 407 switch (epkt->rc_descr.cond) { 408 case CND_INT: 409 switch (epkt->rc_descr.dir) { 410 case DIR_UNKNOWN: 411 err = PX_PANIC; 412 break; 413 } /* DIR */ 414 break; 415 case CND_ILL: 416 switch (epkt->rc_descr.dir) { 417 case DIR_IRR: 418 err = PX_PANIC; 419 break; 420 } /* DIR */ 421 break; 422 } /* CND */ 423 break; 424 case PH_UNKNOWN: 425 switch (epkt->rc_descr.cond) { 426 case CND_ILL: 427 switch (epkt->rc_descr.dir) { 428 case DIR_IRR: 429 err = PX_PANIC; 430 break; 431 } /* DIR */ 432 break; 433 } /* CND */ 434 break; 435 } /* PH */ 436 break; 437 case OP_MSIQ: 438 switch (epkt->rc_descr.phase) { 439 case PH_UNKNOWN: 440 switch (epkt->rc_descr.cond) { 441 case CND_ILL: 442 switch (epkt->rc_descr.dir) { 443 case DIR_IRR: 444 err = PX_PANIC; 445 break; 446 } /* DIR */ 447 break; 448 case CND_OV: 449 switch (epkt->rc_descr.dir) { 450 case DIR_IRR: 451 err = px_intr_handle_errors(dip, derr, 452 epkt); 453 break; 454 } /* DIR */ 455 break; 456 } /* CND */ 457 break; 458 } /* PH */ 459 break; 460 case OP_PCIEMSG: 461 switch (epkt->rc_descr.phase) { 462 case PH_UNKNOWN: 463 switch (epkt->rc_descr.cond) { 464 case CND_ILL: 465 switch (epkt->rc_descr.dir) { 466 case DIR_INGRESS: 467 err = PX_PANIC; 468 break; 469 } /* DIR */ 470 } /* CND */ 471 } /* PH */ 472 } /* OP */ 473 474 return (err); 475 } 476