1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26#include "assym.h" 27 28/* 29 * Niagara processor specific assembly routines 30 */ 31 32#include <sys/asm_linkage.h> 33#include <sys/machasi.h> 34#include <sys/machparam.h> 35#include <sys/hypervisor_api.h> 36#include <sys/niagararegs.h> 37#include <sys/machasi.h> 38#include <sys/niagaraasi.h> 39#include <vm/hat_sfmmu.h> 40 41 /* 42 * hv_niagara_getperf(uint64_t perfreg, uint64_t *datap) 43 */ 44 ENTRY(hv_niagara_getperf) 45 mov %o1, %o4 ! save datap 46 mov HV_NIAGARA_GETPERF, %o5 47 ta FAST_TRAP 48 brz,a %o0, 1f 49 stx %o1, [%o4] 501: 51 retl 52 nop 53 SET_SIZE(hv_niagara_getperf) 54 55 /* 56 * hv_niagara_setperf(uint64_t perfreg, uint64_t data) 57 */ 58 ENTRY(hv_niagara_setperf) 59 mov HV_NIAGARA_SETPERF, %o5 60 ta FAST_TRAP 61 retl 62 nop 63 SET_SIZE(hv_niagara_setperf) 64 65/* 66 * Invalidate all of the entries within the TSB, by setting the inv bit 67 * in the tte_tag field of each tsbe. 68 * 69 * We take advantage of the fact that the TSBs are page aligned and a 70 * multiple of PAGESIZE to use ASI_BLK_INIT_xxx ASI. 71 * 72 * See TSB_LOCK_ENTRY and the miss handlers for how this works in practice 73 * (in short, we set all bits in the upper word of the tag, and we give the 74 * invalid bit precedence over other tag bits in both places). 75 */ 76 ENTRY(cpu_inv_tsb) 77 78 /* 79 * The following code assumes that the tsb_base (%o0) is 256 bytes 80 * aligned and the tsb_bytes count is multiple of 256 bytes. 81 */ 82 83 wr %g0, ASI_BLK_INIT_ST_QUAD_LDD_P, %asi 84 set TSBTAG_INVALID, %o2 85 sllx %o2, 32, %o2 ! INV bit in upper 32 bits of the tag 861: 87 stxa %o2, [%o0+0x0]%asi 88 stxa %o2, [%o0+0x40]%asi 89 stxa %o2, [%o0+0x80]%asi 90 stxa %o2, [%o0+0xc0]%asi 91 92 stxa %o2, [%o0+0x10]%asi 93 stxa %o2, [%o0+0x20]%asi 94 stxa %o2, [%o0+0x30]%asi 95 96 stxa %o2, [%o0+0x50]%asi 97 stxa %o2, [%o0+0x60]%asi 98 stxa %o2, [%o0+0x70]%asi 99 100 stxa %o2, [%o0+0x90]%asi 101 stxa %o2, [%o0+0xa0]%asi 102 stxa %o2, [%o0+0xb0]%asi 103 104 stxa %o2, [%o0+0xd0]%asi 105 stxa %o2, [%o0+0xe0]%asi 106 stxa %o2, [%o0+0xf0]%asi 107 108 subcc %o1, 0x100, %o1 109 bgu,pt %ncc, 1b 110 add %o0, 0x100, %o0 111 112 membar #Sync 113 retl 114 nop 115 116 SET_SIZE(cpu_inv_tsb) 117 118 /* 119 * hv_niagara_mmustat_conf(uint64_t buf, uint64_t *prev_buf) 120 */ 121 ENTRY(hv_niagara_mmustat_conf) 122 mov %o1, %o4 ! save prev_buf 123 mov HV_NIAGARA_MMUSTAT_CONF, %o5 124 ta FAST_TRAP 125 retl 126 stx %o1, [%o4] 127 SET_SIZE(hv_niagara_mmustat_conf) 128 129 /* 130 * hv_niagara_mmustat_info(uint64_t *buf) 131 */ 132 ENTRY(hv_niagara_mmustat_info) 133 mov %o0, %o4 ! save buf 134 mov HV_NIAGARA_MMUSTAT_INFO, %o5 135 ta FAST_TRAP 136 retl 137 stx %o1, [%o4] 138 SET_SIZE(hv_niagara_mmustat_info) 139 140