1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26#include "assym.h" 27 28/* 29 * Niagara2 processor specific assembly routines 30 */ 31 32#include <sys/asm_linkage.h> 33#include <sys/machasi.h> 34#include <sys/machparam.h> 35#include <sys/hypervisor_api.h> 36#include <sys/niagara2regs.h> 37#include <sys/machasi.h> 38#include <sys/niagaraasi.h> 39#include <vm/hat_sfmmu.h> 40 41 /* 42 * hv_niagara_getperf(uint64_t perfreg, uint64_t *datap) 43 */ 44 ENTRY(hv_niagara_getperf) 45 mov %o1, %o4 ! save datap 46#if defined(NIAGARA2_IMPL) 47 mov HV_NIAGARA2_GETPERF, %o5 48#elif defined(VFALLS_IMPL) 49 mov HV_VFALLS_GETPERF, %o5 50#elif defined(KT_IMPL) 51 mov HV_KT_GETPERF, %o5 52#endif 53 ta FAST_TRAP 54 brz,a %o0, 1f 55 stx %o1, [%o4] 561: 57 retl 58 nop 59 SET_SIZE(hv_niagara_getperf) 60 61 /* 62 * hv_niagara_setperf(uint64_t perfreg, uint64_t data) 63 */ 64 ENTRY(hv_niagara_setperf) 65#if defined(NIAGARA2_IMPL) 66 mov HV_NIAGARA2_SETPERF, %o5 67#elif defined(VFALLS_IMPL) 68 mov HV_VFALLS_SETPERF, %o5 69#elif defined(KT_IMPL) 70 mov HV_KT_SETPERF, %o5 71#endif 72 ta FAST_TRAP 73 retl 74 nop 75 SET_SIZE(hv_niagara_setperf) 76 77/* 78 * Invalidate all of the entries within the TSB, by setting the inv bit 79 * in the tte_tag field of each tsbe. 80 * 81 * We take advantage of the fact that the TSBs are page aligned and a 82 * multiple of PAGESIZE to use ASI_BLK_INIT_xxx ASI. 83 * 84 * See TSB_LOCK_ENTRY and the miss handlers for how this works in practice 85 * (in short, we set all bits in the upper word of the tag, and we give the 86 * invalid bit precedence over other tag bits in both places). 87 */ 88 ENTRY(cpu_inv_tsb) 89 90 /* 91 * The following code assumes that the tsb_base (%o0) is 256 bytes 92 * aligned and the tsb_bytes count is multiple of 256 bytes. 93 */ 94 95 wr %g0, ASI_BLK_INIT_ST_QUAD_LDD_P, %asi 96 set TSBTAG_INVALID, %o2 97 sllx %o2, 32, %o2 ! INV bit in upper 32 bits of the tag 981: 99 stxa %o2, [%o0+0x0]%asi 100 stxa %o2, [%o0+0x40]%asi 101 stxa %o2, [%o0+0x80]%asi 102 stxa %o2, [%o0+0xc0]%asi 103 104 stxa %o2, [%o0+0x10]%asi 105 stxa %o2, [%o0+0x20]%asi 106 stxa %o2, [%o0+0x30]%asi 107 108 stxa %o2, [%o0+0x50]%asi 109 stxa %o2, [%o0+0x60]%asi 110 stxa %o2, [%o0+0x70]%asi 111 112 stxa %o2, [%o0+0x90]%asi 113 stxa %o2, [%o0+0xa0]%asi 114 stxa %o2, [%o0+0xb0]%asi 115 116 stxa %o2, [%o0+0xd0]%asi 117 stxa %o2, [%o0+0xe0]%asi 118 stxa %o2, [%o0+0xf0]%asi 119 120 subcc %o1, 0x100, %o1 121 bgu,pt %ncc, 1b 122 add %o0, 0x100, %o0 123 124 membar #Sync 125 retl 126 nop 127 128 SET_SIZE(cpu_inv_tsb) 129 130 /* 131 * The rd instruction uses less resources than casx on Niagara2 and VF 132 * CPUs. 133 */ 134 ENTRY(cpu_atomic_delay) 135 rd %ccr, %g0 136 rd %ccr, %g0 137 retl 138 rd %ccr, %g0 139 SET_SIZE(cpu_atomic_delay) 140