1*5d9d9091SRichard Lowe/* 2*5d9d9091SRichard Lowe * CDDL HEADER START 3*5d9d9091SRichard Lowe * 4*5d9d9091SRichard Lowe * The contents of this file are subject to the terms of the 5*5d9d9091SRichard Lowe * Common Development and Distribution License (the "License"). 6*5d9d9091SRichard Lowe * You may not use this file except in compliance with the License. 7*5d9d9091SRichard Lowe * 8*5d9d9091SRichard Lowe * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*5d9d9091SRichard Lowe * or http://www.opensolaris.org/os/licensing. 10*5d9d9091SRichard Lowe * See the License for the specific language governing permissions 11*5d9d9091SRichard Lowe * and limitations under the License. 12*5d9d9091SRichard Lowe * 13*5d9d9091SRichard Lowe * When distributing Covered Code, include this CDDL HEADER in each 14*5d9d9091SRichard Lowe * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*5d9d9091SRichard Lowe * If applicable, add the following below this CDDL HEADER, with the 16*5d9d9091SRichard Lowe * fields enclosed by brackets "[]" replaced with your own identifying 17*5d9d9091SRichard Lowe * information: Portions Copyright [yyyy] [name of copyright owner] 18*5d9d9091SRichard Lowe * 19*5d9d9091SRichard Lowe * CDDL HEADER END 20*5d9d9091SRichard Lowe */ 21*5d9d9091SRichard Lowe/* 22*5d9d9091SRichard Lowe * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23*5d9d9091SRichard Lowe * Use is subject to license terms. 24*5d9d9091SRichard Lowe */ 25*5d9d9091SRichard Lowe 26*5d9d9091SRichard Lowe#include "assym.h" 27*5d9d9091SRichard Lowe 28*5d9d9091SRichard Lowe/* 29*5d9d9091SRichard Lowe * Niagara2 processor specific assembly routines 30*5d9d9091SRichard Lowe */ 31*5d9d9091SRichard Lowe 32*5d9d9091SRichard Lowe#include <sys/asm_linkage.h> 33*5d9d9091SRichard Lowe#include <sys/machasi.h> 34*5d9d9091SRichard Lowe#include <sys/machparam.h> 35*5d9d9091SRichard Lowe#include <sys/hypervisor_api.h> 36*5d9d9091SRichard Lowe#include <sys/niagara2regs.h> 37*5d9d9091SRichard Lowe#include <sys/machasi.h> 38*5d9d9091SRichard Lowe#include <sys/niagaraasi.h> 39*5d9d9091SRichard Lowe#include <vm/hat_sfmmu.h> 40*5d9d9091SRichard Lowe 41*5d9d9091SRichard Lowe /* 42*5d9d9091SRichard Lowe * hv_niagara_getperf(uint64_t perfreg, uint64_t *datap) 43*5d9d9091SRichard Lowe */ 44*5d9d9091SRichard Lowe ENTRY(hv_niagara_getperf) 45*5d9d9091SRichard Lowe mov %o1, %o4 ! save datap 46*5d9d9091SRichard Lowe#if defined(NIAGARA2_IMPL) 47*5d9d9091SRichard Lowe mov HV_NIAGARA2_GETPERF, %o5 48*5d9d9091SRichard Lowe#elif defined(VFALLS_IMPL) 49*5d9d9091SRichard Lowe mov HV_VFALLS_GETPERF, %o5 50*5d9d9091SRichard Lowe#elif defined(KT_IMPL) 51*5d9d9091SRichard Lowe mov HV_KT_GETPERF, %o5 52*5d9d9091SRichard Lowe#endif 53*5d9d9091SRichard Lowe ta FAST_TRAP 54*5d9d9091SRichard Lowe brz,a %o0, 1f 55*5d9d9091SRichard Lowe stx %o1, [%o4] 56*5d9d9091SRichard Lowe1: 57*5d9d9091SRichard Lowe retl 58*5d9d9091SRichard Lowe nop 59*5d9d9091SRichard Lowe SET_SIZE(hv_niagara_getperf) 60*5d9d9091SRichard Lowe 61*5d9d9091SRichard Lowe /* 62*5d9d9091SRichard Lowe * hv_niagara_setperf(uint64_t perfreg, uint64_t data) 63*5d9d9091SRichard Lowe */ 64*5d9d9091SRichard Lowe ENTRY(hv_niagara_setperf) 65*5d9d9091SRichard Lowe#if defined(NIAGARA2_IMPL) 66*5d9d9091SRichard Lowe mov HV_NIAGARA2_SETPERF, %o5 67*5d9d9091SRichard Lowe#elif defined(VFALLS_IMPL) 68*5d9d9091SRichard Lowe mov HV_VFALLS_SETPERF, %o5 69*5d9d9091SRichard Lowe#elif defined(KT_IMPL) 70*5d9d9091SRichard Lowe mov HV_KT_SETPERF, %o5 71*5d9d9091SRichard Lowe#endif 72*5d9d9091SRichard Lowe ta FAST_TRAP 73*5d9d9091SRichard Lowe retl 74*5d9d9091SRichard Lowe nop 75*5d9d9091SRichard Lowe SET_SIZE(hv_niagara_setperf) 76*5d9d9091SRichard Lowe 77*5d9d9091SRichard Lowe/* 78*5d9d9091SRichard Lowe * Invalidate all of the entries within the TSB, by setting the inv bit 79*5d9d9091SRichard Lowe * in the tte_tag field of each tsbe. 80*5d9d9091SRichard Lowe * 81*5d9d9091SRichard Lowe * We take advantage of the fact that the TSBs are page aligned and a 82*5d9d9091SRichard Lowe * multiple of PAGESIZE to use ASI_BLK_INIT_xxx ASI. 83*5d9d9091SRichard Lowe * 84*5d9d9091SRichard Lowe * See TSB_LOCK_ENTRY and the miss handlers for how this works in practice 85*5d9d9091SRichard Lowe * (in short, we set all bits in the upper word of the tag, and we give the 86*5d9d9091SRichard Lowe * invalid bit precedence over other tag bits in both places). 87*5d9d9091SRichard Lowe */ 88*5d9d9091SRichard Lowe ENTRY(cpu_inv_tsb) 89*5d9d9091SRichard Lowe 90*5d9d9091SRichard Lowe /* 91*5d9d9091SRichard Lowe * The following code assumes that the tsb_base (%o0) is 256 bytes 92*5d9d9091SRichard Lowe * aligned and the tsb_bytes count is multiple of 256 bytes. 93*5d9d9091SRichard Lowe */ 94*5d9d9091SRichard Lowe 95*5d9d9091SRichard Lowe wr %g0, ASI_BLK_INIT_ST_QUAD_LDD_P, %asi 96*5d9d9091SRichard Lowe set TSBTAG_INVALID, %o2 97*5d9d9091SRichard Lowe sllx %o2, 32, %o2 ! INV bit in upper 32 bits of the tag 98*5d9d9091SRichard Lowe1: 99*5d9d9091SRichard Lowe stxa %o2, [%o0+0x0]%asi 100*5d9d9091SRichard Lowe stxa %o2, [%o0+0x40]%asi 101*5d9d9091SRichard Lowe stxa %o2, [%o0+0x80]%asi 102*5d9d9091SRichard Lowe stxa %o2, [%o0+0xc0]%asi 103*5d9d9091SRichard Lowe 104*5d9d9091SRichard Lowe stxa %o2, [%o0+0x10]%asi 105*5d9d9091SRichard Lowe stxa %o2, [%o0+0x20]%asi 106*5d9d9091SRichard Lowe stxa %o2, [%o0+0x30]%asi 107*5d9d9091SRichard Lowe 108*5d9d9091SRichard Lowe stxa %o2, [%o0+0x50]%asi 109*5d9d9091SRichard Lowe stxa %o2, [%o0+0x60]%asi 110*5d9d9091SRichard Lowe stxa %o2, [%o0+0x70]%asi 111*5d9d9091SRichard Lowe 112*5d9d9091SRichard Lowe stxa %o2, [%o0+0x90]%asi 113*5d9d9091SRichard Lowe stxa %o2, [%o0+0xa0]%asi 114*5d9d9091SRichard Lowe stxa %o2, [%o0+0xb0]%asi 115*5d9d9091SRichard Lowe 116*5d9d9091SRichard Lowe stxa %o2, [%o0+0xd0]%asi 117*5d9d9091SRichard Lowe stxa %o2, [%o0+0xe0]%asi 118*5d9d9091SRichard Lowe stxa %o2, [%o0+0xf0]%asi 119*5d9d9091SRichard Lowe 120*5d9d9091SRichard Lowe subcc %o1, 0x100, %o1 121*5d9d9091SRichard Lowe bgu,pt %ncc, 1b 122*5d9d9091SRichard Lowe add %o0, 0x100, %o0 123*5d9d9091SRichard Lowe 124*5d9d9091SRichard Lowe membar #Sync 125*5d9d9091SRichard Lowe retl 126*5d9d9091SRichard Lowe nop 127*5d9d9091SRichard Lowe 128*5d9d9091SRichard Lowe SET_SIZE(cpu_inv_tsb) 129*5d9d9091SRichard Lowe 130*5d9d9091SRichard Lowe /* 131*5d9d9091SRichard Lowe * The rd instruction uses less resources than casx on Niagara2 and VF 132*5d9d9091SRichard Lowe * CPUs. 133*5d9d9091SRichard Lowe */ 134*5d9d9091SRichard Lowe ENTRY(cpu_atomic_delay) 135*5d9d9091SRichard Lowe rd %ccr, %g0 136*5d9d9091SRichard Lowe rd %ccr, %g0 137*5d9d9091SRichard Lowe retl 138*5d9d9091SRichard Lowe rd %ccr, %g0 139*5d9d9091SRichard Lowe SET_SIZE(cpu_atomic_delay) 140