1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/types.h> 30 #include <sys/systm.h> 31 #include <sys/archsystm.h> 32 #include <sys/machparam.h> 33 #include <sys/machsystm.h> 34 #include <sys/cpu.h> 35 #include <sys/elf_SPARC.h> 36 #include <vm/hat_sfmmu.h> 37 #include <vm/page.h> 38 #include <vm/vm_dep.h> 39 #include <sys/cpuvar.h> 40 #include <sys/async.h> 41 #include <sys/cmn_err.h> 42 #include <sys/debug.h> 43 #include <sys/dditypes.h> 44 #include <sys/sunddi.h> 45 #include <sys/cpu_module.h> 46 #include <sys/prom_debug.h> 47 #include <sys/vmsystm.h> 48 #include <sys/prom_plat.h> 49 #include <sys/sysmacros.h> 50 #include <sys/intreg.h> 51 #include <sys/machtrap.h> 52 #include <sys/ontrap.h> 53 #include <sys/ivintr.h> 54 #include <sys/atomic.h> 55 #include <sys/panic.h> 56 #include <sys/dtrace.h> 57 #include <sys/simulate.h> 58 #include <sys/fault.h> 59 #include <sys/niagara2regs.h> 60 #include <sys/hsvc.h> 61 #include <sys/trapstat.h> 62 63 uint_t root_phys_addr_lo_mask = 0xffffffffU; 64 char cpu_module_name[] = "SUNW,UltraSPARC-T2"; 65 66 /* 67 * Hypervisor services information for the NIAGARA2 CPU module 68 */ 69 static boolean_t niagara2_hsvc_available = B_TRUE; 70 static uint64_t niagara2_sup_minor; /* Supported minor number */ 71 static hsvc_info_t niagara2_hsvc = { 72 HSVC_REV_1, NULL, HSVC_GROUP_NIAGARA2_CPU, NIAGARA2_HSVC_MAJOR, 73 NIAGARA2_HSVC_MINOR, cpu_module_name 74 }; 75 76 void 77 cpu_setup(void) 78 { 79 extern int mmu_exported_pagesize_mask; 80 extern int cpc_has_overflow_intr; 81 int status; 82 83 /* 84 * Negotiate the API version for Niagara2 specific hypervisor 85 * services. 86 */ 87 status = hsvc_register(&niagara2_hsvc, &niagara2_sup_minor); 88 if (status != 0) { 89 cmn_err(CE_WARN, "%s: cannot negotiate hypervisor services " 90 "group: 0x%lx major: 0x%lx minor: 0x%lx errno: %d", 91 niagara2_hsvc.hsvc_modname, niagara2_hsvc.hsvc_group, 92 niagara2_hsvc.hsvc_major, niagara2_hsvc.hsvc_minor, status); 93 niagara2_hsvc_available = B_FALSE; 94 } 95 96 /* 97 * The setup common to all CPU modules is done in cpu_setup_common 98 * routine. 99 */ 100 cpu_setup_common(NULL); 101 102 cache |= (CACHE_PTAG | CACHE_IOCOHERENT); 103 104 if ((mmu_exported_pagesize_mask & 105 DEFAULT_SUN4V_MMU_PAGESIZE_MASK) != 106 DEFAULT_SUN4V_MMU_PAGESIZE_MASK) 107 cmn_err(CE_PANIC, "machine description" 108 " does not have required sun4v page sizes" 109 " 8K, 64K and 4M: MD mask is 0x%x", 110 mmu_exported_pagesize_mask); 111 112 cpu_hwcap_flags = AV_SPARC_VIS | AV_SPARC_VIS2 | AV_SPARC_ASI_BLK_INIT; 113 114 /* 115 * Niagara2 supports a 48-bit subset of the full 64-bit virtual 116 * address space. Virtual addresses between 0x0000800000000000 117 * and 0xffff.7fff.ffff.ffff inclusive lie within a "VA Hole" 118 * and must never be mapped. In addition, software must not use 119 * pages within 4GB of the VA hole as instruction pages to 120 * avoid problems with prefetching into the VA hole. 121 */ 122 hole_start = (caddr_t)((1ull << (va_bits - 1)) - (1ull << 32)); 123 hole_end = (caddr_t)((0ull - (1ull << (va_bits - 1))) + (1ull << 32)); 124 125 /* 126 * Niagara2 has a performance counter overflow interrupt 127 */ 128 cpc_has_overflow_intr = 1; 129 130 /* 131 * Enable 4M pages for OOB. 132 */ 133 max_uheap_lpsize = MMU_PAGESIZE4M; 134 max_ustack_lpsize = MMU_PAGESIZE4M; 135 max_privmap_lpsize = MMU_PAGESIZE4M; 136 } 137 138 /* 139 * Set the magic constants of the implementation. 140 */ 141 void 142 cpu_fiximp(struct cpu_node *cpunode) 143 { 144 /* 145 * The Cache node is optional in MD. Therefore in case "Cache" 146 * node does not exists in MD, set the default L2 cache associativity, 147 * size, linesize. 148 */ 149 if (cpunode->ecache_size == 0) 150 cpunode->ecache_size = L2CACHE_SIZE; 151 if (cpunode->ecache_linesize == 0) 152 cpunode->ecache_linesize = L2CACHE_LINESIZE; 153 if (cpunode->ecache_associativity == 0) 154 cpunode->ecache_associativity = L2CACHE_ASSOCIATIVITY; 155 } 156 157 void 158 cpu_map_exec_units(struct cpu *cp) 159 { 160 ASSERT(MUTEX_HELD(&cpu_lock)); 161 162 /* 163 * The cpu_ipipe and cpu_fpu fields are initialized based on 164 * the execution unit sharing information from the MD. They 165 * default to the CPU id in the absence of such information. 166 */ 167 cp->cpu_m.cpu_ipipe = cpunodes[cp->cpu_id].exec_unit_mapping; 168 if (cp->cpu_m.cpu_ipipe == NO_EU_MAPPING_FOUND) 169 cp->cpu_m.cpu_ipipe = (id_t)(cp->cpu_id); 170 171 cp->cpu_m.cpu_fpu = cpunodes[cp->cpu_id].fpu_mapping; 172 if (cp->cpu_m.cpu_fpu == NO_EU_MAPPING_FOUND) 173 cp->cpu_m.cpu_fpu = (id_t)(cp->cpu_id); 174 175 /* 176 * Niagara 2 defines the core to be at the FPU level 177 */ 178 cp->cpu_m.cpu_core = cp->cpu_m.cpu_fpu; 179 } 180 181 static int niagara2_cpucnt; 182 183 void 184 cpu_init_private(struct cpu *cp) 185 { 186 extern void niagara_kstat_init(void); 187 188 ASSERT(MUTEX_HELD(&cpu_lock)); 189 190 cpu_map_exec_units(cp); 191 192 if ((niagara2_cpucnt++ == 0) && (niagara2_hsvc_available == B_TRUE)) 193 niagara_kstat_init(); 194 } 195 196 /*ARGSUSED*/ 197 void 198 cpu_uninit_private(struct cpu *cp) 199 { 200 extern void niagara_kstat_fini(void); 201 202 ASSERT(MUTEX_HELD(&cpu_lock)); 203 204 if ((--niagara2_cpucnt == 0) && (niagara2_hsvc_available == B_TRUE)) 205 niagara_kstat_fini(); 206 } 207 208 /* 209 * On Niagara2, any flush will cause all preceding stores to be 210 * synchronized wrt the i$, regardless of address or ASI. In fact, 211 * the address is ignored, so we always flush address 0. 212 */ 213 /*ARGSUSED*/ 214 void 215 dtrace_flush_sec(uintptr_t addr) 216 { 217 doflush(0); 218 } 219 220 /* 221 * Trapstat support for Niagara2 processor 222 * The Niagara2 provides HWTW support for TSB lookup and with HWTW 223 * enabled no TSB hit information will be available. Therefore setting 224 * the time spent in TLB miss handler for TSB hits to 0. 225 */ 226 int 227 cpu_trapstat_conf(int cmd) 228 { 229 int status = 0; 230 231 switch (cmd) { 232 case CPU_TSTATCONF_INIT: 233 case CPU_TSTATCONF_FINI: 234 case CPU_TSTATCONF_ENABLE: 235 case CPU_TSTATCONF_DISABLE: 236 break; 237 default: 238 status = EINVAL; 239 break; 240 } 241 return (status); 242 } 243 244 void 245 cpu_trapstat_data(void *buf, uint_t tstat_pgszs) 246 { 247 tstat_pgszdata_t *tstatp = (tstat_pgszdata_t *)buf; 248 int i; 249 250 for (i = 0; i < tstat_pgszs; i++, tstatp++) { 251 tstatp->tpgsz_kernel.tmode_itlb.ttlb_tlb.tmiss_count = 0; 252 tstatp->tpgsz_kernel.tmode_itlb.ttlb_tlb.tmiss_time = 0; 253 tstatp->tpgsz_user.tmode_itlb.ttlb_tlb.tmiss_count = 0; 254 tstatp->tpgsz_user.tmode_itlb.ttlb_tlb.tmiss_time = 0; 255 tstatp->tpgsz_kernel.tmode_dtlb.ttlb_tlb.tmiss_count = 0; 256 tstatp->tpgsz_kernel.tmode_dtlb.ttlb_tlb.tmiss_time = 0; 257 tstatp->tpgsz_user.tmode_dtlb.ttlb_tlb.tmiss_count = 0; 258 tstatp->tpgsz_user.tmode_dtlb.ttlb_tlb.tmiss_time = 0; 259 } 260 } 261 262 /* NI2 L2$ index is pa[32:28]^pa[17:13].pa[19:18]^pa[12:11].pa[10:6] */ 263 uint_t 264 page_pfn_2_color_cpu(pfn_t pfn, uchar_t szc) 265 { 266 uint_t color; 267 268 ASSERT(szc <= TTE256M); 269 270 pfn = PFN_BASE(pfn, szc); 271 color = ((pfn >> 15) ^ pfn) & 0x1f; 272 if (szc >= TTE4M) 273 return (color); 274 275 color = (color << 2) | ((pfn >> 5) & 0x3); 276 277 return (szc <= TTE64K ? color : (color >> 1)); 278 } 279 280 #if TTE256M != 5 281 #error TTE256M is not 5 282 #endif 283 284 uint_t 285 page_get_nsz_color_mask_cpu(uchar_t szc, uint_t mask) 286 { 287 static uint_t ni2_color_masks[5] = {0x63, 0x1e, 0x3e, 0x1f, 0x1f}; 288 ASSERT(szc < TTE256M); 289 290 mask &= ni2_color_masks[szc]; 291 return ((szc == TTE64K || szc == TTE512K) ? (mask >> 1) : mask); 292 } 293 294 uint_t 295 page_get_nsz_color_cpu(uchar_t szc, uint_t color) 296 { 297 ASSERT(szc < TTE256M); 298 return ((szc == TTE64K || szc == TTE512K) ? (color >> 1) : color); 299 } 300 301 uint_t 302 page_get_color_shift_cpu(uchar_t szc, uchar_t nszc) 303 { 304 ASSERT(nszc > szc); 305 ASSERT(nszc <= TTE256M); 306 307 if (szc <= TTE64K) 308 return ((nszc >= TTE4M) ? 2 : ((nszc >= TTE512K) ? 1 : 0)); 309 if (szc == TTE512K) 310 return (1); 311 312 return (0); 313 } 314 315 /*ARGSUSED*/ 316 pfn_t 317 page_next_pfn_for_color_cpu(pfn_t pfn, uchar_t szc, uint_t color, 318 uint_t ceq_mask, uint_t color_mask) 319 { 320 pfn_t pstep = PNUM_SIZE(szc); 321 pfn_t npfn, pfn_ceq_mask, pfn_color; 322 pfn_t tmpmask, mask = (pfn_t)-1; 323 324 ASSERT((color & ~ceq_mask) == 0); 325 326 if (((page_pfn_2_color_cpu(pfn, szc) ^ color) & ceq_mask) == 0) { 327 328 /* we start from the page with correct color */ 329 if (szc >= TTE512K) { 330 if (szc >= TTE4M) { 331 /* page color is PA[32:28] */ 332 pfn_ceq_mask = ceq_mask << 15; 333 } else { 334 /* page color is PA[32:28].PA[19:19] */ 335 pfn_ceq_mask = ((ceq_mask & 1) << 6) | 336 ((ceq_mask >> 1) << 15); 337 } 338 pfn = ADD_MASKED(pfn, pstep, pfn_ceq_mask, mask); 339 return (pfn); 340 } else { 341 /* 342 * We deal 64K or 8K page. Check if we could the 343 * satisfy the request without changing PA[32:28] 344 */ 345 pfn_ceq_mask = ((ceq_mask & 3) << 5) | (ceq_mask >> 2); 346 npfn = ADD_MASKED(pfn, pstep, pfn_ceq_mask, mask); 347 348 if ((((npfn ^ pfn) >> 15) & 0x1f) == 0) 349 return (npfn); 350 351 /* 352 * for next pfn we have to change bits PA[32:28] 353 * set PA[63:28] and PA[19:18] of the next pfn 354 */ 355 npfn = (pfn >> 15) << 15; 356 npfn |= (ceq_mask & color & 3) << 5; 357 pfn_ceq_mask = (szc == TTE8K) ? 0 : 358 (ceq_mask & 0x1c) << 13; 359 npfn = ADD_MASKED(npfn, (1 << 15), pfn_ceq_mask, mask); 360 361 /* 362 * set bits PA[17:13] to match the color 363 */ 364 ceq_mask >>= 2; 365 color = (color >> 2) & ceq_mask; 366 npfn |= ((npfn >> 15) ^ color) & ceq_mask; 367 return (npfn); 368 } 369 } 370 371 /* 372 * we start from the page with incorrect color - rare case 373 */ 374 if (szc >= TTE512K) { 375 if (szc >= TTE4M) { 376 /* page color is in bits PA[32:28] */ 377 npfn = ((pfn >> 20) << 20) | (color << 15); 378 pfn_ceq_mask = (ceq_mask << 15) | 0x7fff; 379 } else { 380 /* try get the right color by changing bit PA[19:19] */ 381 npfn = pfn + pstep; 382 if (((page_pfn_2_color_cpu(npfn, szc) ^ color) & 383 ceq_mask) == 0) 384 return (npfn); 385 386 /* page color is PA[32:28].PA[19:19] */ 387 pfn_ceq_mask = ((ceq_mask & 1) << 6) | 388 ((ceq_mask >> 1) << 15) | (0xff << 7); 389 pfn_color = ((color & 1) << 6) | ((color >> 1) << 15); 390 npfn = ((pfn >> 20) << 20) | pfn_color; 391 } 392 393 while (npfn <= pfn) { 394 npfn = ADD_MASKED(npfn, pstep, pfn_ceq_mask, mask); 395 } 396 return (npfn); 397 } 398 399 /* 400 * We deal 64K or 8K page of incorrect color. 401 * Try correcting color without changing PA[32:28] 402 */ 403 404 pfn_ceq_mask = ((ceq_mask & 3) << 5) | (ceq_mask >> 2); 405 pfn_color = ((color & 3) << 5) | (color >> 2); 406 npfn = (pfn & ~(pfn_t)0x7f); 407 npfn |= (((pfn >> 15) & 0x1f) ^ pfn_color) & pfn_ceq_mask; 408 npfn = (szc == TTE64K) ? (npfn & ~(pfn_t)0x7) : npfn; 409 410 if (((page_pfn_2_color_cpu(npfn, szc) ^ color) & ceq_mask) == 0) { 411 412 /* the color is fixed - find the next page */ 413 while (npfn <= pfn) { 414 npfn = ADD_MASKED(npfn, pstep, pfn_ceq_mask, mask); 415 } 416 if ((((npfn ^ pfn) >> 15) & 0x1f) == 0) 417 return (npfn); 418 } 419 420 /* to fix the color need to touch PA[32:28] */ 421 npfn = (szc == TTE8K) ? ((pfn >> 15) << 15) : 422 (((pfn >> 18) << 18) | ((color & 0x1c) << 13)); 423 tmpmask = (szc == TTE8K) ? 0 : (ceq_mask & 0x1c) << 13; 424 425 while (npfn <= pfn) { 426 npfn = ADD_MASKED(npfn, (1 << 15), tmpmask, mask); 427 } 428 429 /* set bits PA[19:13] to match the color */ 430 npfn |= (((npfn >> 15) & 0x1f) ^ pfn_color) & pfn_ceq_mask; 431 npfn = (szc == TTE64K) ? (npfn & ~(pfn_t)0x7) : npfn; 432 433 ASSERT(((page_pfn_2_color_cpu(npfn, szc) ^ color) & ceq_mask) == 0); 434 435 return (npfn); 436 } 437 438 /* 439 * init page coloring 440 */ 441 void 442 page_coloring_init_cpu() 443 { 444 int i; 445 446 hw_page_array[0].hp_colors = 1 << 7; 447 hw_page_array[1].hp_colors = 1 << 7; 448 hw_page_array[2].hp_colors = 1 << 6; 449 450 for (i = 3; i < mmu_page_sizes; i++) { 451 hw_page_array[i].hp_colors = 1 << 5; 452 } 453 } 454 455 /* 456 * group colorequiv colors on N2 by low order bits of the color first 457 */ 458 void 459 page_set_colorequiv_arr_cpu(void) 460 { 461 static uint_t nequiv_shades_log2[MMU_PAGE_SIZES] = {2, 5, 0, 0, 0, 0}; 462 463 if (colorequiv > 1) { 464 int i; 465 uint_t sv_a = lowbit(colorequiv) - 1; 466 467 if (sv_a > 15) 468 sv_a = 15; 469 470 for (i = 0; i < MMU_PAGE_SIZES; i++) { 471 uint_t colors; 472 uint_t a = sv_a; 473 474 if ((colors = hw_page_array[i].hp_colors) <= 1) 475 continue; 476 while ((colors >> a) == 0) 477 a--; 478 if (a > (colorequivszc[i] & 0xf) + 479 (colorequivszc[i] >> 4)) { 480 if (a <= nequiv_shades_log2[i]) { 481 colorequivszc[i] = a; 482 } else { 483 colorequivszc[i] = 484 ((a - nequiv_shades_log2[i]) << 4) | 485 nequiv_shades_log2[i]; 486 } 487 } 488 } 489 } 490 } 491