1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/systm.h> 30 #include <sys/archsystm.h> 31 #include <sys/machparam.h> 32 #include <sys/machsystm.h> 33 #include <sys/cpu.h> 34 #include <sys/elf_SPARC.h> 35 #include <vm/hat_sfmmu.h> 36 #include <vm/page.h> 37 #include <sys/cpuvar.h> 38 #include <sys/async.h> 39 #include <sys/cmn_err.h> 40 #include <sys/debug.h> 41 #include <sys/dditypes.h> 42 #include <sys/sunddi.h> 43 #include <sys/cpu_module.h> 44 #include <sys/prom_debug.h> 45 #include <sys/vmsystm.h> 46 #include <sys/prom_plat.h> 47 #include <sys/sysmacros.h> 48 #include <sys/intreg.h> 49 #include <sys/machtrap.h> 50 #include <sys/ontrap.h> 51 #include <sys/ivintr.h> 52 #include <sys/atomic.h> 53 #include <sys/panic.h> 54 #include <sys/dtrace.h> 55 #include <sys/simulate.h> 56 #include <sys/fault.h> 57 #include <sys/niagara2regs.h> 58 #include <sys/hsvc.h> 59 #include <sys/trapstat.h> 60 61 uint_t root_phys_addr_lo_mask = 0xffffffffU; 62 char cpu_module_name[] = "SUNW,UltraSPARC-T2"; 63 64 /* 65 * Hypervisor services information for the NIAGARA2 CPU module 66 */ 67 static boolean_t niagara2_hsvc_available = B_TRUE; 68 static uint64_t niagara2_sup_minor; /* Supported minor number */ 69 static hsvc_info_t niagara2_hsvc = { 70 HSVC_REV_1, NULL, HSVC_GROUP_NIAGARA2_CPU, NIAGARA2_HSVC_MAJOR, 71 NIAGARA2_HSVC_MINOR, cpu_module_name 72 }; 73 74 void 75 cpu_setup(void) 76 { 77 extern int mmu_exported_pagesize_mask; 78 extern int cpc_has_overflow_intr; 79 int status; 80 81 /* 82 * Negotiate the API version for Niagara2 specific hypervisor 83 * services. 84 */ 85 status = hsvc_register(&niagara2_hsvc, &niagara2_sup_minor); 86 if (status != 0) { 87 cmn_err(CE_WARN, "%s: cannot negotiate hypervisor services " 88 "group: 0x%lx major: 0x%lx minor: 0x%lx errno: %d", 89 niagara2_hsvc.hsvc_modname, niagara2_hsvc.hsvc_group, 90 niagara2_hsvc.hsvc_major, niagara2_hsvc.hsvc_minor, status); 91 niagara2_hsvc_available = B_FALSE; 92 } 93 94 /* 95 * The setup common to all CPU modules is done in cpu_setup_common 96 * routine. 97 */ 98 cpu_setup_common(NULL); 99 100 cache |= (CACHE_PTAG | CACHE_IOCOHERENT); 101 102 if ((mmu_exported_pagesize_mask & 103 DEFAULT_SUN4V_MMU_PAGESIZE_MASK) != 104 DEFAULT_SUN4V_MMU_PAGESIZE_MASK) 105 cmn_err(CE_PANIC, "machine description" 106 " does not have required sun4v page sizes" 107 " 8K, 64K and 4M: MD mask is 0x%x", 108 mmu_exported_pagesize_mask); 109 110 cpu_hwcap_flags = AV_SPARC_VIS | AV_SPARC_VIS2 | AV_SPARC_ASI_BLK_INIT; 111 112 /* 113 * Niagara2 supports a 48-bit subset of the full 64-bit virtual 114 * address space. Virtual addresses between 0x0000800000000000 115 * and 0xffff.7fff.ffff.ffff inclusive lie within a "VA Hole" 116 * and must never be mapped. In addition, software must not use 117 * pages within 4GB of the VA hole as instruction pages to 118 * avoid problems with prefetching into the VA hole. 119 */ 120 hole_start = (caddr_t)((1ull << (va_bits - 1)) - (1ull << 32)); 121 hole_end = (caddr_t)((0ull - (1ull << (va_bits - 1))) + (1ull << 32)); 122 123 /* 124 * Niagara2 has a performance counter overflow interrupt 125 */ 126 cpc_has_overflow_intr = 1; 127 } 128 129 /* 130 * Set the magic constants of the implementation. 131 */ 132 void 133 cpu_fiximp(struct cpu_node *cpunode) 134 { 135 /* 136 * The Cache node is optional in MD. Therefore in case "Cache" 137 * node does not exists in MD, set the default L2 cache associativity, 138 * size, linesize. 139 */ 140 if (cpunode->ecache_size == 0) 141 cpunode->ecache_size = L2CACHE_SIZE; 142 if (cpunode->ecache_linesize == 0) 143 cpunode->ecache_linesize = L2CACHE_LINESIZE; 144 if (cpunode->ecache_associativity == 0) 145 cpunode->ecache_associativity = L2CACHE_ASSOCIATIVITY; 146 } 147 148 static int niagara2_cpucnt; 149 150 void 151 cpu_init_private(struct cpu *cp) 152 { 153 extern int niagara_kstat_init(void); 154 155 /* 156 * The cpu_ipipe field is initialized based on the execution 157 * unit sharing information from the MD. It defaults to the 158 * virtual CPU id in the absence of such information. 159 */ 160 cp->cpu_m.cpu_ipipe = cpunodes[cp->cpu_id].exec_unit_mapping; 161 if (cp->cpu_m.cpu_ipipe == NO_EU_MAPPING_FOUND) 162 cp->cpu_m.cpu_ipipe = (id_t)(cp->cpu_id); 163 164 ASSERT(MUTEX_HELD(&cpu_lock)); 165 if ((niagara2_cpucnt++ == 0) && (niagara2_hsvc_available == B_TRUE)) 166 (void) niagara_kstat_init(); 167 } 168 169 /*ARGSUSED*/ 170 void 171 cpu_uninit_private(struct cpu *cp) 172 { 173 extern int niagara_kstat_fini(void); 174 175 ASSERT(MUTEX_HELD(&cpu_lock)); 176 if ((--niagara2_cpucnt == 0) && (niagara2_hsvc_available == B_TRUE)) 177 (void) niagara_kstat_fini(); 178 } 179 180 /* 181 * On Niagara2, any flush will cause all preceding stores to be 182 * synchronized wrt the i$, regardless of address or ASI. In fact, 183 * the address is ignored, so we always flush address 0. 184 */ 185 /*ARGSUSED*/ 186 void 187 dtrace_flush_sec(uintptr_t addr) 188 { 189 doflush(0); 190 } 191 192 /* 193 * Trapstat support for Niagara2 processor 194 * The Niagara2 provides HWTW support for TSB lookup and with HWTW 195 * enabled no TSB hit information will be available. Therefore setting 196 * the time spent in TLB miss handler for TSB hits to 0. 197 */ 198 int 199 cpu_trapstat_conf(int cmd) 200 { 201 int status = 0; 202 203 switch (cmd) { 204 case CPU_TSTATCONF_INIT: 205 case CPU_TSTATCONF_FINI: 206 case CPU_TSTATCONF_ENABLE: 207 case CPU_TSTATCONF_DISABLE: 208 break; 209 default: 210 status = EINVAL; 211 break; 212 } 213 return (status); 214 } 215 216 void 217 cpu_trapstat_data(void *buf, uint_t tstat_pgszs) 218 { 219 tstat_pgszdata_t *tstatp = (tstat_pgszdata_t *)buf; 220 int i; 221 222 for (i = 0; i < tstat_pgszs; i++, tstatp++) { 223 tstatp->tpgsz_kernel.tmode_itlb.ttlb_tlb.tmiss_count = 0; 224 tstatp->tpgsz_kernel.tmode_itlb.ttlb_tlb.tmiss_time = 0; 225 tstatp->tpgsz_user.tmode_itlb.ttlb_tlb.tmiss_count = 0; 226 tstatp->tpgsz_user.tmode_itlb.ttlb_tlb.tmiss_time = 0; 227 tstatp->tpgsz_kernel.tmode_dtlb.ttlb_tlb.tmiss_count = 0; 228 tstatp->tpgsz_kernel.tmode_dtlb.ttlb_tlb.tmiss_time = 0; 229 tstatp->tpgsz_user.tmode_dtlb.ttlb_tlb.tmiss_count = 0; 230 tstatp->tpgsz_user.tmode_dtlb.ttlb_tlb.tmiss_time = 0; 231 } 232 } 233