144961713Sgirish /* 244961713Sgirish * CDDL HEADER START 344961713Sgirish * 444961713Sgirish * The contents of this file are subject to the terms of the 544961713Sgirish * Common Development and Distribution License (the "License"). 644961713Sgirish * You may not use this file except in compliance with the License. 744961713Sgirish * 844961713Sgirish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 944961713Sgirish * or http://www.opensolaris.org/os/licensing. 1044961713Sgirish * See the License for the specific language governing permissions 1144961713Sgirish * and limitations under the License. 1244961713Sgirish * 1344961713Sgirish * When distributing Covered Code, include this CDDL HEADER in each 1444961713Sgirish * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1544961713Sgirish * If applicable, add the following below this CDDL HEADER, with the 1644961713Sgirish * fields enclosed by brackets "[]" replaced with your own identifying 1744961713Sgirish * information: Portions Copyright [yyyy] [name of copyright owner] 1844961713Sgirish * 1944961713Sgirish * CDDL HEADER END 2044961713Sgirish */ 21*459190a5Srsmaeda 2244961713Sgirish /* 23fb2f18f8Sesaxe * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 2444961713Sgirish * Use is subject to license terms. 2544961713Sgirish */ 2644961713Sgirish 2744961713Sgirish #pragma ident "%Z%%M% %I% %E% SMI" 2844961713Sgirish 2944961713Sgirish #include <sys/types.h> 3044961713Sgirish #include <sys/systm.h> 3144961713Sgirish #include <sys/archsystm.h> 3244961713Sgirish #include <sys/machparam.h> 3344961713Sgirish #include <sys/machsystm.h> 3444961713Sgirish #include <sys/cpu.h> 3544961713Sgirish #include <sys/elf_SPARC.h> 3644961713Sgirish #include <vm/hat_sfmmu.h> 3744961713Sgirish #include <vm/page.h> 38102033aaSdp78419 #include <vm/vm_dep.h> 3944961713Sgirish #include <sys/cpuvar.h> 4044961713Sgirish #include <sys/async.h> 4144961713Sgirish #include <sys/cmn_err.h> 4244961713Sgirish #include <sys/debug.h> 4344961713Sgirish #include <sys/dditypes.h> 4444961713Sgirish #include <sys/sunddi.h> 4544961713Sgirish #include <sys/cpu_module.h> 4644961713Sgirish #include <sys/prom_debug.h> 4744961713Sgirish #include <sys/vmsystm.h> 4844961713Sgirish #include <sys/prom_plat.h> 4944961713Sgirish #include <sys/sysmacros.h> 5044961713Sgirish #include <sys/intreg.h> 5144961713Sgirish #include <sys/machtrap.h> 5244961713Sgirish #include <sys/ontrap.h> 5344961713Sgirish #include <sys/ivintr.h> 5444961713Sgirish #include <sys/atomic.h> 5544961713Sgirish #include <sys/panic.h> 5644961713Sgirish #include <sys/dtrace.h> 5744961713Sgirish #include <sys/simulate.h> 5844961713Sgirish #include <sys/fault.h> 5944961713Sgirish #include <sys/niagara2regs.h> 6044961713Sgirish #include <sys/hsvc.h> 6144961713Sgirish #include <sys/trapstat.h> 6244961713Sgirish 6344961713Sgirish uint_t root_phys_addr_lo_mask = 0xffffffffU; 6444961713Sgirish char cpu_module_name[] = "SUNW,UltraSPARC-T2"; 6544961713Sgirish 6644961713Sgirish /* 6744961713Sgirish * Hypervisor services information for the NIAGARA2 CPU module 6844961713Sgirish */ 6944961713Sgirish static boolean_t niagara2_hsvc_available = B_TRUE; 7044961713Sgirish static uint64_t niagara2_sup_minor; /* Supported minor number */ 7144961713Sgirish static hsvc_info_t niagara2_hsvc = { 7244961713Sgirish HSVC_REV_1, NULL, HSVC_GROUP_NIAGARA2_CPU, NIAGARA2_HSVC_MAJOR, 7344961713Sgirish NIAGARA2_HSVC_MINOR, cpu_module_name 7444961713Sgirish }; 7544961713Sgirish 7644961713Sgirish void 7744961713Sgirish cpu_setup(void) 7844961713Sgirish { 7944961713Sgirish extern int mmu_exported_pagesize_mask; 8044961713Sgirish extern int cpc_has_overflow_intr; 8144961713Sgirish int status; 8244961713Sgirish 8344961713Sgirish /* 8444961713Sgirish * Negotiate the API version for Niagara2 specific hypervisor 8544961713Sgirish * services. 8644961713Sgirish */ 8744961713Sgirish status = hsvc_register(&niagara2_hsvc, &niagara2_sup_minor); 8844961713Sgirish if (status != 0) { 8944961713Sgirish cmn_err(CE_WARN, "%s: cannot negotiate hypervisor services " 9044961713Sgirish "group: 0x%lx major: 0x%lx minor: 0x%lx errno: %d", 9144961713Sgirish niagara2_hsvc.hsvc_modname, niagara2_hsvc.hsvc_group, 9244961713Sgirish niagara2_hsvc.hsvc_major, niagara2_hsvc.hsvc_minor, status); 9344961713Sgirish niagara2_hsvc_available = B_FALSE; 9444961713Sgirish } 9544961713Sgirish 9644961713Sgirish /* 9744961713Sgirish * The setup common to all CPU modules is done in cpu_setup_common 9844961713Sgirish * routine. 9944961713Sgirish */ 10044961713Sgirish cpu_setup_common(NULL); 10144961713Sgirish 10244961713Sgirish cache |= (CACHE_PTAG | CACHE_IOCOHERENT); 10344961713Sgirish 10444961713Sgirish if ((mmu_exported_pagesize_mask & 10544961713Sgirish DEFAULT_SUN4V_MMU_PAGESIZE_MASK) != 10644961713Sgirish DEFAULT_SUN4V_MMU_PAGESIZE_MASK) 10744961713Sgirish cmn_err(CE_PANIC, "machine description" 10844961713Sgirish " does not have required sun4v page sizes" 10944961713Sgirish " 8K, 64K and 4M: MD mask is 0x%x", 11044961713Sgirish mmu_exported_pagesize_mask); 11144961713Sgirish 11244961713Sgirish cpu_hwcap_flags = AV_SPARC_VIS | AV_SPARC_VIS2 | AV_SPARC_ASI_BLK_INIT; 11344961713Sgirish 11444961713Sgirish /* 11544961713Sgirish * Niagara2 supports a 48-bit subset of the full 64-bit virtual 11644961713Sgirish * address space. Virtual addresses between 0x0000800000000000 11744961713Sgirish * and 0xffff.7fff.ffff.ffff inclusive lie within a "VA Hole" 11844961713Sgirish * and must never be mapped. In addition, software must not use 11944961713Sgirish * pages within 4GB of the VA hole as instruction pages to 12044961713Sgirish * avoid problems with prefetching into the VA hole. 12144961713Sgirish */ 12244961713Sgirish hole_start = (caddr_t)((1ull << (va_bits - 1)) - (1ull << 32)); 12344961713Sgirish hole_end = (caddr_t)((0ull - (1ull << (va_bits - 1))) + (1ull << 32)); 12444961713Sgirish 12544961713Sgirish /* 12644961713Sgirish * Niagara2 has a performance counter overflow interrupt 12744961713Sgirish */ 12844961713Sgirish cpc_has_overflow_intr = 1; 129102033aaSdp78419 130102033aaSdp78419 /* 131102033aaSdp78419 * Enable 4M pages for OOB. 132102033aaSdp78419 */ 133102033aaSdp78419 max_uheap_lpsize = MMU_PAGESIZE4M; 134102033aaSdp78419 max_ustack_lpsize = MMU_PAGESIZE4M; 135102033aaSdp78419 max_privmap_lpsize = MMU_PAGESIZE4M; 13644961713Sgirish } 13744961713Sgirish 13844961713Sgirish /* 13944961713Sgirish * Set the magic constants of the implementation. 14044961713Sgirish */ 14144961713Sgirish void 14244961713Sgirish cpu_fiximp(struct cpu_node *cpunode) 14344961713Sgirish { 14444961713Sgirish /* 14544961713Sgirish * The Cache node is optional in MD. Therefore in case "Cache" 14644961713Sgirish * node does not exists in MD, set the default L2 cache associativity, 14744961713Sgirish * size, linesize. 14844961713Sgirish */ 14944961713Sgirish if (cpunode->ecache_size == 0) 15044961713Sgirish cpunode->ecache_size = L2CACHE_SIZE; 15144961713Sgirish if (cpunode->ecache_linesize == 0) 15244961713Sgirish cpunode->ecache_linesize = L2CACHE_LINESIZE; 15344961713Sgirish if (cpunode->ecache_associativity == 0) 15444961713Sgirish cpunode->ecache_associativity = L2CACHE_ASSOCIATIVITY; 15544961713Sgirish } 15644961713Sgirish 15744961713Sgirish void 158*459190a5Srsmaeda cpu_map_exec_units(struct cpu *cp) 15944961713Sgirish { 160*459190a5Srsmaeda ASSERT(MUTEX_HELD(&cpu_lock)); 16144961713Sgirish 16244961713Sgirish /* 163fb2f18f8Sesaxe * The cpu_ipipe and cpu_fpu fields are initialized based on 164*459190a5Srsmaeda * the execution unit sharing information from the MD. They 165*459190a5Srsmaeda * default to the CPU id in the absence of such information. 16644961713Sgirish */ 16744961713Sgirish cp->cpu_m.cpu_ipipe = cpunodes[cp->cpu_id].exec_unit_mapping; 16844961713Sgirish if (cp->cpu_m.cpu_ipipe == NO_EU_MAPPING_FOUND) 16944961713Sgirish cp->cpu_m.cpu_ipipe = (id_t)(cp->cpu_id); 17044961713Sgirish 171fb2f18f8Sesaxe cp->cpu_m.cpu_fpu = cpunodes[cp->cpu_id].fpu_mapping; 172fb2f18f8Sesaxe if (cp->cpu_m.cpu_fpu == NO_EU_MAPPING_FOUND) 173fb2f18f8Sesaxe cp->cpu_m.cpu_fpu = (id_t)(cp->cpu_id); 174fb2f18f8Sesaxe 175fb2f18f8Sesaxe /* 176fb2f18f8Sesaxe * Niagara 2 defines the core to be at the FPU level 177fb2f18f8Sesaxe */ 178fb2f18f8Sesaxe cp->cpu_m.cpu_core = cp->cpu_m.cpu_fpu; 179*459190a5Srsmaeda } 180*459190a5Srsmaeda 181*459190a5Srsmaeda static int niagara2_cpucnt; 182*459190a5Srsmaeda 183*459190a5Srsmaeda void 184*459190a5Srsmaeda cpu_init_private(struct cpu *cp) 185*459190a5Srsmaeda { 186*459190a5Srsmaeda extern void niagara_kstat_init(void); 187fb2f18f8Sesaxe 18844961713Sgirish ASSERT(MUTEX_HELD(&cpu_lock)); 189*459190a5Srsmaeda 190*459190a5Srsmaeda cpu_map_exec_units(cp); 191*459190a5Srsmaeda 19244961713Sgirish if ((niagara2_cpucnt++ == 0) && (niagara2_hsvc_available == B_TRUE)) 193*459190a5Srsmaeda niagara_kstat_init(); 19444961713Sgirish } 19544961713Sgirish 19644961713Sgirish /*ARGSUSED*/ 19744961713Sgirish void 19844961713Sgirish cpu_uninit_private(struct cpu *cp) 19944961713Sgirish { 200*459190a5Srsmaeda extern void niagara_kstat_fini(void); 20144961713Sgirish 20244961713Sgirish ASSERT(MUTEX_HELD(&cpu_lock)); 203*459190a5Srsmaeda 20444961713Sgirish if ((--niagara2_cpucnt == 0) && (niagara2_hsvc_available == B_TRUE)) 205*459190a5Srsmaeda niagara_kstat_fini(); 20644961713Sgirish } 20744961713Sgirish 20844961713Sgirish /* 20944961713Sgirish * On Niagara2, any flush will cause all preceding stores to be 21044961713Sgirish * synchronized wrt the i$, regardless of address or ASI. In fact, 21144961713Sgirish * the address is ignored, so we always flush address 0. 21244961713Sgirish */ 21344961713Sgirish /*ARGSUSED*/ 21444961713Sgirish void 21544961713Sgirish dtrace_flush_sec(uintptr_t addr) 21644961713Sgirish { 21744961713Sgirish doflush(0); 21844961713Sgirish } 21944961713Sgirish 22044961713Sgirish /* 22144961713Sgirish * Trapstat support for Niagara2 processor 22244961713Sgirish * The Niagara2 provides HWTW support for TSB lookup and with HWTW 22344961713Sgirish * enabled no TSB hit information will be available. Therefore setting 22444961713Sgirish * the time spent in TLB miss handler for TSB hits to 0. 22544961713Sgirish */ 22644961713Sgirish int 22744961713Sgirish cpu_trapstat_conf(int cmd) 22844961713Sgirish { 22944961713Sgirish int status = 0; 23044961713Sgirish 23144961713Sgirish switch (cmd) { 23244961713Sgirish case CPU_TSTATCONF_INIT: 23344961713Sgirish case CPU_TSTATCONF_FINI: 23444961713Sgirish case CPU_TSTATCONF_ENABLE: 23544961713Sgirish case CPU_TSTATCONF_DISABLE: 23644961713Sgirish break; 23744961713Sgirish default: 23844961713Sgirish status = EINVAL; 23944961713Sgirish break; 24044961713Sgirish } 24144961713Sgirish return (status); 24244961713Sgirish } 24344961713Sgirish 24444961713Sgirish void 24544961713Sgirish cpu_trapstat_data(void *buf, uint_t tstat_pgszs) 24644961713Sgirish { 24744961713Sgirish tstat_pgszdata_t *tstatp = (tstat_pgszdata_t *)buf; 24844961713Sgirish int i; 24944961713Sgirish 25044961713Sgirish for (i = 0; i < tstat_pgszs; i++, tstatp++) { 25144961713Sgirish tstatp->tpgsz_kernel.tmode_itlb.ttlb_tlb.tmiss_count = 0; 25244961713Sgirish tstatp->tpgsz_kernel.tmode_itlb.ttlb_tlb.tmiss_time = 0; 25344961713Sgirish tstatp->tpgsz_user.tmode_itlb.ttlb_tlb.tmiss_count = 0; 25444961713Sgirish tstatp->tpgsz_user.tmode_itlb.ttlb_tlb.tmiss_time = 0; 25544961713Sgirish tstatp->tpgsz_kernel.tmode_dtlb.ttlb_tlb.tmiss_count = 0; 25644961713Sgirish tstatp->tpgsz_kernel.tmode_dtlb.ttlb_tlb.tmiss_time = 0; 25744961713Sgirish tstatp->tpgsz_user.tmode_dtlb.ttlb_tlb.tmiss_count = 0; 25844961713Sgirish tstatp->tpgsz_user.tmode_dtlb.ttlb_tlb.tmiss_time = 0; 25944961713Sgirish } 26044961713Sgirish } 261102033aaSdp78419 262102033aaSdp78419 /* NI2 L2$ index is pa[32:28]^pa[17:13].pa[19:18]^pa[12:11].pa[10:6] */ 263102033aaSdp78419 uint_t 264102033aaSdp78419 page_pfn_2_color_cpu(pfn_t pfn, uchar_t szc) 265102033aaSdp78419 { 266102033aaSdp78419 uint_t color; 267102033aaSdp78419 268102033aaSdp78419 ASSERT(szc <= TTE256M); 269102033aaSdp78419 270102033aaSdp78419 pfn = PFN_BASE(pfn, szc); 271102033aaSdp78419 color = ((pfn >> 15) ^ pfn) & 0x1f; 272102033aaSdp78419 if (szc >= TTE4M) 273102033aaSdp78419 return (color); 274102033aaSdp78419 275102033aaSdp78419 color = (color << 2) | ((pfn >> 5) & 0x3); 276102033aaSdp78419 277102033aaSdp78419 return (szc <= TTE64K ? color : (color >> 1)); 278102033aaSdp78419 } 279102033aaSdp78419 280102033aaSdp78419 #if TTE256M != 5 281102033aaSdp78419 #error TTE256M is not 5 282102033aaSdp78419 #endif 283102033aaSdp78419 284102033aaSdp78419 uint_t 285102033aaSdp78419 page_get_nsz_color_mask_cpu(uchar_t szc, uint_t mask) 286102033aaSdp78419 { 287102033aaSdp78419 static uint_t ni2_color_masks[5] = {0x63, 0x1e, 0x3e, 0x1f, 0x1f}; 288102033aaSdp78419 ASSERT(szc < TTE256M); 289102033aaSdp78419 290102033aaSdp78419 mask &= ni2_color_masks[szc]; 291102033aaSdp78419 return ((szc == TTE64K || szc == TTE512K) ? (mask >> 1) : mask); 292102033aaSdp78419 } 293102033aaSdp78419 294102033aaSdp78419 uint_t 295102033aaSdp78419 page_get_nsz_color_cpu(uchar_t szc, uint_t color) 296102033aaSdp78419 { 297102033aaSdp78419 ASSERT(szc < TTE256M); 298102033aaSdp78419 return ((szc == TTE64K || szc == TTE512K) ? (color >> 1) : color); 299102033aaSdp78419 } 300102033aaSdp78419 301102033aaSdp78419 uint_t 302102033aaSdp78419 page_get_color_shift_cpu(uchar_t szc, uchar_t nszc) 303102033aaSdp78419 { 304102033aaSdp78419 ASSERT(nszc > szc); 305102033aaSdp78419 ASSERT(nszc <= TTE256M); 306102033aaSdp78419 307102033aaSdp78419 if (szc <= TTE64K) 308102033aaSdp78419 return ((nszc >= TTE4M) ? 2 : ((nszc >= TTE512K) ? 1 : 0)); 309102033aaSdp78419 if (szc == TTE512K) 310102033aaSdp78419 return (1); 311102033aaSdp78419 312102033aaSdp78419 return (0); 313102033aaSdp78419 } 314102033aaSdp78419 315102033aaSdp78419 /*ARGSUSED*/ 316102033aaSdp78419 pfn_t 317102033aaSdp78419 page_next_pfn_for_color_cpu(pfn_t pfn, uchar_t szc, uint_t color, 318102033aaSdp78419 uint_t ceq_mask, uint_t color_mask) 319102033aaSdp78419 { 320102033aaSdp78419 pfn_t pstep = PNUM_SIZE(szc); 321102033aaSdp78419 pfn_t npfn, pfn_ceq_mask, pfn_color; 322102033aaSdp78419 pfn_t tmpmask, mask = (pfn_t)-1; 323102033aaSdp78419 324102033aaSdp78419 ASSERT((color & ~ceq_mask) == 0); 325102033aaSdp78419 326102033aaSdp78419 if (((page_pfn_2_color_cpu(pfn, szc) ^ color) & ceq_mask) == 0) { 327102033aaSdp78419 328102033aaSdp78419 /* we start from the page with correct color */ 329102033aaSdp78419 if (szc >= TTE512K) { 330102033aaSdp78419 if (szc >= TTE4M) { 331102033aaSdp78419 /* page color is PA[32:28] */ 332102033aaSdp78419 pfn_ceq_mask = ceq_mask << 15; 333102033aaSdp78419 } else { 334102033aaSdp78419 /* page color is PA[32:28].PA[19:19] */ 335102033aaSdp78419 pfn_ceq_mask = ((ceq_mask & 1) << 6) | 336102033aaSdp78419 ((ceq_mask >> 1) << 15); 337102033aaSdp78419 } 338102033aaSdp78419 pfn = ADD_MASKED(pfn, pstep, pfn_ceq_mask, mask); 339102033aaSdp78419 return (pfn); 340102033aaSdp78419 } else { 341102033aaSdp78419 /* 342102033aaSdp78419 * We deal 64K or 8K page. Check if we could the 343102033aaSdp78419 * satisfy the request without changing PA[32:28] 344102033aaSdp78419 */ 345102033aaSdp78419 pfn_ceq_mask = ((ceq_mask & 3) << 5) | (ceq_mask >> 2); 346102033aaSdp78419 npfn = ADD_MASKED(pfn, pstep, pfn_ceq_mask, mask); 347102033aaSdp78419 348102033aaSdp78419 if ((((npfn ^ pfn) >> 15) & 0x1f) == 0) 349102033aaSdp78419 return (npfn); 350102033aaSdp78419 351102033aaSdp78419 /* 352102033aaSdp78419 * for next pfn we have to change bits PA[32:28] 353102033aaSdp78419 * set PA[63:28] and PA[19:18] of the next pfn 354102033aaSdp78419 */ 355102033aaSdp78419 npfn = (pfn >> 15) << 15; 356102033aaSdp78419 npfn |= (ceq_mask & color & 3) << 5; 357102033aaSdp78419 pfn_ceq_mask = (szc == TTE8K) ? 0 : 358102033aaSdp78419 (ceq_mask & 0x1c) << 13; 359102033aaSdp78419 npfn = ADD_MASKED(npfn, (1 << 15), pfn_ceq_mask, mask); 360102033aaSdp78419 361102033aaSdp78419 /* 362102033aaSdp78419 * set bits PA[17:13] to match the color 363102033aaSdp78419 */ 364102033aaSdp78419 ceq_mask >>= 2; 365102033aaSdp78419 color = (color >> 2) & ceq_mask; 366102033aaSdp78419 npfn |= ((npfn >> 15) ^ color) & ceq_mask; 367102033aaSdp78419 return (npfn); 368102033aaSdp78419 } 369102033aaSdp78419 } 370102033aaSdp78419 371102033aaSdp78419 /* 372102033aaSdp78419 * we start from the page with incorrect color - rare case 373102033aaSdp78419 */ 374102033aaSdp78419 if (szc >= TTE512K) { 375102033aaSdp78419 if (szc >= TTE4M) { 376102033aaSdp78419 /* page color is in bits PA[32:28] */ 377102033aaSdp78419 npfn = ((pfn >> 20) << 20) | (color << 15); 378102033aaSdp78419 pfn_ceq_mask = (ceq_mask << 15) | 0x7fff; 379102033aaSdp78419 } else { 380102033aaSdp78419 /* try get the right color by changing bit PA[19:19] */ 381102033aaSdp78419 npfn = pfn + pstep; 382102033aaSdp78419 if (((page_pfn_2_color_cpu(npfn, szc) ^ color) & 383102033aaSdp78419 ceq_mask) == 0) 384102033aaSdp78419 return (npfn); 385102033aaSdp78419 386102033aaSdp78419 /* page color is PA[32:28].PA[19:19] */ 387102033aaSdp78419 pfn_ceq_mask = ((ceq_mask & 1) << 6) | 388102033aaSdp78419 ((ceq_mask >> 1) << 15) | (0xff << 7); 389102033aaSdp78419 pfn_color = ((color & 1) << 6) | ((color >> 1) << 15); 390102033aaSdp78419 npfn = ((pfn >> 20) << 20) | pfn_color; 391102033aaSdp78419 } 392102033aaSdp78419 393102033aaSdp78419 while (npfn <= pfn) { 394102033aaSdp78419 npfn = ADD_MASKED(npfn, pstep, pfn_ceq_mask, mask); 395102033aaSdp78419 } 396102033aaSdp78419 return (npfn); 397102033aaSdp78419 } 398102033aaSdp78419 399102033aaSdp78419 /* 400102033aaSdp78419 * We deal 64K or 8K page of incorrect color. 401102033aaSdp78419 * Try correcting color without changing PA[32:28] 402102033aaSdp78419 */ 403102033aaSdp78419 404102033aaSdp78419 pfn_ceq_mask = ((ceq_mask & 3) << 5) | (ceq_mask >> 2); 405102033aaSdp78419 pfn_color = ((color & 3) << 5) | (color >> 2); 406102033aaSdp78419 npfn = (pfn & ~(pfn_t)0x7f); 407102033aaSdp78419 npfn |= (((pfn >> 15) & 0x1f) ^ pfn_color) & pfn_ceq_mask; 408102033aaSdp78419 npfn = (szc == TTE64K) ? (npfn & ~(pfn_t)0x7) : npfn; 409102033aaSdp78419 410102033aaSdp78419 if (((page_pfn_2_color_cpu(npfn, szc) ^ color) & ceq_mask) == 0) { 411102033aaSdp78419 412102033aaSdp78419 /* the color is fixed - find the next page */ 413102033aaSdp78419 while (npfn <= pfn) { 414102033aaSdp78419 npfn = ADD_MASKED(npfn, pstep, pfn_ceq_mask, mask); 415102033aaSdp78419 } 416102033aaSdp78419 if ((((npfn ^ pfn) >> 15) & 0x1f) == 0) 417102033aaSdp78419 return (npfn); 418102033aaSdp78419 } 419102033aaSdp78419 420102033aaSdp78419 /* to fix the color need to touch PA[32:28] */ 421102033aaSdp78419 npfn = (szc == TTE8K) ? ((pfn >> 15) << 15) : 422102033aaSdp78419 (((pfn >> 18) << 18) | ((color & 0x1c) << 13)); 423102033aaSdp78419 tmpmask = (szc == TTE8K) ? 0 : (ceq_mask & 0x1c) << 13; 424102033aaSdp78419 425102033aaSdp78419 while (npfn <= pfn) { 426102033aaSdp78419 npfn = ADD_MASKED(npfn, (1 << 15), tmpmask, mask); 427102033aaSdp78419 } 428102033aaSdp78419 429102033aaSdp78419 /* set bits PA[19:13] to match the color */ 430102033aaSdp78419 npfn |= (((npfn >> 15) & 0x1f) ^ pfn_color) & pfn_ceq_mask; 431102033aaSdp78419 npfn = (szc == TTE64K) ? (npfn & ~(pfn_t)0x7) : npfn; 432102033aaSdp78419 433102033aaSdp78419 ASSERT(((page_pfn_2_color_cpu(npfn, szc) ^ color) & ceq_mask) == 0); 434102033aaSdp78419 435102033aaSdp78419 return (npfn); 436102033aaSdp78419 } 437102033aaSdp78419 438102033aaSdp78419 /* 439102033aaSdp78419 * init page coloring 440102033aaSdp78419 */ 441102033aaSdp78419 void 442102033aaSdp78419 page_coloring_init_cpu() 443102033aaSdp78419 { 444102033aaSdp78419 int i; 445102033aaSdp78419 446102033aaSdp78419 hw_page_array[0].hp_colors = 1 << 7; 447102033aaSdp78419 hw_page_array[1].hp_colors = 1 << 7; 448102033aaSdp78419 hw_page_array[2].hp_colors = 1 << 6; 449102033aaSdp78419 450102033aaSdp78419 for (i = 3; i < mmu_page_sizes; i++) { 451102033aaSdp78419 hw_page_array[i].hp_colors = 1 << 5; 452102033aaSdp78419 } 453102033aaSdp78419 } 454fe70c9cfSdp78419 455fe70c9cfSdp78419 /* 456fe70c9cfSdp78419 * group colorequiv colors on N2 by low order bits of the color first 457fe70c9cfSdp78419 */ 458fe70c9cfSdp78419 void 459fe70c9cfSdp78419 page_set_colorequiv_arr_cpu(void) 460fe70c9cfSdp78419 { 461fe70c9cfSdp78419 static uint_t nequiv_shades_log2[MMU_PAGE_SIZES] = {2, 5, 0, 0, 0, 0}; 462fe70c9cfSdp78419 463fe70c9cfSdp78419 if (colorequiv > 1) { 464fe70c9cfSdp78419 int i; 465fe70c9cfSdp78419 uint_t sv_a = lowbit(colorequiv) - 1; 466fe70c9cfSdp78419 467fe70c9cfSdp78419 if (sv_a > 15) 468fe70c9cfSdp78419 sv_a = 15; 469fe70c9cfSdp78419 470fe70c9cfSdp78419 for (i = 0; i < MMU_PAGE_SIZES; i++) { 471fe70c9cfSdp78419 uint_t colors; 472fe70c9cfSdp78419 uint_t a = sv_a; 473fe70c9cfSdp78419 474fe70c9cfSdp78419 if ((colors = hw_page_array[i].hp_colors) <= 1) 475fe70c9cfSdp78419 continue; 476fe70c9cfSdp78419 while ((colors >> a) == 0) 477fe70c9cfSdp78419 a--; 478fe70c9cfSdp78419 if (a > (colorequivszc[i] & 0xf) + 479fe70c9cfSdp78419 (colorequivszc[i] >> 4)) { 480fe70c9cfSdp78419 if (a <= nequiv_shades_log2[i]) { 481fe70c9cfSdp78419 colorequivszc[i] = a; 482fe70c9cfSdp78419 } else { 483fe70c9cfSdp78419 colorequivszc[i] = 484fe70c9cfSdp78419 ((a - nequiv_shades_log2[i]) << 4) | 485fe70c9cfSdp78419 nequiv_shades_log2[i]; 486fe70c9cfSdp78419 } 487fe70c9cfSdp78419 } 488fe70c9cfSdp78419 } 489fe70c9cfSdp78419 } 490fe70c9cfSdp78419 } 491