1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/types.h> 30 #include <sys/systm.h> 31 #include <sys/archsystm.h> 32 #include <sys/machparam.h> 33 #include <sys/machsystm.h> 34 #include <sys/cpu.h> 35 #include <sys/elf_SPARC.h> 36 #include <vm/hat_sfmmu.h> 37 #include <vm/page.h> 38 #include <sys/cpuvar.h> 39 #include <sys/async.h> 40 #include <sys/cmn_err.h> 41 #include <sys/debug.h> 42 #include <sys/dditypes.h> 43 #include <sys/sunddi.h> 44 #include <sys/cpu_module.h> 45 #include <sys/prom_debug.h> 46 #include <sys/vmsystm.h> 47 #include <sys/prom_plat.h> 48 #include <sys/sysmacros.h> 49 #include <sys/intreg.h> 50 #include <sys/machtrap.h> 51 #include <sys/ontrap.h> 52 #include <sys/ivintr.h> 53 #include <sys/atomic.h> 54 #include <sys/panic.h> 55 #include <sys/dtrace.h> 56 #include <sys/simulate.h> 57 #include <sys/fault.h> 58 #include <sys/niagararegs.h> 59 #include <sys/trapstat.h> 60 61 #define S_VAC_SIZE MMU_PAGESIZE /* XXXQ? */ 62 63 /* 64 * Maximum number of contexts 65 */ 66 #define MAX_NCTXS (1 << 13) 67 68 uint_t root_phys_addr_lo_mask = 0xffffffffU; 69 static niagara_mmustat_t *cpu_tstat_va; /* VA of mmustat buffer */ 70 static uint64_t cpu_tstat_pa; /* PA of mmustat buffer */ 71 72 #ifdef NIAGARA_CHK_VERSION 73 static uint64_t cpu_ver; /* Niagara CPU version reg */ 74 75 /* Niagara CPU version register */ 76 #define VER_MASK_MAJOR_SHIFT 28 77 #define VER_MASK_MAJOR_MASK 0xf 78 79 extern uint64_t va_to_pa(void *); 80 extern uint64_t ni_getver(); /* HV code to get %hver */ 81 extern uint64_t niagara_getver(uint64_t ni_getver_ra, uint64_t *cpu_version); 82 83 #endif /* NIAGARA_CHK_VERSION */ 84 85 void 86 cpu_setup(void) 87 { 88 extern int at_flags; 89 extern int disable_delay_tlb_flush, delay_tlb_flush; 90 extern int mmu_exported_pagesize_mask; 91 extern int get_cpu_pagesizes(void); 92 extern int cpc_has_overflow_intr; 93 94 cache |= (CACHE_PTAG | CACHE_IOCOHERENT); 95 at_flags = EF_SPARC_SUN_US3 | EF_SPARC_32PLUS | EF_SPARC_SUN_US1; 96 97 /* 98 * Use the maximum number of contexts available for Spitfire unless 99 * it has been tuned for debugging. 100 * We are checking against 0 here since this value can be patched 101 * while booting. It can not be patched via /etc/system since it 102 * will be patched too late and thus cause the system to panic. 103 */ 104 if (nctxs == 0) 105 nctxs = MAX_NCTXS; 106 107 if (use_page_coloring) { 108 do_pg_coloring = 1; 109 if (use_virtual_coloring) 110 do_virtual_coloring = 1; 111 } 112 /* 113 * Initalize supported page sizes information before the PD. 114 * If no information is available, then initialize the 115 * mmu_exported_pagesize_mask to a reasonable value for that processor. 116 */ 117 mmu_exported_pagesize_mask = get_cpu_pagesizes(); 118 if (mmu_exported_pagesize_mask <= 0) { 119 mmu_exported_pagesize_mask = (1 << TTE8K) | (1 << TTE64K) | 120 (1 << TTE4M) | (1 << TTE256M); 121 } 122 123 /* 124 * Tune pp_slots to use up to 1/8th of the tlb entries. 125 */ 126 pp_slots = MIN(8, MAXPP_SLOTS); 127 128 /* 129 * Block stores invalidate all pages of the d$ so pagecopy 130 * et. al. do not need virtual translations with virtual 131 * coloring taken into consideration. 132 */ 133 pp_consistent_coloring = 0; 134 isa_list = 135 "sparcv9 sparcv8plus sparcv8 sparcv8-fsmuld sparcv7 " 136 "sparc sparcv9+vis sparcv9+vis2 sparcv8plus+vis sparcv8plus+vis2"; 137 138 cpu_hwcap_flags |= AV_SPARC_ASI_BLK_INIT; 139 140 /* 141 * Niagara supports a 48-bit subset of the full 64-bit virtual 142 * address space. Virtual addresses between 0x0000800000000000 143 * and 0xffff.7fff.ffff.ffff inclusive lie within a "VA Hole" 144 * and must never be mapped. In addition, software must not use 145 * pages within 4GB of the VA hole as instruction pages to 146 * avoid problems with prefetching into the VA hole. 147 * 148 * VA hole information should be obtained from the machine 149 * description. 150 */ 151 hole_start = (caddr_t)(0x800000000000ul - (1ul << 32)); 152 hole_end = (caddr_t)(0xffff800000000000ul + (1ul << 32)); 153 154 /* 155 * The kpm mapping window. 156 * kpm_size: 157 * The size of a single kpm range. 158 * The overall size will be: kpm_size * vac_colors. 159 * kpm_vbase: 160 * The virtual start address of the kpm range within the kernel 161 * virtual address space. kpm_vbase has to be kpm_size aligned. 162 */ 163 kpm_size = (size_t)(2ull * 1024 * 1024 * 1024 * 1024); /* 2TB */ 164 kpm_size_shift = 41; 165 kpm_vbase = (caddr_t)0xfffffa0000000000ull; /* 16EB - 6TB */ 166 167 /* 168 * The traptrace code uses either %tick or %stick for 169 * timestamping. We have %stick so we can use it. 170 */ 171 traptrace_use_stick = 1; 172 173 /* 174 * sun4v provides demap_all 175 */ 176 if (!disable_delay_tlb_flush) 177 delay_tlb_flush = 1; 178 /* 179 * Niagara has a performance counter overflow interrupt 180 */ 181 cpc_has_overflow_intr = 1; 182 } 183 184 #define MB * 1024 * 1024 185 /* 186 * Set the magic constants of the implementation. 187 */ 188 void 189 cpu_fiximp(struct cpu_node *cpunode) 190 { 191 extern int vac_size, vac_shift; 192 extern uint_t vac_mask; 193 int i, a; 194 195 /* 196 * The assumption here is that fillsysinfo will eventually 197 * have code to fill this info in from the PD. 198 * We hard code this for niagara now. 199 * Once the PD access library is done this code 200 * might need to be changed to get the info from the PD 201 */ 202 if (cpunode->ecache_size == 0) 203 cpunode->ecache_size = 3 MB; 204 if (cpunode->ecache_linesize == 0) 205 cpunode->ecache_linesize = 64; 206 if (cpunode->ecache_associativity == 0) 207 cpunode->ecache_associativity = 12; 208 209 cpunode->ecache_setsize = 210 cpunode->ecache_size / cpunode->ecache_associativity; 211 212 if (ecache_setsize == 0) 213 ecache_setsize = cpunode->ecache_setsize; 214 if (ecache_alignsize == 0) 215 ecache_alignsize = cpunode->ecache_linesize; 216 217 vac_size = S_VAC_SIZE; 218 vac_mask = MMU_PAGEMASK & (vac_size - 1); 219 i = 0; a = vac_size; 220 while (a >>= 1) 221 ++i; 222 vac_shift = i; 223 shm_alignment = vac_size; 224 vac = 0; 225 } 226 227 static int niagara_cpucnt; 228 229 void 230 cpu_init_private(struct cpu *cp) 231 { 232 extern int niagara_kstat_init(void); 233 234 #ifdef NIAGARA_CHK_VERSION 235 /* 236 * Prevent booting on a Niagara 1.x processor as it is no longer 237 * supported. 238 * 239 * This is a temporary hack until everyone has switched to the 240 * firmware which prevents booting on a Niagara 1.x processor. 241 */ 242 if (niagara_getver(va_to_pa((void *)ni_getver), &cpu_ver) == H_EOK && 243 ((cpu_ver >> VER_MASK_MAJOR_SHIFT) & VER_MASK_MAJOR_MASK) <= 1) 244 cmn_err(CE_PANIC, "CPU%d: Niagara 1.x no longer supported.", 245 cp->cpu_id); 246 #endif /* NIAGARA_CHK_VERSION */ 247 248 /* 249 * This code change assumes that the virtual cpu ids are identical 250 * to the physical cpu ids which is true for ontario but not for 251 * niagara in general. 252 * This is a temporary fix which will later be modified to obtain 253 * the execution unit sharing information from MD table. 254 */ 255 cp->cpu_m.cpu_ipipe = (id_t)(cp->cpu_id / 4); 256 257 ASSERT(MUTEX_HELD(&cpu_lock)); 258 if (niagara_cpucnt++ == 0) { 259 (void) niagara_kstat_init(); 260 } 261 } 262 263 void 264 cpu_uninit_private(struct cpu *cp) 265 { 266 extern int niagara_kstat_fini(void); 267 268 ASSERT(MUTEX_HELD(&cpu_lock)); 269 if (--niagara_cpucnt == 0) { 270 (void) niagara_kstat_fini(); 271 } 272 } 273 274 /* 275 * On Niagara, any flush will cause all preceding stores to be 276 * synchronized wrt the i$, regardless of address or ASI. In fact, 277 * the address is ignored, so we always flush address 0. 278 */ 279 void 280 dtrace_flush_sec(uintptr_t addr) 281 { 282 doflush(0); 283 } 284 285 #define IS_FLOAT(i) (((i) & 0x1000000) != 0) 286 #define IS_IBIT_SET(x) (x & 0x2000) 287 #define IS_VIS1(op, op3)(op == 2 && op3 == 0x36) 288 #define IS_PARTIAL_OR_SHORT_FLOAT_LD_ST(op, op3, asi) \ 289 (op == 3 && (op3 == IOP_V8_LDDFA || \ 290 op3 == IOP_V8_STDFA) && asi > ASI_SNFL) 291 int 292 vis1_partial_support(struct regs *rp, k_siginfo_t *siginfo, uint_t *fault) 293 { 294 char *badaddr; 295 int instr; 296 uint_t optype, op3, asi; 297 uint_t rd, ignor; 298 299 if (!USERMODE(rp->r_tstate)) 300 return (-1); 301 302 instr = fetch_user_instr((caddr_t)rp->r_pc); 303 304 rd = (instr >> 25) & 0x1f; 305 optype = (instr >> 30) & 0x3; 306 op3 = (instr >> 19) & 0x3f; 307 ignor = (instr >> 5) & 0xff; 308 if (IS_IBIT_SET(instr)) { 309 asi = (uint32_t)((rp->r_tstate >> TSTATE_ASI_SHIFT) & 310 TSTATE_ASI_MASK); 311 } else { 312 asi = ignor; 313 } 314 315 if (!IS_VIS1(optype, op3) && 316 !IS_PARTIAL_OR_SHORT_FLOAT_LD_ST(optype, op3, asi)) { 317 return (-1); 318 } 319 switch (simulate_unimp(rp, &badaddr)) { 320 case SIMU_RETRY: 321 break; /* regs are already set up */ 322 /*NOTREACHED*/ 323 324 case SIMU_SUCCESS: 325 /* 326 * skip the successfully 327 * simulated instruction 328 */ 329 rp->r_pc = rp->r_npc; 330 rp->r_npc += 4; 331 break; 332 /*NOTREACHED*/ 333 334 case SIMU_FAULT: 335 siginfo->si_signo = SIGSEGV; 336 siginfo->si_code = SEGV_MAPERR; 337 siginfo->si_addr = badaddr; 338 *fault = FLTBOUNDS; 339 break; 340 341 case SIMU_DZERO: 342 siginfo->si_signo = SIGFPE; 343 siginfo->si_code = FPE_INTDIV; 344 siginfo->si_addr = (caddr_t)rp->r_pc; 345 *fault = FLTIZDIV; 346 break; 347 348 case SIMU_UNALIGN: 349 siginfo->si_signo = SIGBUS; 350 siginfo->si_code = BUS_ADRALN; 351 siginfo->si_addr = badaddr; 352 *fault = FLTACCESS; 353 break; 354 355 case SIMU_ILLEGAL: 356 default: 357 siginfo->si_signo = SIGILL; 358 op3 = (instr >> 19) & 0x3F; 359 if ((IS_FLOAT(instr) && (op3 == IOP_V8_STQFA) || 360 (op3 == IOP_V8_STDFA))) 361 siginfo->si_code = ILL_ILLADR; 362 else 363 siginfo->si_code = ILL_ILLOPC; 364 siginfo->si_addr = (caddr_t)rp->r_pc; 365 *fault = FLTILL; 366 break; 367 } 368 return (0); 369 } 370 371 /* 372 * Trapstat support for Niagara processor 373 */ 374 int 375 cpu_trapstat_conf(int cmd) 376 { 377 size_t len; 378 uint64_t mmustat_pa, hvret; 379 int status = 0; 380 381 switch (cmd) { 382 case CPU_TSTATCONF_INIT: 383 ASSERT(cpu_tstat_va == NULL); 384 len = (NCPU+1) * sizeof (niagara_mmustat_t); 385 cpu_tstat_va = contig_mem_alloc_align(len, 386 sizeof (niagara_mmustat_t)); 387 if (cpu_tstat_va == NULL) 388 status = EAGAIN; 389 else { 390 bzero(cpu_tstat_va, len); 391 cpu_tstat_pa = va_to_pa(cpu_tstat_va); 392 } 393 break; 394 395 case CPU_TSTATCONF_FINI: 396 if (cpu_tstat_va) { 397 len = (NCPU+1) * sizeof (niagara_mmustat_t); 398 contig_mem_free(cpu_tstat_va, len); 399 cpu_tstat_va = NULL; 400 cpu_tstat_pa = 0; 401 } 402 break; 403 404 case CPU_TSTATCONF_ENABLE: 405 hvret = hv_niagara_mmustat_conf((cpu_tstat_pa + 406 (CPU->cpu_id+1) * sizeof (niagara_mmustat_t)), 407 (uint64_t *)&mmustat_pa); 408 if (hvret != H_EOK) 409 status = EINVAL; 410 break; 411 412 case CPU_TSTATCONF_DISABLE: 413 hvret = hv_niagara_mmustat_conf(0, (uint64_t *)&mmustat_pa); 414 if (hvret != H_EOK) 415 status = EINVAL; 416 break; 417 418 default: 419 status = EINVAL; 420 break; 421 } 422 return (status); 423 } 424 425 void 426 cpu_trapstat_data(void *buf, uint_t tstat_pgszs) 427 { 428 niagara_mmustat_t *mmustatp; 429 tstat_pgszdata_t *tstatp = (tstat_pgszdata_t *)buf; 430 int i, pgcnt; 431 432 if (cpu_tstat_va == NULL) 433 return; 434 435 mmustatp = &((niagara_mmustat_t *)cpu_tstat_va)[CPU->cpu_id+1]; 436 if (tstat_pgszs > NIAGARA_MMUSTAT_PGSZS) 437 tstat_pgszs = NIAGARA_MMUSTAT_PGSZS; 438 439 for (i = 0; i < tstat_pgszs; i++, tstatp++) { 440 tstatp->tpgsz_kernel.tmode_itlb.ttlb_tlb.tmiss_count = 441 mmustatp->kitsb[i].tsbhit_count; 442 tstatp->tpgsz_kernel.tmode_itlb.ttlb_tlb.tmiss_time = 443 mmustatp->kitsb[i].tsbhit_time; 444 tstatp->tpgsz_user.tmode_itlb.ttlb_tlb.tmiss_count = 445 mmustatp->uitsb[i].tsbhit_count; 446 tstatp->tpgsz_user.tmode_itlb.ttlb_tlb.tmiss_time = 447 mmustatp->uitsb[i].tsbhit_time; 448 tstatp->tpgsz_kernel.tmode_dtlb.ttlb_tlb.tmiss_count = 449 mmustatp->kdtsb[i].tsbhit_count; 450 tstatp->tpgsz_kernel.tmode_dtlb.ttlb_tlb.tmiss_time = 451 mmustatp->kdtsb[i].tsbhit_time; 452 tstatp->tpgsz_user.tmode_dtlb.ttlb_tlb.tmiss_count = 453 mmustatp->udtsb[i].tsbhit_count; 454 tstatp->tpgsz_user.tmode_dtlb.ttlb_tlb.tmiss_time = 455 mmustatp->udtsb[i].tsbhit_time; 456 } 457 } 458