1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/types.h> 30 #include <sys/systm.h> 31 #include <sys/archsystm.h> 32 #include <sys/machparam.h> 33 #include <sys/machsystm.h> 34 #include <sys/cpu.h> 35 #include <sys/elf_SPARC.h> 36 #include <vm/hat_sfmmu.h> 37 #include <vm/page.h> 38 #include <sys/cpuvar.h> 39 #include <sys/async.h> 40 #include <sys/cmn_err.h> 41 #include <sys/debug.h> 42 #include <sys/dditypes.h> 43 #include <sys/sunddi.h> 44 #include <sys/cpu_module.h> 45 #include <sys/prom_debug.h> 46 #include <sys/vmsystm.h> 47 #include <sys/prom_plat.h> 48 #include <sys/sysmacros.h> 49 #include <sys/intreg.h> 50 #include <sys/machtrap.h> 51 #include <sys/ontrap.h> 52 #include <sys/ivintr.h> 53 #include <sys/atomic.h> 54 #include <sys/panic.h> 55 #include <sys/dtrace.h> 56 #include <sys/simulate.h> 57 #include <sys/fault.h> 58 #include <sys/niagararegs.h> 59 #include <sys/trapstat.h> 60 #include <sys/hsvc.h> 61 62 #define NI_MMU_PAGESIZE_MASK ((1 << TTE8K) | (1 << TTE64K) | (1 << TTE4M) \ 63 | (1 << TTE256M)) 64 65 uint_t root_phys_addr_lo_mask = 0xffffffffU; 66 static niagara_mmustat_t *cpu_tstat_va; /* VA of mmustat buffer */ 67 static uint64_t cpu_tstat_pa; /* PA of mmustat buffer */ 68 char cpu_module_name[] = "SUNW,UltraSPARC-T1"; 69 70 /* 71 * Hypervisor services information for the NIAGARA CPU module 72 */ 73 static boolean_t niagara_hsvc_available = B_TRUE; 74 static uint64_t niagara_sup_minor; /* Supported minor number */ 75 static hsvc_info_t niagara_hsvc = { 76 HSVC_REV_1, NULL, HSVC_GROUP_NIAGARA_CPU, 1, 0, cpu_module_name 77 }; 78 79 void 80 cpu_setup(void) 81 { 82 extern int mmu_exported_pagesize_mask; 83 extern int cpc_has_overflow_intr; 84 int status; 85 char *ni_isa_set[] = { 86 "sparcv9+vis", 87 "sparcv9+vis2", 88 "sparcv8plus+vis", 89 "sparcv8plus+vis2", 90 NULL 91 }; 92 93 /* 94 * Negotiate the API version for Niagara specific hypervisor 95 * services. 96 */ 97 status = hsvc_register(&niagara_hsvc, &niagara_sup_minor); 98 if (status != 0) { 99 cmn_err(CE_WARN, "%s: cannot negotiate hypervisor services " 100 "group: 0x%lx major: 0x%lx minor: 0x%lx errno: %d\n", 101 niagara_hsvc.hsvc_modname, niagara_hsvc.hsvc_group, 102 niagara_hsvc.hsvc_major, niagara_hsvc.hsvc_minor, status); 103 niagara_hsvc_available = B_FALSE; 104 } 105 106 /* 107 * The setup common to all CPU modules is done in cpu_setup_common 108 * routine. 109 */ 110 cpu_setup_common(ni_isa_set); 111 112 cache |= (CACHE_PTAG | CACHE_IOCOHERENT); 113 114 if (broken_md_flag) { 115 /* 116 * Turn on the missing bits supported by Niagara CPU in 117 * MMU pagesize mask returned by MD. 118 */ 119 mmu_exported_pagesize_mask |= NI_MMU_PAGESIZE_MASK; 120 } else { 121 if ((mmu_exported_pagesize_mask & 122 DEFAULT_SUN4V_MMU_PAGESIZE_MASK) != 123 DEFAULT_SUN4V_MMU_PAGESIZE_MASK) 124 cmn_err(CE_PANIC, "machine description" 125 " does not have required sun4v page sizes" 126 " 8K, 64K and 4M: MD mask is 0x%x", 127 mmu_exported_pagesize_mask); 128 } 129 130 cpu_hwcap_flags |= AV_SPARC_ASI_BLK_INIT; 131 132 /* 133 * Niagara supports a 48-bit subset of the full 64-bit virtual 134 * address space. Virtual addresses between 0x0000800000000000 135 * and 0xffff.7fff.ffff.ffff inclusive lie within a "VA Hole" 136 * and must never be mapped. In addition, software must not use 137 * pages within 4GB of the VA hole as instruction pages to 138 * avoid problems with prefetching into the VA hole. 139 */ 140 hole_start = (caddr_t)((1ull << (va_bits - 1)) - (1ull << 32)); 141 hole_end = (caddr_t)((0ull - (1ull << (va_bits - 1))) + (1ull << 32)); 142 143 /* 144 * Niagara has a performance counter overflow interrupt 145 */ 146 cpc_has_overflow_intr = 1; 147 148 shctx_on = 0; 149 } 150 151 #define MB(n) ((n) * 1024 * 1024) 152 /* 153 * Set the magic constants of the implementation. 154 */ 155 void 156 cpu_fiximp(struct cpu_node *cpunode) 157 { 158 /* 159 * The Cache node is optional in MD. Therefore in case "Cache" 160 * node does not exists in MD, set the default L2 cache associativity, 161 * size, linesize. 162 */ 163 if (cpunode->ecache_size == 0) 164 cpunode->ecache_size = MB(3); 165 if (cpunode->ecache_linesize == 0) 166 cpunode->ecache_linesize = 64; 167 if (cpunode->ecache_associativity == 0) 168 cpunode->ecache_associativity = 12; 169 } 170 171 void 172 cpu_map_exec_units(struct cpu *cp) 173 { 174 ASSERT(MUTEX_HELD(&cpu_lock)); 175 176 /* 177 * The cpu_ipipe and cpu_fpu fields are initialized based on 178 * the execution unit sharing information from the MD. They 179 * default to the CPU id in the absence of such information. 180 */ 181 cp->cpu_m.cpu_ipipe = cpunodes[cp->cpu_id].exec_unit_mapping; 182 if (cp->cpu_m.cpu_ipipe == NO_EU_MAPPING_FOUND) 183 cp->cpu_m.cpu_ipipe = (id_t)(cp->cpu_id); 184 185 cp->cpu_m.cpu_fpu = cpunodes[cp->cpu_id].fpu_mapping; 186 if (cp->cpu_m.cpu_fpu == NO_EU_MAPPING_FOUND) 187 cp->cpu_m.cpu_fpu = (id_t)(cp->cpu_id); 188 189 /* 190 * Niagara defines the the core to be at the ipipe level 191 */ 192 cp->cpu_m.cpu_core = cp->cpu_m.cpu_ipipe; 193 } 194 195 static int niagara_cpucnt; 196 197 void 198 cpu_init_private(struct cpu *cp) 199 { 200 extern void niagara_kstat_init(void); 201 202 ASSERT(MUTEX_HELD(&cpu_lock)); 203 204 cpu_map_exec_units(cp); 205 206 if ((niagara_cpucnt++ == 0) && (niagara_hsvc_available == B_TRUE)) 207 niagara_kstat_init(); 208 } 209 210 /*ARGSUSED*/ 211 void 212 cpu_uninit_private(struct cpu *cp) 213 { 214 extern void niagara_kstat_fini(void); 215 216 ASSERT(MUTEX_HELD(&cpu_lock)); 217 218 if ((--niagara_cpucnt == 0) && (niagara_hsvc_available == B_TRUE)) 219 niagara_kstat_fini(); 220 } 221 222 /* 223 * On Niagara, any flush will cause all preceding stores to be 224 * synchronized wrt the i$, regardless of address or ASI. In fact, 225 * the address is ignored, so we always flush address 0. 226 */ 227 void 228 dtrace_flush_sec(uintptr_t addr) 229 { 230 doflush(0); 231 } 232 233 #define IS_FLOAT(i) (((i) & 0x1000000) != 0) 234 #define IS_IBIT_SET(x) (x & 0x2000) 235 #define IS_VIS1(op, op3)(op == 2 && op3 == 0x36) 236 #define IS_PARTIAL_OR_SHORT_FLOAT_LD_ST(op, op3, asi) \ 237 (op == 3 && (op3 == IOP_V8_LDDFA || \ 238 op3 == IOP_V8_STDFA) && asi > ASI_SNFL) 239 int 240 vis1_partial_support(struct regs *rp, k_siginfo_t *siginfo, uint_t *fault) 241 { 242 char *badaddr; 243 int instr; 244 uint_t optype, op3, asi; 245 uint_t rd, ignor; 246 247 if (!USERMODE(rp->r_tstate)) 248 return (-1); 249 250 instr = fetch_user_instr((caddr_t)rp->r_pc); 251 252 rd = (instr >> 25) & 0x1f; 253 optype = (instr >> 30) & 0x3; 254 op3 = (instr >> 19) & 0x3f; 255 ignor = (instr >> 5) & 0xff; 256 if (IS_IBIT_SET(instr)) { 257 asi = (uint32_t)((rp->r_tstate >> TSTATE_ASI_SHIFT) & 258 TSTATE_ASI_MASK); 259 } else { 260 asi = ignor; 261 } 262 263 if (!IS_VIS1(optype, op3) && 264 !IS_PARTIAL_OR_SHORT_FLOAT_LD_ST(optype, op3, asi)) { 265 return (-1); 266 } 267 switch (simulate_unimp(rp, &badaddr)) { 268 case SIMU_RETRY: 269 break; /* regs are already set up */ 270 /*NOTREACHED*/ 271 272 case SIMU_SUCCESS: 273 /* 274 * skip the successfully 275 * simulated instruction 276 */ 277 rp->r_pc = rp->r_npc; 278 rp->r_npc += 4; 279 break; 280 /*NOTREACHED*/ 281 282 case SIMU_FAULT: 283 siginfo->si_signo = SIGSEGV; 284 siginfo->si_code = SEGV_MAPERR; 285 siginfo->si_addr = badaddr; 286 *fault = FLTBOUNDS; 287 break; 288 289 case SIMU_DZERO: 290 siginfo->si_signo = SIGFPE; 291 siginfo->si_code = FPE_INTDIV; 292 siginfo->si_addr = (caddr_t)rp->r_pc; 293 *fault = FLTIZDIV; 294 break; 295 296 case SIMU_UNALIGN: 297 siginfo->si_signo = SIGBUS; 298 siginfo->si_code = BUS_ADRALN; 299 siginfo->si_addr = badaddr; 300 *fault = FLTACCESS; 301 break; 302 303 case SIMU_ILLEGAL: 304 default: 305 siginfo->si_signo = SIGILL; 306 op3 = (instr >> 19) & 0x3F; 307 if ((IS_FLOAT(instr) && (op3 == IOP_V8_STQFA) || 308 (op3 == IOP_V8_STDFA))) 309 siginfo->si_code = ILL_ILLADR; 310 else 311 siginfo->si_code = ILL_ILLOPC; 312 siginfo->si_addr = (caddr_t)rp->r_pc; 313 *fault = FLTILL; 314 break; 315 } 316 return (0); 317 } 318 319 /* 320 * Trapstat support for Niagara processor 321 */ 322 int 323 cpu_trapstat_conf(int cmd) 324 { 325 size_t len; 326 uint64_t mmustat_pa, hvret; 327 int status = 0; 328 329 if (niagara_hsvc_available == B_FALSE) 330 return (ENOTSUP); 331 332 switch (cmd) { 333 case CPU_TSTATCONF_INIT: 334 ASSERT(cpu_tstat_va == NULL); 335 len = (NCPU+1) * sizeof (niagara_mmustat_t); 336 cpu_tstat_va = contig_mem_alloc_align(len, 337 sizeof (niagara_mmustat_t)); 338 if (cpu_tstat_va == NULL) 339 status = EAGAIN; 340 else { 341 bzero(cpu_tstat_va, len); 342 cpu_tstat_pa = va_to_pa(cpu_tstat_va); 343 } 344 break; 345 346 case CPU_TSTATCONF_FINI: 347 if (cpu_tstat_va) { 348 len = (NCPU+1) * sizeof (niagara_mmustat_t); 349 contig_mem_free(cpu_tstat_va, len); 350 cpu_tstat_va = NULL; 351 cpu_tstat_pa = 0; 352 } 353 break; 354 355 case CPU_TSTATCONF_ENABLE: 356 hvret = hv_niagara_mmustat_conf((cpu_tstat_pa + 357 (CPU->cpu_id+1) * sizeof (niagara_mmustat_t)), 358 (uint64_t *)&mmustat_pa); 359 if (hvret != H_EOK) 360 status = EINVAL; 361 break; 362 363 case CPU_TSTATCONF_DISABLE: 364 hvret = hv_niagara_mmustat_conf(0, (uint64_t *)&mmustat_pa); 365 if (hvret != H_EOK) 366 status = EINVAL; 367 break; 368 369 default: 370 status = EINVAL; 371 break; 372 } 373 return (status); 374 } 375 376 void 377 cpu_trapstat_data(void *buf, uint_t tstat_pgszs) 378 { 379 niagara_mmustat_t *mmustatp; 380 tstat_pgszdata_t *tstatp = (tstat_pgszdata_t *)buf; 381 int i, pgcnt; 382 383 if (cpu_tstat_va == NULL) 384 return; 385 386 mmustatp = &((niagara_mmustat_t *)cpu_tstat_va)[CPU->cpu_id+1]; 387 if (tstat_pgszs > NIAGARA_MMUSTAT_PGSZS) 388 tstat_pgszs = NIAGARA_MMUSTAT_PGSZS; 389 390 for (i = 0; i < tstat_pgszs; i++, tstatp++) { 391 tstatp->tpgsz_kernel.tmode_itlb.ttlb_tlb.tmiss_count = 392 mmustatp->kitsb[i].tsbhit_count; 393 tstatp->tpgsz_kernel.tmode_itlb.ttlb_tlb.tmiss_time = 394 mmustatp->kitsb[i].tsbhit_time; 395 tstatp->tpgsz_user.tmode_itlb.ttlb_tlb.tmiss_count = 396 mmustatp->uitsb[i].tsbhit_count; 397 tstatp->tpgsz_user.tmode_itlb.ttlb_tlb.tmiss_time = 398 mmustatp->uitsb[i].tsbhit_time; 399 tstatp->tpgsz_kernel.tmode_dtlb.ttlb_tlb.tmiss_count = 400 mmustatp->kdtsb[i].tsbhit_count; 401 tstatp->tpgsz_kernel.tmode_dtlb.ttlb_tlb.tmiss_time = 402 mmustatp->kdtsb[i].tsbhit_time; 403 tstatp->tpgsz_user.tmode_dtlb.ttlb_tlb.tmiss_count = 404 mmustatp->udtsb[i].tsbhit_count; 405 tstatp->tpgsz_user.tmode_dtlb.ttlb_tlb.tmiss_time = 406 mmustatp->udtsb[i].tsbhit_time; 407 } 408 } 409