1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* Copyright (c) 1984, 1986, 1987, 1988, 1989 AT&T */ 27 /* All Rights Reserved */ 28 29 /* 30 * Portions of this source code were derived from Berkeley 4.3 BSD 31 * under license from the Regents of the University of California. 32 */ 33 34 #pragma ident "%Z%%M% %I% %E% SMI" 35 36 /* 37 * UNIX machine dependent virtual memory support. 38 */ 39 40 #include <sys/vm.h> 41 #include <sys/exec.h> 42 #include <sys/cmn_err.h> 43 #include <sys/cpu_module.h> 44 #include <sys/cpu.h> 45 #include <sys/elf_SPARC.h> 46 #include <sys/archsystm.h> 47 #include <vm/hat_sfmmu.h> 48 #include <sys/memnode.h> 49 #include <sys/mem_cage.h> 50 #include <vm/vm_dep.h> 51 52 #if defined(__sparcv9) && defined(SF_ERRATA_57) 53 caddr_t errata57_limit; 54 #endif 55 56 uint_t page_colors = 0; 57 uint_t page_colors_mask = 0; 58 uint_t page_coloring_shift = 0; 59 int consistent_coloring; 60 61 uint_t mmu_page_sizes = DEFAULT_MMU_PAGE_SIZES; 62 uint_t max_mmu_page_sizes = MMU_PAGE_SIZES; 63 uint_t mmu_hashcnt = DEFAULT_MAX_HASHCNT; 64 uint_t max_mmu_hashcnt = MAX_HASHCNT; 65 size_t mmu_ism_pagesize = DEFAULT_ISM_PAGESIZE; 66 67 /* 68 * The sun4u hardware mapping sizes which will always be supported are 69 * 8K, 64K, 512K and 4M. If sun4u based machines need to support other 70 * page sizes, platform or cpu specific routines need to modify the value. 71 * The base pagesize (p_szc == 0) must always be supported by the hardware. 72 */ 73 int mmu_exported_pagesize_mask = (1 << TTE8K) | (1 << TTE64K) | 74 (1 << TTE512K) | (1 << TTE4M); 75 uint_t mmu_exported_page_sizes; 76 77 uint_t szc_2_userszc[MMU_PAGE_SIZES]; 78 uint_t userszc_2_szc[MMU_PAGE_SIZES]; 79 80 extern uint_t vac_colors_mask; 81 extern int vac_shift; 82 83 hw_pagesize_t hw_page_array[] = { 84 {MMU_PAGESIZE, MMU_PAGESHIFT, 0, MMU_PAGESIZE >> MMU_PAGESHIFT}, 85 {MMU_PAGESIZE64K, MMU_PAGESHIFT64K, 0, 86 MMU_PAGESIZE64K >> MMU_PAGESHIFT}, 87 {MMU_PAGESIZE512K, MMU_PAGESHIFT512K, 0, 88 MMU_PAGESIZE512K >> MMU_PAGESHIFT}, 89 {MMU_PAGESIZE4M, MMU_PAGESHIFT4M, 0, MMU_PAGESIZE4M >> MMU_PAGESHIFT}, 90 {MMU_PAGESIZE32M, MMU_PAGESHIFT32M, 0, 91 MMU_PAGESIZE32M >> MMU_PAGESHIFT}, 92 {MMU_PAGESIZE256M, MMU_PAGESHIFT256M, 0, 93 MMU_PAGESIZE256M >> MMU_PAGESHIFT}, 94 {0, 0, 0, 0} 95 }; 96 97 /* 98 * use_text_pgsz64k, use_initdata_pgsz64k and use_text_pgsz4m 99 * can be set in platform or CPU specific code but user can change the 100 * default values via /etc/system. 101 */ 102 103 int use_text_pgsz64k = 0; 104 int use_text_pgsz4m = 0; 105 int use_initdata_pgsz64k = 0; 106 107 /* 108 * disable_text_largepages and disable_initdata_largepages bitmaks are set in 109 * platform or CPU specific code to disable page sizes that should not be 110 * used. These variables normally shouldn't be changed via /etc/system. A 111 * particular page size for text or inititialized data will be used by default 112 * if both one of use_* variables is set to 1 AND this page size is not 113 * disabled in the corresponding disable_* bitmask variable. 114 */ 115 116 int disable_text_largepages = (1 << TTE4M) | (1 << TTE64K); 117 int disable_initdata_largepages = (1 << TTE64K); 118 119 /* 120 * Minimum segment size tunables before 64K or 4M large pages 121 * should be used to map it. 122 */ 123 size_t text_pgsz64k_minsize = MMU_PAGESIZE64K; 124 size_t text_pgsz4m_minsize = MMU_PAGESIZE4M; 125 size_t initdata_pgsz64k_minsize = MMU_PAGESIZE64K; 126 127 size_t max_shm_lpsize = ULONG_MAX; 128 129 /* 130 * Platforms with smaller or larger TLBs may wish to change this. Most 131 * sun4u platforms can hold 1024 8K entries by default and most processes 132 * are observed to be < 6MB on these machines, so we decide to move up 133 * here to give ourselves some wiggle room for other, smaller segments. 134 */ 135 int auto_lpg_tlb_threshold = 768; 136 int auto_lpg_minszc = TTE4M; 137 int auto_lpg_maxszc = TTE4M; 138 size_t auto_lpg_heap_default = MMU_PAGESIZE; 139 size_t auto_lpg_stack_default = MMU_PAGESIZE; 140 size_t auto_lpg_va_default = MMU_PAGESIZE; 141 size_t auto_lpg_remap_threshold = 0; 142 /* 143 * Number of pages in 1 GB. Don't enable automatic large pages if we have 144 * fewer than this many pages. 145 */ 146 pgcnt_t auto_lpg_min_physmem = 1 << (30 - MMU_PAGESHIFT); 147 148 /* 149 * map_addr_proc() is the routine called when the system is to 150 * choose an address for the user. We will pick an address 151 * range which is just below the current stack limit. The 152 * algorithm used for cache consistency on machines with virtual 153 * address caches is such that offset 0 in the vnode is always 154 * on a shm_alignment'ed aligned address. Unfortunately, this 155 * means that vnodes which are demand paged will not be mapped 156 * cache consistently with the executable images. When the 157 * cache alignment for a given object is inconsistent, the 158 * lower level code must manage the translations so that this 159 * is not seen here (at the cost of efficiency, of course). 160 * 161 * addrp is a value/result parameter. 162 * On input it is a hint from the user to be used in a completely 163 * machine dependent fashion. For MAP_ALIGN, addrp contains the 164 * minimal alignment. 165 * 166 * On output it is NULL if no address can be found in the current 167 * processes address space or else an address that is currently 168 * not mapped for len bytes with a page of red zone on either side. 169 * If vacalign is true, then the selected address will obey the alignment 170 * constraints of a vac machine based on the given off value. 171 */ 172 /*ARGSUSED4*/ 173 void 174 map_addr_proc(caddr_t *addrp, size_t len, offset_t off, int vacalign, 175 caddr_t userlimit, struct proc *p, uint_t flags) 176 { 177 struct as *as = p->p_as; 178 caddr_t addr; 179 caddr_t base; 180 size_t slen; 181 uintptr_t align_amount; 182 int allow_largepage_alignment = 1; 183 184 base = p->p_brkbase; 185 if (userlimit < as->a_userlimit) { 186 /* 187 * This happens when a program wants to map something in 188 * a range that's accessible to a program in a smaller 189 * address space. For example, a 64-bit program might 190 * be calling mmap32(2) to guarantee that the returned 191 * address is below 4Gbytes. 192 */ 193 ASSERT(userlimit > base); 194 slen = userlimit - base; 195 } else { 196 slen = p->p_usrstack - base - (((size_t)rctl_enforced_value( 197 rctlproc_legacy[RLIMIT_STACK], p->p_rctls, p) + PAGEOFFSET) 198 & PAGEMASK); 199 } 200 len = (len + PAGEOFFSET) & PAGEMASK; 201 202 /* 203 * Redzone for each side of the request. This is done to leave 204 * one page unmapped between segments. This is not required, but 205 * it's useful for the user because if their program strays across 206 * a segment boundary, it will catch a fault immediately making 207 * debugging a little easier. 208 */ 209 len += (2 * PAGESIZE); 210 211 /* 212 * If the request is larger than the size of a particular 213 * mmu level, then we use that level to map the request. 214 * But this requires that both the virtual and the physical 215 * addresses be aligned with respect to that level, so we 216 * do the virtual bit of nastiness here. 217 * 218 * For 32-bit processes, only those which have specified 219 * MAP_ALIGN or an addr will be aligned on a page size > 4MB. Otherwise 220 * we can potentially waste up to 256MB of the 4G process address 221 * space just for alignment. 222 */ 223 if (p->p_model == DATAMODEL_ILP32 && ((flags & MAP_ALIGN) == 0 || 224 ((uintptr_t)*addrp) != 0)) { 225 allow_largepage_alignment = 0; 226 } 227 if ((mmu_page_sizes == max_mmu_page_sizes) && 228 allow_largepage_alignment && 229 (len >= MMU_PAGESIZE256M)) { /* 256MB mappings */ 230 align_amount = MMU_PAGESIZE256M; 231 } else if ((mmu_page_sizes == max_mmu_page_sizes) && 232 allow_largepage_alignment && 233 (len >= MMU_PAGESIZE32M)) { /* 32MB mappings */ 234 align_amount = MMU_PAGESIZE32M; 235 } else if (len >= MMU_PAGESIZE4M) { /* 4MB mappings */ 236 align_amount = MMU_PAGESIZE4M; 237 } else if (len >= MMU_PAGESIZE512K) { /* 512KB mappings */ 238 align_amount = MMU_PAGESIZE512K; 239 } else if (len >= MMU_PAGESIZE64K) { /* 64KB mappings */ 240 align_amount = MMU_PAGESIZE64K; 241 } else { 242 /* 243 * Align virtual addresses on a 64K boundary to ensure 244 * that ELF shared libraries are mapped with the appropriate 245 * alignment constraints by the run-time linker. 246 */ 247 align_amount = ELF_SPARC_MAXPGSZ; 248 if ((flags & MAP_ALIGN) && ((uintptr_t)*addrp != 0) && 249 ((uintptr_t)*addrp < align_amount)) 250 align_amount = (uintptr_t)*addrp; 251 } 252 253 /* 254 * 64-bit processes require 1024K alignment of ELF shared libraries. 255 */ 256 if (p->p_model == DATAMODEL_LP64) 257 align_amount = MAX(align_amount, ELF_SPARCV9_MAXPGSZ); 258 #ifdef VAC 259 if (vac && vacalign && (align_amount < shm_alignment)) 260 align_amount = shm_alignment; 261 #endif 262 263 if ((flags & MAP_ALIGN) && ((uintptr_t)*addrp > align_amount)) { 264 align_amount = (uintptr_t)*addrp; 265 } 266 len += align_amount; 267 268 /* 269 * Look for a large enough hole starting below the stack limit. 270 * After finding it, use the upper part. Addition of PAGESIZE is 271 * for the redzone as described above. 272 */ 273 as_purge(as); 274 if (as_gap(as, len, &base, &slen, AH_HI, NULL) == 0) { 275 caddr_t as_addr; 276 277 addr = base + slen - len + PAGESIZE; 278 as_addr = addr; 279 /* 280 * Round address DOWN to the alignment amount, 281 * add the offset, and if this address is less 282 * than the original address, add alignment amount. 283 */ 284 addr = (caddr_t)((uintptr_t)addr & (~(align_amount - 1l))); 285 addr += (long)(off & (align_amount - 1l)); 286 if (addr < as_addr) { 287 addr += align_amount; 288 } 289 290 ASSERT(addr <= (as_addr + align_amount)); 291 ASSERT(((uintptr_t)addr & (align_amount - 1l)) == 292 ((uintptr_t)(off & (align_amount - 1l)))); 293 *addrp = addr; 294 295 #if defined(SF_ERRATA_57) 296 if (AS_TYPE_64BIT(as) && addr < errata57_limit) { 297 *addrp = NULL; 298 } 299 #endif 300 } else { 301 *addrp = NULL; /* no more virtual space */ 302 } 303 } 304 305 /* 306 * Platform-dependent page scrub call. 307 */ 308 void 309 pagescrub(page_t *pp, uint_t off, uint_t len) 310 { 311 /* 312 * For now, we rely on the fact that pagezero() will 313 * always clear UEs. 314 */ 315 pagezero(pp, off, len); 316 } 317 318 /*ARGSUSED*/ 319 void 320 sync_data_memory(caddr_t va, size_t len) 321 { 322 cpu_flush_ecache(); 323 } 324 325 /* 326 * platform specific large pages for kernel heap support 327 */ 328 void 329 mmu_init_kcontext() 330 { 331 extern void set_kcontextreg(); 332 333 if (kcontextreg) 334 set_kcontextreg(); 335 } 336 337 void 338 contig_mem_init(void) 339 { 340 /* not applicable to sun4u */ 341 } 342