1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* Copyright (c) 1984, 1986, 1987, 1988, 1989 AT&T */ 28 /* All Rights Reserved */ 29 30 /* 31 * Portions of this source code were derived from Berkeley 4.3 BSD 32 * under license from the Regents of the University of California. 33 */ 34 35 #pragma ident "%Z%%M% %I% %E% SMI" 36 37 /* 38 * UNIX machine dependent virtual memory support. 39 */ 40 41 #include <sys/vm.h> 42 #include <sys/exec.h> 43 #include <sys/cmn_err.h> 44 #include <sys/cpu_module.h> 45 #include <sys/cpu.h> 46 #include <sys/elf_SPARC.h> 47 #include <sys/archsystm.h> 48 #include <vm/hat_sfmmu.h> 49 #include <sys/memnode.h> 50 #include <sys/mem_cage.h> 51 #include <vm/vm_dep.h> 52 53 #if defined(__sparcv9) && defined(SF_ERRATA_57) 54 caddr_t errata57_limit; 55 #endif 56 57 uint_t page_colors = 0; 58 uint_t page_colors_mask = 0; 59 uint_t page_coloring_shift = 0; 60 int consistent_coloring; 61 62 uint_t mmu_page_sizes = DEFAULT_MMU_PAGE_SIZES; 63 uint_t max_mmu_page_sizes = MMU_PAGE_SIZES; 64 uint_t mmu_hashcnt = DEFAULT_MAX_HASHCNT; 65 uint_t max_mmu_hashcnt = MAX_HASHCNT; 66 size_t mmu_ism_pagesize = DEFAULT_ISM_PAGESIZE; 67 68 /* 69 * The sun4u hardware mapping sizes which will always be supported are 70 * 8K, 64K, 512K and 4M. If sun4u based machines need to support other 71 * page sizes, platform or cpu specific routines need to modify the value. 72 * The base pagesize (p_szc == 0) must always be supported by the hardware. 73 */ 74 int mmu_exported_pagesize_mask = (1 << TTE8K) | (1 << TTE64K) | 75 (1 << TTE512K) | (1 << TTE4M); 76 uint_t mmu_exported_page_sizes; 77 78 uint_t szc_2_userszc[MMU_PAGE_SIZES]; 79 uint_t userszc_2_szc[MMU_PAGE_SIZES]; 80 81 extern uint_t vac_colors_mask; 82 extern int vac_shift; 83 84 hw_pagesize_t hw_page_array[] = { 85 {MMU_PAGESIZE, MMU_PAGESHIFT, MMU_PAGESIZE >> MMU_PAGESHIFT}, 86 {MMU_PAGESIZE64K, MMU_PAGESHIFT64K, MMU_PAGESIZE64K >> MMU_PAGESHIFT}, 87 {MMU_PAGESIZE512K, MMU_PAGESHIFT512K, 88 MMU_PAGESIZE512K >> MMU_PAGESHIFT}, 89 {MMU_PAGESIZE4M, MMU_PAGESHIFT4M, MMU_PAGESIZE4M >> MMU_PAGESHIFT}, 90 {MMU_PAGESIZE32M, MMU_PAGESHIFT32M, MMU_PAGESIZE32M >> MMU_PAGESHIFT}, 91 {MMU_PAGESIZE256M, MMU_PAGESHIFT256M, 92 MMU_PAGESIZE256M >> MMU_PAGESHIFT}, 93 {0, 0, 0} 94 }; 95 96 /* 97 * use_text_pgsz64k, use_initdata_pgsz64k and use_text_pgsz4m 98 * can be set in platform or CPU specific code but user can change the 99 * default values via /etc/system. 100 */ 101 102 int use_text_pgsz64k = 0; 103 int use_text_pgsz4m = 0; 104 int use_initdata_pgsz64k = 0; 105 106 /* 107 * disable_text_largepages and disable_initdata_largepages bitmaks are set in 108 * platform or CPU specific code to disable page sizes that should not be 109 * used. These variables normally shouldn't be changed via /etc/system. A 110 * particular page size for text or inititialized data will be used by default 111 * if both one of use_* variables is set to 1 AND this page size is not 112 * disabled in the corresponding disable_* bitmask variable. 113 */ 114 115 int disable_text_largepages = (1 << TTE4M) | (1 << TTE64K); 116 int disable_initdata_largepages = (1 << TTE64K); 117 118 /* 119 * Minimum segment size tunables before 64K or 4M large pages 120 * should be used to map it. 121 */ 122 size_t text_pgsz64k_minsize = MMU_PAGESIZE64K; 123 size_t text_pgsz4m_minsize = MMU_PAGESIZE4M; 124 size_t initdata_pgsz64k_minsize = MMU_PAGESIZE64K; 125 126 /* 127 * map_addr_proc() is the routine called when the system is to 128 * choose an address for the user. We will pick an address 129 * range which is just below the current stack limit. The 130 * algorithm used for cache consistency on machines with virtual 131 * address caches is such that offset 0 in the vnode is always 132 * on a shm_alignment'ed aligned address. Unfortunately, this 133 * means that vnodes which are demand paged will not be mapped 134 * cache consistently with the executable images. When the 135 * cache alignment for a given object is inconsistent, the 136 * lower level code must manage the translations so that this 137 * is not seen here (at the cost of efficiency, of course). 138 * 139 * addrp is a value/result parameter. 140 * On input it is a hint from the user to be used in a completely 141 * machine dependent fashion. For MAP_ALIGN, addrp contains the 142 * minimal alignment. 143 * 144 * On output it is NULL if no address can be found in the current 145 * processes address space or else an address that is currently 146 * not mapped for len bytes with a page of red zone on either side. 147 * If vacalign is true, then the selected address will obey the alignment 148 * constraints of a vac machine based on the given off value. 149 */ 150 /*ARGSUSED4*/ 151 void 152 map_addr_proc(caddr_t *addrp, size_t len, offset_t off, int vacalign, 153 caddr_t userlimit, struct proc *p, uint_t flags) 154 { 155 struct as *as = p->p_as; 156 caddr_t addr; 157 caddr_t base; 158 size_t slen; 159 uintptr_t align_amount; 160 int allow_largepage_alignment = 1; 161 162 base = p->p_brkbase; 163 if (userlimit < as->a_userlimit) { 164 /* 165 * This happens when a program wants to map something in 166 * a range that's accessible to a program in a smaller 167 * address space. For example, a 64-bit program might 168 * be calling mmap32(2) to guarantee that the returned 169 * address is below 4Gbytes. 170 */ 171 ASSERT(userlimit > base); 172 slen = userlimit - base; 173 } else { 174 slen = p->p_usrstack - base - (((size_t)rctl_enforced_value( 175 rctlproc_legacy[RLIMIT_STACK], p->p_rctls, p) + PAGEOFFSET) 176 & PAGEMASK); 177 } 178 len = (len + PAGEOFFSET) & PAGEMASK; 179 180 /* 181 * Redzone for each side of the request. This is done to leave 182 * one page unmapped between segments. This is not required, but 183 * it's useful for the user because if their program strays across 184 * a segment boundary, it will catch a fault immediately making 185 * debugging a little easier. 186 */ 187 len += (2 * PAGESIZE); 188 189 /* 190 * If the request is larger than the size of a particular 191 * mmu level, then we use that level to map the request. 192 * But this requires that both the virtual and the physical 193 * addresses be aligned with respect to that level, so we 194 * do the virtual bit of nastiness here. 195 * 196 * For 32-bit processes, only those which have specified 197 * MAP_ALIGN or an addr will be aligned on a page size > 4MB. Otherwise 198 * we can potentially waste up to 256MB of the 4G process address 199 * space just for alignment. 200 */ 201 if (p->p_model == DATAMODEL_ILP32 && ((flags & MAP_ALIGN) == 0 || 202 ((uintptr_t)*addrp) != 0)) { 203 allow_largepage_alignment = 0; 204 } 205 if ((mmu_page_sizes == max_mmu_page_sizes) && 206 allow_largepage_alignment && 207 (len >= MMU_PAGESIZE256M)) { /* 256MB mappings */ 208 align_amount = MMU_PAGESIZE256M; 209 } else if ((mmu_page_sizes == max_mmu_page_sizes) && 210 allow_largepage_alignment && 211 (len >= MMU_PAGESIZE32M)) { /* 32MB mappings */ 212 align_amount = MMU_PAGESIZE32M; 213 } else if (len >= MMU_PAGESIZE4M) { /* 4MB mappings */ 214 align_amount = MMU_PAGESIZE4M; 215 } else if (len >= MMU_PAGESIZE512K) { /* 512KB mappings */ 216 align_amount = MMU_PAGESIZE512K; 217 } else if (len >= MMU_PAGESIZE64K) { /* 64KB mappings */ 218 align_amount = MMU_PAGESIZE64K; 219 } else { 220 /* 221 * Align virtual addresses on a 64K boundary to ensure 222 * that ELF shared libraries are mapped with the appropriate 223 * alignment constraints by the run-time linker. 224 */ 225 align_amount = ELF_SPARC_MAXPGSZ; 226 if ((flags & MAP_ALIGN) && ((uintptr_t)*addrp != 0) && 227 ((uintptr_t)*addrp < align_amount)) 228 align_amount = (uintptr_t)*addrp; 229 } 230 231 /* 232 * 64-bit processes require 1024K alignment of ELF shared libraries. 233 */ 234 if (p->p_model == DATAMODEL_LP64) 235 align_amount = MAX(align_amount, ELF_SPARCV9_MAXPGSZ); 236 #ifdef VAC 237 if (vac && vacalign && (align_amount < shm_alignment)) 238 align_amount = shm_alignment; 239 #endif 240 241 if ((flags & MAP_ALIGN) && ((uintptr_t)*addrp > align_amount)) { 242 align_amount = (uintptr_t)*addrp; 243 } 244 len += align_amount; 245 246 /* 247 * Look for a large enough hole starting below the stack limit. 248 * After finding it, use the upper part. Addition of PAGESIZE is 249 * for the redzone as described above. 250 */ 251 as_purge(as); 252 if (as_gap(as, len, &base, &slen, AH_HI, NULL) == 0) { 253 caddr_t as_addr; 254 255 addr = base + slen - len + PAGESIZE; 256 as_addr = addr; 257 /* 258 * Round address DOWN to the alignment amount, 259 * add the offset, and if this address is less 260 * than the original address, add alignment amount. 261 */ 262 addr = (caddr_t)((uintptr_t)addr & (~(align_amount - 1l))); 263 addr += (long)(off & (align_amount - 1l)); 264 if (addr < as_addr) { 265 addr += align_amount; 266 } 267 268 ASSERT(addr <= (as_addr + align_amount)); 269 ASSERT(((uintptr_t)addr & (align_amount - 1l)) == 270 ((uintptr_t)(off & (align_amount - 1l)))); 271 *addrp = addr; 272 273 #if defined(SF_ERRATA_57) 274 if (AS_TYPE_64BIT(as) && addr < errata57_limit) { 275 *addrp = NULL; 276 } 277 #endif 278 } else { 279 *addrp = NULL; /* no more virtual space */ 280 } 281 } 282 283 /* 284 * Platforms with smaller or larger TLBs may wish to change this. Most 285 * sun4u platforms can hold 1024 8K entries by default and most processes 286 * are observed to be < 6MB on these machines, so we decide to move up 287 * here to give ourselves some wiggle room for other, smaller segments. 288 */ 289 int auto_lpg_tlb_threshold = 768; 290 int auto_lpg_minszc = TTE4M; 291 int auto_lpg_maxszc = TTE4M; 292 size_t auto_lpg_heap_default = MMU_PAGESIZE; 293 size_t auto_lpg_stack_default = MMU_PAGESIZE; 294 size_t auto_lpg_va_default = MMU_PAGESIZE; 295 size_t auto_lpg_remap_threshold = 0; 296 297 /* 298 * Suggest a page size to be used to map a segment of type maptype and length 299 * len. Returns a page size (not a size code). 300 * If remap is non-NULL, fill in a value suggesting whether or not to remap 301 * this segment. 302 */ 303 size_t 304 map_pgsz(int maptype, struct proc *p, caddr_t addr, size_t len, int *remap) 305 { 306 uint_t n; 307 size_t pgsz = 0; 308 309 if (remap) 310 *remap = (len > auto_lpg_remap_threshold); 311 312 switch (maptype) { 313 case MAPPGSZ_ISM: 314 n = hat_preferred_pgsz(p->p_as->a_hat, addr, len, maptype); 315 pgsz = hw_page_array[n].hp_size; 316 317 /* 318 * For non-Panther systems, the following code sets the [D]ISM 319 * pagesize to 4M if either of the DTLBs happens to be 320 * programmed to a different large pagesize. 321 * The Panther code might hit this case as well, 322 * if and only if the addr is not aligned to >= 4M. 323 */ 324 if ((pgsz > 0) && (pgsz < MMU_PAGESIZE4M)) 325 pgsz = MMU_PAGESIZE4M; 326 break; 327 328 case MAPPGSZ_VA: 329 n = hat_preferred_pgsz(p->p_as->a_hat, addr, len, maptype); 330 pgsz = hw_page_array[n].hp_size; 331 if ((pgsz <= MMU_PAGESIZE) || 332 !IS_P2ALIGNED(addr, pgsz) || !IS_P2ALIGNED(len, pgsz)) 333 pgsz = map_pgszva(p, addr, len); 334 break; 335 336 case MAPPGSZ_STK: 337 pgsz = map_pgszstk(p, addr, len); 338 break; 339 340 case MAPPGSZ_HEAP: 341 pgsz = map_pgszheap(p, addr, len); 342 break; 343 } 344 return (pgsz); 345 } 346 347 /* 348 * Platform-dependent page scrub call. 349 */ 350 void 351 pagescrub(page_t *pp, uint_t off, uint_t len) 352 { 353 /* 354 * For now, we rely on the fact that pagezero() will 355 * always clear UEs. 356 */ 357 pagezero(pp, off, len); 358 } 359 360 /*ARGSUSED*/ 361 void 362 sync_data_memory(caddr_t va, size_t len) 363 { 364 cpu_flush_ecache(); 365 } 366 367 /* 368 * platform specific large pages for kernel heap support 369 */ 370 void 371 mmu_init_kcontext() 372 { 373 extern void set_kcontextreg(); 374 375 if (kcontextreg) 376 set_kcontextreg(); 377 } 378 379 void 380 contig_mem_init(void) 381 { 382 /* not applicable to sun4u */ 383 } 384