17c478bd9Sstevel@tonic-gate /*
27c478bd9Sstevel@tonic-gate * CDDL HEADER START
37c478bd9Sstevel@tonic-gate *
47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the
525cf1a30Sjl139090 * Common Development and Distribution License (the "License").
625cf1a30Sjl139090 * You may not use this file except in compliance with the License.
77c478bd9Sstevel@tonic-gate *
87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing.
107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions
117c478bd9Sstevel@tonic-gate * and limitations under the License.
127c478bd9Sstevel@tonic-gate *
137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each
147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the
167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying
177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner]
187c478bd9Sstevel@tonic-gate *
197c478bd9Sstevel@tonic-gate * CDDL HEADER END
207c478bd9Sstevel@tonic-gate */
217c478bd9Sstevel@tonic-gate /*
2225cf1a30Sjl139090 * Copyright 2006 Sun Microsystems, Inc. All rights reserved.
237c478bd9Sstevel@tonic-gate * Use is subject to license terms.
247c478bd9Sstevel@tonic-gate */
257c478bd9Sstevel@tonic-gate
267c478bd9Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI"
277c478bd9Sstevel@tonic-gate
287c478bd9Sstevel@tonic-gate #include <sys/types.h>
297c478bd9Sstevel@tonic-gate #include <vm/hat.h>
307c478bd9Sstevel@tonic-gate #include <vm/hat_sfmmu.h>
317c478bd9Sstevel@tonic-gate #include <vm/page.h>
327c478bd9Sstevel@tonic-gate #include <sys/pte.h>
337c478bd9Sstevel@tonic-gate #include <sys/systm.h>
347c478bd9Sstevel@tonic-gate #include <sys/mman.h>
357c478bd9Sstevel@tonic-gate #include <sys/sysmacros.h>
367c478bd9Sstevel@tonic-gate #include <sys/machparam.h>
377c478bd9Sstevel@tonic-gate #include <sys/vtrace.h>
387c478bd9Sstevel@tonic-gate #include <sys/kmem.h>
397c478bd9Sstevel@tonic-gate #include <sys/mmu.h>
407c478bd9Sstevel@tonic-gate #include <sys/cmn_err.h>
417c478bd9Sstevel@tonic-gate #include <sys/cpu.h>
427c478bd9Sstevel@tonic-gate #include <sys/cpuvar.h>
437c478bd9Sstevel@tonic-gate #include <sys/debug.h>
447c478bd9Sstevel@tonic-gate #include <sys/lgrp.h>
457c478bd9Sstevel@tonic-gate #include <sys/archsystm.h>
467c478bd9Sstevel@tonic-gate #include <sys/machsystm.h>
477c478bd9Sstevel@tonic-gate #include <sys/vmsystm.h>
487c478bd9Sstevel@tonic-gate #include <sys/bitmap.h>
497c478bd9Sstevel@tonic-gate #include <vm/rm.h>
507c478bd9Sstevel@tonic-gate #include <sys/t_lock.h>
517c478bd9Sstevel@tonic-gate #include <sys/vm_machparam.h>
527c478bd9Sstevel@tonic-gate #include <sys/promif.h>
537c478bd9Sstevel@tonic-gate #include <sys/prom_isa.h>
547c478bd9Sstevel@tonic-gate #include <sys/prom_plat.h>
557c478bd9Sstevel@tonic-gate #include <sys/prom_debug.h>
567c478bd9Sstevel@tonic-gate #include <sys/privregs.h>
577c478bd9Sstevel@tonic-gate #include <sys/bootconf.h>
587c478bd9Sstevel@tonic-gate #include <sys/memlist.h>
597c478bd9Sstevel@tonic-gate #include <sys/memlist_plat.h>
607c478bd9Sstevel@tonic-gate #include <sys/cpu_module.h>
617c478bd9Sstevel@tonic-gate #include <sys/reboot.h>
627c478bd9Sstevel@tonic-gate #include <sys/kdi.h>
637c478bd9Sstevel@tonic-gate #include <sys/fpu/fpusystm.h>
647c478bd9Sstevel@tonic-gate
657c478bd9Sstevel@tonic-gate /*
667c478bd9Sstevel@tonic-gate * External routines and data structures
677c478bd9Sstevel@tonic-gate */
687c478bd9Sstevel@tonic-gate extern void sfmmu_cache_flushcolor(int, pfn_t);
697c478bd9Sstevel@tonic-gate
707c478bd9Sstevel@tonic-gate /*
717c478bd9Sstevel@tonic-gate * Static routines
727c478bd9Sstevel@tonic-gate */
737c478bd9Sstevel@tonic-gate static void sfmmu_set_tlb(void);
747c478bd9Sstevel@tonic-gate
757c478bd9Sstevel@tonic-gate /*
767c478bd9Sstevel@tonic-gate * Global Data:
777c478bd9Sstevel@tonic-gate */
787c478bd9Sstevel@tonic-gate caddr_t textva, datava;
797c478bd9Sstevel@tonic-gate tte_t ktext_tte, kdata_tte; /* ttes for kernel text and data */
807c478bd9Sstevel@tonic-gate
817c478bd9Sstevel@tonic-gate int enable_bigktsb = 1;
827c478bd9Sstevel@tonic-gate
837c478bd9Sstevel@tonic-gate tte_t bigktsb_ttes[MAX_BIGKTSB_TTES];
847c478bd9Sstevel@tonic-gate int bigktsb_nttes = 0;
857c478bd9Sstevel@tonic-gate
867c478bd9Sstevel@tonic-gate
877c478bd9Sstevel@tonic-gate /*
887c478bd9Sstevel@tonic-gate * Controls the logic which enables the use of the
897c478bd9Sstevel@tonic-gate * QUAD_LDD_PHYS ASI for TSB accesses.
907c478bd9Sstevel@tonic-gate */
917c478bd9Sstevel@tonic-gate int ktsb_phys = 0;
927c478bd9Sstevel@tonic-gate
937c478bd9Sstevel@tonic-gate
947c478bd9Sstevel@tonic-gate
957c478bd9Sstevel@tonic-gate /*
967c478bd9Sstevel@tonic-gate * This routine remaps the kernel using large ttes
977c478bd9Sstevel@tonic-gate * All entries except locked ones will be removed from the tlb.
987c478bd9Sstevel@tonic-gate * It assumes that both the text and data segments reside in a separate
997c478bd9Sstevel@tonic-gate * 4mb virtual and physical contigous memory chunk. This routine
1007c478bd9Sstevel@tonic-gate * is only executed by the first cpu. The remaining cpus execute
1017c478bd9Sstevel@tonic-gate * sfmmu_mp_startup() instead.
1027c478bd9Sstevel@tonic-gate * XXX It assumes that the start of the text segment is KERNELBASE. It should
1037c478bd9Sstevel@tonic-gate * actually be based on start.
1047c478bd9Sstevel@tonic-gate */
1057c478bd9Sstevel@tonic-gate void
sfmmu_remap_kernel(void)1067c478bd9Sstevel@tonic-gate sfmmu_remap_kernel(void)
1077c478bd9Sstevel@tonic-gate {
1087c478bd9Sstevel@tonic-gate pfn_t pfn;
1097c478bd9Sstevel@tonic-gate uint_t attr;
1107c478bd9Sstevel@tonic-gate int flags;
1117c478bd9Sstevel@tonic-gate
1127c478bd9Sstevel@tonic-gate extern char end[];
1137c478bd9Sstevel@tonic-gate extern struct as kas;
1147c478bd9Sstevel@tonic-gate
1157c478bd9Sstevel@tonic-gate textva = (caddr_t)(KERNELBASE & MMU_PAGEMASK4M);
1167c478bd9Sstevel@tonic-gate pfn = va_to_pfn(textva);
1177c478bd9Sstevel@tonic-gate if (pfn == PFN_INVALID)
1187c478bd9Sstevel@tonic-gate prom_panic("can't find kernel text pfn");
1197c478bd9Sstevel@tonic-gate pfn &= TTE_PFNMASK(TTE4M);
1207c478bd9Sstevel@tonic-gate
1217c478bd9Sstevel@tonic-gate attr = PROC_TEXT | HAT_NOSYNC;
1227c478bd9Sstevel@tonic-gate flags = HAT_LOAD_LOCK | SFMMU_NO_TSBLOAD;
1237c478bd9Sstevel@tonic-gate sfmmu_memtte(&ktext_tte, pfn, attr, TTE4M);
1247c478bd9Sstevel@tonic-gate /*
1257c478bd9Sstevel@tonic-gate * We set the lock bit in the tte to lock the translation in
1267c478bd9Sstevel@tonic-gate * the tlb. Note we cannot lock Panther 32M/256M pages into the tlb.
1277c478bd9Sstevel@tonic-gate * This note is here to make sure that no one tries to remap the
1287c478bd9Sstevel@tonic-gate * kernel using 32M or 256M tte's on Panther cpus.
1297c478bd9Sstevel@tonic-gate */
1307c478bd9Sstevel@tonic-gate TTE_SET_LOCKED(&ktext_tte);
1317c478bd9Sstevel@tonic-gate sfmmu_tteload(kas.a_hat, &ktext_tte, textva, NULL, flags);
1327c478bd9Sstevel@tonic-gate
1337c478bd9Sstevel@tonic-gate datava = (caddr_t)((uintptr_t)end & MMU_PAGEMASK4M);
1347c478bd9Sstevel@tonic-gate pfn = va_to_pfn(datava);
1357c478bd9Sstevel@tonic-gate if (pfn == PFN_INVALID)
1367c478bd9Sstevel@tonic-gate prom_panic("can't find kernel data pfn");
1377c478bd9Sstevel@tonic-gate pfn &= TTE_PFNMASK(TTE4M);
1387c478bd9Sstevel@tonic-gate
1397c478bd9Sstevel@tonic-gate attr = PROC_DATA | HAT_NOSYNC;
1407c478bd9Sstevel@tonic-gate sfmmu_memtte(&kdata_tte, pfn, attr, TTE4M);
1417c478bd9Sstevel@tonic-gate /*
1427c478bd9Sstevel@tonic-gate * We set the lock bit in the tte to lock the translation in
1437c478bd9Sstevel@tonic-gate * the tlb. We also set the mod bit to avoid taking dirty bit
1447c478bd9Sstevel@tonic-gate * traps on kernel data.
1457c478bd9Sstevel@tonic-gate */
1467c478bd9Sstevel@tonic-gate TTE_SET_LOCKED(&kdata_tte);
1477c478bd9Sstevel@tonic-gate TTE_SET_LOFLAGS(&kdata_tte, 0, TTE_HWWR_INT);
1487c478bd9Sstevel@tonic-gate sfmmu_tteload(kas.a_hat, &kdata_tte, datava,
1497c478bd9Sstevel@tonic-gate (struct page *)NULL, flags);
1507c478bd9Sstevel@tonic-gate
1517c478bd9Sstevel@tonic-gate /*
1527c478bd9Sstevel@tonic-gate * create bigktsb ttes if necessary.
1537c478bd9Sstevel@tonic-gate */
1547c478bd9Sstevel@tonic-gate if (enable_bigktsb) {
1557c478bd9Sstevel@tonic-gate int i = 0;
1567c478bd9Sstevel@tonic-gate caddr_t va = ktsb_base;
1577c478bd9Sstevel@tonic-gate size_t tsbsz = ktsb_sz;
1587c478bd9Sstevel@tonic-gate tte_t tte;
1597c478bd9Sstevel@tonic-gate
1607c478bd9Sstevel@tonic-gate ASSERT(va >= datava + MMU_PAGESIZE4M);
1617c478bd9Sstevel@tonic-gate ASSERT(tsbsz >= MMU_PAGESIZE4M);
1627c478bd9Sstevel@tonic-gate ASSERT(IS_P2ALIGNED(tsbsz, tsbsz));
1637c478bd9Sstevel@tonic-gate ASSERT(IS_P2ALIGNED(va, tsbsz));
1647c478bd9Sstevel@tonic-gate attr = PROC_DATA | HAT_NOSYNC;
1657c478bd9Sstevel@tonic-gate while (tsbsz != 0) {
1667c478bd9Sstevel@tonic-gate ASSERT(i < MAX_BIGKTSB_TTES);
1677c478bd9Sstevel@tonic-gate pfn = va_to_pfn(va);
1687c478bd9Sstevel@tonic-gate ASSERT(pfn != PFN_INVALID);
1697c478bd9Sstevel@tonic-gate ASSERT((pfn & ~TTE_PFNMASK(TTE4M)) == 0);
1707c478bd9Sstevel@tonic-gate sfmmu_memtte(&tte, pfn, attr, TTE4M);
1717c478bd9Sstevel@tonic-gate ASSERT(TTE_IS_MOD(&tte));
1727c478bd9Sstevel@tonic-gate /*
1737c478bd9Sstevel@tonic-gate * No need to lock if we use physical addresses.
1747c478bd9Sstevel@tonic-gate * Since we invalidate the kernel TSB using virtual
1757c478bd9Sstevel@tonic-gate * addresses, it's an optimization to load them now
1767c478bd9Sstevel@tonic-gate * so that we won't have to load them later.
1777c478bd9Sstevel@tonic-gate */
1787c478bd9Sstevel@tonic-gate if (!ktsb_phys) {
1797c478bd9Sstevel@tonic-gate TTE_SET_LOCKED(&tte);
1807c478bd9Sstevel@tonic-gate }
1817c478bd9Sstevel@tonic-gate sfmmu_tteload(kas.a_hat, &tte, va, NULL, flags);
1827c478bd9Sstevel@tonic-gate bigktsb_ttes[i] = tte;
1837c478bd9Sstevel@tonic-gate va += MMU_PAGESIZE4M;
1847c478bd9Sstevel@tonic-gate tsbsz -= MMU_PAGESIZE4M;
1857c478bd9Sstevel@tonic-gate i++;
1867c478bd9Sstevel@tonic-gate }
1877c478bd9Sstevel@tonic-gate bigktsb_nttes = i;
1887c478bd9Sstevel@tonic-gate }
1897c478bd9Sstevel@tonic-gate
1907c478bd9Sstevel@tonic-gate sfmmu_set_tlb();
1917c478bd9Sstevel@tonic-gate }
1927c478bd9Sstevel@tonic-gate
19325cf1a30Sjl139090 #ifndef UTSB_PHYS
1947c478bd9Sstevel@tonic-gate /*
1957c478bd9Sstevel@tonic-gate * Unmap all references to user TSBs from the TLB of the current processor.
1967c478bd9Sstevel@tonic-gate */
1977c478bd9Sstevel@tonic-gate static void
sfmmu_clear_user_tsbs()1987c478bd9Sstevel@tonic-gate sfmmu_clear_user_tsbs()
1997c478bd9Sstevel@tonic-gate {
2007c478bd9Sstevel@tonic-gate caddr_t va;
2017c478bd9Sstevel@tonic-gate caddr_t end_va;
2027c478bd9Sstevel@tonic-gate
2037c478bd9Sstevel@tonic-gate /* Demap all pages in the VA range for the first user TSB */
2047c478bd9Sstevel@tonic-gate va = utsb_vabase;
2057c478bd9Sstevel@tonic-gate end_va = va + tsb_slab_size;
2067c478bd9Sstevel@tonic-gate while (va < end_va) {
207*1e2e7a75Shuah vtag_flushpage(va, (uint64_t)ksfmmup);
2087c478bd9Sstevel@tonic-gate va += MMU_PAGESIZE;
2097c478bd9Sstevel@tonic-gate }
2107c478bd9Sstevel@tonic-gate
2117c478bd9Sstevel@tonic-gate /* Demap all pages in the VA range for the second user TSB */
2127c478bd9Sstevel@tonic-gate va = utsb4m_vabase;
2137c478bd9Sstevel@tonic-gate end_va = va + tsb_slab_size;
2147c478bd9Sstevel@tonic-gate while (va < end_va) {
215*1e2e7a75Shuah vtag_flushpage(va, (uint64_t)ksfmmup);
2167c478bd9Sstevel@tonic-gate va += MMU_PAGESIZE;
2177c478bd9Sstevel@tonic-gate }
2187c478bd9Sstevel@tonic-gate }
21925cf1a30Sjl139090 #endif /* UTSB_PHYS */
2207c478bd9Sstevel@tonic-gate
2217c478bd9Sstevel@tonic-gate /*
2227c478bd9Sstevel@tonic-gate * Setup the kernel's locked tte's
2237c478bd9Sstevel@tonic-gate */
2247c478bd9Sstevel@tonic-gate void
sfmmu_set_tlb(void)2257c478bd9Sstevel@tonic-gate sfmmu_set_tlb(void)
2267c478bd9Sstevel@tonic-gate {
2277c478bd9Sstevel@tonic-gate uint_t index;
2287c478bd9Sstevel@tonic-gate struct cpu_node *cpunode;
2297c478bd9Sstevel@tonic-gate
2307c478bd9Sstevel@tonic-gate cpunode = &cpunodes[getprocessorid()];
2317c478bd9Sstevel@tonic-gate index = cpunode->itlb_size;
2327c478bd9Sstevel@tonic-gate
2337c478bd9Sstevel@tonic-gate /*
2347c478bd9Sstevel@tonic-gate * NOTE: the prom will do an explicit unmap of the VAs from the TLBs
2357c478bd9Sstevel@tonic-gate * in the following functions before loading the new value into the
2367c478bd9Sstevel@tonic-gate * TLB. Thus if there was an entry already in the TLB at a different
2377c478bd9Sstevel@tonic-gate * location, it will get unmapped before we load the entry at the
2387c478bd9Sstevel@tonic-gate * specified location.
2397c478bd9Sstevel@tonic-gate */
2407c478bd9Sstevel@tonic-gate (void) prom_itlb_load(index - 1, *(uint64_t *)&ktext_tte, textva);
2417c478bd9Sstevel@tonic-gate index = cpunode->dtlb_size;
2427c478bd9Sstevel@tonic-gate (void) prom_dtlb_load(index - 1, *(uint64_t *)&kdata_tte, datava);
2437c478bd9Sstevel@tonic-gate (void) prom_dtlb_load(index - 2, *(uint64_t *)&ktext_tte, textva);
2447c478bd9Sstevel@tonic-gate index -= 3;
2457c478bd9Sstevel@tonic-gate
24625cf1a30Sjl139090 #ifndef UTSB_PHYS
2477c478bd9Sstevel@tonic-gate utsb_dtlb_ttenum = index--;
2487c478bd9Sstevel@tonic-gate utsb4m_dtlb_ttenum = index--;
2497c478bd9Sstevel@tonic-gate sfmmu_clear_user_tsbs();
25025cf1a30Sjl139090 #endif /* UTSB_PHYS */
2517c478bd9Sstevel@tonic-gate
2527c478bd9Sstevel@tonic-gate if (!ktsb_phys && enable_bigktsb) {
2537c478bd9Sstevel@tonic-gate int i;
2547c478bd9Sstevel@tonic-gate caddr_t va = ktsb_base;
2557c478bd9Sstevel@tonic-gate uint64_t tte;
2567c478bd9Sstevel@tonic-gate
2577c478bd9Sstevel@tonic-gate ASSERT(bigktsb_nttes <= MAX_BIGKTSB_TTES);
2587c478bd9Sstevel@tonic-gate for (i = 0; i < bigktsb_nttes; i++) {
2597c478bd9Sstevel@tonic-gate tte = *(uint64_t *)&bigktsb_ttes[i];
2607c478bd9Sstevel@tonic-gate (void) prom_dtlb_load(index, tte, va);
2617c478bd9Sstevel@tonic-gate va += MMU_PAGESIZE4M;
2627c478bd9Sstevel@tonic-gate index--;
2637c478bd9Sstevel@tonic-gate }
2647c478bd9Sstevel@tonic-gate }
2657c478bd9Sstevel@tonic-gate
2667c478bd9Sstevel@tonic-gate dtlb_resv_ttenum = index + 1;
2677c478bd9Sstevel@tonic-gate }
2687c478bd9Sstevel@tonic-gate
2697c478bd9Sstevel@tonic-gate /*
2707c478bd9Sstevel@tonic-gate * This routine is executed by all other cpus except the first one
2717c478bd9Sstevel@tonic-gate * at initialization time. It is responsible for taking over the
2727c478bd9Sstevel@tonic-gate * mmu from the prom. We follow these steps.
2737c478bd9Sstevel@tonic-gate * Lock the kernel's ttes in the TLB
2747c478bd9Sstevel@tonic-gate * Initialize the tsb hardware registers
2757c478bd9Sstevel@tonic-gate * Take over the trap table
2767c478bd9Sstevel@tonic-gate * Flush the prom's locked entries from the TLB
2777c478bd9Sstevel@tonic-gate */
2787c478bd9Sstevel@tonic-gate void
sfmmu_mp_startup(void)2797c478bd9Sstevel@tonic-gate sfmmu_mp_startup(void)
2807c478bd9Sstevel@tonic-gate {
2817c478bd9Sstevel@tonic-gate sfmmu_set_tlb();
2827c478bd9Sstevel@tonic-gate setwstate(WSTATE_KERN);
2837c478bd9Sstevel@tonic-gate prom_set_traptable(&trap_table);
2847c478bd9Sstevel@tonic-gate install_va_to_tte();
2857c478bd9Sstevel@tonic-gate }
2867c478bd9Sstevel@tonic-gate
2877c478bd9Sstevel@tonic-gate void
kdi_tlb_page_lock(caddr_t va,int do_dtlb)2887c478bd9Sstevel@tonic-gate kdi_tlb_page_lock(caddr_t va, int do_dtlb)
2897c478bd9Sstevel@tonic-gate {
2907c478bd9Sstevel@tonic-gate tte_t tte;
2917c478bd9Sstevel@tonic-gate pfn_t pfn = va_to_pfn(va);
2927c478bd9Sstevel@tonic-gate
2937c478bd9Sstevel@tonic-gate tte.tte_inthi = TTE_VALID_INT | TTE_SZ_INT(TTE8K) | TTE_PFN_INTHI(pfn);
2947c478bd9Sstevel@tonic-gate tte.tte_intlo = TTE_PFN_INTLO(pfn) | TTE_LCK_INT | TTE_CP_INT |
2957c478bd9Sstevel@tonic-gate TTE_PRIV_INT | TTE_HWWR_INT;
2967c478bd9Sstevel@tonic-gate
297*1e2e7a75Shuah vtag_flushpage(va, (uint64_t)ksfmmup);
2987c478bd9Sstevel@tonic-gate
299*1e2e7a75Shuah sfmmu_itlb_ld_kva(va, &tte);
3007c478bd9Sstevel@tonic-gate if (do_dtlb)
301*1e2e7a75Shuah sfmmu_dtlb_ld_kva(va, &tte);
3027c478bd9Sstevel@tonic-gate }
3037c478bd9Sstevel@tonic-gate
3047c478bd9Sstevel@tonic-gate /*ARGSUSED*/
3057c478bd9Sstevel@tonic-gate void
kdi_tlb_page_unlock(caddr_t va,int do_dtlb)3067c478bd9Sstevel@tonic-gate kdi_tlb_page_unlock(caddr_t va, int do_dtlb)
3077c478bd9Sstevel@tonic-gate {
308*1e2e7a75Shuah vtag_flushpage(va, (uint64_t)ksfmmup);
3097c478bd9Sstevel@tonic-gate }
3107c478bd9Sstevel@tonic-gate
3117c478bd9Sstevel@tonic-gate /* clear user TSB information (applicable to hardware TSB walkers) */
3127c478bd9Sstevel@tonic-gate void
sfmmu_clear_utsbinfo()3137c478bd9Sstevel@tonic-gate sfmmu_clear_utsbinfo()
3147c478bd9Sstevel@tonic-gate {
3157c478bd9Sstevel@tonic-gate }
3167c478bd9Sstevel@tonic-gate
3177c478bd9Sstevel@tonic-gate /*ARGSUSED*/
3187c478bd9Sstevel@tonic-gate void
sfmmu_setup_tsbinfo(sfmmu_t * sfmmup)3197c478bd9Sstevel@tonic-gate sfmmu_setup_tsbinfo(sfmmu_t *sfmmup)
3207c478bd9Sstevel@tonic-gate {
3217c478bd9Sstevel@tonic-gate }
3227c478bd9Sstevel@tonic-gate
3237c478bd9Sstevel@tonic-gate /*
3247c478bd9Sstevel@tonic-gate * Invalidate a TSB. If floating point is enabled we use
3257c478bd9Sstevel@tonic-gate * a fast block-store routine, otherwise we use the old method
3267c478bd9Sstevel@tonic-gate * of walking the TSB setting each tag to TSBTAG_INVALID.
3277c478bd9Sstevel@tonic-gate */
3287c478bd9Sstevel@tonic-gate void
sfmmu_inv_tsb(caddr_t tsb_base,uint_t tsb_bytes)3297c478bd9Sstevel@tonic-gate sfmmu_inv_tsb(caddr_t tsb_base, uint_t tsb_bytes)
3307c478bd9Sstevel@tonic-gate {
3317c478bd9Sstevel@tonic-gate extern void sfmmu_inv_tsb_fast(caddr_t, uint_t);
3327c478bd9Sstevel@tonic-gate struct tsbe *tsbaddr;
3337c478bd9Sstevel@tonic-gate
3347c478bd9Sstevel@tonic-gate /* CONSTCOND */
3357c478bd9Sstevel@tonic-gate if (fpu_exists) {
3367c478bd9Sstevel@tonic-gate sfmmu_inv_tsb_fast(tsb_base, tsb_bytes);
3377c478bd9Sstevel@tonic-gate return;
3387c478bd9Sstevel@tonic-gate }
3397c478bd9Sstevel@tonic-gate
3407c478bd9Sstevel@tonic-gate for (tsbaddr = (struct tsbe *)tsb_base;
3417c478bd9Sstevel@tonic-gate (uintptr_t)tsbaddr < (uintptr_t)(tsb_base + tsb_bytes);
3427c478bd9Sstevel@tonic-gate tsbaddr++) {
3437c478bd9Sstevel@tonic-gate tsbaddr->tte_tag.tag_inthi = TSBTAG_INVALID;
3447c478bd9Sstevel@tonic-gate }
3457c478bd9Sstevel@tonic-gate
3467c478bd9Sstevel@tonic-gate if (ktsb_phys && tsb_base == ktsb_base)
3477c478bd9Sstevel@tonic-gate dcache_flushall();
3487c478bd9Sstevel@tonic-gate }
3497c478bd9Sstevel@tonic-gate
3507c478bd9Sstevel@tonic-gate /*
3517c478bd9Sstevel@tonic-gate * Completely flush the D-cache on all cpus.
3527c478bd9Sstevel@tonic-gate */
3537c478bd9Sstevel@tonic-gate void
sfmmu_cache_flushall()3547c478bd9Sstevel@tonic-gate sfmmu_cache_flushall()
3557c478bd9Sstevel@tonic-gate {
3567c478bd9Sstevel@tonic-gate int i;
3577c478bd9Sstevel@tonic-gate
3587c478bd9Sstevel@tonic-gate for (i = 0; i < CACHE_NUM_COLOR; i++)
3597c478bd9Sstevel@tonic-gate sfmmu_cache_flushcolor(i, 0);
3607c478bd9Sstevel@tonic-gate }
361