1*7c478bd9Sstevel@tonic-gate /* 2*7c478bd9Sstevel@tonic-gate * CDDL HEADER START 3*7c478bd9Sstevel@tonic-gate * 4*7c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*7c478bd9Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*7c478bd9Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*7c478bd9Sstevel@tonic-gate * with the License. 8*7c478bd9Sstevel@tonic-gate * 9*7c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*7c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*7c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 12*7c478bd9Sstevel@tonic-gate * and limitations under the License. 13*7c478bd9Sstevel@tonic-gate * 14*7c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*7c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*7c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*7c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*7c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*7c478bd9Sstevel@tonic-gate * 20*7c478bd9Sstevel@tonic-gate * CDDL HEADER END 21*7c478bd9Sstevel@tonic-gate */ 22*7c478bd9Sstevel@tonic-gate /* 23*7c478bd9Sstevel@tonic-gate * Copyright (c) 1999-2000 by Sun Microsystems, Inc. 24*7c478bd9Sstevel@tonic-gate * All rights reserved. 25*7c478bd9Sstevel@tonic-gate */ 26*7c478bd9Sstevel@tonic-gate 27*7c478bd9Sstevel@tonic-gate #ifndef _SYS_SBBCREG_H 28*7c478bd9Sstevel@tonic-gate #define _SYS_SBBCREG_H 29*7c478bd9Sstevel@tonic-gate 30*7c478bd9Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 31*7c478bd9Sstevel@tonic-gate 32*7c478bd9Sstevel@tonic-gate #ifdef __cplusplus 33*7c478bd9Sstevel@tonic-gate extern "C" { 34*7c478bd9Sstevel@tonic-gate #endif 35*7c478bd9Sstevel@tonic-gate 36*7c478bd9Sstevel@tonic-gate /* 37*7c478bd9Sstevel@tonic-gate * Register definitions for SBBC, a PCI device. 38*7c478bd9Sstevel@tonic-gate */ 39*7c478bd9Sstevel@tonic-gate #define SBBC_SC_MODE 0x00000020 40*7c478bd9Sstevel@tonic-gate 41*7c478bd9Sstevel@tonic-gate typedef struct pad12 { 42*7c478bd9Sstevel@tonic-gate uint32_t pad[3]; 43*7c478bd9Sstevel@tonic-gate }pad12_t; 44*7c478bd9Sstevel@tonic-gate 45*7c478bd9Sstevel@tonic-gate /* 46*7c478bd9Sstevel@tonic-gate * SBBC registers. 47*7c478bd9Sstevel@tonic-gate */ 48*7c478bd9Sstevel@tonic-gate struct sbbc_regs_map { 49*7c478bd9Sstevel@tonic-gate uint32_t devid; /* 0x0.0000 All, device ID */ 50*7c478bd9Sstevel@tonic-gate pad12_t pada; 51*7c478bd9Sstevel@tonic-gate uint32_t devtemp; /* 0x0.0010 All */ 52*7c478bd9Sstevel@tonic-gate pad12_t padb; 53*7c478bd9Sstevel@tonic-gate uint32_t incon_scratch; /* 0x0.0020 All */ 54*7c478bd9Sstevel@tonic-gate pad12_t padc; 55*7c478bd9Sstevel@tonic-gate uint32_t incon_tstl1; /* 0x0.0030 AR and SDC */ 56*7c478bd9Sstevel@tonic-gate pad12_t padd; 57*7c478bd9Sstevel@tonic-gate uint32_t incon_tsterr; /* 0x0.0040 AR and SDC */ 58*7c478bd9Sstevel@tonic-gate pad12_t pade; 59*7c478bd9Sstevel@tonic-gate uint32_t device_conf; /* 0x0.0050 All, device configuration */ 60*7c478bd9Sstevel@tonic-gate pad12_t padf; 61*7c478bd9Sstevel@tonic-gate uint32_t device_rstcntl; /* 0x0.0060 SBBC,AR,dev reset control */ 62*7c478bd9Sstevel@tonic-gate pad12_t padg; 63*7c478bd9Sstevel@tonic-gate uint32_t device_rststat; /* 0x0.0070 All, device reset status */ 64*7c478bd9Sstevel@tonic-gate pad12_t padh; 65*7c478bd9Sstevel@tonic-gate uint32_t device_errstat; /* 0x0.0080 SBBC, device reset */ 66*7c478bd9Sstevel@tonic-gate pad12_t padi; 67*7c478bd9Sstevel@tonic-gate uint32_t device_errcntl; /* 0x0.0090 SBBC,device error control */ 68*7c478bd9Sstevel@tonic-gate pad12_t padj; 69*7c478bd9Sstevel@tonic-gate uint32_t jtag_cntl; /* 0x0.00a0 SBBC and SDC,JTAG control */ 70*7c478bd9Sstevel@tonic-gate pad12_t padk; 71*7c478bd9Sstevel@tonic-gate uint32_t jtag_cmd; /* 0x0.00b0 SBBC and SDC,JTAG command */ 72*7c478bd9Sstevel@tonic-gate pad12_t padl; 73*7c478bd9Sstevel@tonic-gate uint32_t i2c_addrcmd; /* 0x0.00c0 SBBC,I2C addr and command */ 74*7c478bd9Sstevel@tonic-gate pad12_t padm; 75*7c478bd9Sstevel@tonic-gate uint32_t i2c_data; /* 0x0.00d0 SBBC, I2C data */ 76*7c478bd9Sstevel@tonic-gate pad12_t padn; 77*7c478bd9Sstevel@tonic-gate uint32_t pci_errstat; /* 0x0.00e0 SBBC, PCI error status */ 78*7c478bd9Sstevel@tonic-gate pad12_t pad2[45]; 79*7c478bd9Sstevel@tonic-gate uint32_t consbus_conf; /* 0x0.0300 All */ 80*7c478bd9Sstevel@tonic-gate pad12_t pado; 81*7c478bd9Sstevel@tonic-gate uint32_t consbus_erraddr; /* 0x0.0310 SBBC */ 82*7c478bd9Sstevel@tonic-gate pad12_t padp; 83*7c478bd9Sstevel@tonic-gate uint32_t consbus_errack; /* 0x0.0320 SBBC */ 84*7c478bd9Sstevel@tonic-gate pad12_t pad4[18]; 85*7c478bd9Sstevel@tonic-gate uint32_t pad5; 86*7c478bd9Sstevel@tonic-gate uint32_t consbus_port0_err; /* 0x0.0400 All */ 87*7c478bd9Sstevel@tonic-gate pad12_t pad6[19]; 88*7c478bd9Sstevel@tonic-gate uint32_t pad7[2]; 89*7c478bd9Sstevel@tonic-gate uint32_t consbus_part_dom_err; /* 0x0.04f0 SBBC and CBH */ 90*7c478bd9Sstevel@tonic-gate pad12_t pad8[235]; 91*7c478bd9Sstevel@tonic-gate uint32_t pad8a[2]; 92*7c478bd9Sstevel@tonic-gate uint32_t sbbc_synch; /* 0x0.1000 SBBC */ 93*7c478bd9Sstevel@tonic-gate pad12_t padq[20]; 94*7c478bd9Sstevel@tonic-gate uint32_t padqa[3]; 95*7c478bd9Sstevel@tonic-gate uint32_t dev_access_tim0; /* 0x0.1100 SBBC */ 96*7c478bd9Sstevel@tonic-gate pad12_t padr; 97*7c478bd9Sstevel@tonic-gate uint32_t dev_access_tim1; /* 0x0.1110 SBBC */ 98*7c478bd9Sstevel@tonic-gate pad12_t pads; 99*7c478bd9Sstevel@tonic-gate uint32_t dev_access_tim2; /* 0x0.1120 SBBC */ 100*7c478bd9Sstevel@tonic-gate pad12_t padt; 101*7c478bd9Sstevel@tonic-gate uint32_t dev_access_tim3; /* 0x0.1130 SBBC */ 102*7c478bd9Sstevel@tonic-gate pad12_t padu; 103*7c478bd9Sstevel@tonic-gate uint32_t dev_access_tim4; /* 0x0.1140 SBBC */ 104*7c478bd9Sstevel@tonic-gate pad12_t padv; 105*7c478bd9Sstevel@tonic-gate uint32_t dev_access_tim5; /* 0x0.1150 SBBC */ 106*7c478bd9Sstevel@tonic-gate pad12_t pad9[14]; 107*7c478bd9Sstevel@tonic-gate uint32_t pad9a[1]; 108*7c478bd9Sstevel@tonic-gate uint32_t spare_in_out; /* 0x0.1200 SBBC */ 109*7c478bd9Sstevel@tonic-gate pad12_t pad10[127]; 110*7c478bd9Sstevel@tonic-gate uint32_t pad10a[2]; 111*7c478bd9Sstevel@tonic-gate uint32_t monitor_cntl; /* 0x0.1800 SBBC */ 112*7c478bd9Sstevel@tonic-gate pad12_t pad11[170]; 113*7c478bd9Sstevel@tonic-gate uint32_t pad11a[1]; 114*7c478bd9Sstevel@tonic-gate uint32_t port_intr_gen0; /* 0x0.2000 SBBC */ 115*7c478bd9Sstevel@tonic-gate pad12_t padw; 116*7c478bd9Sstevel@tonic-gate uint32_t port_intr_gen1; /* 0x0.2010 SBBC */ 117*7c478bd9Sstevel@tonic-gate pad12_t padx; 118*7c478bd9Sstevel@tonic-gate uint32_t syscntlr_intr_gen; /* 0x0.2020 SBBC */ 119*7c478bd9Sstevel@tonic-gate pad12_t pad12[61]; 120*7c478bd9Sstevel@tonic-gate uint32_t sys_intr_status; /* 0x0.2300 SBBC */ 121*7c478bd9Sstevel@tonic-gate pad12_t pady; 122*7c478bd9Sstevel@tonic-gate uint32_t sys_intr_enable; /* 0x0.2310 SBBC */ 123*7c478bd9Sstevel@tonic-gate pad12_t padz; 124*7c478bd9Sstevel@tonic-gate uint32_t pci_intr_status; /* 0x0.2320 SBBC */ 125*7c478bd9Sstevel@tonic-gate pad12_t padaa; 126*7c478bd9Sstevel@tonic-gate uint32_t pci_intr_enable; /* 0x0.2330 SBBC */ 127*7c478bd9Sstevel@tonic-gate pad12_t pad13[614]; 128*7c478bd9Sstevel@tonic-gate uint32_t pad13a[1]; 129*7c478bd9Sstevel@tonic-gate uint32_t pci_to_consbus_map; /* 0x0.4000 SBBC */ 130*7c478bd9Sstevel@tonic-gate pad12_t padab; 131*7c478bd9Sstevel@tonic-gate uint32_t consbus_to_pci_map; /* 0x0.4010 SBBC */ 132*7c478bd9Sstevel@tonic-gate }; 133*7c478bd9Sstevel@tonic-gate 134*7c478bd9Sstevel@tonic-gate 135*7c478bd9Sstevel@tonic-gate /* 136*7c478bd9Sstevel@tonic-gate * SSC DEV presence registers 137*7c478bd9Sstevel@tonic-gate */ 138*7c478bd9Sstevel@tonic-gate struct ssc_devpresence_regs_map { 139*7c478bd9Sstevel@tonic-gate uint8_t devpres_reg0; 140*7c478bd9Sstevel@tonic-gate uint8_t devpres_reg1; 141*7c478bd9Sstevel@tonic-gate uint8_t devpres_reg2; 142*7c478bd9Sstevel@tonic-gate uint8_t devpres_reg3; 143*7c478bd9Sstevel@tonic-gate uint8_t devpres_reg4; 144*7c478bd9Sstevel@tonic-gate uint8_t devpres_reg5; 145*7c478bd9Sstevel@tonic-gate uint8_t devpres_reg6; 146*7c478bd9Sstevel@tonic-gate uint8_t devpres_reg7; 147*7c478bd9Sstevel@tonic-gate uint8_t devpres_reg8; 148*7c478bd9Sstevel@tonic-gate uint8_t devpres_reg9; 149*7c478bd9Sstevel@tonic-gate uint8_t devpres_rega; 150*7c478bd9Sstevel@tonic-gate uint8_t devpres_regb; 151*7c478bd9Sstevel@tonic-gate }; 152*7c478bd9Sstevel@tonic-gate 153*7c478bd9Sstevel@tonic-gate /* 154*7c478bd9Sstevel@tonic-gate * EChip 155*7c478bd9Sstevel@tonic-gate * 0088.0000 - 0089.FFFF 156*7c478bd9Sstevel@tonic-gate */ 157*7c478bd9Sstevel@tonic-gate struct ssc_echip_regs { 158*7c478bd9Sstevel@tonic-gate uint8_t offset[0x20000]; 159*7c478bd9Sstevel@tonic-gate }; 160*7c478bd9Sstevel@tonic-gate 161*7c478bd9Sstevel@tonic-gate /* 162*7c478bd9Sstevel@tonic-gate * Device Presence 163*7c478bd9Sstevel@tonic-gate * 008A.0000 - 008B.FFFF 164*7c478bd9Sstevel@tonic-gate */ 165*7c478bd9Sstevel@tonic-gate struct ssc_devpresence_regs { 166*7c478bd9Sstevel@tonic-gate uint8_t offset[0x20000]; 167*7c478bd9Sstevel@tonic-gate }; 168*7c478bd9Sstevel@tonic-gate 169*7c478bd9Sstevel@tonic-gate /* 170*7c478bd9Sstevel@tonic-gate * I2C Mux 171*7c478bd9Sstevel@tonic-gate * 008C.0000 - 008D.FFFF 172*7c478bd9Sstevel@tonic-gate */ 173*7c478bd9Sstevel@tonic-gate struct ssc_i2cmux_regs { 174*7c478bd9Sstevel@tonic-gate uint8_t offset[0x20000]; 175*7c478bd9Sstevel@tonic-gate }; 176*7c478bd9Sstevel@tonic-gate 177*7c478bd9Sstevel@tonic-gate /* 178*7c478bd9Sstevel@tonic-gate * Error Interrupts Status and Control 179*7c478bd9Sstevel@tonic-gate * 008E.0000 - 008F.FFFF 180*7c478bd9Sstevel@tonic-gate */ 181*7c478bd9Sstevel@tonic-gate struct ssc_errintr_statcntl_regs { 182*7c478bd9Sstevel@tonic-gate uint8_t offset[0x20000]; 183*7c478bd9Sstevel@tonic-gate }; 184*7c478bd9Sstevel@tonic-gate 185*7c478bd9Sstevel@tonic-gate /* 186*7c478bd9Sstevel@tonic-gate * Console Bus Window 187*7c478bd9Sstevel@tonic-gate * 0400.0000 - 07FF.FFFF 188*7c478bd9Sstevel@tonic-gate */ 189*7c478bd9Sstevel@tonic-gate struct ssc_console_bus { 190*7c478bd9Sstevel@tonic-gate uint8_t offset[0x4000000]; 191*7c478bd9Sstevel@tonic-gate }; 192*7c478bd9Sstevel@tonic-gate 193*7c478bd9Sstevel@tonic-gate /* 194*7c478bd9Sstevel@tonic-gate * SSC EILD registers 195*7c478bd9Sstevel@tonic-gate */ 196*7c478bd9Sstevel@tonic-gate struct ssc_eild_reg_map { 197*7c478bd9Sstevel@tonic-gate uint8_t darb_intr; 198*7c478bd9Sstevel@tonic-gate uint8_t darb_intr_mask; 199*7c478bd9Sstevel@tonic-gate uint8_t sbbc_cons_err; 200*7c478bd9Sstevel@tonic-gate uint8_t sbbc_cons_err_mask; 201*7c478bd9Sstevel@tonic-gate uint8_t pwr_supply; 202*7c478bd9Sstevel@tonic-gate }; 203*7c478bd9Sstevel@tonic-gate 204*7c478bd9Sstevel@tonic-gate /* 205*7c478bd9Sstevel@tonic-gate * PCI SBBC slave mapping 206*7c478bd9Sstevel@tonic-gate */ 207*7c478bd9Sstevel@tonic-gate struct pci_sbbc { 208*7c478bd9Sstevel@tonic-gate uint8_t fprom[0x800000]; /* FPROM */ 209*7c478bd9Sstevel@tonic-gate struct sbbc_regs_map sbbc_internal_regs; /* sbbc registers */ 210*7c478bd9Sstevel@tonic-gate uint8_t dontcare[0x7BFEC]; /* non-sbbc registers */ 211*7c478bd9Sstevel@tonic-gate struct ssc_echip_regs echip_regs; 212*7c478bd9Sstevel@tonic-gate struct ssc_devpresence_regs devpres_regs; 213*7c478bd9Sstevel@tonic-gate struct ssc_i2cmux_regs i2cmux_regs; 214*7c478bd9Sstevel@tonic-gate struct ssc_errintr_statcntl_regs errintr_scntl_regs; 215*7c478bd9Sstevel@tonic-gate uint8_t sram[0x100000]; 216*7c478bd9Sstevel@tonic-gate uint8_t reserved[0x3600000]; 217*7c478bd9Sstevel@tonic-gate struct ssc_console_bus consbus; 218*7c478bd9Sstevel@tonic-gate }; 219*7c478bd9Sstevel@tonic-gate 220*7c478bd9Sstevel@tonic-gate 221*7c478bd9Sstevel@tonic-gate /* 222*7c478bd9Sstevel@tonic-gate * SBBC registers. 223*7c478bd9Sstevel@tonic-gate */ 224*7c478bd9Sstevel@tonic-gate struct sbbc_common_devregs { 225*7c478bd9Sstevel@tonic-gate uint32_t devid; /* All, device ID */ 226*7c478bd9Sstevel@tonic-gate uint32_t devtemp; /* All */ 227*7c478bd9Sstevel@tonic-gate uint32_t incon_scratch; /* All */ 228*7c478bd9Sstevel@tonic-gate uint32_t incon_tstl1; /* AR and SDC */ 229*7c478bd9Sstevel@tonic-gate uint32_t incon_tsterr; /* AR and SDC */ 230*7c478bd9Sstevel@tonic-gate uint32_t device_conf; /* All, device configuration */ 231*7c478bd9Sstevel@tonic-gate uint32_t device_rstcntl; /* SBBC and AR, dev reset control */ 232*7c478bd9Sstevel@tonic-gate uint32_t device_rststat; /* All, device reset status */ 233*7c478bd9Sstevel@tonic-gate uint32_t device_errstat; /* SBBC, device reset */ 234*7c478bd9Sstevel@tonic-gate uint32_t device_errcntl; /* SBBC, device error control */ 235*7c478bd9Sstevel@tonic-gate uint32_t jtag_cntl; /* SBBC and SDC, JTAG control */ 236*7c478bd9Sstevel@tonic-gate uint32_t jtag_cmd; /* SBBC and SDC, JTAG command */ 237*7c478bd9Sstevel@tonic-gate uint32_t i2c_addrcmd; /* SBBC, I2C address and command */ 238*7c478bd9Sstevel@tonic-gate uint32_t i2c_data; /* SBBC, I2C data */ 239*7c478bd9Sstevel@tonic-gate uint32_t pci_errstat; /* SBBC, PCI error status */ 240*7c478bd9Sstevel@tonic-gate uint32_t domain_conf; /* CBH */ 241*7c478bd9Sstevel@tonic-gate uint32_t safari_port0_conf; /* AR and SDC */ 242*7c478bd9Sstevel@tonic-gate uint32_t safari_port1_conf; /* AR and SDC */ 243*7c478bd9Sstevel@tonic-gate uint32_t safari_port2_conf; /* AR and SDC */ 244*7c478bd9Sstevel@tonic-gate uint32_t safari_port3_conf; /* AR and SDC */ 245*7c478bd9Sstevel@tonic-gate uint32_t safari_port4_conf; /* AR and SDC */ 246*7c478bd9Sstevel@tonic-gate uint32_t safari_port5_conf; /* AR and SDC */ 247*7c478bd9Sstevel@tonic-gate uint32_t safari_port6_conf; /* AR and SDC */ 248*7c478bd9Sstevel@tonic-gate uint32_t safari_port7_conf; /* AR and SDC */ 249*7c478bd9Sstevel@tonic-gate uint32_t safari_port8_conf; /* AR and SDC */ 250*7c478bd9Sstevel@tonic-gate uint32_t safari_port9_conf; /* AR and SDC */ 251*7c478bd9Sstevel@tonic-gate uint32_t safari_port0_err; /* AR and SDC */ 252*7c478bd9Sstevel@tonic-gate uint32_t safari_port1_err; /* AR and SDC */ 253*7c478bd9Sstevel@tonic-gate uint32_t safari_port2_err; /* AR and SDC */ 254*7c478bd9Sstevel@tonic-gate uint32_t safari_port3_err; /* AR and SDC */ 255*7c478bd9Sstevel@tonic-gate uint32_t safari_port4_err; /* AR and SDC */ 256*7c478bd9Sstevel@tonic-gate uint32_t safari_port5_err; /* AR and SDC */ 257*7c478bd9Sstevel@tonic-gate uint32_t safari_port6_err; /* AR and SDC */ 258*7c478bd9Sstevel@tonic-gate uint32_t safari_port7_err; /* AR and SDC */ 259*7c478bd9Sstevel@tonic-gate uint32_t safari_port8_err; /* AR and SDC */ 260*7c478bd9Sstevel@tonic-gate uint32_t safari_port9_err; /* AR and SDC */ 261*7c478bd9Sstevel@tonic-gate uint32_t consbus_conf; /* All */ 262*7c478bd9Sstevel@tonic-gate uint32_t consbus_erraddr; /* SBBC */ 263*7c478bd9Sstevel@tonic-gate uint32_t consbus_errack; /* SBBC */ 264*7c478bd9Sstevel@tonic-gate uint32_t consbus_errinj0; /* CBH */ 265*7c478bd9Sstevel@tonic-gate uint32_t consbus_errinj1; /* CBH */ 266*7c478bd9Sstevel@tonic-gate uint32_t consbus_port0_err; /* All */ 267*7c478bd9Sstevel@tonic-gate uint32_t consbus_port1_err; /* SDC and CBH */ 268*7c478bd9Sstevel@tonic-gate uint32_t consbus_port2_err; /* SDC and CBH */ 269*7c478bd9Sstevel@tonic-gate uint32_t consbus_port3_err; /* SDC and CBH */ 270*7c478bd9Sstevel@tonic-gate uint32_t consbus_port4_err; /* SDC and CBH */ 271*7c478bd9Sstevel@tonic-gate uint32_t consbus_port5_err; /* CBH */ 272*7c478bd9Sstevel@tonic-gate uint32_t consbus_port6_err; /* CBH */ 273*7c478bd9Sstevel@tonic-gate uint32_t consbus_port7_err; /* CBH */ 274*7c478bd9Sstevel@tonic-gate uint32_t consbus_port8_err; /* CBH */ 275*7c478bd9Sstevel@tonic-gate uint32_t consbus_port9_err; /* CBH */ 276*7c478bd9Sstevel@tonic-gate uint32_t consbus_porta_err; /* CBH */ 277*7c478bd9Sstevel@tonic-gate uint32_t consbus_portb_err; /* CBH */ 278*7c478bd9Sstevel@tonic-gate uint32_t consbus_portc_err; /* CBH */ 279*7c478bd9Sstevel@tonic-gate uint32_t consbus_portd_err; /* CBH */ 280*7c478bd9Sstevel@tonic-gate uint32_t consbus_porte_err; /* CBH */ 281*7c478bd9Sstevel@tonic-gate uint32_t consbus_part_dom_err; /* SBBC and CBH */ 282*7c478bd9Sstevel@tonic-gate uint32_t sbbc_synch; /* SBBC */ 283*7c478bd9Sstevel@tonic-gate uint32_t dev_access_tim0; /* SBBC */ 284*7c478bd9Sstevel@tonic-gate uint32_t dev_access_tim1; /* SBBC */ 285*7c478bd9Sstevel@tonic-gate uint32_t dev_access_tim2; /* SBBC */ 286*7c478bd9Sstevel@tonic-gate uint32_t dev_access_tim3; /* SBBC */ 287*7c478bd9Sstevel@tonic-gate uint32_t dev_access_tim4; /* SBBC */ 288*7c478bd9Sstevel@tonic-gate uint32_t dev_access_tim5; /* SBBC */ 289*7c478bd9Sstevel@tonic-gate uint32_t spare_in_out; /* SBBC */ 290*7c478bd9Sstevel@tonic-gate uint32_t monitor_cntl; /* SBBC */ 291*7c478bd9Sstevel@tonic-gate uint32_t port_intr_gen0; /* SBBC */ 292*7c478bd9Sstevel@tonic-gate uint32_t port_intr_gen1; /* SBBC */ 293*7c478bd9Sstevel@tonic-gate uint32_t syscntlr_intr_gen; /* SBBC */ 294*7c478bd9Sstevel@tonic-gate uint32_t sys_intr_status; /* SBBC */ 295*7c478bd9Sstevel@tonic-gate uint32_t sys_intr_enable; /* SBBC */ 296*7c478bd9Sstevel@tonic-gate uint32_t pci_intr_status; /* SBBC */ 297*7c478bd9Sstevel@tonic-gate uint32_t pci_intr_enable; /* SBBC */ 298*7c478bd9Sstevel@tonic-gate uint32_t pci_to_consbus_map; /* SBBC */ 299*7c478bd9Sstevel@tonic-gate uint32_t consbus_to_pci_map; /* SBBC */ 300*7c478bd9Sstevel@tonic-gate uint32_t scm_consbus_addrmap; /* CBH */ 301*7c478bd9Sstevel@tonic-gate uint32_t ar_slot0_trans_cnt; /* AR */ 302*7c478bd9Sstevel@tonic-gate uint32_t ar_slot1_trans_cnt; /* AR */ 303*7c478bd9Sstevel@tonic-gate uint32_t ar_slot2_trans_cnt; /* AR */ 304*7c478bd9Sstevel@tonic-gate uint32_t ar_slot3_trans_cnt; /* AR */ 305*7c478bd9Sstevel@tonic-gate uint32_t ar_slot4_trans_cnt; /* AR */ 306*7c478bd9Sstevel@tonic-gate uint32_t ar_slot5_trans_cnt; /* AR */ 307*7c478bd9Sstevel@tonic-gate uint32_t ar_slot6_trans_cnt; /* AR */ 308*7c478bd9Sstevel@tonic-gate uint32_t ar_slot7_trans_cnt; /* AR */ 309*7c478bd9Sstevel@tonic-gate uint32_t ar_slot8_trans_cnt; /* AR */ 310*7c478bd9Sstevel@tonic-gate uint32_t ar_slot9_trans_cnt; /* AR */ 311*7c478bd9Sstevel@tonic-gate uint32_t ar_trans_cnt_oflow; /* AR */ 312*7c478bd9Sstevel@tonic-gate uint32_t ar_trans_cnt_uflow; /* AR */ 313*7c478bd9Sstevel@tonic-gate uint32_t ar_l1l1_conf; /* AR */ 314*7c478bd9Sstevel@tonic-gate uint32_t lock_step_err; /* AR and SDC */ 315*7c478bd9Sstevel@tonic-gate uint32_t l2_check_err; /* AR and SDC */ 316*7c478bd9Sstevel@tonic-gate uint32_t incon_tstl1_slave; /* AR */ 317*7c478bd9Sstevel@tonic-gate uint32_t incon_tstl2_slave; /* AR and SDC */ 318*7c478bd9Sstevel@tonic-gate uint32_t ecc_status; /* SDC */ 319*7c478bd9Sstevel@tonic-gate uint32_t event_counter0; /* SDC */ 320*7c478bd9Sstevel@tonic-gate uint32_t event_counter1; /* SDC */ 321*7c478bd9Sstevel@tonic-gate uint32_t event_counter2; /* SDC */ 322*7c478bd9Sstevel@tonic-gate uint32_t monitor_counter_cntl; /* AR and SDC */ 323*7c478bd9Sstevel@tonic-gate uint32_t ar_transid_match; /* AR */ 324*7c478bd9Sstevel@tonic-gate }; 325*7c478bd9Sstevel@tonic-gate 326*7c478bd9Sstevel@tonic-gate 327*7c478bd9Sstevel@tonic-gate #ifdef __cplusplus 328*7c478bd9Sstevel@tonic-gate } 329*7c478bd9Sstevel@tonic-gate #endif 330*7c478bd9Sstevel@tonic-gate 331*7c478bd9Sstevel@tonic-gate #endif /* _SYS_SBBCREG_H */ 332