1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PCIPSY_H 27 #define _SYS_PCIPSY_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /* 36 * Performance counters information. 37 */ 38 #define PSYCHO_SHIFT_PIC0 8 39 #define PSYCHO_SHIFT_PIC1 0 40 41 /* 42 * Psycho-specific register offsets & bit field positions. 43 */ 44 45 /* 46 * Offsets of global registers: 47 */ 48 #define PSYCHO_CB_DEVICE_ID_REG_OFFSET 0x00000000 49 #define PSYCHO_CB_CONTROL_STATUS_REG_OFFSET 0x00000010 50 51 /* 52 * psycho performance counters offsets. 53 */ 54 #define PSYCHO_PERF_PCR_OFFSET 0x00000100 55 #define PSYCHO_PERF_PIC_OFFSET 0x00000108 56 57 /* 58 * Offsets of registers in the interrupt block: 59 */ 60 #define PSYCHO_IB_SLOT_INTR_MAP_REG_OFFSET 0x00000C00 61 #define PSYCHO_IB_OBIO_INTR_MAP_REG_OFFSET 0x00001000 62 #define PSYCHO_IB_OBIO_CLEAR_INTR_REG_OFFSET 0x00001800 63 64 /* 65 * Offsets of registers in the PBM block: 66 */ 67 #define PSYCHO_PCI_PBM_REG_BASE 0x00002000 68 #define PSYCHO_PCI_CTRL_REG_OFFSET 0x00000000 69 #define PSYCHO_PCI_ASYNC_FLT_STATUS_REG_OFFSET 0x00000010 70 #define PSYCHO_PCI_ASYNC_FLT_ADDR_REG_OFFSET 0x00000018 71 #define PSYCHO_PCI_DIAG_REG_OFFSET 0x00000020 72 73 /* 74 * Offsets of registers in the streaming cache block: 75 */ 76 #define PSYCHO_SC_CTRL_REG_OFFSET 0x00000800 77 #define PSYCHO_SC_INVL_REG_OFFSET 0x00000808 78 #define PSYCHO_SC_SYNC_REG_OFFSET 0x00000810 79 #define PSYCHO_SC_A_DATA_DIAG_OFFSET 0x0000b000 80 #define PSYCHO_SC_A_TAG_DIAG_OFFSET 0x0000b800 81 #define PSYCHO_SC_A_LTAG_DIAG_OFFSET 0x0000b900 82 #define PSYCHO_SC_B_DATA_DIAG_OFFSET 0x0000c000 83 #define PSYCHO_SC_B_TAG_DIAG_OFFSET 0x0000c800 84 #define PSYCHO_SC_B_LTAG_DIAG_OFFSET 0x0000c900 85 86 /* 87 * Address space offsets and sizes: 88 */ 89 #define PSYCHO_PCI_CONFIG 0x001000000ull 90 #define PSYCHO_PCI_A_IO 0x002000000ull 91 #define PSYCHO_PCI_B_IO 0x002010000ull 92 #define PSYCHO_PCI_A_MEMORY 0x100000000ull 93 #define PSYCHO_PCI_B_MEMORY 0x180000000ull 94 #define PSYCHO_PCI_IO_SIZE 0x000010000ull 95 #define PSYCHO_PCI_MEM_SIZE 0x080000000ull 96 97 /* 98 * psycho control register bit definitions: 99 */ 100 #define PSYCHO_CB_CONTROL_STATUS_MODE 0x0000000000000001ull 101 #define PSYCHO_CB_CONTROL_STATUS_IMPL 0xf000000000000000ull 102 #define PSYCHO_CB_CONTROL_STATUS_IMPL_SHIFT 60 103 #define PSYCHO_CB_CONTROL_STATUS_VER 0x0f00000000000000ull 104 #define PSYCHO_CB_CONTROL_STATUS_VER_SHIFT 56 105 106 /* 107 * psycho ECC UE AFSR bit definitions: 108 */ 109 #define PSYCHO_ECC_UE_AFSR_BYTEMASK 0x0000ffff00000000ull 110 #define PSYCHO_ECC_UE_AFSR_BYTEMASK_SHIFT 32 111 #define PSYCHO_ECC_UE_AFSR_DW_OFFSET 0x00000000e0000000ull 112 #define PSYCHO_ECC_UE_AFSR_DW_OFFSET_SHIFT 29 113 #define PSYCHO_ECC_UE_AFSR_ID 0x000000001f000000ull 114 #define PSYCHO_ECC_UE_AFSR_ID_SHIFT 24 115 #define PSYCHO_ECC_UE_AFSR_BLK 0x0000000000800000ull 116 117 /* 118 * psycho ECC CE AFSR bit definitions: 119 */ 120 #define PSYCHO_ECC_CE_AFSR_SYND 0x00ff000000000000ull 121 #define PSYCHO_ECC_CE_AFSR_SYND_SHIFT 48 122 #define PSYCHO_ECC_CE_AFSR_BYTEMASK 0x0000ffff00000000ull 123 #define PSYCHO_ECC_CE_AFSR_BYTEMASK_SHIFT 32 124 #define PSYCHO_ECC_CE_AFSR_DW_OFFSET 0x00000000e0000000ull 125 #define PSYCHO_ECC_CE_AFSR_DW_OFFSET_SHIFT 29 126 #define PSYCHO_ECC_CE_AFSR_UPA_MID 0x000000001f000000ull 127 #define PSYCHO_ECC_CE_AFSR_UPA_MID_SHIFT 24 128 #define PSYCHO_ECC_CE_AFSR_BLK 0x0000000000800000ull 129 130 /* 131 * psycho pci control register bits: 132 */ 133 #define PSYCHO_PCI_CTRL_ARB_PARK 0x0000000000200000ull 134 #define PSYCHO_PCI_CTRL_SBH_INT_EN 0x0000000000000400ull 135 #define PSYCHO_PCI_CTRL_WAKEUP_EN 0x0000000000000200ull 136 #define PSYCHO_PCI_CTRL_ERR_INT_EN 0x0000000000000100ull 137 #define PSYCHO_PCI_CTRL_ARB_EN_MASK 0x000000000000000full 138 139 /* 140 * psycho PCI asynchronous fault status register bit definitions: 141 */ 142 #define PSYCHO_PCI_AFSR_PE_SHIFT 60 143 #define PSYCHO_PCI_AFSR_SE_SHIFT 56 144 #define PSYCHO_PCI_AFSR_E_MA 0x0000000000000008ull 145 #define PSYCHO_PCI_AFSR_E_TA 0x0000000000000004ull 146 #define PSYCHO_PCI_AFSR_E_RTRY 0x0000000000000002ull 147 #define PSYCHO_PCI_AFSR_E_PERR 0x0000000000000001ull 148 #define PSYCHO_PCI_AFSR_E_MASK 0x000000000000000full 149 #define PSYCHO_PCI_AFSR_BYTEMASK 0x0000ffff00000000ull 150 #define PSYCHO_PCI_AFSR_BYTEMASK_SHIFT 32 151 #define PSYCHO_PCI_AFSR_BLK 0x0000000080000000ull 152 #define PSYCHO_PCI_AFSR_MID 0x000000003e000000ull 153 #define PSYCHO_PCI_AFSR_MID_SHIFT 25 154 155 /* 156 * psycho PCI diagnostic register bit definitions: 157 */ 158 #define PSYCHO_PCI_DIAG_DIS_DWSYNC 0x0000000000000010ull 159 160 #define PBM_AFSR_TO_PRIERR(afsr) \ 161 (afsr >> PSYCHO_PCI_AFSR_PE_SHIFT & PSYCHO_PCI_AFSR_E_MASK) 162 #define PBM_AFSR_TO_SECERR(afsr) \ 163 (afsr >> PSYCHO_PCI_AFSR_SE_SHIFT & PSYCHO_PCI_AFSR_E_MASK) 164 #define PBM_AFSR_TO_BYTEMASK(afsr) \ 165 ((afsr & PSYCHO_PCI_AFSR_BYTEMASK) >> PSYCHO_PCI_AFSR_BYTEMASK_SHIFT) 166 167 #define PCI_BRIDGE_TYPE(cmn_p) PCI_PSYCHO 168 /* 169 * for sabre 170 */ 171 #define DMA_WRITE_SYNC_REG 0x1C20 172 173 extern uint_t cb_thermal_intr(caddr_t a); 174 175 #define PCI_ID_TO_IGN(pci_id) ((pci_ign_t)UPAID_TO_IGN(pci_id)) 176 177 /* 178 * The following macro defines the 40-bit bus width support for UPA bus 179 * in DVMA and iommu bypass transfers: 180 */ 181 182 #define UPA_IOMMU_BYPASS_END 0xFFFC00FFFFFFFFFFull 183 184 #ifdef __cplusplus 185 } 186 #endif 187 188 #endif /* _SYS_PCIPSY_H */ 189