1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_PCIPSY_H 28 #define _SYS_PCIPSY_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* 37 * Performance counters information. 38 */ 39 #define PSYCHO_SHIFT_PIC0 8 40 #define PSYCHO_SHIFT_PIC1 0 41 42 /* 43 * Psycho-specific register offsets & bit field positions. 44 */ 45 46 /* 47 * Offsets of global registers: 48 */ 49 #define PSYCHO_CB_DEVICE_ID_REG_OFFSET 0x00000000 50 #define PSYCHO_CB_CONTROL_STATUS_REG_OFFSET 0x00000010 51 52 /* 53 * psycho performance counters offsets. 54 */ 55 #define PSYCHO_PERF_PCR_OFFSET 0x00000100 56 #define PSYCHO_PERF_PIC_OFFSET 0x00000108 57 58 /* 59 * Offsets of registers in the interrupt block: 60 */ 61 #define PSYCHO_IB_SLOT_INTR_MAP_REG_OFFSET 0x00000C00 62 #define PSYCHO_IB_OBIO_INTR_MAP_REG_OFFSET 0x00001000 63 #define PSYCHO_IB_OBIO_CLEAR_INTR_REG_OFFSET 0x00001800 64 65 /* 66 * Offsets of registers in the PBM block: 67 */ 68 #define PSYCHO_PCI_PBM_REG_BASE 0x00002000 69 #define PSYCHO_PCI_CTRL_REG_OFFSET 0x00000000 70 #define PSYCHO_PCI_ASYNC_FLT_STATUS_REG_OFFSET 0x00000010 71 #define PSYCHO_PCI_ASYNC_FLT_ADDR_REG_OFFSET 0x00000018 72 #define PSYCHO_PCI_DIAG_REG_OFFSET 0x00000020 73 74 /* 75 * Offsets of registers in the streaming cache block: 76 */ 77 #define PSYCHO_SC_CTRL_REG_OFFSET 0x00000800 78 #define PSYCHO_SC_INVL_REG_OFFSET 0x00000808 79 #define PSYCHO_SC_SYNC_REG_OFFSET 0x00000810 80 #define PSYCHO_SC_A_DATA_DIAG_OFFSET 0x0000b000 81 #define PSYCHO_SC_A_TAG_DIAG_OFFSET 0x0000b800 82 #define PSYCHO_SC_A_LTAG_DIAG_OFFSET 0x0000b900 83 #define PSYCHO_SC_B_DATA_DIAG_OFFSET 0x0000c000 84 #define PSYCHO_SC_B_TAG_DIAG_OFFSET 0x0000c800 85 #define PSYCHO_SC_B_LTAG_DIAG_OFFSET 0x0000c900 86 87 /* 88 * Address space offsets and sizes: 89 */ 90 #define PSYCHO_PCI_CONFIG 0x001000000ull 91 #define PSYCHO_PCI_A_IO 0x002000000ull 92 #define PSYCHO_PCI_B_IO 0x002010000ull 93 #define PSYCHO_PCI_A_MEMORY 0x100000000ull 94 #define PSYCHO_PCI_B_MEMORY 0x180000000ull 95 #define PSYCHO_PCI_IO_SIZE 0x000010000ull 96 #define PSYCHO_PCI_MEM_SIZE 0x080000000ull 97 98 /* 99 * psycho control register bit definitions: 100 */ 101 #define PSYCHO_CB_CONTROL_STATUS_MODE 0x0000000000000001ull 102 #define PSYCHO_CB_CONTROL_STATUS_IMPL 0xf000000000000000ull 103 #define PSYCHO_CB_CONTROL_STATUS_IMPL_SHIFT 60 104 #define PSYCHO_CB_CONTROL_STATUS_VER 0x0f00000000000000ull 105 #define PSYCHO_CB_CONTROL_STATUS_VER_SHIFT 56 106 107 /* 108 * psycho ECC UE AFSR bit definitions: 109 */ 110 #define PSYCHO_ECC_UE_AFSR_BYTEMASK 0x0000ffff00000000ull 111 #define PSYCHO_ECC_UE_AFSR_BYTEMASK_SHIFT 32 112 #define PSYCHO_ECC_UE_AFSR_DW_OFFSET 0x00000000e0000000ull 113 #define PSYCHO_ECC_UE_AFSR_DW_OFFSET_SHIFT 29 114 #define PSYCHO_ECC_UE_AFSR_ID 0x000000001f000000ull 115 #define PSYCHO_ECC_UE_AFSR_ID_SHIFT 24 116 #define PSYCHO_ECC_UE_AFSR_BLK 0x0000000000800000ull 117 118 /* 119 * psycho ECC CE AFSR bit definitions: 120 */ 121 #define PSYCHO_ECC_CE_AFSR_SYND 0x00ff000000000000ull 122 #define PSYCHO_ECC_CE_AFSR_SYND_SHIFT 48 123 #define PSYCHO_ECC_CE_AFSR_BYTEMASK 0x0000ffff00000000ull 124 #define PSYCHO_ECC_CE_AFSR_BYTEMASK_SHIFT 32 125 #define PSYCHO_ECC_CE_AFSR_DW_OFFSET 0x00000000e0000000ull 126 #define PSYCHO_ECC_CE_AFSR_DW_OFFSET_SHIFT 29 127 #define PSYCHO_ECC_CE_AFSR_UPA_MID 0x000000001f000000ull 128 #define PSYCHO_ECC_CE_AFSR_UPA_MID_SHIFT 24 129 #define PSYCHO_ECC_CE_AFSR_BLK 0x0000000000800000ull 130 131 /* 132 * psycho pci control register bits: 133 */ 134 #define PSYCHO_PCI_CTRL_ARB_PARK 0x0000000000200000ull 135 #define PSYCHO_PCI_CTRL_SBH_INT_EN 0x0000000000000400ull 136 #define PSYCHO_PCI_CTRL_WAKEUP_EN 0x0000000000000200ull 137 #define PSYCHO_PCI_CTRL_ERR_INT_EN 0x0000000000000100ull 138 #define PSYCHO_PCI_CTRL_ARB_EN_MASK 0x000000000000000full 139 140 /* 141 * psycho PCI asynchronous fault status register bit definitions: 142 */ 143 #define PSYCHO_PCI_AFSR_PE_SHIFT 60 144 #define PSYCHO_PCI_AFSR_SE_SHIFT 56 145 #define PSYCHO_PCI_AFSR_E_MA 0x0000000000000008ull 146 #define PSYCHO_PCI_AFSR_E_TA 0x0000000000000004ull 147 #define PSYCHO_PCI_AFSR_E_RTRY 0x0000000000000002ull 148 #define PSYCHO_PCI_AFSR_E_PERR 0x0000000000000001ull 149 #define PSYCHO_PCI_AFSR_E_MASK 0x000000000000000full 150 #define PSYCHO_PCI_AFSR_BYTEMASK 0x0000ffff00000000ull 151 #define PSYCHO_PCI_AFSR_BYTEMASK_SHIFT 32 152 #define PSYCHO_PCI_AFSR_BLK 0x0000000080000000ull 153 #define PSYCHO_PCI_AFSR_MID 0x000000003e000000ull 154 #define PSYCHO_PCI_AFSR_MID_SHIFT 25 155 156 /* 157 * psycho PCI diagnostic register bit definitions: 158 */ 159 #define PSYCHO_PCI_DIAG_DIS_DWSYNC 0x0000000000000010ull 160 161 #define PBM_AFSR_TO_PRIERR(afsr) \ 162 (afsr >> PSYCHO_PCI_AFSR_PE_SHIFT & PSYCHO_PCI_AFSR_E_MASK) 163 #define PBM_AFSR_TO_SECERR(afsr) \ 164 (afsr >> PSYCHO_PCI_AFSR_SE_SHIFT & PSYCHO_PCI_AFSR_E_MASK) 165 #define PBM_AFSR_TO_BYTEMASK(afsr) \ 166 ((afsr & PSYCHO_PCI_AFSR_BYTEMASK) >> PSYCHO_PCI_AFSR_BYTEMASK_SHIFT) 167 168 #define PCI_BRIDGE_TYPE(cmn_p) PCI_PSYCHO 169 /* 170 * for sabre 171 */ 172 #define DMA_WRITE_SYNC_REG 0x1C20 173 174 extern uint_t cb_thermal_intr(caddr_t a); 175 176 #define PCI_ID_TO_IGN(pci_id) ((pci_ign_t)UPAID_TO_IGN(pci_id)) 177 #ifdef __cplusplus 178 } 179 #endif 180 181 #endif /* _SYS_PCIPSY_H */ 182