17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*00d0963fSdilpreet * Common Development and Distribution License (the "License"). 6*00d0963fSdilpreet * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 22*00d0963fSdilpreet * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 237c478bd9Sstevel@tonic-gate * Use is subject to license terms. 247c478bd9Sstevel@tonic-gate */ 257c478bd9Sstevel@tonic-gate 267c478bd9Sstevel@tonic-gate #ifndef _SYS_DB21554_CTRL_H 277c478bd9Sstevel@tonic-gate #define _SYS_DB21554_CTRL_H 287c478bd9Sstevel@tonic-gate 297c478bd9Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 307c478bd9Sstevel@tonic-gate 317c478bd9Sstevel@tonic-gate #ifdef __cplusplus 327c478bd9Sstevel@tonic-gate extern "C" { 337c478bd9Sstevel@tonic-gate #endif 347c478bd9Sstevel@tonic-gate 357c478bd9Sstevel@tonic-gate /* definitions for device state */ 367c478bd9Sstevel@tonic-gate #define DB_SECONDARY_NEXUS 0x80000000 /* secondary towards host */ 377c478bd9Sstevel@tonic-gate #define DB_PRIMARY_NEXUS 0x40000000 /* primary towards host */ 387c478bd9Sstevel@tonic-gate #define DB_ATTACHED 0x00000001 /* driver attached */ 397c478bd9Sstevel@tonic-gate #define DB_SUSPENDED 0x00100000 407c478bd9Sstevel@tonic-gate #define DB_DEBUG_MODE_ON 0x01000000 417c478bd9Sstevel@tonic-gate 427c478bd9Sstevel@tonic-gate #define DB_PCI_CONF_RNUMBER 0 437c478bd9Sstevel@tonic-gate #define DB_PCI_CONF_OFFSET 0 447c478bd9Sstevel@tonic-gate #define DB_CSR_MEMBAR_RNUMBER 1 457c478bd9Sstevel@tonic-gate #define DB_CSR_MEM_OFFSET 0 467c478bd9Sstevel@tonic-gate #define DB_CSR_SIZE 0x1000 /* 4K CSR space */ 477c478bd9Sstevel@tonic-gate #define DB_CSR_IOBAR_RNUMBER 2 487c478bd9Sstevel@tonic-gate #define DB_CSR_IO_OFFSET 0 497c478bd9Sstevel@tonic-gate #define DB_PCI_TIMEOUT 10000 /* 10 ms */ 507c478bd9Sstevel@tonic-gate #define DB_PCI_WAIT_MS 0 517c478bd9Sstevel@tonic-gate #define DB_CONF_FAILURE -1 527c478bd9Sstevel@tonic-gate 537c478bd9Sstevel@tonic-gate #define DB_PIF_SECONDARY_TO_HOST 0x80 547c478bd9Sstevel@tonic-gate #define DB_PIF_PRIMARY_TO_HOST 0x40 557c478bd9Sstevel@tonic-gate 567c478bd9Sstevel@tonic-gate /* 577c478bd9Sstevel@tonic-gate * the following definition is used to save the state of all PCI children 587c478bd9Sstevel@tonic-gate * under us. 597c478bd9Sstevel@tonic-gate */ 607c478bd9Sstevel@tonic-gate typedef struct db_cfg_state { 617c478bd9Sstevel@tonic-gate dev_info_t *dip; 627c478bd9Sstevel@tonic-gate uchar_t cache_line_size; 637c478bd9Sstevel@tonic-gate uchar_t latency_timer; 647c478bd9Sstevel@tonic-gate uchar_t header_type; 657c478bd9Sstevel@tonic-gate uchar_t sec_latency_timer; 667c478bd9Sstevel@tonic-gate ushort_t command; 677c478bd9Sstevel@tonic-gate ushort_t bridge_control; 687c478bd9Sstevel@tonic-gate } db_cfg_state_t; 697c478bd9Sstevel@tonic-gate 707c478bd9Sstevel@tonic-gate /* the main control structure of our device */ 717c478bd9Sstevel@tonic-gate typedef struct db_ctrl { 727c478bd9Sstevel@tonic-gate dev_info_t *dip; 737c478bd9Sstevel@tonic-gate uint32_t dev_state; /* device state */ 747c478bd9Sstevel@tonic-gate caddr_t csr_mem; /* pointer to CSR map in memory space */ 757c478bd9Sstevel@tonic-gate caddr_t csr_io; /* pointer to CSR map in IO space */ 767c478bd9Sstevel@tonic-gate caddr_t conf_io; /* pointer to Conf indirect map */ 777c478bd9Sstevel@tonic-gate 787c478bd9Sstevel@tonic-gate /* our bus range information */ 79*00d0963fSdilpreet pci_bus_range_t range; 807c478bd9Sstevel@tonic-gate 817c478bd9Sstevel@tonic-gate /* any device tuning parameters here. */ 827c478bd9Sstevel@tonic-gate uint16_t p_command; 837c478bd9Sstevel@tonic-gate uint16_t s_command; 847c478bd9Sstevel@tonic-gate int8_t p_latency_timer; 857c478bd9Sstevel@tonic-gate int8_t p_cache_line_size; 867c478bd9Sstevel@tonic-gate int8_t s_latency_timer; 877c478bd9Sstevel@tonic-gate int8_t s_cache_line_size; 887c478bd9Sstevel@tonic-gate int8_t p_pwrite_threshold; 897c478bd9Sstevel@tonic-gate int8_t s_pwrite_threshold; 907c478bd9Sstevel@tonic-gate int8_t p_dread_threshold; 917c478bd9Sstevel@tonic-gate int8_t s_dread_threshold; 927c478bd9Sstevel@tonic-gate int8_t delayed_trans_order; 937c478bd9Sstevel@tonic-gate int8_t serr_fwd_enable; 947c478bd9Sstevel@tonic-gate 957c478bd9Sstevel@tonic-gate /* for child initialization */ 967c478bd9Sstevel@tonic-gate uint8_t latency_timer; 977c478bd9Sstevel@tonic-gate uint8_t cache_line_size; 987c478bd9Sstevel@tonic-gate 997c478bd9Sstevel@tonic-gate /* error holders */ 1007c478bd9Sstevel@tonic-gate uint32_t db_pci_err_count; /* indirect cycle timeout count */ 1017c478bd9Sstevel@tonic-gate #ifdef DEBUG 1027c478bd9Sstevel@tonic-gate uint32_t db_pci_max_wait_count; /* indirect cycle wait count */ 1037c478bd9Sstevel@tonic-gate #endif 1047c478bd9Sstevel@tonic-gate /* cpr related. */ 1057c478bd9Sstevel@tonic-gate uint_t config_state_index; 1067c478bd9Sstevel@tonic-gate db_cfg_state_t *db_config_state_p; 1077c478bd9Sstevel@tonic-gate 1087c478bd9Sstevel@tonic-gate /* all map handles below */ 1097c478bd9Sstevel@tonic-gate ddi_acc_handle_t csr_mem_handle; /* CSR memory handle */ 1107c478bd9Sstevel@tonic-gate ddi_acc_handle_t csr_io_handle; /* CSR IO handle */ 1117c478bd9Sstevel@tonic-gate ddi_acc_handle_t conf_handle; /* config space handle */ 1127c478bd9Sstevel@tonic-gate ddi_iblock_cookie_t i_block_cookie; /* interrupt cookie */ 1137c478bd9Sstevel@tonic-gate kmutex_t db_busown; /* bus config own mutex */ 1147c478bd9Sstevel@tonic-gate kmutex_t db_mutex; 1157c478bd9Sstevel@tonic-gate uint_t db_soft_state; 1167c478bd9Sstevel@tonic-gate #define DB_SOFT_STATE_CLOSED 0x00 1177c478bd9Sstevel@tonic-gate #define DB_SOFT_STATE_OPEN 0x01 1187c478bd9Sstevel@tonic-gate #define DB_SOFT_STATE_OPEN_EXCL 0x02 1197c478bd9Sstevel@tonic-gate int fm_cap; 1207c478bd9Sstevel@tonic-gate ddi_iblock_cookie_t fm_ibc; 1217c478bd9Sstevel@tonic-gate }db_ctrl_t; 1227c478bd9Sstevel@tonic-gate 1237c478bd9Sstevel@tonic-gate typedef struct db_acc_cfg_addr { 1247c478bd9Sstevel@tonic-gate uchar_t c_busnum; /* bus number */ 1257c478bd9Sstevel@tonic-gate uchar_t c_devnum; /* device number */ 1267c478bd9Sstevel@tonic-gate uchar_t c_funcnum; /* function number */ 1277c478bd9Sstevel@tonic-gate uchar_t c_fill; /* reserve field */ 1287c478bd9Sstevel@tonic-gate } db_acc_cfg_addr_t; 1297c478bd9Sstevel@tonic-gate 1307c478bd9Sstevel@tonic-gate typedef struct db_acc_pvt { 1317c478bd9Sstevel@tonic-gate db_acc_cfg_addr_t dev_addr; /* pci device address */ 1327c478bd9Sstevel@tonic-gate uint32_t *addr; /* upstream/downstream config addr */ 1337c478bd9Sstevel@tonic-gate uint32_t *data; /* upstream/downstream config data */ 1347c478bd9Sstevel@tonic-gate uint8_t *bus_own; /* reg to check if bus owned */ 1357c478bd9Sstevel@tonic-gate uint8_t *bus_release; /* reg to check if bus released */ 1367c478bd9Sstevel@tonic-gate uint8_t mask; /* bitmask for upstream/downstream */ 1377c478bd9Sstevel@tonic-gate ushort_t access_mode; /* access through IO or Config */ 1387c478bd9Sstevel@tonic-gate db_ctrl_t *dbp; 1397c478bd9Sstevel@tonic-gate ddi_acc_handle_t handle; /* handle for bus access DDI calls */ 1407c478bd9Sstevel@tonic-gate } db_acc_pvt_t; 1417c478bd9Sstevel@tonic-gate 1427c478bd9Sstevel@tonic-gate /* We can use the following modes for generating indirect PCI transcations */ 1437c478bd9Sstevel@tonic-gate #define DB_IO_MAP_DIRECT 1 /* memory mapped IO */ 1447c478bd9Sstevel@tonic-gate #define DB_IO_MAP_INDIRECT 2 /* indirect map IO */ 1457c478bd9Sstevel@tonic-gate #define DB_CONF_MAP_INDIRECT_CONF 4 /* access config via config regs */ 1467c478bd9Sstevel@tonic-gate #define DB_CONF_MAP_INDIRECT_IO 8 /* access config via IO regs */ 1477c478bd9Sstevel@tonic-gate #define DB_PCI_CONF_CYCLE_TYPE0 0x100 /* type 0 conf cycle */ 1487c478bd9Sstevel@tonic-gate #define DB_PCI_CONF_CYCLE_TYPE1 0x200 /* type 1 conf cycle */ 1497c478bd9Sstevel@tonic-gate 1507c478bd9Sstevel@tonic-gate #ifdef __cplusplus 1517c478bd9Sstevel@tonic-gate } 1527c478bd9Sstevel@tonic-gate #endif 1537c478bd9Sstevel@tonic-gate 1547c478bd9Sstevel@tonic-gate #endif /* _SYS_DB21554_CTRL_H */ 155