1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_MACHTHREAD_H 28 #define _SYS_MACHTHREAD_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #include <sys/asi.h> 33 #include <sys/sun4asi.h> 34 #include <sys/machasi.h> 35 #include <sys/bitmap.h> 36 37 #ifdef __cplusplus 38 extern "C" { 39 #endif 40 41 #ifdef _ASM 42 43 #define THREAD_REG %g7 /* pointer to current thread data */ 44 45 /* 46 * Get the processor implementation from the version register. 47 */ 48 #define GET_CPU_IMPL(out) \ 49 rdpr %ver, out; \ 50 srlx out, 32, out; \ 51 sll out, 16, out; \ 52 srl out, 16, out; 53 54 #ifdef _STARFIRE 55 /* 56 * CPU_INDEX(r, scr) 57 * Returns cpu id in r. 58 * On Starfire, this is read from the Port Controller's Port ID 59 * register in local space. 60 * 61 * Need to load the 64 bit address of the PC's PortID reg 62 * using only one register. Kludge the 41 bits address constant to 63 * be 32bits by shifting it 12 bits to the right first. 64 */ 65 #define LOCAL_PC_PORTID_ADDR_SRL12 0x1FFF4000 66 #define PC_PORT_ID 0xD0 67 68 #define CPU_INDEX(r, scr) \ 69 rdpr %pstate, scr; \ 70 andn scr, PSTATE_IE | PSTATE_AM, r; \ 71 wrpr r, 0, %pstate; \ 72 set LOCAL_PC_PORTID_ADDR_SRL12, r; \ 73 sllx r, 12, r; \ 74 or r, PC_PORT_ID, r; \ 75 lduwa [r]ASI_IO, r; \ 76 wrpr scr, 0, %pstate 77 78 #else /* _STARFIRE */ 79 80 /* 81 * UPA supports up to 32 devices while Safari supports up to 82 * 1024 devices (utilizing the SSM protocol). Based upon the 83 * value of NCPU, a 5- or 10-bit mask will be needed for 84 * extracting the cpu id. 85 */ 86 #if NCPU > 32 87 #define CPU_MASK 0x3ff 88 #else 89 #define CPU_MASK 0x1f 90 #endif /* NCPU > 32 */ 91 92 /* 93 * CPU_INDEX(r, scr) 94 * Returns cpu id in r. 95 * For UPA based systems, the cpu id corresponds to the mid field in 96 * the UPA config register. For Safari based machines, the cpu id 97 * corresponds to the aid field in the Safari config register. 98 * 99 * XXX - scr reg is not used here. 100 */ 101 #define CPU_INDEX(r, scr) \ 102 ldxa [%g0]ASI_UPA_CONFIG, r; \ 103 srlx r, 17, r; \ 104 and r, CPU_MASK, r 105 106 #endif /* _STARFIRE */ 107 108 /* 109 * Given a cpu id extract the appropriate word 110 * in the cpuset mask for this cpu id. 111 */ 112 #if CPUSET_SIZE > CLONGSIZE 113 #define CPU_INDEXTOSET(base, index, scr) \ 114 srl index, BT_ULSHIFT, scr; \ 115 and index, BT_ULMASK, index; \ 116 sll scr, CLONGSHIFT, scr; \ 117 add base, scr, base 118 #else 119 #define CPU_INDEXTOSET(base, index, scr) 120 #endif /* CPUSET_SIZE */ 121 122 123 /* 124 * Assembly macro to find address of the current CPU. 125 * Used when coming in from a user trap - cannot use THREAD_REG. 126 * Args are destination register and one scratch register. 127 */ 128 #define CPU_ADDR(reg, scr) \ 129 .global cpu; \ 130 CPU_INDEX(scr, reg); \ 131 sll scr, CPTRSHIFT, scr; \ 132 set cpu, reg; \ 133 ldn [reg + scr], reg 134 135 #define CINT64SHIFT 3 136 137 /* 138 * Assembly macro to find the physical address of the current CPU. 139 * All memory references using VA must be limited to nucleus 140 * memory to avoid any MMU side effect. 141 */ 142 #define CPU_PADDR(reg, scr) \ 143 .global cpu_pa; \ 144 CPU_INDEX(scr, reg); \ 145 sll scr, CINT64SHIFT, scr; \ 146 set cpu_pa, reg; \ 147 ldx [reg + scr], reg 148 149 #endif /* _ASM */ 150 151 /* 152 * If a high level trap handler decides to call sys_trap() to execute some 153 * base level code, context and other registers must be set to proper 154 * values to run kernel. This is true for most part of the kernel, except 155 * for user_rtt, a substantial part of which is executed with registers 156 * ready to run user code. The following macro may be used to detect this 157 * condition and handle it. Please note that, in general, we can't restart 158 * arbitrary piece of code running at tl > 0; user_rtt is a special case 159 * that can be handled. 160 * 161 * Entry condition: 162 * 163 * %tl = 2 164 * pstate.ag = 1 165 * 166 * Register usage: 167 * 168 * scr1, scr2 - destroyed 169 * normal %g5 and %g6 - destroyed 170 * 171 */ 172 /* BEGIN CSTYLED */ 173 #define RESET_USER_RTT_REGS(scr1, scr2, label) \ 174 /* \ 175 * do nothing if %tl != 2. this an attempt to stop this \ 176 * piece of code from executing more than once before going \ 177 * back to TL=0. more specifically, the changes we are doing \ 178 * to %wstate, %canrestore and %otherwin can't be done more \ 179 * than once before going to TL=0. note that it is okay to \ 180 * execute this more than once if we restart at user_rtt and \ 181 * come back from there. \ 182 */ \ 183 rdpr %tl, scr1; \ 184 cmp scr1, 2; \ 185 bne,a,pn %xcc, label; \ 186 nop; \ 187 /* \ 188 * read tstate[2].%tpc. do nothing if it is not \ 189 * between rtt_ctx_start and rtt_ctx_end. \ 190 */ \ 191 rdpr %tpc, scr1; \ 192 set rtt_ctx_end, scr2; \ 193 cmp scr1, scr2; \ 194 bgu,a,pt %xcc, label; \ 195 nop; \ 196 set rtt_ctx_start, scr2; \ 197 cmp scr1, scr2; \ 198 blu,a,pt %xcc, label; \ 199 nop; \ 200 /* \ 201 * pickup tstate[2].cwp \ 202 */ \ 203 rdpr %tstate, scr1; \ 204 and scr1, TSTATE_CWP, scr1; \ 205 /* \ 206 * set tstate[1].cwp to tstate[2].cwp. fudge \ 207 * tstate[1].tpc and tstate[1].tnpc to restart \ 208 * user_rtt. \ 209 */ \ 210 wrpr %g0, 1, %tl; \ 211 set TSTATE_KERN | TSTATE_IE, scr2; \ 212 or scr1, scr2, scr2; \ 213 wrpr %g0, scr2, %tstate; \ 214 set user_rtt, scr1; \ 215 wrpr %g0, scr1, %tpc; \ 216 add scr1, 4, scr1; \ 217 wrpr %g0, scr1, %tnpc; \ 218 /* \ 219 * restore %tl \ 220 */ \ 221 wrpr %g0, 2, %tl; \ 222 /* \ 223 * set %wstate \ 224 */ \ 225 rdpr %wstate, scr1; \ 226 sllx scr1, WSTATE_SHIFT, scr1; \ 227 wrpr scr1, WSTATE_K64, %wstate; \ 228 /* \ 229 * setup window registers \ 230 * %cleanwin <-- nwin - 1 \ 231 * %otherwin <-- %canrestore \ 232 * %canrestore <-- 0 \ 233 */ \ 234 sethi %hi(nwin_minus_one), scr1; \ 235 ld [scr1 + %lo(nwin_minus_one)], scr1; \ 236 wrpr %g0, scr1, %cleanwin; \ 237 rdpr %canrestore, scr1; \ 238 wrpr %g0, scr1, %otherwin; \ 239 wrpr %g0, 0, %canrestore; \ 240 /* \ 241 * set THREAD_REG, as we have restored user \ 242 * registers in user_rtt. we trash %g5 and %g6 \ 243 * in the process. \ 244 */ \ 245 rdpr %pstate, scr1; \ 246 wrpr scr1, PSTATE_AG, %pstate; \ 247 /* \ 248 * using normal globals now \ 249 */ \ 250 CPU_ADDR(%g5, %g6); \ 251 ldn [%g5 + CPU_THREAD], %g6; \ 252 mov %g6, THREAD_REG; \ 253 rdpr %pstate, %g5; \ 254 wrpr %g5, PSTATE_AG, %pstate; \ 255 /* \ 256 * back to alternate globals. \ 257 * set PCONTEXT to run kernel. \ 258 * no need to demap I/DTLB as we \ 259 * never went back to user mode. \ 260 */ \ 261 mov MMU_PCONTEXT, scr1; \ 262 sethi %hi(kcontextreg), scr2; \ 263 ldx [scr2 + %lo(kcontextreg)], scr2; \ 264 stxa scr2, [scr1]ASI_MMU_CTX; \ 265 sethi %hi(FLUSH_ADDR), scr1; \ 266 flush scr1; 267 268 /* END CSTYLED */ 269 270 #ifdef __cplusplus 271 } 272 #endif 273 274 #endif /* _SYS_MACHTHREAD_H */ 275