1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_MACHSYSTM_H 28 #define _SYS_MACHSYSTM_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 /* 33 * Numerous platform-dependent interfaces that don't seem to belong 34 * in any other header file. 35 * 36 * This file should not be included by code that purports to be 37 * platform-independent. 38 */ 39 40 #ifndef _ASM 41 #include <sys/types.h> 42 #include <sys/scb.h> 43 #include <sys/varargs.h> 44 #include <sys/machparam.h> 45 #include <sys/thread.h> 46 #include <vm/seg_enum.h> 47 #include <sys/processor.h> 48 #include <sys/sunddi.h> 49 #include <sys/memlist.h> 50 #include <sys/async.h> 51 #include <sys/errorq.h> 52 #endif /* _ASM */ 53 54 #ifdef __cplusplus 55 extern "C" { 56 #endif 57 58 #ifdef _KERNEL 59 60 #ifndef _ASM 61 /* 62 * The following enum types determine how interrupts are distributed 63 * on a sun4u system. 64 */ 65 enum intr_policies { 66 /* 67 * Target interrupt at the CPU running the add_intrspec 68 * thread. Also used to target all interrupts at the panicing 69 * CPU. 70 */ 71 INTR_CURRENT_CPU = 0, 72 73 /* 74 * Target all interrupts at the boot cpu 75 */ 76 INTR_BOOT_CPU, 77 78 /* 79 * Flat distribution of all interrupts 80 */ 81 INTR_FLAT_DIST, 82 83 /* 84 * Weighted distribution of all interrupts 85 */ 86 INTR_WEIGHTED_DIST 87 }; 88 89 90 /* 91 * Structure that defines the interrupt distribution list. It contains 92 * enough info about the interrupt so that it can callback the parent 93 * nexus driver and retarget the interrupt to a different CPU. 94 */ 95 struct intr_dist { 96 struct intr_dist *next; /* link to next in list */ 97 void (*func)(void *); /* Callback function */ 98 void *arg; /* Nexus parent callback arg 1 */ 99 }; 100 101 /* 102 * Miscellaneous cpu_state changes 103 */ 104 extern void power_down(const char *); 105 extern void do_shutdown(void); 106 107 /* 108 * Number of seconds until power is shut off 109 */ 110 extern int thermal_powerdown_delay; 111 112 113 /* 114 * prom-related 115 */ 116 extern int obpdebug; 117 extern int forthdebug_supported; 118 extern uint_t tba_taken_over; 119 extern void forthdebug_init(void); 120 extern void init_vx_handler(void); 121 extern void kern_preprom(void); 122 extern void kern_postprom(void); 123 124 /* 125 * externally (debugger or prom) initiated panic 126 */ 127 extern struct regs sync_reg_buf; 128 extern uint64_t sync_tt; 129 extern void sync_handler(void); 130 131 /* 132 * Trap-related 133 */ 134 struct regs; 135 extern void trap(struct regs *rp, caddr_t addr, uint32_t type, 136 uint32_t mmu_fsr); 137 extern void *get_tba(void); 138 extern void *set_tba(void *); 139 extern caddr_t set_trap_table(void); 140 extern struct scb trap_table; 141 142 struct trap_info { 143 struct regs *trap_regs; 144 uint_t trap_type; 145 caddr_t trap_addr; 146 uint_t trap_mmu_fsr; 147 }; 148 149 /* 150 * misc. primitives 151 */ 152 extern void debug_flush_windows(void); 153 extern void flush_windows(void); 154 extern int getprocessorid(void); 155 extern void reestablish_curthread(void); 156 157 extern void stphys(uint64_t physaddr, int value); 158 extern int ldphys(uint64_t physaddr); 159 extern void stdphys(uint64_t physaddr, uint64_t value); 160 extern uint64_t lddphys(uint64_t physaddr); 161 162 extern void stphysio(u_longlong_t physaddr, uint_t value); 163 extern uint_t ldphysio(u_longlong_t physaddr); 164 extern void sthphysio(u_longlong_t physaddr, ushort_t value); 165 extern ushort_t ldhphysio(u_longlong_t physaddr); 166 extern void stbphysio(u_longlong_t physaddr, uchar_t value); 167 extern uchar_t ldbphysio(u_longlong_t physaddr); 168 extern void stdphysio(u_longlong_t physaddr, u_longlong_t value); 169 extern u_longlong_t lddphysio(u_longlong_t physaddr); 170 171 extern int pf_is_dmacapable(pfn_t); 172 173 extern int dip_to_cpu_id(dev_info_t *dip, processorid_t *cpu_id); 174 175 extern void set_cmp_error_steering(void); 176 177 /* 178 * SPARCv9 %ver register and field definitions 179 */ 180 181 #define ULTRA_VER_MANUF(x) ((x) >> 48) 182 #define ULTRA_VER_IMPL(x) (((x) >> 32) & 0xFFFF) 183 #define ULTRA_VER_MASK(x) (((x) >> 24) & 0xFF) 184 185 extern uint64_t ultra_getver(void); 186 187 /* 188 * bootup-time 189 */ 190 extern int ncpunode; 191 extern int niobus; 192 193 extern void segnf_init(void); 194 extern void kern_setup1(void); 195 extern void startup(void); 196 extern void post_startup(void); 197 extern void install_va_to_tte(void); 198 extern void setwstate(uint_t); 199 extern void create_va_to_tte(void); 200 extern int memscrub_init(void); 201 202 extern void kcpc_hw_init(void); 203 extern void kcpc_hw_startup_cpu(ushort_t); 204 extern int kcpc_hw_load_pcbe(void); 205 206 /* 207 * Interrupts 208 */ 209 struct cpu; 210 extern struct cpu cpu0; 211 extern size_t intr_add_pools; 212 extern struct intr_req *intr_add_head; 213 extern struct intr_req *intr_add_tail; 214 extern struct scb *set_tbr(struct scb *); 215 216 extern void init_intr_threads(struct cpu *); 217 extern uint_t disable_vec_intr(void); 218 extern void enable_vec_intr(uint_t); 219 extern void setintrenable(int); 220 221 extern void intr_dist_add(void (*f)(void *), void *); 222 extern void intr_dist_rem(void (*f)(void *), void *); 223 extern void intr_dist_add_weighted(void (*f)(void *, int32_t, int32_t), void *); 224 extern void intr_dist_rem_weighted(void (*f)(void *, int32_t, int32_t), void *); 225 226 extern uint32_t intr_dist_cpuid(void); 227 228 void intr_dist_cpuid_add_device_weight(uint32_t cpuid, dev_info_t *dip, 229 int32_t weight); 230 void intr_dist_cpuid_rem_device_weight(uint32_t cpuid, dev_info_t *dip); 231 232 extern void intr_redist_all_cpus(void); 233 extern void intr_redist_all_cpus_shutdown(void); 234 235 extern void send_dirint(int, int); 236 extern void setsoftint(uint_t); 237 extern void setsoftint_tl1(uint64_t, uint64_t); 238 extern void siron(void); 239 extern uint64_t getidsr(void); 240 extern void intr_enqueue_req(uint_t pil, uint32_t inum); 241 extern void intr_dequeue_req(uint_t pil, uint32_t inum); 242 extern void wr_clr_softint(uint_t); 243 244 /* 245 * Time- and %tick-related 246 */ 247 extern hrtime_t rdtick(void); 248 extern void tick_write_delta(uint64_t); 249 extern void tickcmpr_set(uint64_t); 250 extern void tickcmpr_reset(void); 251 extern void tickcmpr_disable(void); 252 extern int tickcmpr_disabled(void); 253 extern uint32_t cbe_level14_inum; 254 255 /* 256 * Caches 257 */ 258 extern int vac; 259 extern int cache; 260 extern int use_mp; 261 extern uint_t vac_mask; 262 extern uint64_t ecache_flushaddr; 263 extern int dcache_size; /* Maximum dcache size */ 264 extern int dcache_linesize; /* Minimum dcache linesize */ 265 extern int icache_size; /* Maximum icache size */ 266 extern int icache_linesize; /* Minimum icache linesize */ 267 extern int ecache_alignsize; /* Maximum ecache linesize for struct align */ 268 extern int ecache_size; /* Maximum ecache size */ 269 extern int ecache_associativity; /* ecache associativity */ 270 extern int ecache_setsize; /* Maximum ecache setsize possible */ 271 extern int cpu_setsize; /* Maximum ecache setsize of configured cpus */ 272 273 /* 274 * VM 275 */ 276 extern int do_pg_coloring; 277 extern int do_virtual_coloring; 278 extern int use_page_coloring; 279 extern int use_virtual_coloring; 280 extern uint_t vac_colors_mask; 281 282 extern void ndata_alloc_init(struct memlist *, uintptr_t, uintptr_t); 283 extern void *ndata_alloc(struct memlist *, size_t, size_t); 284 extern void *ndata_extra_base(struct memlist *, size_t); 285 extern size_t ndata_maxsize(struct memlist *); 286 extern size_t ndata_spare(struct memlist *, size_t, size_t); 287 extern int ndata_alloc_cpus(struct memlist *); 288 extern int ndata_alloc_page_freelists(struct memlist *, int); 289 extern int ndata_alloc_dmv(struct memlist *); 290 extern int ndata_alloc_tsbs(struct memlist *, pgcnt_t); 291 extern int ndata_alloc_hat(struct memlist *, pgcnt_t, pgcnt_t); 292 extern caddr_t alloc_page_freelists(int, caddr_t, int); 293 extern caddr_t alloc_hme_buckets(caddr_t, int); 294 extern size_t page_ctrs_sz(void); 295 extern caddr_t page_ctrs_alloc(caddr_t); 296 extern void page_freelist_coalesce_all(int); 297 extern void ppmapinit(void); 298 extern void hwblkpagecopy(const void *, void *); 299 extern void hw_pa_bcopy32(uint64_t, uint64_t); 300 301 extern int pp_slots; 302 extern int pp_consistent_coloring; 303 304 /* 305 * ppcopy/hwblkpagecopy interaction. See ppage.c. 306 */ 307 #define PPAGE_STORE_VCOLORING 0x1 /* use vcolors to maintain consistency */ 308 #define PPAGE_LOAD_VCOLORING 0x2 /* use vcolors to maintain consistency */ 309 #define PPAGE_STORES_POLLUTE 0x4 /* stores pollute VAC */ 310 #define PPAGE_LOADS_POLLUTE 0x8 /* loads pollute VAC */ 311 312 /* 313 * VIS-accelerated copy/zero 314 */ 315 extern int use_hw_bcopy; 316 extern uint_t hw_copy_limit_1; 317 extern uint_t hw_copy_limit_2; 318 extern uint_t hw_copy_limit_4; 319 extern uint_t hw_copy_limit_8; 320 extern int use_hw_bzero; 321 322 #ifdef CHEETAH 323 #define VIS_COPY_THRESHOLD 256 324 #else 325 #define VIS_COPY_THRESHOLD 900 326 #endif 327 328 /* 329 * MP 330 */ 331 extern void idle_other_cpus(void); 332 extern void resume_other_cpus(void); 333 extern void stop_other_cpus(void); 334 extern void idle_stop_xcall(void); 335 extern void set_idle_cpu(int); 336 extern void unset_idle_cpu(int); 337 extern void mp_cpu_quiesce(struct cpu *); 338 339 /* 340 * Error handling 341 */ 342 extern void set_error_enable(uint64_t neer); 343 extern void set_error_enable_tl1(uint64_t neer, uint64_t action); 344 extern uint64_t get_error_enable(void); 345 extern void get_asyncflt(uint64_t *afsr); 346 extern void set_asyncflt(uint64_t afsr); 347 extern void get_asyncaddr(uint64_t *afar); 348 extern void scrubphys(uint64_t paddr, int ecache_size); 349 extern void clearphys(uint64_t paddr, int ecache_size, int ecache_linesize); 350 extern void flushecacheline(uint64_t paddr, int ecache_size); 351 extern int ce_scrub_xdiag_recirc(struct async_flt *, errorq_t *, 352 errorq_elem_t *, size_t); 353 extern char *flt_to_error_type(struct async_flt *); 354 355 /* 356 * Panic at TL > 0 357 */ 358 extern uint64_t cpu_pa[]; 359 extern void ptl1_init_cpu(struct cpu *); 360 361 /* 362 * Defines for DR interfaces 363 */ 364 #define DEVI_BRANCH_CHILD 0x01 /* Walk immediate children of root */ 365 #define DEVI_BRANCH_CONFIGURE 0x02 /* Configure branch after create */ 366 #define DEVI_BRANCH_DESTROY 0x04 /* Destroy branch after unconfigure */ 367 #define DEVI_BRANCH_EVENT 0x08 /* Post NDI event */ 368 #define DEVI_BRANCH_PROM 0x10 /* Branches derived from PROM nodes */ 369 #define DEVI_BRANCH_SID 0x20 /* SID node branches */ 370 #define DEVI_BRANCH_ROOT 0x40 /* Node is the root of a branch */ 371 372 typedef struct devi_branch { 373 void *arg; 374 void (*devi_branch_callback)(dev_info_t *, void *, uint_t); 375 int type; 376 union { 377 int (*prom_branch_select)(dnode_t, void *, uint_t); 378 int (*sid_branch_create)(dev_info_t *, void *, uint_t); 379 } create; 380 } devi_branch_t; 381 382 383 /* 384 * Prototypes which really belongs to sunddi.c, and should be moved to 385 * sunddi.c if there is another platform using these calls. 386 */ 387 extern int e_ddi_branch_create(dev_info_t *pdip, devi_branch_t *bp, 388 dev_info_t **dipp, uint_t flags); 389 extern int e_ddi_branch_configure(dev_info_t *rdip, dev_info_t **dipp, 390 uint_t flags); 391 extern int e_ddi_branch_unconfigure(dev_info_t *rdip, dev_info_t **dipp, 392 uint_t flags); 393 extern int e_ddi_branch_destroy(dev_info_t *rdip, dev_info_t **dipp, 394 uint_t flags); 395 extern void e_ddi_branch_hold(dev_info_t *rdip); 396 extern void e_ddi_branch_rele(dev_info_t *rdip); 397 extern int e_ddi_branch_held(dev_info_t *rdip); 398 extern int e_ddi_branch_referenced(dev_info_t *rdip, 399 int (*cb)(dev_info_t *dip, void *, uint_t), void *arg); 400 401 /* 402 * Constants which define the "hole" in the 64-bit sfmmu address space. 403 * These are set to specific values by the CPU module code. 404 */ 405 extern caddr_t hole_start, hole_end; 406 407 /* kpm mapping window */ 408 extern size_t kpm_size; 409 extern uchar_t kpm_size_shift; 410 extern caddr_t kpm_vbase; 411 412 #define INVALID_VADDR(a) (((a) >= hole_start && (a) < hole_end)) 413 414 extern void adjust_hw_copy_limits(int); 415 416 #endif /* _ASM */ 417 418 /* 419 * Actions for set_error_enable_tl1 420 */ 421 #define EER_SET_ABSOLUTE 0x0 422 #define EER_SET_SETBITS 0x1 423 #define EER_SET_CLRBITS 0x2 424 425 #endif /* _KERNEL */ 426 427 #ifdef __cplusplus 428 } 429 #endif 430 431 #endif /* _SYS_MACHSYSTM_H */ 432